| Entries |
| Document | Title | Date |
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| 20080201555 | Image processing apparatus, method for controlling image processing apparatus, control program, and recording medium - An image processing apparatus is disclosed that includes an image processing unit section and an information processing unit section. The image processing unit section includes an image scanner that performs an image processing function and a SDK application that expands and controls the function of the image processing apparatus. The information processing unit section includes an operations panel that selectively performs operations between a basic application and the SDK application and a MFP service that transmits an instruction signal to the SDK application so as to control the image scanner in accordance with the operation on the operations panel. The information processing unit section confirms the corresponding relationship between the MFP service and the SDK application when the image processing apparatus performs a starting process and makes the SDK application correspond to the MFP service in accordance with the confirmation results. | 08-21-2008 |
| 20080209167 | APPARATUS AND METHOD FOR ADAPTIVE MULTIMEDIA RECEPTION AND TRANSMISSION IN COMMUNICATION ENVIRONMENTS - The present invention provides a method and apparatus for configuration of adaptive integrated circuitry, to provide one or more operating modes or other functionality in a communication device, such as a cellular telephone, a GSM telephone, another type of mobile telephone or mobile station, or any other type of media communication device, including video, voice or radio, or other forms of multimedia. The adaptive integrated circuitry is configured and reconfigured for multiple tasks, such as channel acquisition, voice transmission, or multimedia and other data processing. In the preferred embodiment, the configuration and reconfiguration occurs to adaptively optimize the performance of the particular activity over time, such as to increase the speed of channel acquisition, increase throughput rates, increase perceived voice and media quality, and decrease the rate of dropped communication sessions. | 08-28-2008 |
| 20080229061 | Processor Element for use in a Network of Processor Elements - In order to detect objects using a processor element for use in a network of processor elements which are connected to one another, the processor element comprises a processor, at least one interface for coupling to further processor elements of the network and an oscillator having a connection for coupling to an electrode outside the processor element. | 09-18-2008 |
| 20080263319 | UNIVERSAL DIGITAL BLOCK WITH INTEGRATED ARITHMETIC LOGIC UNIT - An array of universal digital blocks include programmable logic device sections that have uncommitted user programmable logic functions and structural datapath sections that include dedicated and highly configurable arithmetic operators. A routing channel matrix programmably connects to different programmable logic device sections and datapath sections in the different universal digital blocks. | 10-23-2008 |
| 20080282063 | METHODS AND APPARATUS FOR LATENCY CONTROL IN A MULTIPROCESSOR SYSTEM - Methods and apparatus provide for a multiprocessor system including: a plurality of sub-processors operatively coupled to one another over a ring bus, whereby data may be transmitted over one or more paths on the ring bus between pairs of the sub-processors; and a plurality of programmable delay circuits, each associated with at least one of the sub-processors, and each being operable to alter a delay of data transfer at least one of into and out of its associated sub-processor in order to alter one or more latencies associated with the paths on the ring bus between pairs of the sub-processors. | 11-13-2008 |
| 20080294873 | Microcomputer - A built-in memory is divided into the following two types: first memories | 11-27-2008 |
| 20080294874 | ALLOCATION OF COMBINED OR SEPARATE DATA AND CONTROL PLANES - A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication. | 11-27-2008 |
| 20080301406 | SYSTEM AND METHOD FOR ALLOCATING COMMUNICATIONS TO PROCESSORS IN A MULTIPROCESSOR SYSTEM - In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific | 12-04-2008 |
| 20080313426 | Information Processing Apparatus and Information Processing Method - An asynchronous communicating part executes an asynchronous communication between a first device and a second device. A first process executing part executes a processing in the first device by use of the asynchronous communication as a trigger. A second process executing part executes a processing in the second device by use of the asynchronous communication as a trigger. A trigger signal sending part sends a trigger signal from the first device to the second device. A response signal replying part replies a response signal from the second device to the first device when the second device receives the trigger signal. Thus, the first process executing part and the second process executing part execute the processing in the first device and the second device using the asynchronous communication as the trigger, so that the processing in the first device and the processing in the second device are synchronized. | 12-18-2008 |
| 20080313427 | DIRECTORY-BASED DATA TRANSFER PROTOCOL FOR MULTIPROCESSOR SYSTEM - A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state. | 12-18-2008 |
| 20080320278 | SYSTEM AND METHOD FOR EFFICIENT DATA TRANSMISSION IN A MULTI-PROCESSOR ENVIRONMENT - A system and method which provides for efficient data transmission between multiple microprocessors in a computer system is disclosed. A physical data path is divided into one or more data queues which may be virtual connection queues. The virtual connection queues are configured to adaptively split or merge based on traffic conditions therein. | 12-25-2008 |
| 20080320279 | MANAGEMENT OF A COMMUNICATION LINK EXTENDED TO ONE OR MORE SLAVE DEVICES - A master device for managing a communications link to slave devices (for example in the context of a Wireless USB cluster), wherein the master device is configured to facilitate avoidance of unnecessary waking of the slave devices. | 12-25-2008 |
| 20090013153 | PROCESSOR EXCLUSIVITY IN A PARTITIONED SYSTEM - A computer system including a plurality of physical processors (CPs) having physical processor performances (PCPs), a plurality of logical processors (LCPs), a plurality of logical partitions (LPARs) where each partition includes one or more of the logical processors (LCPs), and a system assist processor having a control element. The control element controls the virtualization of the physical processors (CPs), the logical partitions (LPARs) and the logical processors (LCPs) and allocates the physical processor performances (PCPs) to the logical partitions (LPARs). The control element operates to exclusively bind logical processors (LCPs) to the physical processors (CPs). For a logical processor (LCP) exclusively bound to a physical processor (CP), the logical processor (LCP) has exclusive use of the underlying physical processor (CP) and no other logical processor (LCP) can be dispatched on the underlying physical processor (CP) even if the underlying physical processor (CP) is otherwise available. | 01-08-2009 |
| 20090019258 | FAULT TOLERANT SELF-OPTIMIZING MULTI-PROCESSOR SYSTEM AND METHOD THEREOF - A fault-tolerant self-optimizing multi-processor system is disclosed that includes a plurality of redundant network switching units and a plurality of processors electrically coupled to the network switching units. Each processor comprises a local memory, local storage, multiple network interfaces and a routing agent (RA). The RAs form a unidirectional virtual ring (UVR) network using the redundant network switching units. The UVR network may coordinate all of the processors for data matching, failure detection/recovery and system management functions. Once data is matched via the UVR network, application programs communicate directly via the network switching units, thus fully exploiting the hardware redundancy. Each of the RAs may implement a tuple space daemon responsible for data matching and delivery, forwarding unsatisfied data requests to a downstream processor or dropping expired tuples from UVR circulation. The RAs provide overall system fault tolerance and are responsible for delivering data sources to the matching processors. | 01-15-2009 |
| 20090019259 | MULTIPROCESSING METHOD AND MULTIPROCESSOR SYSTEM - A multiprocessing method and a multiprocessor system capable of reducing time lost due to sequential waiting when procedures (program units) having dependencies are executed in which an order of execution of a plurality of program units in a sequential execution program and dependencies of the plurality of program units are registered, the execution states of the plurality of program units are managed based on the registered dependencies, executable program units are determined, and are assigned to server processors sequentially and executed are disclosed. | 01-15-2009 |
| 20090024833 | Multiprocessor Node Controller Circuit and Method - Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory/directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data. Further, the memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips. In some such embodiments, the ratio of (memory data space) to (directory data space) on each card is set to a value that is based on a size of the multiprocessor computer system. | 01-22-2009 |
| 20090031106 | RECONFIGURABLE DEVICE - There is provided a reconfigurable device that includes a plurality of processing blocks ( | 01-29-2009 |
| 20090043986 | Processor Array System With Data Reallocation Function Among High-Speed PEs - A processor array system which is able to perform load balancing among PEs at high speed is provided. When an instruction code | 02-12-2009 |
| 20090055626 | METHOD OF SHARING COARSE GRAINED ARRAY AND PROCESSOR USING THE METHOD - A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a first instruction set, a second processor core including a plurality of second functional units which execute a second instruction set, and a coarse grained array including a plurality of third functional units which execute a portion of instructions of the first instruction set and/or the second instruction set, instead of the first processor core and/or the second processor core. | 02-26-2009 |
| 20090055627 | Efficient Pipeline Parallelism Using Frame Shared Memory - A systems and methods are disclosed that provide an efficient parallel pipeline for data processing using a multi-core processor. Embodiments allocate a shared memory portion of the memory that is accessible from more than one context of execution and/or process a frame in a plurality of processing stages processed by a context of execution. In some embodiments, each of the plurality of processing stages may be bound to a processing core of the multi-core processor. In other embodiments include one or more processing stages with a point-to-point communication mechanism that operates in shared memory. | 02-26-2009 |
| 20090063813 | METHOD AND SYSTEM FOR FLEXIBLE AND NEGOTIABLE EXCHANGE OF LINK LAYER FUNCTIONAL PARAMETERS - A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent intervention or redundancy. | 03-05-2009 |
| 20090070552 | RECONFIGURABLE MULTI-PROCESSING COARSE-GRAIN ARRAY - A signal processing device adapted for simultaneous processing of at least two process threads in a multi-processing manner is disclosed. In one embodiment, the device comprises a plurality of functional units capable of executing word- or subword-level operations on data. The device further comprises means for interconnecting the plurality of functional units, the means for interconnecting supporting a plurality of dynamically switchable interconnect arrangements, and at least one of the interconnect arrangements interconnects the plurality of functional units into at least two non-overlapping processing units each with a pre-determined topology. The device further comprises at least two control modules each assigned to one of the processing units. | 03-12-2009 |
| 20090089540 | Processor architecture for executing transfers between wide operand memories - A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers. | 04-02-2009 |
| 20090089541 | MULTIPROCESSING DEVICE AND INFORMATION PROCESSING DEVICE - Instructions executed by a plurality of processors including a specific processor and the other processors connected to the specific processor are stored in an instruction storage memory. The instructions stored in the instruction storage memory are transferred to and retained in an instruction execution memory, and when an instruction is executed by one of the plurality of processors, a required instruction is retrieved by the processor. A leading address of a position where the required instruction of the other processors is retained in the instruction execution memory is stored in an address storage memory. A memory control circuit coordinates access to the instruction execution memory by the plurality of processors and controls access to the address storage memory by the specific processor. | 04-02-2009 |
| 20090119481 | Computer memory architecture for hybrid serial and parallel computing systems - In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties. For example, towards switching between the serial mode and the parallel mode, the serial processor is configured to send a signal to start pre-fetching of data from the shared memory. | 05-07-2009 |
| 20090119482 | Image forming device, image formation controlling method, and image formation controlling program - An image forming device includes a plurality of input units, a plurality of processing units, and a plurality of output units which are arranged to perform image-data processing. The image forming device includes a processing operation executing unit configured to instruct a processing operation of each of a predetermined input unit, a predetermined processing unit, and a predetermined output unit. A controlled unit reporting unit is configured in the processing operation executing unit to notify a controlled unit of processing to be performed, to each of the predetermined input unit, the predetermined processing unit, and the predetermined output unit. | 05-07-2009 |
| 20090138675 | ATOMIC COMPARE AND SWAP USING DEDICATED PROCESSOR - An atomic compare and swap operation that can be implemented in processor system having first and second processors that have different sized memory transfer capabilities. The first processor notifies the second processor to perform a compare and swap operation on an address in main memory. The address has a size less than or equal to a maximum memory transfer size for the second processor and greater than a maximum memory transfer size for the first processor. The second processor atomically performs the compare and swap operation and notifies the first processor of the success or failure of the compare and swap operation. | 05-28-2009 |
| 20090150652 | COMPUTER MONITORING SYSTEM AND MONITORING METHOD - An exemplary computer monitoring system includes a central processing unit (CPU) connected to a computer, a first microprocessor, a second microprocessor, and a select switch connected to a terminal device. The CPU is connected to the select switch via the first microprocessor and the second microprocessor respectively for transmitting data. When one of the first and second microprocessors is halted, the other one of the first and second microprocessors is selected by the select switch under the control of the CPU. The CPU sends a reset signal to the halted microprocessor to reset it. A monitoring method using the computer monitoring system for improving stability and reliability of the computer monitoring system is disclosed. | 06-11-2009 |
| 20090158008 | SOFTWARE PARAMETERIZABLE CONTROL BLOCKS FOR USE IN PHYSICAL LAYER PROCESSING - A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode. | 06-18-2009 |
| 20090164754 | Hierarchical block-identified data communication for unified handling of structured data and data compression - Data transmission efficiency for structured data can be improved by representing structured data using immutable blocks. The contents of the immutable blocks can include data and/or pointers to immutable blocks. An immutable data block cannot be altered after creation of the block. When data represented as immutable blocks is transmitted from one processor to another processor, the transmitter sends block contents for blocks that have not previously been defined at the receiver, and sends block IDs (as opposed to block contents) for blocks that have previously been defined at the receiver. The systematic use of block IDs instead of block contents in transmission where possible can significantly reduce transmission bandwidth requirements. | 06-25-2009 |
| 20090172352 | DYNAMIC RECONFIGURABLE CIRCUIT - A dynamic reconfigurable circuit including a plurality of processing elements each provided with an arithmetic data input port, a configuration data input port and an output port, a data network that is coupled to the arithmetic data input ports and the output ports of the plurality of processing elements, a configuration memory that is coupled via a configuration path to the configuration data input port of a first processor element being at least one of the plurality of processing elements, and an immediate value network that is independent from the data network and that is coupled to the configuration data input port of a second processor element being at least one of the plurality of processing elements. An internal register of a third processor element is coupled to the immediate value network so that data stored in the internal register can be outputted to the immediate value network. | 07-02-2009 |
| 20090193227 | Multi-stream on-chip memory - An interface to on-chip memory is described, which provides for using on-chip memory by a RISC superscalar processor, enhanced with methods which execute vector operations by treating the vectors as “streams”, which are fed through one or two function units in a pipelined manner. The interface provides concurrent multiple streams, while at the same time serving “conventional” requests from the host RISC superscalar processor. | 07-30-2009 |
| 20090193228 | MULTIPROCESSOR SYSTEM AND METHOD OF SYNCHRONIZATION FOR MULTIPROCESSOR SYSTEM - Each of processors has a barrier write register and a barrier read register. Each barrier write register is wired to each barrier read register by a dedicated wiring block. For example, a 1-bit barrier write register of a processor is connected, via the wiring block, to a first bit of each 8-bit barrier read register contained in the processors, and a 1-bit barrier write register of another processor is connected, via a wiring block, to a second bit of each 8-bit barrier read register contained in the processors. For example, a processor writes information to its own barrier write register, thereby notifying synchronization stand-by to the other processors and reads its own barrier read register, thereby recognizing whether the other processors are in synchronization stand-by or not. Therefore, a special dedicated instruction is not required along barrier synchronization processing, and the processing can be made at a high speed. | 07-30-2009 |
| 20090198957 | System and Method for Performing Dynamic Request Routing Based on Broadcast Queue Depths - A system and method for performing dynamic request routing based on broadcast depth queue information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide queue depth information to each of the other processor chips in the system. The queue depth information identifies a number of requests or amount of data in each of the queues of a processor chip that originated the heartbeat signal. The queue depth information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data. | 08-06-2009 |
| 20090198958 | System and Method for Performing Dynamic Request Routing Based on Broadcast Source Request Information - A system and method for performing dynamic request routing based on broadcast source request information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information identifies the number of active source requests sent by the processor chip that originated the heartbeat signal. The source request information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data. | 08-06-2009 |
| 20090235048 | INFORMATION PROCESSING APPARATUS, SIGNAL TRANSMISSION METHOD, AND BRIDGE - Introduced is an end-point bridge that relays an end point—formed by an external bus in a device tree managed by a first processor unit and an end point formed by an external bus in a device tree managed by a second processor unit. A conversion unit in the end-point bridge replaces a requestor ID contained in an access request packet, for example, which has reached the end point, to the ID of the end point from the ID of a host bridge. The ID of the host bridge is stored in a memory in a manner that the ID of the host bridge is associated with a tag of the packet, and is used to return the requestor ID when a response packet to the request reaches the end point. | 09-17-2009 |
| 20090249030 | Multiprocessor System Having Direct Transfer Function for Program Status Information in Multilink Architecture - A multiprocessor system can directly transmit storage-state information in a multilink architecture. The multiprocessor system includes a first processor; a multiport semiconductor memory device coupled to the first processor; a nonvolatile semiconductor memory device; and a second processor coupled with the multiport semiconductor memory device and the nonvolatile semiconductor memory device in a multilink architecture, storing data, having been written in a shared memory area of the multiport semiconductor memory device by the first processor, in the nonvolatile semiconductor memory device, and directly transmitting storage-state information on whether the storing of the data in the nonvolatile semiconductor memory device has been completed, in response to a request of the first processor, without passing it through the multiport semiconductor memory device. Accordingly a processor indirectly coupled to a nonvolatile memory can directly check a program completion state for write data and thus enhancing a data storage performance of the system. | 10-01-2009 |
| 20090282214 | Network On Chip With Low Latency, High Bandwidth Application Messaging Interconnects That Abstract Hardware Inter-Thread Data Communications Into An Architected State of A Processor - Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, each of a plurality of the IP blocks including at least one computer processor, each such computer processor implementing a plurality of hardware threads of execution; low latency, high bandwidth application messaging interconnects; memory communications controllers; network interface controllers; and routers; each of the IP blocks adapted to a router through a separate one of the low latency, high bandwidth application messaging interconnects, a separate one of the memory communications controllers, and a separate one of the network interface controllers; each application messaging interconnect abstracting into an architected state of each processor, for manipulation by computer programs executing on the processor, hardware inter-thread communications among the hardware threads of execution; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers. | 11-12-2009 |
| 20090282215 | MULTI-PROCESSOR SYSTEM AND MULTI-PROCESSING METHOD IN MULTI-PROCESSOR SYSTEM - Provided are a multi-processor system and a multi-processing method in the multi-processor system. The multi-processor system comprises a plurality of processors each including a data core and a processing core; and switches connecting the data core to the processing core in each of the processors as a combination of a data core-processing core pair. Therefore, the multi-processor system may be useful to remove any overhead for communications and make programming easy and simple. | 11-12-2009 |
| 20100005273 | METHOD FOR SELECTING NODE IN NETWORK SYSTEM AND SYSTEM THEREOF - The present invention relates to a method for selecting a node in a network system and a system thereof. The method performs a writing operation on a majority of the nodes included in at least one cell selected by dividing a network area including a plurality of nodes existing on a large-capacity cluster into a plurality of cells and performs a reading work on the majority of the nodes included in the cells selected by selecting predetermined cells of the divided cells. The present invention minimizes the accessibility of the network by binding the adjacent nodes to form the cells and access to each cell and optimizes hierarchy for the network access by selecting the node for each cell, thereby making it possible to minimize the network access cost. | 01-07-2010 |
| 20100042809 | METHOD AND SYSTEM FOR IMPLEMENTING A STREAM PROCESSING COMPUTER ARCHITECTURE - A method for implementing a stream processing computer architecture includes creating a stream computer processing (SCP) system by forming a super node cluster of processors representing physical computation nodes (“nodes”), communicatively coupling the processors via a local interconnection means (“interconnect”), and communicatively coupling the cluster to an optical circuit switch (OCS), via optical external links (“links”). The OCS is communicatively coupled to another cluster of processors via the links. The method also includes generating a stream computation graph including kernels and data streams, and mapping the graph to the SCP system, which includes assigning the kernels to the clusters and respective nodes, assigning data stream traffic between the kernels to the interconnection when the data stream is between nodes in the same cluster, and assigning traffic between the kernels to the links when the data stream is between nodes in different clusters. The method also includes configuring the OCSs to provide connectivity between mapped clusters. | 02-18-2010 |
| 20100042810 | MULTIPROCESSOR METHOD AND SYSTEM USING STACKED PROCESSOR MODULES AND BOARD-TO-BOARD CONNECTORS - A multiprocessor system is provided, comprising a baseboard, for arranging peripheral equipments; and a plurality of processor modules, each equipped with a processor and a board-to-board connector; wherein the plurality of processor modules are stacked up, with board-to-board connectors being electrically connected between the processor modules and between the processor modules and the baseboard; the processors communicate with the peripheral equipments in accordance with a specific bus specification; and the operations of the plurality of processor modules are coordinated by routes provided between the processor modules and between the processor modules and the baseboard. | 02-18-2010 |
| 20100049942 | DRAGONFLY PROCESSOR INTERCONNECT NETWORK - A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection. | 02-25-2010 |
| 20100049943 | Programmable control pipeline architecture and pipeline processing system thereof - The present invention provides a control pipeline architecture and a pipeline processing system thereof, which is applicable to digital and analog integrated circuit (IC) design flow for convenient hardware implementation. In which, a closed loop control pipeline architecture includes a plurality of control units, and each of the control units connected in series connection with one another to form a closed loop architecture to link an output of one control unit to an input of one next control unit; and an open loop control pipeline architecture included a plurality of control units, each of the control units connected in series connection with one another to form an open loop architecture to link an output of one control unit to an input of one next control unit. | 02-25-2010 |
| 20100070739 | Multiprocessor system and control method thereof - A multiprocessor system according to an embodiment comprises a plurality of processors, an execution control unit to control processing by the plurality of processors and data transfer between the plurality of processors; and an internal data storage unit to store data dependence information indicating status of the data transfer. If control flow of processing by a processor is fixed after a preceding data transfer is registered for execution and another data transfer to a similar destination as the preceding data transfer is necessary, the execution control unit cancels the preceding data transfer based on the data dependence information. | 03-18-2010 |
| 20100077178 | Method and apparatus for extending processing time in one pipeline stage - A single channel or multi-channel system that requires the execution time of a pipeline stage to be extended to a time longer than the time interval between two consecutive input data. Each processor in the system has an input and output port connected to a “bypass switch” (or multiplexer). Input date is sent either to a processor, for processing, or to a processor output port, in which case no processing is performed, through a register using at least one clock cycle to move date from register input to register output. For a single channel requiring an execution time twice the time interval between two consecutive input data, two processors are interconnected by the bypass switch. Data flows from the first processor at the input of the system, through the bypass switches of the interconnected processors, to the output. The bypass switches are configures with respect to the processors such that the system data rate is independent of processor number. | 03-25-2010 |
| 20100095088 | RECONFIGURABLE ELEMENTS - A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells. | 04-15-2010 |
| 20100115236 | HIERARCHICAL SHARED SEMAPHORE REGISTERS - A multiprocessor computer system having a plurality of processing elements comprises one or more core-level hierarchical shared semaphore registers, wherein each core-level hierarchical shared semaphore register is coupled to a different processor core. Each hierarchical shared semaphore register is writable to each of a plurality of streams executing on the coupled processor core. One or more chip-level hierarchical shared semaphore registers are also coupled to plurality of processor cores, each chip-level hierarchical shared semaphore register writable to each of the plurality of processor cores. | 05-06-2010 |
| 20100131739 | INTEGRATED CIRCUIT HAVING DATA PROCESSING STAGES AND ELECTRONIC DEVICE INCLUDING THE INTEGRATED CIRCUIT - An integrated circuit ( | 05-27-2010 |
| 20100153684 | Modular Avionics System of an Aircraft - A modular avionics system includes several cabinets arranged at various locations in an aircraft and interconnected in a network. The cabinets are used for controlling or processing signals from and to sensors, actuators and other systems of the aircraft. The system includes parallel processors, for example transputers. The cabinets comprise at least two core processor modules (CPM | 06-17-2010 |
| 20100153685 | Multiprocessor system - The invention relates to a multiprocessor system on an electronic chip ( | 06-17-2010 |
| 20100161939 | PARALLEL PROCESSING METHOD AND SYSTEM, FOR INSTANCE FOR SUPPORTING EMBEDDED CLUSTER PLATFORMS, COMPUTER PROGRAM PRODUCT THEREFOR - A multi-processing system-on-chip including a cluster of processors having respective CPUs is operated by: defining a master CPU within the respective CPUs to coordinate operation of said multi-processing system, running on the CPU a cluster manager agent. The cluster manager agent is adapted to dynamically migrate software processes between the CPUs of said plurality and change power settings therein. | 06-24-2010 |
| 20100161940 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. | 06-24-2010 |
| 20100217955 | ROUTING ACROSS MULTICORE NETWORKS USING REAL WORLD OR MODELED DATA - The present disclosure relates to a system for routing data across a multicore processing network. The system includes a multicore processing array having a plurality of processing cores, a memory for storing data relating to an object being modeled, the data being associated with coordinate information relating to the object within a coordinate system, and a controller for routing the data from the memory to one or more of the plurality of processing cores of the multicore processing array based on the coordinate information associated with the data. The present disclosure also relates to a method for routing data across a multicore processing network and a computer accessible medium having stored thereon computer executable instructions for performing a procedure for routing data across a multicore processing network. | 08-26-2010 |
| 20100235609 | RING-PATTERN BUS CONNECTED INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM - In an information apparatus including a plurality of processing circuits connected to a ring bus, when processing speeds (throughput) of processing circuits are different or an amount of data in the processing circuit is increased or decreased, deadlock can occur or the throughput can be decreased in the ring bus. In order to solve this problem, a stall state of other processing unit is detected from a packet acquired from the ring bus and a packet is restricted from being newly generated by the processing circuit nor transmitted therefrom when other processing unit is in the stall state. | 09-16-2010 |
| 20100241826 | DATA PROCESSING APPARATUS, DATA PROCESSING METHOD AND PROGRAM - A data processing apparatus can reduce an occupancy rate of a ring bus by suppressing occurrence of a stall packet, and can change a processing sequence. In the data processing apparatus, a buffer is provided in each communication unit connecting the ring bus and the associated processing unit. Transfer of data from the communication unit to the processing unit is controlled by an enable signal. Consequently, occurrence of a stall packet is suppressed. Accordingly, frequency of occurrence of a deadlock state is reduced by decreasing the occupancy rate of the ring bus. | 09-23-2010 |
| 20100268913 | LITHOGRAPHIC APPARATUS, CONTROL SYSTEM, MULTI-CORE PROCESSOR, AND A METHOD TO START TASKS ON A MULTI-CORE PROCESSOR - A multi-core processor includes two or more cores; an external communication facility that is shared by the cores and is capable of communicating with one of the cores at a time; and an internal communication facility capable of communicating simultaneously with each one of the cores; wherein the multi-core processor is configured to: receive a first signal via the external communication facility; relay the first signal to one of the cores; handle the first signal by the one of the cores, thereby generating a second signal; transmit substantially at the same time the second signal to each one of the cores by the internal communication facility; start a task on each one of the cores in response to the receiving of the second signal. | 10-21-2010 |
| 20100268914 | PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS AND DYNAMIC PATHWAY CREATION - A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements. | 10-21-2010 |
| 20100318767 | MULTIPLEXING AUXILIARY PROCESSING ELEMENT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A multiplexing auxiliary processing element (PE) performs a process that includes the operations of receiving signals of a plurality of upstream processing elements (PEs) including a plurality of pairs of PEs arranged on the input side; supplying the signals from the upstream PEs to a multiplex PE that is multiplexed and used so that the signals are subjected to a predetermined process by the multiplex PE; receiving the processed signals subjected to the predetermined process by the multiplex PE and sequentially supplying the signals to a plurality of downstream PEs arranged on the output side; and performing operations of the upstream PEs synchronously with the supply of the processed signals to the corresponding downstream PEs on the basis of setting of the multiplexing auxiliary PE. | 12-16-2010 |
| 20100325387 | ARITHMETIC PROCESSING APPARATUS, PROCESSING UNIT, ARITHMETIC PROCESSING SYSTEM, AND ARITHMETIC PROCESSING METHOD - An arithmetic processing apparatus includes: a plurality of processing units connected in series to each other, wherein each of the processing units includes a limitation information setting section in which limitation information, which indicates the amount of arithmetic processing that each of the processing units is to process for data of each arithmetic processing unit, is set; an arithmetic section which executes arithmetic processing on the data of each arithmetic processing unit, according to the limitation information set in the limitation information setting section, by the same program between the plurality of processing units; and a memory in which processing data subjected to the arithmetic processing by the arithmetic section is stored. | 12-23-2010 |
| 20100325388 | Multi-Core Parallel Processing System - A multiprocessor system on a chip (MPSoC) implements parallel processing and include a plurality of cores with inter-core communication. This communication is implemented by an on-chip switch fabric in communication with each core, or by shared memory in communication with each core. In another embodiment, a parallel processing system is implemented as a Howard Cascade and uses shared memory for implementing inter-chip communication. The parallel processing system includes a plurality of chips, each formed as an MPSoC, and implements communication between the chips using shared memory | 12-23-2010 |
| 20100332795 | COMPUTER SYSTEM INCLUDING RECONFIGURABLE ARITHMETIC DEVICE AND RECONFIGURABLE ARITHMETIC DEVICE - A computer system includes a central processing unit, a random-access-memory interface, a random-access memory in which addresses are allocated in an address space of the random-access-memory interface and a reconfigurable arithmetic device whose arithmetic function is capable of being dynamically changed in accordance with configuration data. The reconfigurable arithmetic device includes input terminals, output terminals, a plurality of processor elements that perform individual arithmetic processes in synchronization with a clock, an inter-processor-element network which connects the input terminals and the output terminals to input ports and output ports of the plurality of processor elements, a random-access memory built into the reconfigurable arithmetic device and a control unit that sets the plurality of processor elements and the inter-processor-element network. | 12-30-2010 |
| 20110010525 | On-chip and Chip-to-chip Routing Using a Processor Element/Router Combination - A system and method is shown for on-chip and chip-to-chip routing. The system and method includes a processor element residing on a processor die to process a data packet received at the processor die. The system and method also include a router residing on the process die to route the data packet received at the processor die. Further, the system and method includes a switch core residing on the processor die to switch a communication channel along which the data packet is to be transmitted. Additionally, the system and method includes a switch core to identify a destination processing element and router (PE/R) module for a data packet, the switch core and the destination PE/R module residing on a common processor die. Moreover, the system and method includes a communication channel to operatively connect the switch core and the destination PE/R module on the common processor die. | 01-13-2011 |
| 20110010526 | CONTROL APPARATUS FOR FAST INTER PROCESSING UNIT DATA EXCHANGE IN AN ARCHITECTURE WITH PROCESSING UNITS OF DIFFERENT BANDWIDTH CONNECTION TO A PIPELINED RING BUS - Nowadays, many architectures have processing units with different bandwidth requirements which are connected over a pipelined ring bus. The proposed invention can optimize the data transfer for the case where processing units with lower bandwidth requirements can be grouped and controlled together for a data transfer, so that the available bus bandwidth can be optimally utilized. | 01-13-2011 |
| 20110047352 | MEMORY COHERENCE DIRECTORY SUPPORTING REMOTELY SOURCED REQUESTS OF NODAL SCOPE - A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node. | 02-24-2011 |
| 20110047353 | RECONFIGURABLE DEVICE | 02-24-2011 |
| 20110055518 | SAFE AND SECURE MULTICORE SYSTEM - The different advantageous embodiments provide a system for partitioning a data processing system comprising a number of cores and a partitioning process. The partitioning process is configured to assign a number of partitions to the number of cores. Each partition in the number of partitions is assigned to a separate number of cores from the number of cores. | 03-03-2011 |
| 20110055519 | METHOD AND SYSTEM FOR IMPLEMENTING A STREAM PROCESSING COMPUTER ARCHITECTURE - A stream processing computer architecture includes creating a stream computer processing (SCP) system by forming a super node cluster of processors representing physical computation nodes (“nodes”), communicatively coupling the processors via a local interconnection means (“interconnect”), and communicatively coupling the cluster to an optical circuit switch (OCS), via optical external links (“links”). The OCS is communicatively coupled to another cluster of processors via the links. The method also includes generating a stream computation graph including kernels and data streams, and mapping the graph to the SCP system, which includes assigning the kernels to the clusters and respective nodes, assigning data stream traffic between the kernels to the interconnection when the data stream is between nodes in the same cluster, and assigning traffic between the kernels to the links when the data stream is between nodes in different clusters. | 03-03-2011 |
| 20110055520 | SYSTEMS, METHODS AND APPARATUS FOR LOCAL PROGRAMMING OF QUANTUM PROCESSOR ELEMENTS - Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices. | 03-03-2011 |
| 20110072239 | DATA MULTICASTING IN A DISTRIBUTED PROCESSOR SYSTEM - Methods, procedures, apparatuses, computer programs, computer-accessible mediums, processing arrangements and systems generally related to data multi-casting in a distributed processor architecture are described. Various implementations may include identifying a plurality of target instructions that are configured to receive a first message from a source; providing target routing instructions to the first message for each of the target instructions including selected information commonly shared by the target instructions; and, when two of the identified target instructions are located in different directions from one another relative to a router, replicating the first message and routing the replicated messages to each of the identified target instructions in the different directions. The providing target routing instructions may further comprise the selected information utilizing a subset of bits that is commonly shared by the target instructions and being identified as a left operand, right operand or predicate operand, and may include the selection of one of a plurality of multiple-instruction subsets of the target instructions. | 03-24-2011 |
| 20110161626 | ROUTING PACKETS IN ON-CHIP NETWORKS - Techniques for packet routing in an on-chip network are provided. In one embodiment, a method for routing packets in a multi-core processor including multiple cores connected by an on-chip network includes identifying ports that are incorrect while routing the packet. After receiving the packet at an input port, some of the ports are excluded from consideration while selecting the output port for the packet. The output port is selected from the remaining ports and the packet is routed to the selected output port. | 06-30-2011 |
| 20110173415 | MULTI-CORE SYSTEM AND DATA TRANSFER METHOD - According to one embodiment, each of routers includes: a cache mechanism that stores data transferred to the other routers or processor elements; and a unit that reads out, when an access generated from each of the processor elements is transferred thereto, if target data of the access is stored in the cache mechanism, the data from the cache mechanism and transmits the data to the processor element as a request source. | 07-14-2011 |
| 20110173416 | DATA PROCESSING DEVICE AND PARALLEL PROCESSING UNIT - A data processing device in which parallel processing elements can efficiently perform processing is provided. A parallel processing module includes plural processing elements, banks A and B provided to correspond to the processing elements and used to store data to be used when the processing elements perform processing, and an I/O bank provided to correspond to the processing elements and used to transfer data to and from an external memory. A first selector circuit selectively couples bank B or the I/O bank to the processing elements. A second selector circuit selectively couples the external memory or the processing elements to the I/O bank. Thus, data can be transferred from the external memory to the I/O bank concurrently with the processing performed by the processing elements. The processing elements can therefore perform processing efficiently. | 07-14-2011 |
| 20110185152 | RECONFIGURABLE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction. | 07-28-2011 |
| 20110197047 | METHOD FOR FORMING A PARALLEL PROCESSING SYSTEM - A definition file included in the present invention includes a plurality of parallel descriptions that respectively define a plurality of parallel processes performed independently. The plurality of parallel descriptions include a first parallel description showing a first parallel process with a plurality of data inputs including at least one data input into which output data of another parallel process is inputted, with data with the same latency from input in a parallel processing system are inputted into the plurality of data inputs. A forming method includes a first step of generating, based on a hardware library in which information on a plurality of types of elements is stored, hardware configuration information including circuit configurations for executing the parallel processes that include at least one of the plurality of types of elements; and a second step of adding a delay element to the hardware configuration information so that data with a same latency from input into the parallel processing system are inputted into the plurality of data inputs of the circuit configuration for executing the first parallel process, and therefore the hardware configuration information is generated by this method. | 08-11-2011 |
| 20110213949 | METHODS AND APPARATUS FOR OPTIMIZING CONCURRENCY IN MULTIPLE CORE SYSTEMS - Various methods and apparatus are described for communicating transactions between one or more initiator IP cores and one or more target IP cores coupled to an interconnect. Tag logic may be located within the interconnect, such as located in an agent, and configured to assign different interconnect tag identification numbers to two or more transactions from a same thread. The tag logic assigns different interconnect tag identification numbers to allow the two or more transactions from the same thread to be outstanding over the interconnect to two or more different target IP cores at the same time, allow the two or more transactions from the same thread to be processed in parallel over the interconnect, and potentially serviced out of issue order while being returned back to the multiple threaded initiator IP core realigned in expected execution order. | 09-01-2011 |
| 20110246746 | APPARATUSES ENABLING CONCURRENT COMMUNICATION BETWEEN AN INTERFACE DIE AND A PLURALITY OF DICE STACKS, INTERLEAVED CONDUCTIVE PATHS IN STACKED DEVICES, AND METHODS FOR FORMING AND OPERATING THE SAME - Various embodiments include apparatuses, stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths. | 10-06-2011 |
| 20110246747 | RECONFIGURABLE CIRCUIT USING VALID SIGNALS AND METHOD OF OPERATING RECONFIGURABLE CIRCUIT - A reconfigurable circuit includes a data execution unit including a plurality of execution elements, each of which performs execution with respect to plural data upon the plural data being all in a valid state, and holds valid-state output data indicative of a result of the execution at an output node while all the plural data are in the valid state, a data selecting unit configured to connect between the execution elements in a reconfigurable manner, and a data input unit configured to supply input data to a series of execution elements to perform a series of executions, wherein a valid or invalid state of given data is specified by a valid signal accompanying and forming a pair with the given data, and the input data supplied from the data input unit to the data execution unit are fixed to valid-state constant data while the series of executions are performed. | 10-06-2011 |
| 20110271078 | PROCESSOR STRUCTURE OF INTEGRATED CIRCUIT - A processor structure of integrated circuit is provided. The processor structure comprises at least one processor capable of configuring an operation component and at least one processor capable of configuring a storage component. The processor capable of configuring an operation component or the processor capable of configuring a storage component cascades the processor capable of configuring an operation component and the processor capable of configuring a storage component. The processor capable of configuring an operation component includes a first arithmetic data control component and at least one operation component, and the first arithmetic data control component executes a configuration instruction to configure the operation function of the operation component. The processor capable of configuring a storage component includes a second arithmetic data control component and at least one memory component, and the second arithmetic data control component executes a configuration instruction to configure the storage function of the memory component. | 11-03-2011 |
| 20110296138 | FAST REMOTE COMMUNICATION AND COMPUTATION BETWEEN PROCESSORS - A method, system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute. | 12-01-2011 |
| 20120017068 | PROCESSORS - A processing system comprises a plurality of processors ( | 01-19-2012 |
| 20120030448 | SINGLE INSTRUCTION MULTIPLE DATE (SIMD) PROCESSOR HAVING A PLURALITY OF PROCESSING ELEMENTS INTERCONNECTED BY A RING BUS - A single instruction multiple data (SIMD) processor having a plurality of processing elements and including: a splitting unit for splitting an address of the read-only parameter data in the data memory into a first part and a second part at a bit position corresponding to the number of the processor elements; and a comparing unit for comparing the number of shifting, on a ring bus, of the read-only parameter data, which is taken from the internal memory at the address in accordance with the first part, with a difference between an own processor element position and a portion of the global address of the read-only parameter data to be accessed, the portion designating a position in the ring of the processor element in which the read-only parameter data to be accessed is stored and corresponding to the second part, to cause the other processor elements to take the read-only parameter data. | 02-02-2012 |
| 20120110303 | Method for Process Synchronization of Embedded Applications in Multi-Core Systems - A system and method for process synchronization in a multi-core computer system. A separate non-caching memory enables a method to synchronize processes executing on multiple processor cores. Since only a very small amount (a few number of bytes), is needed for the synchronization, it is possible to extend the method for inter-processor core message passing by allocating dedicated address space of the on-chip memory for each processor with exclusive write access. Each of the multiple processor cores maintains a dedicated cache while maintaining coherency with the non-cache shared memory. | 05-03-2012 |
| 20120110304 | PIPELINED SERIAL RING BUS - The present invention provides embodiments of an apparatus used to implement a pipelined serial ring bus. One embodiment of the apparatus includes one or more ring buses configured to communicatively couple registers associated with logical elements in a processor. The ring bus(s) are configured to concurrently convey information associated with a plurality of load or store operations. | 05-03-2012 |
| 20120144156 | METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING APPARATUS - A method for controlling an information processing apparatus including a processor which operates an operating system and a kernel which is operated independently of the operating system, and a network interface through which the information processing apparatus is connectable to an other information processing apparatus, the method includes notifying, by the operating system, the kernel of system down information about the operating system, determining, by the kernel, a kind of an Internet protocol included in a packet received from the other information processing apparatus connected through the network interface, creating, by the kernel, a packet for notifying of the system down in accordance with the determined kind of the Internet protocol, and transmitting, by the kernel, the created packet to the other information processing apparatus via the network interface. | 06-07-2012 |
| 20120191946 | FAST REMOTE COMMUNICATION AND COMPUTATION BETWEEN PROCESSORS - A method for fast remote communication and computation between processors is provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute. | 07-26-2012 |
| 20120221831 | Accessing Common Registers In A Multi-Core Processor - Systems and methods for accessing common registers in a multi-core processor are disclosed. In an exemplary embodiment a method may comprise streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain. The method may also comprise reassembling the at least one streamed transaction in the register domain for data access operations at the common registers. | 08-30-2012 |
| 20120239905 | MULTI-CORE DISTRIBUTED PROCESSING FOR MACHINE VISION APPLICATIONS - Embodiments of an apparatus including a first processor core having a local agent running thereon, the agent comprising a local process and a proxy agent and a second processor core having a remote agent running thereon, the remote agent being an instance of the local agent. A shared memory wherein coupled to the first processor core and the second processor core, wherein the local agent and the remote agent communicate via the shared memory. Other embodiments are disclosed and claimed. | 09-20-2012 |
| 20120254586 | QUANTUM AND DIGITAL PROCESSOR HYBRID SYSTEMS AND METHODS TO SOLVE PROBLEMS - Quantum processors and classical computers are employed together to solve computational problems. The classical computer may include a parameter learning module that produces a set of parameters. The quantum processor may be configured with the set of parameters to define a problem Hamiltonian and operated to perform adiabatic quantum computation and/or quantum annealing on the problem Hamiltonian to return a first solution to the problem. The parameter learning module of the classical computer may then be used to revise the set of parameters by performing a classical optimization, such as a classical heuristic optimization. The quantum processor may then be programmed with the revised set of parameters to return a revised solution to the problem. The quantum processor may include a superconducting quantum processor implementing superconducting flux qubits. | 10-04-2012 |
| 20120260063 | MODULAR, DETACHABLE COMPUTE LEAF FOR USE WITH COMPUTING SYSTEM - A detachable, logic leaf module having dendritic projections on a surface is connected to a recessed area on the surface of a cluster interface board. The projections are used for electrically connecting the logic module device to the cluster interface board or the like, the projections on the surface of the logic leaf being flexibly and conductively wired to the receiving area on the surface of the cluster interface board. The logic leaf connector is removable without the need for solder softening thermal cycles or special tools, and permits the simple removal or replacement of an individual leaf at any time. | 10-11-2012 |
| 20120290814 | COMMUNICATION BETWEEN INTERNAL AND EXTERNAL PROCESSORS - Systems, methods of operating a memory device, and methods of arbitrating access to a memory array in a memory device having an internal processor are provided. In one or more embodiments, conflicts in accessing the memory array are reduced by interfacing an external processor, such as a memory controller, with the internal processor, which could be an embedded ALU, through a control interface. The external processor can control access to the memory array, and the internal processor can send signals to the external processor to request access to the memory array. The signals may also request a particular bank in the memory array. In different embodiments, the external processor and the internal processor communicate via the control interface or a standard memory interface to grant access to the memory array, or to a particular bank in the memory array, for example. | 11-15-2012 |
| 20120317396 | COMPUTERS AND MICROCHIPS WITH A PORTION PROTECTED BY AN INTERNAL HARDWARE FIREWALLS - This invention generally relates to one or more computer networks having computers like personal computers or network servers with microprocessors linked by broadband transmission means and having hardware, software, firmware, and other means such that at least one parallel processing operation occurs that involve at least two computers in the network | 12-13-2012 |
| 20120317397 | APPARATUS, METHOD, SYSTEM AND EXECUTABLE MODULE FOR CONFIGURATION AND OPERATION OF ADAPTIVE INTEGRATED CIRCUITRY HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes. | 12-13-2012 |
| 20120331269 | Geodesic Massively Parallel Computer. - Communication latency, now a dominant factor in computer performance, makes physical size, density, and interconnect proximity crucial system design considerations. The present invention addresses consequential supercomputing hardware challenges: spatial packing, communication topology, and thermal management. A massively-parallel computer with dense, spherically framed, geodesic processor arrangement is described. As a mimic of the problem domain, it is particularly apt for climate modelling. However, the invention's methods scale well, are largely independent of processor technology, and apply to a wide range of computing tasks. The computer's interconnect features globally short, highly regular, and tightly matched distances. Communication modes supported include neighbour-to-neighbour messaging on a spherical-shell lattice, and a radial network for system-synchronous clocking, broadcast, packet-switched networking, and IO. A near-isothermal cooling system, physically divorcing heat source and sink, enables extraordinarily compact geodes with lower temperature operation, higher speed, and lower power consumption. | 12-27-2012 |
| 20130007411 | Configurable Allocation of Hardware Resources - Disclosed are various embodiments of configurable allocation of hardware resources. In one embodiment, a processing device includes a configurable communication grid including a plurality of crossbars interconnected by intercommunication paths in a geometric configuration and a plurality of pipeline elements distributed within the configurable communication grid. Each crossbar is designed to direct communications received at an input to a selected output. Each pipeline element is communicatively coupled to an output of a first crossbar adjacent to the pipeline element and an input of a second crossbar adjacent to the pipeline element. In another embodiment, a process matrix includes a plurality of pipeline elements interconnected by a configurable communication grid. The configurable communication grid includes intercommunication paths connecting crossbars in a geometric configuration. The crossbars are configured to implement at least a portion of a hardware pipeline by directing communications between at least a portion of the pipeline elements. | 01-03-2013 |
| 20130024657 | RECONFIGURABLE SEQUENCER STRUCTURE - A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means. | 01-24-2013 |
| 20130054938 | EFFICIENT PIPELINE PARALLELISM USING FRAME SHARED MEMORY - A systems and methods are disclosed that provide an efficient parallel pipeline for data processing using a multi-core processor. Embodiments allocate a shared memory portion of the memory that is accessible from more than one context of execution and/or process a frame in a plurality of processing stages processed by a context of execution. In some embodiments, each of the plurality of processing stages may be bound to a processing core of the multi-core processor. In other embodiments include one or more processing stages with a point-to-point communication mechanism that operates in shared memory. | 02-28-2013 |
| 20130067197 | COMPUTER SUBSYSTEM AND COMPUTER SYSTEM - The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units CPUs and one node controller NC, where any two CPUs in each basic node are interconnected, each CPU in each basic node is connected to the NC in the basic node, the NC in each basic node has a routing function, any two NCs in the M basic nodes are interconnected, and a connection between the L composite nodes formed through a connection between NCs enable communication between any two NCs to require at most three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system. | 03-14-2013 |
| 20130103926 | ESTABLISHING A DATA COMMUNICATIONS CONNECTION BETWEEN A LIGHTWEIGHT KERNEL IN A COMPUTE NODE OF A PARALLEL COMPUTER AND AN INPUT-OUTPUT ('I/O') NODE OF THE PARALLEL COMPUTER - Establishing a data communications connection between a lightweight kernel in a compute node of a parallel computer and an input-output (‘I/O’) node of the parallel computer, including: configuring the compute node with the network address and port value for data communications with the I/O node; establishing a queue pair on the compute node, the queue pair identified by a queue pair number (‘QPN’); receiving, in the I/O node on the parallel computer from the lightweight kernel, a connection request message; establishing by the I/O node on the I/O node a queue pair identified by a QPN for communications with the compute node; and establishing by the I/O node the requested connection by sending to the lightweight kernel a connection reply message. | 04-25-2013 |
| 20130111189 | Circuit Arrangement for a Data Processing System and Method for Data Processing | 05-02-2013 |
| 20130124825 | APPARATUS AND METHOD FOR REDUCING OVERHEAD CAUSED BY COMMUNICATION BETWEEN CLUSTERS - A technique for minimizing overhead caused by copying or moving a value from one cluster to another cluster is provided. A number of operations, for example, a mov operation for moving or copying a value from one cluster to another cluster and a normal operation may be executed concurrently. Accordingly, access to a register file outside of the cluster may be reduced and the performance of code may be improved. | 05-16-2013 |
| 20130138919 | HIERARCHICAL MULTI-CORE PROCESSOR AND METHOD OF PROGRAMMING FOR EFFICIENT DATA PROCESSING - A multi-core processor includes a tree-like structure having a plurality of computing cores arranged in hierarchical levels, the cores all having the same logical architecture. Each core can include computing, interconnecting, and/or storage elements. The functionality of an individual element can be supplied by an entire core in a lower level. A method for programming the processor includes hierarchically decomposing an application into interconnected sub-functions, mapping the sub-functions onto groups of cores at appropriate levels of the processor, and interconnecting the mapped sub-functions so as to hierarchically compose the complete application. Sub-functions can be sequential, concurrent, and/or pipelined. Interconnections can be static or dynamically switchable under program control. Interconnect elements can also be used to implement flow control as needed in pipelined operations to maintain data coherency. The decomposing and mapping process can be iterated on sub-functions so as to optimize load balancing, software performance, and hardware efficiency. | 05-30-2013 |
| 20130151812 | NODE INTERCONNECT ARCHITECTURE TO IMPLEMENT HIGH-PERFORMANCE SUPERCOMPUTER - Node Interconnect architectures to implement a high performance supercomputer are provided. For example, a node interconnect architecture for connecting a multitude of nodes (or processors) of a supercomputer is implemented using an all-to-all electrical and optical connection network which provides two independent communication paths between any two processors of the supercomputer, wherein a communication path includes at most two electrical links and one optical link. | 06-13-2013 |
| 20130151813 | SWITCH SYSTEM FOR DUAL CENTRAL PROCESSING UNITS - An exemplary switch system includes a first central processing unit (CPU), a second CPU, a first switch unit, a second switch unit, and a microcontroller. The first CPU provides an identification signal to the first switch unit and the second switch unit when the first CPU is associated with a motherboard of an electronic device. Both the first switch unit and the second switch unit selectably and electronically connect to the first CPU or the second CPU according to whether or not both the first switch unit and the second switch unit detect the identification signal. The microcontroller is electronically connected between the first switch unit and the second switch unit, and accordingly communicates with the first CPU or the second CPU via the first switch unit and the second switch unit. | 06-13-2013 |
| 20130159669 | LOW LATENCY VARIABLE TRANSFER NETWORK FOR FINE GRAINED PARALLELISM OF VIRTUAL THREADS ACROSS MULTIPLE HARDWARE THREADS - A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core. | 06-20-2013 |
| 20130198488 | INTERCONNECTION NETWORK CONNECTING OPERATION-CONFIGURABLE NODES ACCORDING TO ONE OR MORE LEVELS OF ADJACENCY IN MULTIPLE DIMENSIONS OF COMMUNICATION IN A MULTI-PROCESSOR AND A NEURAL PROCESSOR - A Wings array system for communicating between nodes using store and load instructions is described. Couplings between nodes are made according to a 1 to N adjacency of connections in each dimension of a G×H matrix of nodes, where G≧N and H≧N and N is a positive odd integer. Also, a 3D Wings neural network processor is described as a 3D G×H×K network of neurons, each neuron with an N×N×N array of synaptic weight values stored in coupled memory nodes, where G≧N, H≧N, K≧N, and N is determined from a 1 to N adjacency of connections used in the G×H×K network. Further, a hexagonal processor array is organized according to an INFORM coordinate system having axes at 60 degree spacing. Nodes communicate on row paths parallel to an FM dimension of communication, column paths parallel to an IO dimension of communication, and diagonal paths parallel to an NR dimension of communication. | 08-01-2013 |
| 20130283008 | 3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS FOR MULTIMODAL OPERATION OF SAME - Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image. | 10-24-2013 |
| 20130339663 | RESET OF PROCESSING CORE IN MULTI-CORE PROCESSING SYSTEM - This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core processor. An initialization core may include reset logic that may detect a problematic core or core that is unresponsive or otherwise not operating properly. The initialization core may generate a packet that enables communication with the problematic core. The initialization core may send a reset packet to the problematic core to instruct the problematic core to perform a reset. | 12-19-2013 |
| 20140047212 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has processor elements each of which divides data that is contiguous in one direction into multiple data groups and processes them, a processor element control unit that issues a data shift instruction, and a data transfer network that performs data transfer between adjacent processor elements. The processor elements each have a data storage unit that stores one of the multiple data groups, a data selector that outputs transfer data obtained by selecting either of head data or end data of one data group according to a data shift instruction into a data transfer network, a data shifter that shifts a position at which the data group is stored to the right or to the left according to the data shift instruction, and a data connector that connects the data group which is shifted and the transfer data obtained through the data transfer network. | 02-13-2014 |
| 20140115298 | ASYMMETRIC MESH NoC TOPOLOGIES - A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links. | 04-24-2014 |
| 20140122833 | SERVER ON A CHIP AND NODE CARDS COMPRISING ONE OR MORE OF SAME - A server on a chip that can be a component of a node card. The server on a chip can include a node central processing unit subsystem, a peripheral subsystem, a system interconnect subsystem, and a management subsystem. The central processing unit subsystem can include a plurality of processing cores each running an independent instance of an operating system. The peripheral subsystem includes a plurality of interfaces for various configurations of storage media. The system interconnect subsystem provides for intra-node and inter-node packet connectivity. The management subsystem provides for various system and power management functionalities within the subsystems of the server on a chip. | 05-01-2014 |
| 20140149715 | SCALABLE AND PROGRAMMABLE COMPUTER SYSTEMS - Efficient, scalable, programmable, and reliable computing systems, built from a homogeneous set of relatively humble processors arranged logically or physically into a Recurrent Multi-Stage Interconnection Network (RMIN) is provided. The RMIN may include a plurality of layers, where each of the plurality of layers includes a plurality of nodes. The RMIN may also include a plurality of links configured to connect each of the plurality of layers, and a plurality of recurrent links configured to connect a plurality of nodes in a last layer of the plurality of layers to plurality nodes in a first layer of the plurality of layers. The plurality of links, together with the plurality of recurrent links, may be configured to allow data originating in any layer of the plurality of layers to pass through each of the plurality of layers without interruption. | 05-29-2014 |
| 20140156970 | Versatile PET Coincidence Processor - A common or single type of positron emission tomography (PET) coincidence processor is useable with different PET systems. The ports are configurable to operate with different coincidence algorithms, allowing different numbers of ports to be used in different systems. The ports are configurable to provide different outputs and/or connect with different types of detectors. A programming port allows programming of an appropriate coincidence algorithm so that different such algorithms are usable by the controller. Any one or more of these accessible and/or versatile features are provided on a controller. | 06-05-2014 |
| 20140173247 | PROCESSING APPARATUS AND METHOD OF SYNCHRONIZING A FIRST PROCESSING UNIT AND A SECOND PROCESSING UNIT - A processing apparatus, comprising at least a first processing unit and a second processing unit, is proposed. The first processing unit comprises a set of first stateful elements, the second processing unit comprises a set of second stateful elements. A set of synchronization data lines may connect the first stateful elements to the second stateful elements in a pairwise manner. A control unit may control the first processing unit, the second processing unit and the synchronization data lines so as to copy the states of the first stateful elements in parallel via the synchronization data lines to the second stateful elements in response to a synchronization request. A method of synchronizing the processing units is also proposed. | 06-19-2014 |
| 20140181469 | METHODS AND APPARATUS FOR REDUCING POWER CONSUMPTION WITHIN EMBEDDED SYSTEMS - Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption. | 06-26-2014 |
| 20140189297 | HETERGENEOUS PROCESSOR APPARATUS AND METHOD - A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software. | 07-03-2014 |
| 20140195780 | FORWARDING CONDITION INFORMATION FROM FIRST PROCESSING CIRCUITRY TO SECOND PROCESSING CIRCUITRY - A data processing apparatus comprises first and second processing circuitry. A conditional instruction executed by the second processing circuitry may have an outcome which is dependent on one of a plurality of sets of condition information maintained by the first processing circuitry. A first forwarding path can forward the sets of condition information from the first processing circuitry to a predetermined pipeline stage of a processing pipeline of the second processing circuitry. A request path can transmit a request signal from the second processing circuitry to the first processing circuitry, the request signal indicating a requested set of condition information which was not yet valid when a conditional instruction was at the predetermined pipeline stage. A second forwarding path may forward the requested set of condition information to a subsequent pipeline stage when the information becomes valid. | 07-10-2014 |
| 20140244973 | RECONFIGURABLE ELEMENTS - The present invention provides for a multiprocessor device on either a chip or a stack of chips. The multiprocessor device includes a plurality of processing entities and a memory system. The multiprocessor device further includes at least one interface unit to at least one of an external memory and one or more peripherals. The multiprocessor device includes a bus system interconnecting the processing entities, the memory system and the at least one interface unit. Wherein, the memory system includes a plurality of cache segments, and the plurality of segments are located on a plurality of memory cores, each having a connection to the bus system. | 08-28-2014 |
| 20140281377 | Identifying Logical Planes Formed Of Compute Nodes Of A Subcommunicator In A Parallel Computer - In a parallel computer, a plurality of logical planes formed of compute nodes of a subcommunicator may be identified by: for each compute node of the subcommunicator and for a number of dimensions beginning with a first dimension: establishing, by a plane building node, in a positive direction of the first dimension, all logical planes that include the plane building node and compute nodes of the subcommunicator in a positive direction of a second dimension, where the second dimension is orthogonal to the first dimension; and establishing, by the plane building node, in a negative direction of the first dimension, all logical planes that include the plane building node and compute nodes of the subcommunicator in the positive direction of the second dimension. | 09-18-2014 |
| 20140281378 | THREE-DIMENSIONAL COMPUTER PROCESSOR SYSTEMS HAVING MULTIPLE LOCAL POWER AND COOLING LAYERS AND A GLOBAL INTERCONNECTION STRUCTURE - A computer processor system includes a plurality of multi-chip systems that are physically aggregated and conjoined. Each multi-chip system includes a plurality of chips that are conjoined together, and a local interconnection and input/output wiring layer. A global interconnection network is connected to the local interconnection and input/output wiring layer of each multi-chip system to interconnect the multi-chip systems together. One or more of the multi-chip systems includes a plurality of processor chips that are conjoined together. | 09-18-2014 |
| 20140281379 | Hybrid Programmable Many-Core Device with On-Chip Interconnect - The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner. | 09-18-2014 |
| 20140317379 | INFORMATION PROCESSING SYSTEM, CONTROL APPARATUS, AND METHOD OF CONTROLLING INFORMATION PROCESSING SYSTEM - A parallel computer includes a plurality of processors connected through transmission paths to each other. A job management server determines a communication path passing transmission paths connecting a certain number of processors in accordance with jobs to be input among the processors, and inputs the jobs to the certain number of processors connected through the determined communication path. A link control server controls transmission/reception circuits of the processors connected through transmission paths not included in the communication path among the transmission paths connecting the processors. | 10-23-2014 |
| 20140325180 | ELECTRONIC SYSTEM, CENTRAL PROCESSING UNIT EXPANSION APPARATUS, PORTABLE ELECTRONIC APPARATUS AND PROCESSING METHOD - An electronic system includes a central processing unit (CPU) expansion apparatus and a portable electronic apparatus. The CPU expansion apparatus has a first CPU connector and a first CPU. The portable electronic apparatus has a second CPU connector and a second CPU. When the first CPU connector is connected to the second CPU connector, a data transmission is implemented between the first CPU and the second CPU. A CPU expansion apparatus, portable electronic apparatus and processing method are also disclosed. With the electronic system, CPU expansion apparatus, portable electronic apparatus and processing method according to the invention, the portable electronic apparatus can be connected to an additional CPU externally and is thereby improved in efficiency of processing and computing. | 10-30-2014 |
| 20140325181 | HIERARCHICAL RECONFIGURABLE COMPUTER ARCHITECTURE - A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output. | 10-30-2014 |
| 20140331027 | ASYMMETRIC MESH NOC TOPOLOGIES - A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links | 11-06-2014 |
| 20140337602 | Execution Of An Instruction For Performing a Configuration Virtual Topology Change - In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU. | 11-13-2014 |
| 20140337603 | SEMICONDUCTOR DEVICE - An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate. | 11-13-2014 |
| 20150026432 | DYNAMIC FORMATION OF SYMMETRIC MULTI-PROCESSOR (SMP) DOMAINS - Symmetric multi-processor (SMP) nodes are dynamically configured via SMP sockets that use SMP optically-connected switches to dynamically connect SMP optically-connected links connected to the SMP nodes to form SMP domains based on best matched expected workloads for coherent traffic for exchanging SMP coherent information. The SMP nodes are dynamically added to one of the SMP domains and/or dynamically removed from one of the SMP domains. | 01-22-2015 |
| 20150026433 | ALLOCATION METHOD, APPARATUS, AND PROGRAM FOR ARCHITECTURAL REGISTER - An allocation system and a method for allocating an architectural register in a system having one or more mapping tables. When the allocation system detects a plurality of available architectural registers to an allocation target virtual register, it identifies adjacent instructions to all instructions having the allocation target virtual register in its destination operand, counts the number of uses of the architectural register appearing in the destination operand for each architectural register, summing the number of uses for each architectural register for each entry group in one or more mapping tables having the same assignment rule for correlations with the architectural registers, calculating the total of the numbers of uses of entries for each entry group, and allocating the architectural register to the allocation target virtual register such that the total of the numbers of uses of entries for each entry group approaches uniformity. | 01-22-2015 |
| 20150046677 | APPARATUS, SYSTEMS, AND METHODS FOR PROVIDING COMPUTATIONAL IMAGING PIPELINE - The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect. | 02-12-2015 |
| 20150046678 | APPARATUS, SYSTEMS, AND METHODS FOR PROVIDING CONFIGURABLE COMPUTATIONAL IMAGING PIPELINE - The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect. | 02-12-2015 |
| 20150143082 | Dynamically Erectable Computer System - A fault-tolerant computer system architecture includes two types of operating domains: a conventional first domain (DID) that processes data and instructions, and a novel second domain which includes mentor processors for mentoring the DID according to “meta information” which includes but is not limited to data, algorithms and protective rule sets. The term “mentoring” (as defined herein below) refers to, among other things, applying and using meta information to enforce rule sets and/or dynamically erecting abstractions and virtualizations by which resources in the DID are shuffled around for, inter alia, efficiency and fault correction. Meta Mentor processors create systems and sub-systems by means of fault tolerant mentor switches that route signals to and from hardware and software entities. The systems and sub-systems created are distinct sub-architectures and unique configurations that may be operated as separately or concurrently as defined by the executing processes. | 05-21-2015 |
| 20150339256 | INTER-PROCESSOR SYNCHRONIZATION SYSTEM - An inter-processor synchronization method using point-to-point links, comprises the steps of defining a point-to-point synchronization channel between a source processor and a target processor; executing in the source processor a wait command expecting a notification associated with the synchronization channel, wherein the wait command is designed to stop the source processor until the notification is received; executing in the target processor a notification command designed to transmit through the point-to-point link the notification expected by the source processor; executing in the target processor a wait command expecting a notification associated with the synchronization channel, wherein the wait command is designed to stop the target processor until the notification is received; and executing in the source processor a notification command designed to transmit through the point-to-point link the notification expected by the target processor. | 11-26-2015 |
