| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 712014000 | Processing element memory | 7 |
| 20080282060 | ACTIVE MEMORY COMMAND ENGINE AND METHOD - A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored. | 11-13-2008 |
| 20100199068 | RECONFIGURABLE PROCESSOR FOR REDUCED POWER CONSUMPTION AND METHOD THEREOF - Described herein is a reconfigurable processor which uses a distributed configuration memory structure and an operation method thereof in which power consumption is reduced. A processing unit which configures the reconfigurable processor includes a functional unit, a distributed configuration memory, a no-operation (NOP) register, and a controller. The NOP register stores information which represents whether or not a NOP operation is performed at each clock cycle. The controller controls to deactivate the distributed configuration memory at a clock cycle at which a NOP operation is performed. | 08-05-2010 |
| 20140237214 | APPARATUS AND METHOD OF A CONCURRENT DATA TRANSFER OF MULTIPLE REGIONS OF INTEREST (ROI) IN AN SIMD PROCESSOR SYSTEM - This present invention provides a fast data transfer for a concurrent transfer of multiple ROI areas between an internal memory array and a single memory where each PE can specify the parameter set for the area to be transferred independently from the other PE. For example, for a read transfer, the requests are generated in a way that first the first element of each ROI area is requested from the single memory for each PE before the following elements of each ROI area are requested. After the first element from each ROI area has been received from the single memory in a control processor and has been transferred from the control processor over a bus system to the internal memory array, all elements are in parallel stored to the internal memory array. Then, the second element of each ROI area is requested from the single memory for each PE. The transfer finishes after all elements of each ROI area are transferred to their assigned PEs. | 08-21-2014 |
| 20150082003 | Multiprocessor Having Associated RAM Units - A multiprocessor has a plurality of arithmetic units, each having two input registers and one output register, and a plurality of RAM units each having RAM memory and a pointer associated with the RAM memory such as a program pointer, an address pointer, a stack pointer or a subroutine claim pointer. | 03-19-2015 |
| 20150371694 | HETEROGENEOUS MAGNETIC MEMORY ARCHITECTURE - Technologies are generally described for systems, devices and methods relating to multicore processors. The multicore processors may include first and second tiles with first and second caches, respectively. The first cache may include first magnetoresistive random access memory (MRAM) cells with first storage characteristics. The second cache may include second MRAM cells with second storage characteristics different from the first storage characteristics. In some examples, an interconnect structure may be coupled to the first and second tiles and may be configured to provide communication between the first tile and the second tile. Methods for handling migration between tiles and cores are also described. | 12-24-2015 |
| 20160103786 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
| 20160103788 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
