| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 711151000 | Prioritized access regulation | 56 |
| 20080209137 | Method of specifying access sequence of a storage device - The present invention is to provide a method of specifying access sequence of a storage device, wherein queues with different priority are created in the storage device for recording access requests from at least one server at the front-end of the storage device to manage the access operation, and are recorded corresponding to the front-end servers and the priority thereof respectively via a priority table. When the front-end server makes an access request, the request will be added to the corresponding queue according to the source front-end server, and each queue will be processed according to the priority thereof. The maximum workload of the access request processed every single time of each queue is set respectively. Thus, the access requests of the queues with higher priority will be processed within a shorter time. | 08-28-2008 |
| 20080276049 | Semiconductor memory apparatus, memory access control system and data reading method - In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores the data and priority while maintaining a corresponding relationship thereof; a data reading portion reads the data corresponding to address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to the read data storing portion while maintaining a corresponding relationship between the priority information and the data read; and a priority operation control portion which chooses and outputs the data with a highest priority among the priority information and the data that are stored in the read data storing portion while maintaining a corresponding relationship between the priority information and the data. | 11-06-2008 |
| 20080320240 | Method and arrangements for memory access - In one embodiment a multi-input, multi output memory system is disclosed. The system can include a plurality of single ported memory modules, an identifier module to provide an identify to each memory access requests of a plurality of memory access requests. The identity can include a port that receives the memory access request. The system can include a memory access controller coupled to the plurality of single ported memory modules that can control movement of the requests. | 12-25-2008 |
| 20080320241 | Data storage device performance optimization methods and apparatuses - Methods and apparatuses for identifying types of data streams and communicating stream information to improve performance of data storage devices are disclosed. Method embodiments generally comprise identifying one or more isochronous requests among a plurality of requests which may be issued to a data storage device, assigning a completion deadline an isochronous request, and communicating the isochronous request and completion deadline information to the data storage device. Apparatus embodiments generally comprise a request identifier to identify an isochronous request, a logic module to assign a completion deadline to the isochronous request, and a communication module to communicate the isochronous request and the completion deadline to a data storage device. Alternative apparatus embodiments may include a monitor module to monitor a system process operating in the system and determine if the system process issues isochronous requests. Various embodiments may process asynchronous requests, including prioritized asynchronous requests, with the isochronous requests. | 12-25-2008 |
| 20090019238 | Memory Controller Read Queue Dynamic Optimization of Command Selection - A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes fuller, requests are serviced in a manner that maximizes throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted. | 01-15-2009 |
| 20090019239 | Memory Controller Granular Read Queue Dynamic Optimization of Command Selection - A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted. | 01-15-2009 |
| 20090024804 | MEMORY CONTROLLERS FOR PROCESSOR HAVING MULTIPLE PROGRAMMABLE UNITS - A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. | 01-22-2009 |
| 20090077325 | Method and arrangements for memory access - In one embodiment a memory system is disclosed having a first requester group, a first access control module coupled to the first requester group to receive access requests from the first requester group, a second requestor group and a second access control module coupled to the second requestor group to receive access requests from the second requestor group and memory. The memory can be segmented into a plurality of address blocks, where the plurality of address blocks can have an address range. The controller can sequentially rotate write access among the plurality of address blocks to distribute the sequential data among the plurality of address blocks. | 03-19-2009 |
| 20090119463 | SYSTEM AND ARTICLE OF MANUFACTURE FOR DUMPING DATA IN PROCESSING SYSTEMS TO A SHARED STORAGE - Provided are a system and article of manufacture for dumping data in processing systems to a shared storage. A plurality of processing systems receive a signal indicating an event. Each of the processing systems write data used by the processing system to a shared storage device in response to receiving the signal, wherein each processing system writes the data to the shared storage device. | 05-07-2009 |
| 20090204771 | DEVICE FOR CONTROLLING ACCESS FROM A PLURALITY OF MASTERS TO SHARED MEMORY COMPOSED OF A PLURALITY OF BANKS EACH HAVING A PLURALITY OF PAGES - The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections divides a command issued by the corresponding master into a plurality of micro-commands when the access region of the command is over two or more banks among the plurality of banks, each of the micro-commands being a command accessing only one of the two or more banks, and gives each of the micro-commands to an inter-master arbitration section corresponding to the bank including the access region of the micro-command. Each of the inter-master arbitration sections arbitrates micro-commands given from the command division sections to select one. The memory control section selects one of a plurality of micro-commands selected by the inter-master arbitration sections to perform memory access. | 08-13-2009 |
| 20090216962 | PRIORITIZATION OF MULTIPLE CONCURRENT THREADS FOR SCHEDULING REQUESTS TO SHARED MEMORY - A “request scheduler” provides techniques for batching and scheduling buffered thread requests for access to shared memory in a general-purpose computer system. Thread-fairness is provided while preventing short- and long-term thread starvation by using “request batching.” Batching periodically groups outstanding requests from a memory request buffer into larger units termed “batches” that have higher priority than all other buffered requests. Each “batch” may include some maximum number of requests for each bank of the shared memory and for some or all concurrent threads. Further, average thread stall times are reduced by using computed thread rankings in scheduling request servicing from the shared memory. In various embodiments, requests from higher ranked threads are prioritized over requests from lower ranked threads. In various embodiments, a parallelism-aware memory access scheduling policy improves intra-thread bank-level parallelism. Further, rank-based request scheduling may be performed with or without batching. | 08-27-2009 |
| 20090248994 | MEMORY RANK BURST SCHEDULING - A method, device, and system are disclosed. In one embodiment the method includes grouping multiple memory requests into multiple of memory rank queues. Each rank queue contains the memory requests that target addresses within the corresponding memory rank. The method also schedules a minimum burst number of memory requests within one of the memory rank queues to be serviced when the burst number has been reached in the one of the plurality of memory rank queues. Finally, if a memory request exceeds an aging threshold, then that memory request will be serviced | 10-01-2009 |
| 20090254713 | ACCESS CONTROL TO PARTITIONED BLOCKS IN SHARED MEMORY - A method for controlling multiple access to partitioned areas of a shared memory and a portable terminal having the shared memory are disclosed. According to an embodiment of the present invention, the storage area of a shared memory is partitioned to a plurality of storage areas, and each control unit accesses a storage area through each access port to store data and transfers an authority to access the pertinent storage area to the other control unit, thereby allowing access by the other control unit. With the present invention, the data communication time between the plurality of control units can be minimized, and the process efficiency of each control unit can be optimized. | 10-08-2009 |
| 20090254714 | Method and Apparatus for Exploiting Parallelism Across Multiple Traffic Streams Through a Single Channel - Methods of obtaining, enqueueing and executing several memory transactions are described, where the memory transactions may be generated in a first order but executed in a second order. Despite the relaxed ordering, essential programming paradigms such as producer-consumer relationships are not affected. Chipsets and systems using the methods are also described and claimed. | 10-08-2009 |
| 20100011172 | MICROCONTROLLER SYSTEMS HAVING SEPARATE ADDRESS AND DATA BUSES - A microcontroller system includes at least one processor and at least one storage unit for storing data received from or to be sent to the processor. At least two read clients are provided in the processor for retrieving data from the storage unit, and at least one write client is provided in the processor for writing data in the storage unit. The system further includes a memory device provided in the storage unit for storing data, and an arbitration device provided in the storage unit for enabling access to the memory device by the read and the write client. The read clients each have a dedicated read address line connected to the arbitration device for sending a read address of read data to be retrieved from the memory device, and a shared read data bus connected to the memory device for receiving the read data from the read address. | 01-14-2010 |
| 20100049923 | DEVICE AND METHOD TO PROCESS OFDM-BASED SYMBOLS IN WIRELESS NETWORK - A device and a method to efficiently process the symbols coded in OFDM according to the various protocols available. This is achieved through a device to process OFDM-based symbols comprising a base band input data and a base band output data, and comprising at least two programmable execution units connected to at least one working memory, this device being characterized in that, the programmable execution units (EU) are connected to the memory (M- | 02-25-2010 |
| 20100064109 | Managing storage units in multi-core and multi-threaded systems - A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item. When later a high priority storage item is allocated to a selected entry of the storage unit, a comparison operation between the allocated high priority storage item and the indication in the history field for the block containing the selected entry is carried out, and on detection of a match condition a lock indication associated with that entry is set to inhibit further eviction of that high priority storage item. | 03-11-2010 |
| 20100100689 | TRANSACTION PROCESSING IN TRANSACTIONAL MEMORY - A transactional memory processing system provides for the integration of transactional memory concepts at the compiler-level into a higher-level traditional transaction processing system. Atomic blocks at the compiler-level can be specified as atomic block transactions and include the features of atomicity and isolation. Actions within this atomic block transaction include the enlistment of resource managers from a repository. The repository can now include a pre-programmed memory resource manager to manage the transactional memory. As in traditional transactions, a commit protocol can be used to determine if the actions are valid and can be exposed outside of the transaction. Unlike traditional transactions, however, the transaction is not necessarily doomed if all of the actions are not validated. Rather, memory conflicts can cause a rollback and re-execution of the atomic block transaction, which can be repeated as long as necessary, until the memory resource manger votes to commit. | 04-22-2010 |
| 20100153659 | SERVICING MEMORY READ REQUESTS - Included are embodiments for a method for servicing memory read requests. At least one embodiment of a method includes receiving read requests from the I/O device; testing predetermined fields from the read requests to predict a type of read request; and when the type of request is predicted to be a data read request, then route the read request to a first queue. Additionally, some embodiments include when the type of request is predicted to be a control read request, then route the read request to a second queue, wherein the second queue has a higher priority than the first queue; determining which of the first queue and second queue to read; retrieving at least one of the read requests from the determined queue; and processing the retrieved read request. | 06-17-2010 |
| 20100174873 | Priority Promotion for Service Requests - A method for priority promotion of a service request comprises receiving the service request for a target address space into a set of work requests, the set of work requests comprising a plurality of service requests for the target address space, the service request originating from a source address space, the service request having a priority equivalent to a priority of the target address space, the source address space having a higher priority than the target address space; determining a number of service requests for the target address space in the set of work requests; and, in the event the number of service requests for the target address space exceeds a predetermined value, promoting the priority of the service request to the priority of the source address space. | 07-08-2010 |
| 20100318750 | METHOD AND SYSTEM FOR SCHEDULING MEMORY REQUESTS - A system for selecting memory requests. The system includes arbiters and a time ordered list scheduler. Each arbiter selects a memory request for transmission from at least one client. The scheduler is operable to receive and store memory requests from the arbiters and selects a selected memory request for forwarding to a memory system. The scheduler includes a list structure operable to store memory requests received from the arbiters in a fashion to preserve relative time of arrival of the memory requests. The scheduler includes scanners that are prioritized with respect to one another. Scanners are operable to simultaneously scan contents of the list structure from the oldest to newest requests and determine whether a memory request match is found based on associated programmable rules to locate a memory request candidate. A memory request candidate of a highest priority scanner is selected by the scheduler as the selected memory request. | 12-16-2010 |
| 20120079216 | MEMORY CONTROL DEVICE AND METHOD - A priority control register | 03-29-2012 |
| 20120290797 | MAILBOX DATA COMMUNICATIONS - A method of passing message data from a first device to a second device in a software defined radio (SDR) apparatus. A shared memory is defined in the apparatus for access by either one of the first and the second devices. A priority message originating from one of the devices and destined to the other device is loaded into a buffer of the shared memory, and the address of the buffer is passed to the other device. The message in the buffer of the shared memory is then accessed directly from the other device. | 11-15-2012 |
| 20120311273 | System and Method for Synchronization Between Concurrent Transactions Using Transaction Condition Variables - The systems and methods described herein may extend transactional memory implementations to support transaction communicators and/or transaction condition variables for which transaction isolation is relaxed, and through which concurrent transactions can communicate and be synchronized with each other. Transactional accesses to these objects may not be isolated unless called within communicator-isolating transactions. A waiter transaction may invoke a wait method of a transaction condition variable, be added to a wait list for the variable, and be suspended pending notification of a notification event from a notify method of the variable. A notifier transaction may invoke a notify method of the variable, which may remove the waiter from the wait list, schedule the waiter transaction for resumed execution, and notify the waiter of the notification event. A waiter transaction may commit only if the corresponding notifier transaction commits. If the waiter transaction aborts, the notification may be forwarded to another waiter. | 12-06-2012 |
| 20130013869 | INVOKING OPERATING SYSTEM FUNCTIONALITY WITHOUT THE USE OF SYSTEM CALLS - Embodiments of the invention operate within the context of a system with a processor providing memory-monitoring functionality. The lower-privileged code of a first process, such as user application code, communicates directly with higher-privileged code of a second process, such as interrupt-handling code of the operating system kernel, without using a software interrupt or other gate mechanism. This enhances overall system performance by eliminating the saving of state and processing inherent in interrupt handling, and also avoids missing events that may occur while other interrupts are masked during event handling. Specifically, the second process initializes a monitored memory area that is directly accessible by processes having at least the privilege level of the first process. The second process further initializes memory-monitoring hardware of the processor to monitor writes to the monitored memory area, such that the second process will resume execution from a dormant state when a write takes place. | 01-10-2013 |
| 20130061005 | METHOD FOR POWER OPTIMIZED MULTI-PROCESSOR SYNCHRONIZATION - One embodiment of the present invention sets forth a technique for synchronization between two or more processors. The technique implements a spinlock acquire function and a spinlock release function. A processor executing the spinlock acquire function advantageously operates in a low power state while waiting for an opportunity to acquire spinlock. The spinlock acquire function configures a memory monitor to wake up the processor when spinlock is released by a different processor. The spinlock release function releases spinlock by clearing a lock variable and may clear a wait variable. | 03-07-2013 |
| 20130124805 | APPARATUS AND METHOD FOR SERVICING LATENCY-SENSITIVE MEMORY REQUESTS - A shared memory controller and method of operation are provided. The shared memory controller is configured for use with a plurality of processors such as a central processing unit or a graphics processing unit. The shared memory controller includes a command queue configured to hold a plurality of memory commands from the plurality of processors, each memory command having associated priority information. The shared memory controller includes boost logic configured to identify a latency sensitive memory command and update the priority information associated with the memory command to identify the memory command as latency sensitive. The boost logic may be configured to identify a latency sensitive processor command. The boost logic may be configured to track time duration between successive latency sensitive memory commands. | 05-16-2013 |
| 20130151795 | APPARATUS AND METHOD FOR CONTROLLING MEMORY - Disclosed herein are an apparatus and method for controlling memory. The apparatus includes a memory access request buffer unit, a memory access request control unit, and a bank control unit. The memory access request buffer unit determines and stores memory access request order so that the plurality of memory access requests is processed in the order of input except that memory access requests attempting to access the same bank and the same row are successively processed. The memory access request control unit reads the memory access requests from the memory access request buffer unit in the determined order, distributes the memory access requests to banks, and transfers the memory access requests to memory. The bank control unit stores a preset number of memory access requests in each of buffer units for respective banks, and controls the operating state of each of the banks. | 06-13-2013 |
| 20130179645 | EQUALIZING BANDWIDTH FOR MULTIPLE REQUESTERS USING A SHARED MEMORY SYSTEM - A method for equalizing the bandwidth of requesters using a shared memory system is disclosed. In one embodiment, such a method includes receiving multiple access requests to access a shared memory system. Each access request originates from a different requester coupled to the shared memory system. The method then determines which of the access requests has been waiting the longest to access the shared memory system. The access requests are then ordered so that the access request that has been waiting the longest is transmitted to the shared memory system after the other access requests. The requester associated with the longest-waiting access request may then transmit additional access requests to the shared memory system immediately after the longest-waiting access request has been transmitted. A corresponding apparatus and computer program product are also disclosed. | 07-11-2013 |
| 20130185525 | SEMICONDUCTOR CHIP AND METHOD OF CONTROLLING MEMORY - Disclosed herein are a semiconductor chip for adaptively processing a plurality of commands to request memory access, and a method of controlling memory. The semiconductor chip includes a storage unit ad a control unit. The storage unit stores a memory access request to be currently processed and a plurality of memory access requests received before the memory access request to be currently processed in received order. The control unit processes the memory access request to be currently processed and the plurality of memory access requests received before the memory access request to be currently processed, which have been stored in the storage unit, in received order, except that memory access requests attempting to access the same bank and the same row are successively processed. | 07-18-2013 |
| 20130262788 | Systems and Methods for External Priority Controlled Data Transfer - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. As an example a system is discussed that includes a data transfer controller circuit operable to provide a read request to a storage device. The read request indicates a data set to be provided from the storage device and a processing priority of at least a portion of the data set. | 10-03-2013 |
| 20130318310 | PROCESSOR PROCESSING METHOD AND PROCESSOR SYSTEM - A processor processing method is executed by a memory controller, and includes determining based on a log of access of a shared resource by a first application, whether the first application running on a first processor operates normally; and causing a second processor to run a second application other than the first application upon the first application being determined to not be operating normally. | 11-28-2013 |
| 20140052936 | MEMORY QUEUE HANDLING TECHNIQUES FOR REDUCING IMPACT OF HIGH-LATENCY MEMORY OPERATIONS - Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations. | 02-20-2014 |
| 20140052937 | Dynamic QoS Upgrading - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline. | 02-20-2014 |
| 20140108745 | METHOD AND DEVICE FOR MAINTAINING DATA IN A DATA STORAGE SYSTEM COMPRISING A PLURALITY OF DATA STORAGE NODES - A method and device for maintaining data in a data storage system, comprising a plurality of data storage nodes, the method being employed in a storage node in the data storage system and comprising: monitoring and detecting, conditions in the data storage system that imply the need for replication of data between the nodes in the data storage system; initiating replication processes in case such a condition is detected, wherein the replication processes include sending multicast and unicast requests to other storage nodes, said requests including priority flags, receiving multicast and unicast requests from other storage nodes, wherein the received requests include priority flags, ordering the received requests in different queues depending on their priority flags, and dealing with requests in higher priority queues with higher frequency than requests in lower priority queues. | 04-17-2014 |
| 20140115279 | Multi-Master Cache Coherent Speculation Aware Memory Controller with Advanced Arbitration, Virtualization and EDC - This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip memory. This invention includes an arbitration for all memory endpoints including priority, fairness, and starvation bounds; virtualization; and error detection and correction hardware to protect the on-chip SRAM banks including automated scrubbing. | 04-24-2014 |
| 20140143512 | ACCESSING ADDITIONAL MEMORY SPACE WITH MULTIPLE PROCESSORS - An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory. | 05-22-2014 |
| 20140181423 | System and Method for Implementing NUMA-Aware Statistics Counters - The systems and methods described herein may be used to implement scalable statistics counters suitable for use in systems that employ a NUMA style memory architecture. The counters may be implemented as data structures that include a count value portion and a node identifier portion. The counters may be accessible within transactions. The node identifier portion may identify a node on which a thread that most recently incremented the counter was executing or one on which a thread that has requested priority to increment the shared counter was executing. Threads executing on identified nodes may have higher priority to increment the counter than other threads. Threads executing on other nodes may delay their attempts to increment the counter, thus encouraging consecutive updates from threads on a single node. Impatient threads may attempt to update the node identifier portion or may update an anti-starvation variable to indicate a request for priority. | 06-26-2014 |
| 20140181424 | SEMICONDUCTOR MEMORY SYSTEM AND OPERATION METHOD THEREOF - A semiconductor memory system may include a plurality of memory devices each configured to have multiple planes, and an access controller configured to access each of the multiple planes corresponding to each of the plurality of memory devices as a unit memory. | 06-26-2014 |
| 20140195743 | ON-CHIP TRAFFIC PRIORITIZATION IN MEMORY - According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request. | 07-10-2014 |
| 20140195744 | ON-CHIP TRAFFIC PRIORITIZATION IN MEMORY - According to one embodiment, a memory device is provided. The memory device includes a processing element coupled to a crossbar interconnect. The processing element is configured to send a memory access request, including a priority value, to the crossbar interconnect. The crossbar interconnect is configured to route the memory access request to a memory controller associated with the memory access request. The memory controller is coupled to memory and to the crossbar interconnect. The memory controller includes a queue and is configured to compare the priority value of the memory access request to priority values of a plurality of memory access requests stored in the queue of the memory controller to determine a highest priority memory access request and perform a next memory access request based on the highest priority memory access request. | 07-10-2014 |
| 20140201471 | Arbitrating Memory Accesses Via A Shared Memory Fabric - In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed. | 07-17-2014 |
| 20140201472 | INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM - In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network. | 07-17-2014 |
| 20140223113 | SELECTOR SYNCRONIZED WITH MOVEMENT OF DATA IN MEMORY - In one implementation, data values having an order are stored at a memory having a plurality of memory locations. Data values are periodically moved between memory locations according to a movement pattern. A selector is synchronized with the movement of the data values according to the movement pattern to select an output. | 08-07-2014 |
| 20140344528 | TECHNIQUES FOR ASSIGNING PRIORITIES TO MEMORY COPIES - One embodiment sets forth a method for guiding the order in which a parallel processing subsystem executes memory copies. A driver creates semaphores for all but the lowest priority included in a plurality of priorities and associates one priority with each copy hardware channel included in the parallel processing subsystem. The driver then aliases prioritized streams to the copy hardware channels based on the priorities. Upon receiving a request to execute a memory copy within one of the streams, the driver inserts commands into the aliased copy hardware channel. These commands use the semaphores to direct the parallel processing subsystem to execute the memory copy based on the priority of the copy hardware channel. Advantageously, by assigning priorities to streams and, subsequently, strategically requesting memory copies within the prioritized streams, an application developer may fine-tune their software application to increase the overall processing efficiency of the software application. | 11-20-2014 |
| 20140372711 | SCHEDULING MEMORY ACCESSES USING AN EFFICIENT ROW BURST VALUE - A memory accessing agent includes a memory access generating circuit and a memory controller. The memory access generating circuit is adapted to generate multiple memory accesses in a first ordered arrangement. The memory controller is coupled to the memory access generating circuit and has an output port, for providing the multiple memory accesses to the output port in a second ordered arrangement based on the memory accesses and characteristics of an external memory. The memory controller determines the second ordered arrangement by calculating an efficient row burst value and interrupting multiple row-hit requests to schedule a row-miss request based on the efficient row burst value. | 12-18-2014 |
| 20140372712 | CONCURRENT DUMPING OF LARGE ADDRESS SPACE - A method for managing concurrent system dumps of address spaces of memory of a computing system. The method comprises analyzing address space of memory to determine high priority areas and low priority areas of the address space. The method further comprises stopping all application threads of memory. In addition, the method further comprises performing a system dump of all the high priority areas of the address space. Moreover, the method further comprises initiating a background thread that performs a system dump of the low priority areas in background of the address space, and allowing, by the one or more computer processors, all of the application threads of memory to restart. | 12-18-2014 |
| 20150046662 | COALESCING TEXTURE ACCESS AND LOAD/STORE OPERATIONS - A system, method, and computer program product are provided for coalescing memory access requests. A plurality of memory access requests is received in a thread execution order and a portion of the memory access requests are coalesced into memory order, where memory access requests included in the portion are generated by threads in a thread block. A memory operation is generated that is transmitted to a memory system, where the memory operation represents the coalesced portion of memory access requests. | 02-12-2015 |
| 20150067276 | MEMORY SYSTEM AND CONTROLLER - According to one embodiment, according to one embodiment, a memory system includes a first memory, a second memory, an interface, a managing unit, and a control unit. The second memory stores data read out from the first memory. The interface receives a read command. The managing unit manages a corresponding relationship of a first address included in the read command and a second address. The second address is an address indicating a position in the first memory where data designated by the first address is stored. The control unit acquires a plurality of second addresses corresponding to a sequential first address range including the first address in a case where the read command is received, and determine an amount of data to be read out from the first memory to the second memory based on whether the plurality of second addresses is sequential or not. | 03-05-2015 |
| 20150121015 | DEVICE AND METHOD FOR PROCESSING MESSAGE - Embodiments provide a device and method for processing messages according to a priority order and for reducing a message processing time when a response event occurs, in a PLC communication module. | 04-30-2015 |
| 20150134919 | INFORMATION PROCESSING APPARATUS AND DATA ACCESS METHOD - A memory includes a plurality of areas corresponding to a plurality of segments of a storage device. An operation unit stores each of generated access instructions in an area corresponding to a segment of an access destination of the access instruction among the plurality of areas. The operation unit loads data of a segment corresponding to at least one area selected from the plurality of areas from the storage device to another area which is different from the plurality of areas on the memory, and executes an access instruction stored in the selected area, for the loaded segment data. | 05-14-2015 |
| 20160054932 | Memory Controller for Heterogeneous Computer - A memory controller for heterogeneous computer processors dynamically adjusts access priorities by the different processors to maximize performance in the execution of a single parallel application program on both processor architectures. In one embodiment, the memory controller predicts sequential memory accesses by the processor having higher memory latency or fewer access requests to lockout the other processor during those sequences for improved implementation of the intended prioritization. | 02-25-2016 |
| 20160139806 | Independent Ordering Of Independent Transactions - An input/output bridge controls access to a memory by a number of devices and maintains an order of access requests under virtualization. In particular, the bridge manages and enforces order among multiple independent threads of requests to a memory. The bridge populates a number of ordered lists with received access requests based on a corresponding identifier of each access request. A top list is also maintained, where the top list is populated with access requests and a corresponding translated physical address. The bridge forwards access requests from the top list, maintaining the order of each of the independent threads. | 05-19-2016 |
| 20160179429 | CONTROLLING MEMORY ACCESS CONFLICT OF THREADS ON MULTI-CORE PROCESSOR WITH SET OF HIGHEST PRIORITY PROCESSOR CORES BASED ON A THRESHOLD VALUE OF ISSUED-INSTRUCTION EFFICIENCY | 06-23-2016 |
| 20160179712 | Categorizing Memory Pages Based On Page Residences | 06-23-2016 |
| 20160188529 | GUARANTEED QUALITY OF SERVICE IN SYSTEM-ON-A-CHIP UNCORE FABRIC - In an example, a control system may include a system-on-a-chip (SoC), including one processor for real-time operation to manage devices in the control system, and another processor configured to execute auxiliary functions such as a user interface for the control system. The first core and second core may share memory such as dynamic random access memory (DRAM), and may also share an uncore fabric configured to communicatively couple the processors to one or more peripheral devices. The first core may require a guaranteed quality of service (QoS) to memory and/or peripherals. The uncore fabric may be divided into a first “real-time” virtual channel designated for traffic from the first processor, and a second “auxiliary” virtual channel designated for traffic from the second processor. The uncore fabric may apply a suitable selection or weighting algorithm to the virtual channels to guarantee the QoS. | 06-30-2016 |
