Entries |
Document | Title | Date |
20080201534 | REDUCING NUMBER OF REJECTED SNOOP REQUESTS BY EXTENDING TIME TO RESPOND TO SNOOP REQUEST - A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/reorder unit is full in which case the new snoop request is transmitted to a second unit configured to transmit a request to retry resending the new snoop request. Snoop requests have a higher priority than requests from processors and snoop requests are selected by the arbitration mechanism over processor requests unless the arbitration mechanism requests otherwise (“stall request”) to the stall/reorder unit. By snoop requests having a higher priority than processor requests, the number of snoop requests rejected is reduced. By having the arbitration mechanism issue a stall request, the processor will not be starved. | 08-21-2008 |
20080222367 | Branching Memory-Bus Module with Multiple Downlink Ports to Standard Fully-Buffered Memory Modules - A branching memory-bus module has one uplink port and two or more downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the multiple downlink ports to two or more branches of memory modules. Frames sent upstream to the processor by a memory module on a downlink port are repeated to the uplink port. A branching Advanced Memory Buffer (AMB) on the branching memory-bus module has re-timing and re-synchronizing buffers that repeat frames to the multiple downlink ports. Elastic buffers can merge and synchronize frames from different downlink branches. Separate northbound and southbound lanes may be replaced by bidirectional lanes to reduce pin counts. Latency from the host processor to the farthest memory module is reduced by branching compared with a serial daisy-chain of fully-buffered memory modules. Point-to-point bus segments have only two endpoints despite branching by the branching AMB. | 09-11-2008 |
20080229029 | Semiconductor Memory System Having Plurality of Ranks Incorporated Therein - A semiconductor memory system which can integrate a plurality of ranks without occupying an increased area. The semiconductor memory system includes a memory device that has a plurality of ranks each having banks integrated therein, and a shared circuit section that is integrated in the memory device and is shared by the plurality of ranks. The plurality of ranks are selectively operated based on the signals provided from the shared circuit section. | 09-18-2008 |
20080229030 | Efficient Use of Memory Ports in Microcomputer Systems - A microcomputer system includes first and second IP blocks, a multi-port memory, a shared memory field allocated to the second IP block, and a second memory field. A first memory controller is configured to control access to the first and shared memory fields. A second memory controller is configured to control access to the second and shared memory fields. A bus controller operates in response to access request signals provided from the first and second IP blocks. When the second memory controller is in a ready state and the first and second IP blocks request access to the first and shared memory fields, the bus controller provides the first memory controller with access to the access request signal of the first IP block and provides the second memory controller with access to the access request signal of the second IP block. | 09-18-2008 |
20080235462 | Device Having a Low Latency Single Port Memory Unit and a Method for Writing Multiple Data Segments to a Single Port Memory Unit - A method and a device. The device includes a single port memory unit that includes multiple memory regions, whereas each memory region is adapted to receive multiple data segments in parallel; whereas the single port memory unit receives a memory clock signal; characterized by including access logic adapted to receive multiple data segment write requests from multiple data sources; to write, during a first memory clock cycle, multiple data segments to a certain memory region in response to an availability of the certain memory region; to temporarily store rejected data segments; to write, during a second memory clock cycle, at least the rejected data segments, to another memory region. | 09-25-2008 |
20080244197 | EXTERNAL MEMORY CONTROLLER NODE - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 10-02-2008 |
20080263286 | Operation Control of Shared Memory - A method of controlling a shared memory and a user terminal controlling the operation of the shared memory are disclosed. The portable terminal according to an embodiment of the present invention has a memory unit with a storage area partitioned to blocks in a quantity of n and a plurality of processors reading or writing data by accessing a partitioned block. At least one of the partitioned blocks is assigned as a common storage area, accessible by a processor having an access privilege, and the processor having the access privilege performs an operation of maintaining the data stored in the common storage area. With the present invention, the common storage area can be accessed by a plurality of processors, and thus the data transmission time between the processors can be minimized. | 10-23-2008 |
20080263287 | MULTI-PORT MEMORY DEVICE AND COMMUNICATION SYSTEM HAVING THE SAME - A communication system includes a first processor, a second processor, and a multi-port memory device. The multi-port memory device generates a first internal clock signal having a first frequency and a second internal clock signal having a second frequency based on an external clock signal. The multi-port memory device communicates with the first processor in a parallel interface mode synchronously with the first internal clock signal. In addition, the multi-port memory device communicates with the second processor in a serial interface mode synchronously with the second internal clock signal. Therefore, the multi-port memory device applied to the communication system may reduce a number of pins and costs. | 10-23-2008 |
20080288727 | Computing System with Optimized Support for Transactional Memory - A computing system processes memory transactions for parallel processing of multiple threads of execution by support of which an application need not be aware. The computing system transactional memory support provides a Transaction Table in memory and a method of fast detection, of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. | 11-20-2008 |
20080288728 | MULTICORE WIRELESS AND MEDIA SIGNAL PROCESSOR (MSP) - A media signal processor (MSP) architecture is disclosed in this invention To address the shortcomings of conventional high performance processing units, the MSP architecture is designed using a new concept in parallel processing—“Same Instruction Different Operation” (SIDO) and “Same Instruction Multiple Data” (SIMD) architectures. The scalable nature of the architecture makes it possible to add multiple cores to match the processing needs of any type of data processing application. With multiple MSPs working in parallel, multiple data streams can be processed in either parallel or in a sequentially pipelined manner, using a software-based control mechanism. | 11-20-2008 |
20080307170 | MEMORY MODULE AND MEMORY SYSTEM - A memory module includes a plurality of ranks that each include a first pin group and a second pin group for receiving external pin signals, and a rank selecting unit included in each of the plurality of ranks, the rank selecting unit configured to output different rank pin signals to each rank by using signals of the first pin group. | 12-11-2008 |
20090024803 | Multipath accessible semiconductor memory device having shared register and method of operating thereof - A semiconductor memory device for use in a multiprocessor system may be provided. A chip size may be controlled, and a design of circuit may be relatively simplified. The semiconductor memory device for use in a multiprocessor system may include at least two shared memory areas commonly accessible by processors of the multiprocessor system through different ports and assigned with a predetermined memory capacity unit to a portion of a memory cell array, a single shared register adapted outside the memory cell array, corresponding to disable areas formed within the shared memory areas, and/or a switching unit for connecting a decoder of a selected shared memory area to the shared register in response to an applied control signal, to match the shared register to the disable area of the selected shared memory area. A shared register may be commonly used in corresponding to a plurality of shared memory areas, thereby reducing or preventing a chip size increase and simplifying a design of the circuit. | 01-22-2009 |
20090031089 | Transpose Memory And Method Thereof - A transpose memory circuit is provided which comprises a number of dual port memory blocks each having a plurality of storage cells each configured for storing one or more data word. The dual port memory blocks form a storage array for storing at least one input matrix and outputting the at least one input matrix in transposed form. A data input is provided to receive a plurality data words on each cycle and a data output is provided to output a plurality of data words on each cycle. A read address logic is provided to generate read addresses such that one cell of each dual port memory block can be read out on each cycle. A write address logic is provided to generate write addresses such that one cell k of each dual port memory block can be written on each cycle. In each cycle, one storage cell of each dual port memory block is addressed by the read address logic. The data words stored in the addressed storage cells are read out from one dual port memory block and outputted through the data output. In each cycle, one storage cell of each dual port memory block is addressed by the write address logic, where the addressed storage cells have been read out in a preceding cycle and into which storage cells data words received through the data input are written. The transpose memory circuit is provided to receive an input matrix in cycles and to output the transposed input matrix in next cycles without any dead cycles interposed between them. | 01-29-2009 |
20090037669 | Detachable direct memory access arrangement - A new and useful DMA-like arrangement provides fast inter-system transfers of large data volumes. A preferred embodiment of the invention includes a data-transfer-out system and further includes a data-transfer-in system. At least one of the systems has a dual ported memory structure configured in a way so that data can move out of a memory module of the structure from one port while other data can independently move into the memory module through the other port. The systems are detachable with respect to each other, and the memory modules of both systems are correspondingly paired with compatible specifications such as module sizes. Furthermore, these memory modules are physically configured in a way so that inter-system data transfer occurs in a parallel (i.e., module to module) manner without the aid of the CPU of the system that has the dual ported memory structure. | 02-05-2009 |
20090043970 | DEVICE HAVING SHARED MEMORY AND METHOD FOR PROVIDING ACCESS STATUS INFORMATION BY SHARED MEMORY - A device having a shared memory and a method for providing access status information by the shared memory are disclosed. A digital processing device includes n processors and a shared memory. The shared memory is coupled to each processor though a separate bus, its storage area includes m common sections, and generates and outputs access status information related to whether an arbitrary processor is accessing at least one of the common sections. With the present invention, a control sequence of each processor can be simplified at a maximum by allowing the shared memory to generate and output access status information related to the common sections. | 02-12-2009 |
20090055598 | External Memory Controller Node - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 02-26-2009 |
20090063787 | Buffered Memory Module with Multiple Memory Device Data Interface Ports Supporting Double the Memory Capacity - A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and at least one memory module coupled to the memory controller. In the memory systems, each memory module comprises at least one memory hub device integrated in the memory module. In the memory system, each memory hub device in the memory module comprises a first memory device data interface that communicates with a first set of memory devices and a second memory device data interface that communicates with a second set of memory devices. In the memory system, the first set of memory devices which are separate from the second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces. | 03-05-2009 |
20090106503 | Method, device, and system for preventing refresh starvation in shared memory bank - A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register. | 04-23-2009 |
20090125685 | SHARED MEMORY SYSTEM FOR A TIGHTLY-COUPLED MULTIPROCESSOR - A shared memory system for a multicore computer system utilizing an interconnection network that furnishes tens of processing cores or more with the ability to refer concurrently to random addresses in a shared memory space with efficiency comparable to the typical efficiency achieved when referring to private memories. The network is essentially a lean and light-weight combinational circuit, although it may also contain non-deep pipelining. The network is generally composed of a sub-network for writing and a separate multicasting sub-network for reading, whose topologies are based on multiple logarithmic multistage networks, e.g. Baseline Networks, connected in parallel. The shared memory system computes paths between processing cores and memory banks anew at every clock cycle, without rearrangement. It returns an approval reply to every core whose initiative of accessing memory leads to the successful establishment of a path and is fulfilled, or a rejection reply to every core whose initiative is not fulfilled. | 05-14-2009 |
20090150621 | BANK SHARING AND REFRESH IN A SHARED MULTI-PORT MEMORY DEVICE - A method and system for sharing banks of memory in a multi-port memory device between components is provided. The multi-port memory device includes multiple ports to which components of a system are attached, and multiple banks of memory within the multi-port memory device that are shared by each of the ports. A bank availability pin is added to each port for each bank of memory. The bank availability pin is signaled when the bank is available to a particular port and unsignaled when the bank is unavailable. Thus, the multi-port memory device can be shared by several components simultaneously with only a small amount of additional hardware to support the sharing. Also provided are methods for refreshing the banks of memory. | 06-11-2009 |
20090216959 | Multi Port Memory Controller Queuing - The present invention is generally directed to a method, system, and program product wherein at least one command in a first queue is transferred to a second queue. When the first queue can no longer accept command(s) and a second queue is able to accept command(s), the second queue accepts the command(s) that the first queue can not. When the first queue is able to accept command(s), and there are command(s) in the second memory port that should have been in the first queue, the command(s) in the second queue are transferred to the first queue. | 08-27-2009 |
20090216960 | Multi Port Memory Controller Queuing - The present invention is generally directed to a method, system, and program product wherein at least two memory ports associated within a memory controller are capable of transferring commands between one another in unbalanced memory configurations. When the first memory port can no longer accept commands and a second memory port is able to accept commands, the second memory port accepts the commands that the first memory port can not. When the first memory port is able to accept commands, and there are commands in the second memory port that should have been in the first memory port, the commands in the second memory port are transferred to the first memory port. | 08-27-2009 |
20090216961 | MULTI-PORT SEMICONDUCTOR MEMORY DEVICE FOR REDUCING DATA TRANSFER EVENT AND ACCESS METHOD THEREFOR - A multiport semiconductor memory device includes at least three port units coupled respectively to corresponding processors, a shared memory area accessed in common by the processors through the port units, and a data path control unit for controlling a data path between the shared memory area and the port units to perform a data communication between the processors through the shared memory area. | 08-27-2009 |
20090240895 | SYSTEMS AND METHODS FOR COALESCING MEMORY ACCESSES OF PARALLEL THREADS - One embodiment of the present invention sets forth a technique for efficiently and flexibly performing coalesced memory accesses for a thread group. For each read application request that services a thread group, the core interface generates one pending request table (PRT) entry and one or more memory access requests. The core interface determines the number of memory access requests and the size of each memory access request based on the spread of the memory access addresses in the application request. Each memory access request specifies the particular threads that the memory access request services. The PRT entry tracks the number of pending memory access requests. As the memory interface completes each memory access request, the core interface uses information in the memory access request and the corresponding PRT entry to route the returned data. When all the memory access requests associated with a particular PRT entry are complete, the core interface satisfies the corresponding application request and frees the PRT entry. | 09-24-2009 |
20090240896 | MICROPROCESSOR COUPLED TO MULTI-PORT MEMORY - A microprocessor being coupled to a dual-port memory is disclosed. The microprocessor has two or more external memory controllers, being coupled to a system bus. Each of the external memory controllers can be individually coupled to an external memory through its respective port. With the present invention, a plurality of elements (e.g. process module) can access the external memory at the same time, enabling a quick process of data. | 09-24-2009 |
20090240897 | Multi-port memory and system using the same - A multi-port memory, comprising: a memory array made of a plurality of memory cells arranged at intersection points between a plurality of bit lines and a plurality of word lines, the memory array being divided into n (an integer of 2 or greater) memory banks; m (an integer of 2 or greater) input/output ports, each independently performing input and output of a command, an address, data to and from each of the memory banks; and a route switching circuit that sets signal for the command, address, and data between the memory banks and the input/output ports, the route switching circuit controlling a connection state of signal lines between the plurality of input/output ports and the plurality of memory banks. | 09-24-2009 |
20090248993 | MULTIPORT MEMORY AND INFORMATION PROCESSING SYSTEM - In an information processing system, a plurality of information processing devices CHIP | 10-01-2009 |
20090265513 | SOLID STATE DISK CONTROLLER APPARATUS - A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus. | 10-22-2009 |
20090276582 | External Memory Controller Node - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 11-05-2009 |
20090276583 | External Memory Controller Node - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 11-05-2009 |
20090276584 | External Memory Controller Node - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 11-05-2009 |
20090307437 | Multiport Memory Architecture, Devices and Systems Including the Same, and Methods of Using the Same - A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses. | 12-10-2009 |
20090313440 | SHARED MEMORY BURST COMMUNICATIONS - A method and apparatus are provided for sharing multipath-accessible memory between a plurality of processors, the method including connecting the plurality of processors in read/write communication to a same shared memory region; connecting the plurality of processors in read communication to a same semaphore area; selectably connecting one of the plurality of processors in write communication to the same semaphore area; exchanging shared memory access command messages between two processors for negotiating access to the same shared memory region; and storing protected variables indicative of the currently negotiated access to the same shared memory region in the same semaphore area, wherein the shared memory region has a channel relative to each processor, each channel having at least one buffer disposed for transferring a plurality of data packets in a burst mode. | 12-17-2009 |
20100023705 | PROCESSOR ARCHITECTURE HAVING MULTI-PORTED MEMORY - A data processing system includes a multiport memory module including a plurality of first ports and a plurality of second ports. The data processing system includes a plurality of first buses and a plurality of second buses. A plurality of hardware acceleration modules configured to communicate with respective ones of the plurality of first ports via respective ones of the plurality of first buses. The data processing system includes a processor module. A random access memory (RAM) module configured to store data. The processor module and the RAM module communicate with the multiport memory module via respective ones of the plurality of second buses. A shared bus includes a first bus portion configured to communicate with the plurality of hardware acceleration modules at a first rate. A second bus portion configured to communicate with the processor module and the RAM module at a second rate that is different than the first rate. A bus bridge that communicates with the first bus portion and the second bus portion. | 01-28-2010 |
20100077157 | MULTI MASTER DRAM ARCHITECTURE - Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, the memory device may be a package comprising a plurality of stacked memory dies. | 03-25-2010 |
20100088475 | DATA PROCESSING WITH A PLURALITY OF MEMORY BANKS - A data processing circuit comprises an instruction execution circuit ( | 04-08-2010 |
20100106917 | METHOD AND SYSTEM FOR IMPROVING SERIAL PORT MEMORY COMMUNICATION LATENCY AND RELIABILITY - A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval. | 04-29-2010 |
20100169583 | MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE - A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks. | 07-01-2010 |
20100205383 | Memory Controller for Improved Read Port Selection in a Memory Mirrored System - The present invention describes improving the scheduling of read commands on a mirrored memory computer system by utilizing information about pending memory access requests. A conflict queue is configured to track a read/write queue associated with each of a plurality of memory ports on the mirrored memory system. The conflict queue determines a predicted latency on each memory port based on the contents of each of the read/write queues. A compare logic unit is coupled to the conflict queue, wherein the compare logic unit compares a predicted latency of a primary memory and a mirrored memory and schedules read commands to the memory port with the lowest predicted latency. | 08-12-2010 |
20100228926 | MULTI-PORT MEMORY DEVICES AND METHODS - An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion. | 09-09-2010 |
20100235590 | Multi-bank Multi-port Architecture - A memory system including a plurality of ports and a memory core having a plurality of memory banks. Access requests received at the ports are broadcast to the memory banks. Multiple memory banks may be concurrently accessed in response to access requests received on different ports. A memory controller provides the access requests to the memory system, and ensures that a single memory bank is not concurrently accessed by different ports. All access requests are processed with the same latency. If the memory banks include memory cells that must be periodically refreshed, then the memory controller also provides refresh requests to the memory banks. Because multiple memory banks may be concurrently accessed in response to access requests provided on different ports, the memory banks can operate at a lower frequency than the ports. | 09-16-2010 |
20100250865 | Self-Timing For A Multi-Ported Memory System - Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present disclosure employ self-timing for such operational synchronization. According to certain embodiments, self-timing is employed to synchronize all the internal events within the memory so that all the events are spaced in time for appropriate synchronization. For instance, the completion of one event leads to triggering another event, the completion of which leads to triggering another event, and so on. Thus, in one embodiment, the self-timing is achieved by referencing the operational events with the memory (or register file) to each other, rather than to a reference clock duty cycle. | 09-30-2010 |
20100281227 | MULTI-PORT MEMORY DEVICES AND METHODS - Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks. | 11-04-2010 |
20100318749 | SCALABLE MULTI-BANK MEMORY ARCHITECTURE - According to one general aspect, a method may include, in one embodiment, grouping a plurality of at least single-ported memory banks together to substantially act as a single at least dual-ported aggregated memory element. In various embodiments, the method may also include controlling read access to the memory banks such that a read operation may occur from any memory bank in which data is stored. In some embodiments, the method may include controlling write access to the memory banks such that a write operation may occur to any memory bank which is not being accessed by a read operation. | 12-16-2010 |
20100325370 | SHARED-MEMORY SWITCH FABRIC ARCHITECTURE - A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is configured to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of frames of data in the shared memory by sequentially querying the plurality of ports for the frames of data, and arbitrating among a subset of the ports having the frames of data to assign starting locations in the memory banks such that the shared memory is fully provisioned for all of the ports simultaneously operating at the maximum port data rate. | 12-23-2010 |
20110004734 | SYSTEM AND METHOD FOR PROVIDING MORE LOGICAL MEMORY PORTS THAN PHYSICAL MEMORY PORTS - Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle. | 01-06-2011 |
20110055491 | SIMULTANEOUS SWITCHING OF MULTIPLE TIME SLOTS IN AN OPTICAL NETWORK NODE - A switching frame buffer is described in which data units within a sequence of time slots, of a frame, may be simultaneously input and output at ports of the switching frame buffer. In one implementation, a write port may receive data units within a single cycle of the switch. A number of memories may be provided, where first selected ones of the memories constitute memory groups and second selected ones of the memories constitute a memory subsets, each of the memory groups including a corresponding one of the memory subsets. The write port may supply each of a number of copies of the data units to a corresponding one of the memory subsets. Multiplexers may be associated with the groups of the memories and a read port may receive one of the copies of a number of the data units from different ones of the multiplexers. | 03-03-2011 |
20110055492 | MULTIPLE PROCESSING CORE DATA SORTING - Sorting data using a multi-core processing system is disclosed. An unsorted data set is copied from a global memory device to a shared memory device. The global memory device can store data sets for the multi-core processing system. The shared memory device can store unsorted data sets for sorting. The unsorted data set can include a plurality of data elements. The unsorted data set can be sorted into sorted data in parallel on the shared memory device using a cluster of processors of the multi-core processing system. The cluster of processors may include at least as many processors as a number of the data elements in the unsorted data set. The sorted data can be copied from the shared memory device to the global memory device. | 03-03-2011 |
20110087847 | MULTIPLE-PORT MEMORY SYSTEMS AND METHODS - Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition. | 04-14-2011 |
20110138133 | Variable-Width Memory Module and Buffer - A memory module having a plurality of memory devices and a memory buffer that translates between a variable width primary data port and a plurality of fixed width secondary data ports, each of which is coupled to one of the memory devices. The translation is effected by distributing the width of the primary data port to all or to a subset of the secondary data ports. In another aspect, the invention comprises a memory buffer that supports adjustable data width in a variety of ways. | 06-09-2011 |
20110153959 | IMPLEMENTING DATA STORAGE AND DUAL PORT, DUAL-ELEMENT STORAGE DEVICE - A method for implementing data storage and a dual port, dual element storage device are provided. A storage device includes a predefined form factor including a first port and a second port, and a first storage element and a second storage element. A controller coupled between the first port and second port, and the first storage element and second storage element controls access and provides two separate data paths to the first storage element and second storage element. | 06-23-2011 |
20110225374 | SELF-ADJUSTING SCSI STORAGE PORT QUEUE - A method for managing storage space in a storage port queue includes establishing a watermark for the storage port queue. The method further receives, at the storage port associated with the storage port queue, a command having an initiator-target-LUN (ITL) nexus associated therewith. Upon receiving the command, the method determines whether the used space in the storage port queue has reached the watermark. In the event the used space has not reached the watermark, the method processes the command. In the event the used space has reached the watermark and a specified number of commands for the ITL nexus are already present in the storage port queue, the method rejects the command. Otherwise, the method may process the command. A corresponding apparatus and computer program product are also disclosed herein. | 09-15-2011 |
20110276766 | CONFIGURABLE MEMORY CONTROLLER - Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits. | 11-10-2011 |
20110302376 | TWO-PORT MEMORY CAPABLE OF SIMULTANEOUS READ AND WRITE - Described embodiments provide a multi-port memory system that has a plurality of memory banks and an equal number of mapping memory banks, each one of the data memory banks corresponding to one of the mapping memory banks. The multi-port memory reads, from one of the mapping memory banks selected by a read logical bank number, a read physical bank number identifying which one of the data memory banks data is to be read. The memory system also calculates, from at least one physical bank number read from the mapping memory banks other than the mapping memory bank selected by the read logical bank number, a write physical bank number indicating which one of the data memory banks is to be written. The calculation uses a hash of the physical bank numbers, such as by using an Exclusive-OR. This arrangement allows for simultaneous read/write access of the memory with fixed latency. | 12-08-2011 |
20120072677 | Multi-Ported Memory Controller with Ports Associated with Traffic Classes - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline. | 03-22-2012 |
20120089788 | STORAGE CONTROL APPARATUS AND STORAGE CONTROL APPARATUS CONTROL METHOD - A protocol chip and a communication conversion circuit are provided in a channel adapter package that is in charge of communications with a host. The communication conversion circuit communicates with the protocol chip using a procedure that conforms to a communication protocol. The communication conversion circuit communicates with a microprocessor using a procedure that is common to multiple communication protocols. It appears from the microprocessor as though communications are being carried out with the same type of channel adapter package. | 04-12-2012 |
20120144128 | CUSTOM ATOMICS USING AN OFF-CHIP SPECIAL PURPOSE PROCESSOR - An apparatus for executing an atomic memory transaction comprises a processing core in a multi-processing core system, where the processing core is configured to store an atomic program in a cache line. The apparatus further comprises an atomic program execution unit that is configured to execute the atomic program as a single atomic memory transaction with a guarantee of forward progress. | 06-07-2012 |
20120159089 | Integrated device - An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access. An input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros. As connection interconnects, command information interconnects and data interconnects are included. The command information interconnects are formed by private interconnects, while the data interconnects are formed by private interconnects for at least the second direction interconnects. | 06-21-2012 |
20120166739 | MEMORY MODULE AND METHOD FOR ATOMIC OPERATIONS IN A MULTI-LEVEL MEMORY STRUCTURE - A memory module and a corresponding method for handling atomic operations in a multi-level memory system (MLMS) are provided. The memory module receives load and store operations of the atomic operations from a data processing engine (DPE) or an upper level memory module (ULMM). The memory module logs the load operation and/or forward the load operation to a lower level memory module (LLMM) according to predetermined conditions such as cacheability or whether there is a data hit or not. In addition, the memory module executes the store operation, inhibits the store operation, or forwards the store operation to an LLMM according to predetermined conditions such as cacheability, data hit, or whether there is a matching load operation logged in the memory module. The memory module and the method ensure correct, consistent and efficient execution of atomic operations for all DPEs sharing the MLMS. | 06-28-2012 |
20120191921 | EXPANDABLE ASYMMETRIC-CHANNEL MEMORY SYSTEM - An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket. | 07-26-2012 |
20120198179 | AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE - A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure. | 08-02-2012 |
20130019069 | MULTI-CORE PROCESSOR SYSTEM, MEMORY CONTROLLER CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a memory controller that includes multiple ports and shared memory that includes physical address spaces divided among the ports. A CPU acquires from a parallel degree information table, the number of CPUs to which software that is to be executed by the multi-core processor system, is to be assigned. After this acquisition, the CPU determines the CPUs to which the software to be executed is to be assigned and sets for each CPU, physical address spaces corresponding to logical address spaces defined by the software to be executed. After this setting, the CPU notifies an address converter of the addresses and notifies the software to be executed of the start of execution. | 01-17-2013 |
20130031315 | MULTI-DEVICE MEMORY SERIAL ARCHITECTURE - Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second port to interface with yet another memory device, and a switch to selectively electrically connect the memory controller to a circuit path leading to the second port or to the memory array, wherein the switch may be responsive to a signal generated by the memory controller. | 01-31-2013 |
20130031316 | SYSTEM AND METHOD FOR PROVIDING MORE LOGICAL MEMORY PORTS THAN PHYSICAL MEMORY PORTS - Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle. | 01-31-2013 |
20130036274 | ON-CHIP MEMORY (OCM) PHYSICAL BANK PARALLELISM - According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle. | 02-07-2013 |
20130067173 | METHOD AND APPARATUS FOR MULTIPLE ACCESS OF PLURAL MEMORY BANKS - A processor with on-chip memory including a plurality of physical memory banks is disclosed. The processor includes a method, and corresponding apparatus, of enabling multi-access to the plurality of physical memory banks The method comprises selecting a subset of multiple access requests to be executed in at least one clock cycle over at least one of a number of access ports connected to the plurality of physical memory banks, the selected subset of access requests addressed to different physical memory banks, among the plurality of memory banks, and scheduling the selected subset of access requests, each over a separate access port. | 03-14-2013 |
20130086332 | Task Queuing in a Multi-Flow Network Processor Architecture - Described embodiments generate tasks corresponding to each packet received by a network processor. A destination processing module receives a task and determines, based on the task size, a queue in which to store the task, and whether the task is larger than space available within a current memory block of the queue. If the task is larger, an address of a next memory block in a memory is determined, and the address is provided to a source processing module of the task. The source processing module writes the task to the memory based on a provided offset address and the address of the next memory block, if provided. If a task is written to more than one memory block, the destination processing module preloads the address of the next memory block to a local memory to process queued tasks without stalling to retrieve the address of the next memory block. | 04-04-2013 |
20130097390 | Memory controller and methods - A memory controller that allows shared access to a memory device via a plurality of write ports and read ports. | 04-18-2013 |
20130145107 | IDLE POWER CONTROL IN MULTI-DISPLAY SYSTEMS - A system and method for reducing power consumption of a video subsystem. A computer system includes multiple display devices supported by a graphics processor. A memory for storing video data for the multiple display devices utilizes multiple channels for higher bandwidth. A systems controller within the graphics processor determines a retraining condition, such as an idle power state, is satisfied for one or more channels of the multiple memory channels. The graphics processor divides each respective screen for the multiple display devices into multiple horizontal bars. For each one of the multiple horizontal bars, the corresponding data may be rearranged from being distributed across the multiple channels to being stored in a single one of the multiple channels. The systems controller determines a given channel is an upcoming free channel. This free channel is retrained while it is free. Retraining may include at least reducing its memory clock (MCLK) frequency. | 06-06-2013 |
20130173865 | REGISTER FILE ORGANIZATION TO SHARE PROCESS CONTEXT FOR HETEROGENEOUS MULTIPLE PROCESSORS OR JOINT PROCESSOR - A register file organization is used to support multiple accesses from more than one processor or pipeline. This shared register file is organized for a multiple processor device that includes a high performance (HP) and a low power (LP) core. The shared register file includes separate HP and LP storage units coupled to separate HP and LP write and read ports. | 07-04-2013 |
20130191604 | MEMORY ACCESS FOR DIGITAL SIGNAL PROCESSING - Memory access in a digital signal processing system is described. In one example, the digital signal processing system comprises a multi-port memory that is constructed from a memory interface connected to a number of single-port memory devices. The memory interface provides access ports that processors can use to access data stored on the single-port memory devices using a single address space. A processor can be connected to several access ports, and use these to request access to data at several different memory addresses at the same time. The digital signal processing system is configured such that the total number of single-port memory devices connected to the memory interface is a prime number greater than or equal to three. Because a prime number of memory devices are used, the likelihood of the data for the different memory addresses being on the same single-port memory device is minimised, increasing memory access speed. | 07-25-2013 |
20130205100 | MULTI-PORT MEMORY BASED ON DRAM CORE - A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports. | 08-08-2013 |
20130227223 | LATCHING PSEUDO-DUAL-PORT MEMORY MULTIPLEXER - A pseudo-dual-port (PDP) memory system includes a memory array, timing and control logic, and multiplexer-latch (MUX-latch). The MUX-latch comprises integrated address selection logic and latching logic, such that the combination multiplexes and latches an address in a single change in response to a state change in the read select or write select signals. The multiplexing and latching defines a single operation or state change in the MUX-latch. Since the multiplexing delay and the latching delay for a read operation are coincident with each other rather than being incurred one after the other, memory read operations are fast. | 08-29-2013 |
20130282991 | METHOD AND SYSTEM FOR IMPROVING SERIAL PORT MEMORY COMMUNICATION LATENCY AND RELIABILITY - A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval. | 10-24-2013 |
20130290646 | FIFO BUFFER SYSTEM PROVIDING SAME CLOCK CYCLE RESPONSE TO POP COMMANDS - A first-in first-out (FIFO) buffer system includes FIFO control logic and first and second storage partitions. Each storage partition includes a corresponding single-port memory bank and a prefetch buffer. The FIFO control logic alternates processing of PUSH commands between the first and second storage partitions. Additionally, the FIFO control logic anticipates POP commands based on the FIFO order and the alternating PUSH arrangement by initiating prefetches of data so that data to be accessed by a POP command is available at either the prefetch buffer (if the prefetch has completed) or the output of the single-port memory bank (if the prefetch has not yet completed) of the corresponding storage partition at the time the POP command is received, thereby enabling the output of the data for the POP command in the same clock cycle in which the POP command is received. | 10-31-2013 |
20130290647 | INFORMATION-PROCESSING DEVICE - According to one embodiment, a memory device is connectable to a host device. The memory device includes a first interface unit, a controller unit, a second memory and a second interface. The first interface unit receives a write command from the host device. The controller unit acquires the write-data associated with the write command stored in a first memory area of a first memory in the host device, the write-data being copied from a second memory area of the first memory. The second interface causes the second memory to write the write-data in the second memory. | 10-31-2013 |
20130297890 | MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS - A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system. | 11-07-2013 |
20130311727 | MEMORY CONTROL METHOD AND SYSTEM - A memory control method includes assigning based on a table to which an allocated device that executes a first process in a first application is registered, the first process in the first application to the allocated device registered; notifying a port connector of identification information of a port of memory, the port to be used by the first application, and registering a number of the port into the table; and allocating a storage area to the port and registering an address of the storage area into the table. | 11-21-2013 |
20130346706 | DATA READING/WRITING METHOD AND MEMORY DEVICE - A data reading/writing method is provided and includes: determining an active memory lookup table, and a standby memory lookup table; taking a plurality of memory units as a unit, and initializing a memory unit that corresponds to each unit in the active memory lookup table and the standby memory lookup table to a different value; and when a reading operation and a writing operation exist simultaneously, and a value corresponding to a reading address is equal to a value corresponding to a writing address in the active memory lookup table, reading data from an effective single-port memory that is indicated by the reading address and in the active memory lookup table, writing data into a standby single-port memory that is indicated by the writing address and in the standby memory lookup table, and identifying single-port memories where effective data and idle data of the writing address are located. | 12-26-2013 |
20140006725 | STORAGE VIRTUALIZATION APPARATUS AND STORAGE VIRTUALIZATION METHOD | 01-02-2014 |
20140013061 | System And Method To Reduce Memory Access Latencies Using Selective Replication Across Multiple Memory Ports - In one embodiment, a system comprises a plurality of memory ports. The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index. The system further comprises a first address hashing unit configured to receive a request including at least one virtual memory address. Each virtual memory address is associated with a replication factor, and the virtual memory address refers to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address. The hardware based address refers to data in the memory ports within a subset indicated by the corresponding subset index. | 01-09-2014 |
20140025902 | HANDLING COLLISIONS BETWEEN ACCESSES IN MULTIPORT MEMORIES - A multiport memory having an array of storage cells for storing data; a plurality of data access ports; and access control circuitry to assign each data access port to one of the sets of access control lines and corresponding data lines. The control circuitry has collision detection circuitry to detect a colliding data access request received at a second data access port that requests access to a row of storage cells currently being accessed by a data access request received at a first data access port. The control circuitry is responsive to the detected collision to assign the set of access control lines and corresponding data lines currently assigned to the first data access port to the second data access port and to subsequently assign the first data access port to the set of access control lines and corresponding data lines previously assigned to the second access port. | 01-23-2014 |
20140047197 | MULTIPORT MEMORY EMULATION USING SINGLE-PORT MEMORY DEVICES - A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks. An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal. Simultaneous read and write operations are possible. | 02-13-2014 |
20140052934 | Memory with Alternative Command Interfaces - A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose. | 02-20-2014 |
20140052935 | SCALABLE MULTI-BANK MEMORY ARCHITECTURE - According to one general aspect, a method may include, in one embodiment, grouping a plurality of at least single-ported memory banks together to substantially act as a single at least dual-ported aggregated memory element. In various embodiments, the method may also include controlling read access to the memory banks such that a read operation may occur from any memory bank in which data is stored. In some embodiments, the method may include controlling write access to the memory banks such that a write operation may occur to any memory bank which is not being accessed by a read operation. | 02-20-2014 |
20140115277 | METHOD AND APPARATUS FOR OFFLOADING STORAGE WORKLOAD - Exemplary embodiments provide a technique to offload storage workload. In one aspect, a computer comprises: a memory; and a controller operable to manage a relationship among port information of an initiator port, information of a logical volume storing data from the initiator port, and port information of a target port to be used for storing data from the initiator port to the logical volume, and to cause another computer to process a storage function of a storage system including the logical volume and the target port by creating a virtual machine for executing the storage function and by configuring the relationship on said another computer, said another computer sending the data to the logical volume of the storage system after executing the storage function. In specific embodiments, by executing the storage function on said another computer, the workload of executing the storage function on the storage system is eliminated. | 04-24-2014 |
20140143511 | INTERFACE CONVERSION DEVICE AND STORAGE DEVICE USING THE SAME - An interface conversion device, applicable to a storage device, includes a first connection port, a second connection port, a measuring unit and a processing unit. The first connection port transmits a first signal and a power signal via a first communication interface. The second connection port transmits a second signal and the power signal to the storage device via a second communication interface. The first communication interface and the second communication interface are different from each other. The measuring unit receives the power signal from the first connection port to measure the power signal and produce a measurement signal. The measuring unit outputs the power signal to the second connection port. The processing unit receives and converts the first signal into the second signal and outputs the second signal via the second connection port. The processing unit receives the measurement signal to calculate a power consumption value. | 05-22-2014 |
20140215164 | Multiport Memory Architecture - The present disclosure describes techniques and apparatuses for multiport memory architecture. In some aspects serial data is received from a data port and converted to n-bit-wide words of data. The n-bit-wide words of data are then buffered as a k-word-long block of parallel data into a line of a multiline buffer as a block of k*n bits of data. The block of k*n bits of data is then transmitted to a multiport memory via a write bus effective to write the block of k*n bits of data to the multiport memory. | 07-31-2014 |
20140258644 | TRANSACTIONAL MEMORY THAT PERFORMS AN ATOMIC METERING COMMAND - A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC, the TM pulls an input value (IV). The TM uses the memory address to read a word including multiple credit values from a memory unit. Circuitry within the TM selects a pair of credit values, subtracts the IV from each of the pair of credit values thereby generating a pair of decremented credit values, compares the pair of decremented credit values with a threshold value, respectively, thereby generating a pair of indicator values, performs a lookup based upon the pair of indicator values and the meter pair indicator value, and outputs a selector value and a result value that represents a meter color. The selector value determines the credit values written back to the memory unit. | 09-11-2014 |
20140281283 | DUAL HOST EMBEDDED SHARED DEVICE CONTROLLER - Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data. | 09-18-2014 |
20140281284 | MULTI-READ PORT MEMORY - A method includes receiving a multi-port read request for retrieval of data stored in three memories, each comprising two memory modules and a parity module. The multi-port read request is associated with first data stored at a first memory address, second data stored at a second memory address, and third data stored at a third memory address. When the first memory address, the second memory address, and the third memory address are associated with a first memory module, first data is retrieved from the first memory module, second data is reconstructed using data from a second memory module and a first parity module, and third data is reconstructed using data from a fourth memory module and a seventh memory module. The first data, the second data, and the third data are provided in response to the multi-port read request. | 09-18-2014 |
20140281285 | REGISTER FILE DEVICE - A register file device includes: a multi-port latch; and a write circuit that generates a signal to be written in the multi-port latch, the write circuit generating the signal on the basis of a plurality of data groups each including a write control signal, a write address, and a piece of write data, wherein the write circuit includes: a detection circuit that detects at least two write control signals occurred simultaneously among write control signals, and a changing circuit that changes write data corresponding to one of the write control signal to become same as write data corresponding to another of the write control signal. | 09-18-2014 |
20140289482 | MULTI-PORT MEMORY AND OPERATION - Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications. | 09-25-2014 |
20140310482 | System And Method For Storing Multiple Copies of Data In A High Speed Memory System - A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by storing a second encoded copy of data in a multi-port XOR memory bank. | 10-16-2014 |
20140351526 | DATA STORAGE CONTROLLER WITH MULTIPLE PIPELINES - Techniques are disclosed relating to processing data in a storage controller. In one embodiment, a method includes receiving data at a storage controller of a storage device. The method further includes processing data units of the data in parallel via a plurality of write pipelines in the storage controller. The method further includes writing the data units to a storage medium of the storage device. In some embodiments, the method may include inserting header information into the data for a plurality of data units before processing, and the header information may include sequence information. In some embodiments, writing the data units may include writing according to a sequence determined prior to processing the data units. | 11-27-2014 |
20150026418 | SYSTEM AND METHOD FOR INCREASED CAPACITY AND SCALABILITY OF A MEMORY TOPOLOGY - A system and method for serial interface topologies is disclosed. A serial interface topology includes a replication device configured to receive control information from a controller interface. The replication device is configured to transmit two or more copies of substantially replicated control information to a device control interface. A data interface is configured to provide differential, point-to-point communication of data with the device controller interface. | 01-22-2015 |
20150032975 | Method and System for Improving Serial Port Memory Communication Latency and Reliability - A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval. | 01-29-2015 |
20150058580 | METHOD AND SYSTEM FOR MEMORY OVERSUBSCRIPTION FOR VIRTUAL MACHINES - A method for oversubscribing a host memory of a host running a virtual machine monitor (VMM), comprising, examining a virtual machine (VM) memory for a VM for metadata associated with the VM memory, the metadata maintained by a guest OS running on the VM, collecting the metadata for the VM memory, and managing the VM memory using the metadata for oversubscribing a host memory. | 02-26-2015 |
20150067275 | SINGLE PORT MEMORY THAT EMULATES DUAL PORT MEMORY - A single-port memory that operates in single-cycle dual-port mode has a logical capacity of N=k·m memory words and (k+1) single-port RAM having an overall physical capacity of (k+1)·m memory words. A status register holds words identifying which RAM bank has the last data at the i | 03-05-2015 |
20150089164 | HIGH CAPACITY MEMORY SYSTEMS - In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends. | 03-26-2015 |
20150143060 | On-Chip Memory (OCM) Physical Bank Parallelism - According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle. | 05-21-2015 |
20150331634 | CONTINUOUS-FLOW CONFLICT-FREE MIXED-RADIX FAST FOURIER TRANSFORM IN MULTI-BANK MEMORY - A method and a processor to perform continuous-flow conflict-free mixed-radix FFT for data in a memory are provided. Multiple butterfly calculations of small radix are launched generally in parallel in mixed-radix FFT using conflict-free address generation with a memory. The multiple butterfly calculations of data entries may be staged in a processor, such that the memory read and write operations may be executed continuously without access conflicts. | 11-19-2015 |
20160070507 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY DEVICE - According to one embodiment, a controller writes data in a first plane among the plurality of planes, and writes management information in a second plane among the plurality of planes. The controller performs a first process of reading first data from the first plane and a second process of reading the management information from the second plane in parallel. The management information is associated with second data to be read on and after next time. | 03-10-2016 |
20160147648 | METHOD AND APPARATUS FOR MEMORY MANAGEMENT - A method and apparatus of memory management are disclosed. Pooling of at least one memory to generate a memory pool, dividing the memory pool to generate at least one memory space, and allocating a respective memory space to a respective CPU in a one-to-one correspondence manner are performed. Further, the respective memory space allocated to the respective CPU is set as a pinned memory of the respective CPU. Additionally, setting unallocated memory space as a shared memory pool, obtaining a memory value that represents usage of the respective memory space by the respective CPU during operation, and determining if the memory value exceeds a preset threshold range are performed. Selecting, if the memory value exceeds the preset threshold range, additional memory space from the memory pool to allocate to the respective CPU or reallocating at least a portion of the respective memory space allocated to the CPU are performed. | 05-26-2016 |
20190147923 | MULTI-PORT STORAGE-CLASS MEMORY INTERFACE | 05-16-2019 |