| Entries |
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| 20080209120 | Accelerating cache performance by active cache validation - Described is a technology by which a web proxy server evaluates its cached objects, and when an object is invalid, performs a freshness check on that object, independent of any client requests. As a result, the cache contains objects that have a greater likelihood of being fresh when requested by a client. By scanning a web cache data structure to determine whether corresponding cached content is still valid, and sending a freshness check to a web server when the content is not valid, the cache is kept up to date. The scanning may be periodic or based upon some other triggering event, and all of the cache's corresponding entries may be scanned, or some smaller subset of the entries. In one example implementation, a web proxy server that contains the cache includes a freshness check mechanism that scans and keeps the cached objects up to date. | 08-28-2008 |
| 20090013127 | Systems and Methods for Determining Refresh Rate of Memory Based on RF Activities - Systems and methods for determining a refresh rate of volatile memory are provided. In this regard, a representative system, among others, includes a radio frequency (RF) device; a computing device that communicates with the RF device, the computing device including a refresh manager that monitors activities of the RF device; and volatile memory that communicates with the refresh manager of the computing device, wherein the refresh manager determines a refresh rate of the volatile memory based on the monitored activities of the RF device. A representative method, among others, for determining the refresh rate of volatile memory, includes monitoring activities of a radio frequency (RF) device; and adjusting a refresh rate of volatile memory based on the monitored activities of the RF device. | 01-08-2009 |
| 20090077307 | DRAM selective self refresh - In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described. | 03-19-2009 |
| 20090083479 | MULTIPORT SEMICONDUCTOR MEMORY DEVICE AND ASSOCIATED REFRESH METHOD - A semiconductor memory device used in a multiprocessor system is configured to perform a partial refresh operation based on the state of an access port instead of performing a refresh operation per memory bank via a bank address. The multiprocessor system includes a plurality of processors and the memory device includes a memory cell array and a plurality of ports correspondingly connected to the plurality of processors. The memory cell array includes a plurality of memory areas having predetermined memory capacity. Each of the plurality of memory areas is assigned to at least one of the plurality of ports. Each of the plurality of memory areas is accessed by any one of at least one corresponding processors through a corresponding port. A refresh controller is disposed between the plurality of ports and the plurality of memory areas and is configured to refresh at least one memory area assigned to a port connected to a processor which is in a predetermined operating mode. | 03-26-2009 |
| 20090089494 | Memory control apparatus, memory control method, and computer program - Disclosed herein is a memory control apparatus including a plurality of memory control sections, each of which has connected thereto one or more memories that require periodic refresh and is configured to perform data write, data read, and refresh operations on the one or more memories. The memory control sections issue, to each of the one or more memories, refresh commands at optimum intervals and with arbitrary timing such that commands that consume high power do not conflict with each other. | 04-02-2009 |
| 20090094412 | Concurrently communicating refresh and read/write commands with a memory device - Disclosed are, inter alia, methods, apparatus, computer-readable media, mechanisms, and means for communicating with a memory device, such as by a memory controller, a refresh command at least partially overlapping in time with a read and/or write command. The refresh command typically specifies a group of locations (e.g., a bank) for being at least partially refreshed. | 04-09-2009 |
| 20090106488 | STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY MEMORY ARRAY AND METHOD EMPLOYING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (DRAM) IN CONJUNCTION WITH A DATA CACHE AND SEPARATE READ AND WRITE REGISTERS AND TAG BLOCKS - A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time. | 04-23-2009 |
| 20090144491 | METHOD AND SYSTEM FOR IMPLEMENTING PRIORITIZED REFRESH OF DRAM BASED CACHE - A method for implementing prioritized refresh of a multiple way, set associative DRAM based cache includes identifying, for each of a plurality of sets of the cache, the existence of a most recently used way that has not been accessed during a current assessment period; and for each set, refreshing only the identified most recently used way of the set not accessed during the current assessment period, while ignoring the remaining ways of the set; wherein a complete examination of each set for most recently used ways therein during the current assessment period constitutes a sweep of the cache. | 06-04-2009 |
| 20090144492 | STRUCTURE FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED CACHE - A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache. | 06-04-2009 |
| 20090193186 | EMBEDDED DRAM HAVING MULTI-USE REFRESH CYCLES - An embedded DRAM (eDRAM) having multi-use refresh cycles is described. In one embodiment, there is a multi-level cache memory system that comprises a pending write queue configured to receive pending prefetch operations from at least one of the levels of cache. A prefetch queue is configured to receive prefetch operations for at least one of the levels of cache. A refresh controller is configured to determine addresses within each level of cache that are due for a refresh. The refresh controller is configured to assert a refresh write-in signal to write data supplied from the pending write queue specified for an address due for a refresh rather than refresh existing data. The refresh controller asserts the refresh write-in signal in response to a determination that there is pending data to supply to the address specified to have the refresh. The refresh controller is further configured to assert a refresh read-out signal to send refreshed data to the prefetch queue of a higher level of cache as a prefetch operation in response to a determination that the refreshed data is useful. | 07-30-2009 |
| 20090193187 | DESIGN STRUCTURE FOR AN EMBEDDED DRAM HAVING MULTI-USE REFRESH CYCLES - A design structure for an embedded DRAM (eDRAM) having multi-use refresh cycles is described. In one embodiment, there is a multi-level cache memory system that comprises a pending write queue configured to receive pending prefetch operations from at least one of the levels of cache. A prefetch queue is configured to receive prefetch operations for at least one of the levels of cache. A refresh controller is configured to determine addresses within each level of cache that are due for a refresh. The refresh controller is configured to assert a refresh write-in signal to write data supplied from the pending write queue specified for an address due for a refresh rather than refresh existing data. The refresh controller asserts the refresh write-in signal in response to a determination that there is pending data to supply to the address specified to have the refresh. The refresh controller is further configured to assert a refresh read-out signal to send refreshed data to the prefetch queue of a higher level of cache as a prefetch operation in response to a determination that the refreshed data is useful. | 07-30-2009 |
| 20090204753 | SYSTEM FOR REFRESHING CACHE RESULTS - A system and method for refreshing a cache based on query responses provided by a searching system in response to queries, includes providing a cache entry for each unique query, if space is available in the cache, and assigning a temperature value to each cache entry based on a frequency of occurrence of the corresponding query An age value is assigned to each cache entry based on a time of last refresh or creation of the corresponding query response. The age of the cache entries is periodically updated, and the temperature of a cache entry is updated when a corresponding query reoccurs. If system resources are available, the query response of a cache entry is refreshed based on the temperature and age of the cache entry. If resources are not available, the refreshing is limited. | 08-13-2009 |
| 20090235020 | VARIOUS METHODS AND APPARATUS FOR ADDRESS TILING - Various methods and apparatus are described for a memory scheduler. The memory scheduler couples to a target memory core that includes a bank of memories. The memory scheduler contains two or more configurable address tiling functions to transform an incoming address of data requested in a request to the target memory core to determine what physical addresses in the bank of memories will service the first request. The two or more configurable address tiling functions are programmable by a user to create two or more distinctly different memory regions in the target memory core. Each memory region has its own distinct tiling function based on configuration parameters 1) selected by the user and 2) stored in tiling registers in the memory scheduler. The multiple tiling functions are configured to operate concurrently in the integrated circuit. | 09-17-2009 |
| 20090248972 | Dynamic Memory Supporting Simultaneous Refresh and Data-Access Transactions - Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions. | 10-01-2009 |
| 20090271569 | PARTITIONED MANAGEMENT DATA CACHE - A system and method for decreasing system management data access time. A system includes a device, a cache memory coupled to the device, and a cache memory refresh controller. The device provides system management information. The cache memory stores system management information. The system management information stored in the cache is partitioned into a first portion and a second portion. The cache refresh program refreshes the system management information stored in the cache memory. The first portion is refreshed after expiration of a predetermined refresh time interval. The second portion is refreshed when the second portion is accessed. | 10-29-2009 |
| 20090282189 | MEMORY CONTROLLER WITH REFRESH LOGIC TO ACCOMODATE LOW-RETENTION STORAGE ROWS IN A MEMORY DEVICE - A memory controller is disclosed that provides refresh control circuitry to generate first refresh commands directed to a first row of storage cells within a memory device at a first rate. The refresh control circuitry generates second refresh commands directed to a second row of storage cells within the memory device at a second rate. Output circuitry outputs the first and second refresh commands to the memory device. | 11-12-2009 |
| 20100064101 | MEMORY CONTROLLER AND DATA PROCESSING SYSTEM - A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption. | 03-11-2010 |
| 20100077140 | SCALABLE SCHEDULERS FOR MEMORY CONTROLLERS - Methods and apparatus to improve throughput and efficiency in memory devices are described. In one embodiment, a memory controller may include scheduler logic to issue read or write requests to a memory device in an optimal fashion, e.g., to maximize bandwidth and/or reduce latency. Other embodiments are also disclosed and claimed. | 03-25-2010 |
| 20100095058 | INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF AUTOMATIC INTERNAL REFRESH OF MEMORY ARRAY - A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No on-board cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle. | 04-15-2010 |
| 20100106901 | MEMORY REFRESHING APPARATUS AND METHOD FOR MEMORY REFRESH - The optimization of a refresh cycle is carried out in harmony with the error occurrence state in the memory with the presence of a normal patrol controlling section controlling a normal patrol operation that patrols the memory; an additional patrol controlling section controlling an additional patrol operation that patrols, if a first error in the memory is detected during the normal patrol operation, an error occurring area in which the first error occurs and which is included in the memory; a measuring section ( | 04-29-2010 |
| 20100146201 | MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM - Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks. | 06-10-2010 |
| 20100262769 | METHOD AND CIRCUIT FOR ADJUSTING A SELF-REFRESH RATE TO MAINTAIN DYNAMIC DATA AT LOW SUPPLY VOLTAGES - A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The method includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor. | 10-14-2010 |
| 20100274960 | MEMORY CONTROL METHOD OF MEMORY DEVICE AND MEMORY CONTROL SYSTEM THEREOF - One exemplary memory control method of a memory device includes: determining at least a physical row partition including a plurality of physical rows selected from the memory device; and for each physical row partition, mapping interleaved virtual rows to the selected physical rows. Each physical row partition is a portion of the memory device. Bank addresses of adjacent virtual rows are different. Another exemplary memory control method of a memory device includes: assigning an indicator to each physical row partition in the memory device for indicating if the corresponding physical row partition is to be refreshed; and controlling a partial refresh operation of the memory device according to the indicator of each physical row partition. Each physical row partition is a portion of the memory device. | 10-28-2010 |
| 20100287336 | EXTERNAL I/O SIGNAL AND DRAM REFRESH SIGNAL SYNCHRONIZATION METHOD AND ITS CIRCUIT - In an LSI that determines timing of DRAM refresh by a refresh timer to synchronize an external I/O signal and DRAM refresh timing with each other, a circuit configuration capable of controlling a value of the refresh timer by a CPU at arbitrary timing is employed. Alternatively, a circuit configuration capable of controlling the value of the refresh timer at arbitrary timing by an external terminal, or a circuit configuration capable of controlling the refresh timing directly from the external terminal without through the refresh timer. | 11-11-2010 |
| 20100293326 | MEMORY DEVICE CONTROL FOR SELF-REFRESH MODE - To ensure that a memory device operates in self-refresh mode, the memory controller includes (1) a normal-mode output buffer for driving a clock enable signal CKE onto the memory device's CKE input and (2) a power island for driving a clock enable signal CKE_prime onto that same input. To power down the memory controller, the normal-mode output buffer drives signal CKE low, then the power island drives signal CKE_prime low, then the memory controller (except for the power island) is powered down. The power island continues to drive the memory device's CKE input low to ensure that the memory device stays in self-refresh mode while the memory controller is powered substantially off. To resume normal operations, the power module powers up the memory controller, then the normal-mode output buffer drives signal CKE low, then the power island is disabled, then the memory controller resumes normal operations of the memory device. | 11-18-2010 |
| 20100318733 | Memory system performing refresh operation - The memory system includes a memory cell array including a plurality of memory sectors and a controller configured to write data in the memory cell array in response to a writing signal. The controller is configured to refresh at least one of the plurality memory sectors when the writing signal is provided. | 12-16-2010 |
| 20110047326 | DRAM SELECTIVE SELF REFRESH - In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described. | 02-24-2011 |
| 20110066798 | Semiconductor device having calibration circuit that adjusts an impedance of output buffer and data processing system including the same - A calibration operation can be performed automatically at a semiconductor device without issuing a calibration command from a controller. Because a calibration operation is performed in response to a fact that the auto refresh command has been issued for a predetermined number of times, a periodical calibration operation can be secured and a read operation or a write operation is not requested from a controller during a calibration operation. | 03-17-2011 |
| 20110087835 | Semiconductor memory device and data processing system - To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation. | 04-14-2011 |
| 20110107022 | REDUCING POWER CONSUMPTION FOR DYNAMIC MEMORIES USING DISTRIBUTED REFRESH CONTROL - A method for refreshing memory is provided. The method comprises determining when a first memory of a plurality of memories is not being accessed and sending a refresh opportunity command from a master refresh controller to one of a plurality of local refresh controllers when the first memory is not being accessed, wherein the one of a plurality of local refresh controllers controls only the first memory. The method further comprises determining when the first memory needs refreshing and refreshing the first memory. | 05-05-2011 |
| 20110131371 | METHOD AND SYSTEM FOR REFRESHING DYNAMIC RANDOM ACCESS MEMORY - A method and system for refreshing DRAM having a plurality of banks, each of the banks including a plurality of rows includes dividing all banks in DRAM into a plurality of groups of banks, each of the groups having n banks, wherein n is an integer greater than or equal to 1. A threshold of available retention time for each group of banks is determined. Each row of banks in each group of banks is refreshed. Refreshing one row of a bank in one group of banks includes determining whether a refresh operation for the row of the bank conflicts with an access operation for the bank where the row of the bank is located. If there is a conflict, then it is determined whether to perform the refresh operation or the access operation for the current row of the bank. If it is determined to perform the access operation, the access operation is continued. If it is determined to perform the recess operation, the current row of the bank is refreshed. DRAM access performance is improved. | 06-02-2011 |
| 20110153927 | Storage Control Device, Electronic Device, and Storage Control Method - According to one embodiment, a storage control device includes a controller, a detector, and a refreshing module. The controller writes image data, which is to be output to a display module, to a storage device and outputs the image data from the storage device to the display module. The detector detects a blanking period during which the controller does not write the image data to the storage device and does not output the image data from the storage device to the display module. The refreshing module refreshes the storage device by rewriting the image data to the storage device at a predetermined time interval if the detector detects a blanking period. | 06-23-2011 |
| 20110161578 | SEMICONDUCTOR MEMORY DEVICE PERFORMING PARTIAL SELF REFRESH AND MEMORY SYSTEM INCLUDING SAME - A semiconductor memory device capable of performing a partial self refresh and semiconductor memory system including same is provided. The semiconductor memory device includes: a memory circuit including a memory array; a skip address storage unit storing an address of an excluded region not requiring refresh in the memory array as a skip address; a refresh address generator providing an address of a region of the memory array requiring refresh as a refresh address; and an address comparator receiving and comparing the skip address and refresh address, and providing a refresh control signal to the memory circuit based on the comparison. | 06-30-2011 |
| 20110161579 | Method and System for Minimizing Impact of Refresh Operations on Volatile Memory Performance - A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly scheduled refresh can be skipped in response to detecting a request for the regularly scheduled refresh. | 06-30-2011 |
| 20110197020 | ELECTRONIC DEVICE - An electronic device includes a memory control circuit that controls a DRAM, and the memory control circuit performs: a first distributed refresh process for issuing refresh commands to the DRAM at a predetermined interval so that storage elements of which the DRAM is configured are refreshed at least once in a predetermined period Ts; a concentrated refresh process for issuing, triggered by a predetermined request to the DRAM, a predetermined number of times Nc of the refresh commands in a burst at an interval that is shorter than the predetermined interval; and a second distributed refresh process for, when the predetermined number of times Nc of refresh commands have been issued, calculating a refresh interval Tr for refreshing remaining storage elements that have not yet been refreshed in the predetermined period Ts and issues refresh commands at the calculated refresh interval Tr. | 08-11-2011 |
| 20110219182 | SYSTEM AND METHOD FOR MANAGING SELF-REFRESH IN A MULTI-RANK MEMORY - Multi-rank memories and methods for self-refreshing multi-rank memories are disclosed. One such multi-rank memory includes a plurality of ranks of memory and self-refresh logic coupled to the plurality of ranks of memory. The self-refresh logic is configured to refresh a first rank of memory in a self-refresh state in response to refreshing a second rank of memory not in a self-refresh state in response to receiving a non-self-refresh refresh command for the second rank of memory. | 09-08-2011 |
| 20110225355 | SEMICONDUCTOR DEVICE, REFRESH CONTROL METHOD THEREOF AND COMPUTER SYSTEM - A semiconductor device comprises a first memory cell array, a register storing information of whether or not one of the word lines in an active state exists in a unit area and storing address information, and a control circuit controlling a refresh operation for a refresh word line based on the information in the register when receiving a refresh request. When the one of the word lines in an active state does not exist, memory cells connected to the refresh word line are refreshed. When the one of the word lines in an active state exists, the one of the word lines in an active state is set into an inactive state temporarily and the memory cells connected to the refresh word line are refreshed after precharging bit lines of the memory cells. | 09-15-2011 |
| 20110246713 | FAST EXIT FROM SELF-REFRESH STATE OF A MEMORY DEVICE - A system provides for a signal to indicate when a memory device exits from self-refresh. Thus, substantially at the same time (before or after) the memory device exits self-refresh, an indicator signal can be triggered to indicate normal operation or standard refresh operation and normal memory access of the memory device. A memory controller can access the indicator signal to determine whether the memory device is in self-refresh. Thus, the memory controller can more carefully manage the timing of sending a command to the memory device while reducing the delay time typically associated with detecting a self-refresh condition. | 10-06-2011 |
| 20110252193 | METHOD TO STAGGER SELF REFRESHES - A system, device, and method for designating a first rank among a plurality of memory ranks of a Memory Module as a primary rank and a second one or more ranks as secondary ranks, triggering, via hardware logic internal to the Memory Module coupled with the plurality of memory ranks, a refresh of the primary rank at a first time (e.g., Time | 10-13-2011 |
| 20110283060 | Maintenance Operations in a DRAM - A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order. | 11-17-2011 |
| 20110296097 | Mechanisms for Reducing DRAM Power Consumption - Mechanisms are provided for inhibiting precharging of memory cells of a dynamic random access memory (DRAM) structure. The mechanisms receive a command for accessing memory cells of the DRAM structure. The mechanisms further determine, based on the command, if precharging the memory cells following accessing the memory cells is to be inhibited. Moreover, the mechanisms send, in response to the determination indicating that precharging the memory cells is to be inhibited, a command to blocking logic of the DRAM structure to block precharging of the memory cells following accessing the memory cells. | 12-01-2011 |
| 20110296098 | System and Method for Reducing Power Consumption of Memory - Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. In accordance with one embodiment of the present disclosure, a method for improving performance and reducing power consumption in memory may include tracking whether individual units of a memory system are active or inactive. The method may also include placing inactive individual units of the memory system in a self-refresh mode, such that the inactive individual units self-refresh their contents. The method may further include placing active individual units of the memory system in a command-based refresh mode, such that the active individual units are refreshed in response to a received command to refresh their contents. | 12-01-2011 |
| 20110314214 | Memory Sharing System and Memory Sharing Method - A memory sharing system includes a master control device, a slave control device and a memory device. The master control device selectively generates a clock signal to the memory device. The slave control device receives and tracks the clock signal via a delay phase locked loop (DLL) to generate and align an output signal with the clock signal. The master control device arbitrates an access right. | 12-22-2011 |
| 20110320699 | System Refresh in Cache Memory - System refresh in a cache memory includes generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory, activating a refresh request at the centralized refresh controller in response to generating the RTIM pulse, the refresh request associated with a single cache memory bank of the cache memory, receiving a refresh grant in response to activating the refresh request, and transmitting the refresh grant to a bank controller, the bank controller associated, and localized, at the single cache memory bank of the cache memory. | 12-29-2011 |
| 20110320700 | Concurrent Refresh In Cache Memory - Concurrent refresh in a cache memory includes calculating a refresh time interval at a centralized refresh controller, the centralized refresh controller being common to all cache memory banks of the cache memory, transmitting a starting time of the refresh time interval to a bank controller, the bank controller being local to, and associated with, only one cache memory bank of the cache memory, sampling a continuous refresh status indicative of a number of refreshes necessary to maintain data within the cache memory bank associated with the bank controller, requesting a gap in a processing pipeline of the cache memory to facilitate the number of refreshes necessary, receiving a refresh grant in response to the requesting, and transmitting an encoded refresh command to the bank controller, the encoded refresh command indicating a number of refresh operations granted to the cache memory bank associated with the bank controller. | 12-29-2011 |
| 20110320701 | OPTIMIZING EDRAM REFRESH RATES IN A HIGH PERFORMANCE CACHE ARCHITECTURE - Optimizing refresh request transmission rates in a high performance cache comprising: a refresh requestor configured to transmit a refresh request to a cache memory at a first refresh rate, the first refresh rate comprising an interval, the interval comprising receiving a plurality of first signals, the first refresh rate corresponding to a maximum refresh rate, and a refresh counter operatively coupled to the refresh requestor and configured to reset in response to receiving a second signal, increment in response to receiving each of a plurality of refresh requests from the refresh requestor, and reset and transmit a current count to the refresh requestor in response to receiving a third signal, wherein the refresh requestor is configured to transmit a refresh request at a second refresh rate, in response to receiving the current count from the refresh counter and determining that the current count is greater than a refresh threshold. | 12-29-2011 |
| 20110320702 | Operation Frequency Adjusting System and Method - Techniques pertaining to adjusting the operation frequency of a DRAM are disclosed. According to one embodiment, the DRAM operation frequency adjusting system includes a statistic module counting effective operations of a DRAM to obtain a bandwidth utilization rate of the DRAM at a present operation frequency; a parameter configuration module including a target frequency configuration sub-module configured to generate a target operation frequency; and a frequency switch controller for switching a present operation frequency of the DRAM to the target operation frequency. The invention adjusts the operation frequency of a DRAM according to the application environment, and creates a balance between performance and power consumption of DRAMs, and thus improves operation speed of system-on-chips as well as decreases the power consumption. | 12-29-2011 |
| 20120030419 | SENSING DEVICE AND ELECTRONIC APPARATUS - A sensing device and an electronic apparatus in which impairment of performance due to destruction of parameters can be reduced are to be provided. Parameters (sensor parameters | 02-02-2012 |
| 20120030420 | PROTOCOL FOR REFRESH BETWEEN A MEMORY CONTROLLER AND A MEMORY DEVICE - The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller. | 02-02-2012 |
| 20120059984 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor package is disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias. | 03-08-2012 |
| 20120066445 | DYNAMIC RAM PHY INTERFACE WITH CONFIGURABLE POWER STATES - A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers. | 03-15-2012 |
| 20120079182 | FAST EXIT FROM DRAM SELF-REFRESH - Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller. | 03-29-2012 |
| 20120079183 | REDUCED CURRENT REQUIREMENTS FOR DRAM SELF-REFRESH MODES - Embodiments of the invention describe systems, methods, and apparatuses to reduce the instantaneous power necessary to execute a DRAM device initiated self-refresh. Embodiments of the invention describe a DRAM device enabled to stagger self-refreshes between a plurality of banks. Staggering self-refreshes between banks reduces the current required for a DRAM self-refresh, thus reducing the amount of current required by the DRAM device. | 03-29-2012 |
| 20120089773 | DYNAMIC RANDOM ACCESS MEMORY UNIT AND DATA REFRESHING METHOD THEREOF - A dynamic random access memory (DRAM) unit and a data refreshing method thereof are provided. The DRAM unit includes a memory array, a refresh address module, and a refresh control module. The memory array includes multiple memory cells. The refresh address module produces a refresh word line address cyclically during a refresh mode. The refresh control module coupled to the memory array and the refresh address module obtains a start word line address and a stop word line address corresponding to the start word line address to form a memory word line address interval. Then, the refresh control module determines that the refresh word line address is within the memory word line address interval to execute a data charging operation to the memory cells corresponding to the refresh word line address, or stop the data charging operation otherwise, so as to reduce power consumption during the refresh mode. | 04-12-2012 |
| 20120089774 | METHOD AND SYSTEM FOR MITIGATING ADJACENT TRACK ERASURE IN HARD DISK DRIVES - A method, system, and computer program product for mitigating adjacent track erasures in hard disks, includes: determining input/output (I/O) characteristics for a plurality of blocks on a hard disk; assigning the plurality of blocks to a plurality of categories of I/O characteristics by the processor; and clustering content of the blocks assigned to the same category in one or more continuous tracks on the hard disk. Each block is assigned to one category. Blocks with similar I/O characteristics are clustered on one or more continuous tracks. By performing this clustering, blocks with a high number of I/O operations are grouped and stored on fewer tracks than if they were scattered across numerous tracks. This reduces the number of tracks experiencing a high number of I/O operations, and in turn, the amount of refreshing of adjacent tracks is reduced. | 04-12-2012 |
| 20120144105 | Method and Apparatus for Performing Refresh Operations in High-Density Memories - A method for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value. | 06-07-2012 |
| 20120144106 | Memory Device Refresh Commands On the Fly - On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch from a currently-applied refresh rate to a different refresh rate. In response to the condition, the refresh rate is dynamically switched. The switching does not require a change of a mode register. Thus, a refresh rate for the memory device can be dynamically changed on the fly. | 06-07-2012 |
| 20120151131 | MEMORY SYSTEM WITH A PROGRAMMABLE REFRESH CYCLE - A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable. | 06-14-2012 |
| 20120203962 | MEMORY CONTROLLER AND DATA SAVING CONTROL METHOD OF THE SAME - A memory controller that controls data transfer between a volatile memory and a non-volatile memory, wherein data being held in a plurality of volatile memories each having a refresh operation mode and a self-refresh operation mode is transferred to the non-volatile memory. When readout of data from at least one volatile memory has been finished, the volatile memory is shifted from the refresh operation mode to the self-refresh operation mode. Then, control is performed so as to return the volatile memory from the self-refresh operation mode depending on the progress of writing of data to the non-volatile memory. | 08-09-2012 |
| 20120278548 | OPTIMIZING EDRAM REFRESH RATES IN A HIGH PERFORMANCE CACHE ARCHITECTURE - Optimizing EDRAM refresh rates in a high performance cache architecture. An aspect of the invention includes receiving a plurality of first signals. A refresh request is transmitted via a refresh requestor to a cache memory at a first refresh rate which includes an interval, including a subset of the first signals. The first refresh rate corresponds to a maximum refresh rate. A refresh counter is reset based on receiving a second signal. The refresh counter is incremented after receiving each of a number of refresh requests. A current count is transmitted from a refresh counter to the refresh requestor based on receiving a third signal. The refresh request is transmitted at a second refresh rate, which is less than the first refresh rate. The refresh request is transmitted based on receiving the current count from the refresh counter and determining that the current count is greater than a refresh threshold. | 11-01-2012 |
| 20120317352 | Method and Apparatus for Refreshing and Data Scrubbing Memory Device - At least one refresh without scrubbing is performed on a corresponding portion of the memory device with a first frequency. In addition, at least one refresh with scrubbing is performed on a corresponding portion of the memory device with a second frequency less than the first frequency. Accordingly, refresh operations with data scrubbing are performed to prevent data error accumulation. Furthermore, refresh operations without data scrubbing are also performed to reduce undue power consumption from the data scrubbing. | 12-13-2012 |
| 20120331220 | FAST EXIT FROM DRAM SELF-REFRESH - Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller. | 12-27-2012 |
| 20130007357 | MECHANISM FOR FACILITATING FINE-GRAINED SELF-REFRESH CONTROL FOR DYNAMIC MEMORY DEVICES - A mechanism for facilitating improved refresh schemes for memory devices is described. In one embodiment, an apparatus includes a memory device having refresh logic and memory cells, the memory cells including data cells and supplemental cells, the supplemental cells to be observed. The supplemental cells emulate a decay characteristic of the data cells performing regular refresh operations according to an existing refresh policy. The apparatus may further include the refresh logic to receive, from the supplemental cells, observation data relating to decaying of the supplemental cells, and correlate the observation data to data cell performance. The refresh logic to generate a policy recommendation based on the observation data collected by the supplemental cells. | 01-03-2013 |
| 20130031305 | INFORMATION PROCESSING SYSTEM INCLUDING SEMICONDUCTOR DEVICE HAVING SELF-REFRESH MODE - Disclosed herein is an information processing system having first and second devices. The second device alternately issues a self-refresh command and a self-refresh exit command to the first device. The first device performs a refresh operation once in response to the self-refresh command and updates a state of a DLL circuit in response to the self-refresh exit command. | 01-31-2013 |
| 20130046926 | EDRAM REFRESH IN A HIGH PERFORMANCE CACHE ARCHITECTURE - A method for implementing embedded dynamic random access memory (eDRAM) refreshing in a high performance cache architecture. The method includes receiving a memory access request, via a cache controller, from a memory refresh requestor, the memory access request for a memory address range in a cache memory. The method also includes detecting that the cache memory located at the memory address range is available to receive the memory access request and sending the memory access request to a memory request interpreter. The method further includes receiving the memory access request from the cache controller, determining that the memory access request is a request to refresh contents of the memory address range in the cache memory, and refreshing data in the memory address range. | 02-21-2013 |
| 20130080694 | Methods And Apparatus For Refreshing Digital Memory Circuits - Dynamic memory systems require each memory cell to be continually refreshed. During a memory refresh operation, the refreshed memory cells cannot be accessed by a memory read or write operation. In multi-bank dynamic memory systems, concurrent refresh systems allow memory refresh circuitry to refresh memory banks that are not currently involved in memory access operations. To efficiently refresh memory banks and advanced round robin refresh system refreshes memory banks in a nominal round robin manner but skips memory banks blocked by memory access operations. Skipped memory banks are prioritized and then refreshed when they are no longer blocked. | 03-28-2013 |
| 20130124795 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. | 05-16-2013 |
| 20130132661 | METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES - One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices | 05-23-2013 |
| 20130132662 | MEMORY MANAGEMENT UNIT, IMAGE PROCESSING DEVICE, AND INTEGRATED CIRCUIT - A memory management unit manages a state of a memory which is to be accessed by bank interleaving. The memory includes p banks (where p is an integer of 2 or greater). The memory management unit includes a control unit that dynamically determines a bank to be accessed from among the p banks. When predetermined conditions for a reserving state of the memory are satisfied and there is any unused bank in the p banks, the control unit performs power consumption reduction to control the memory to cause power consumption of the unused bank(s) to be less than power consumption of other banks in the p banks except the unused bank(s). | 05-23-2013 |
| 20130138878 | Method for Scheduling Memory Refresh Operations Including Power States - A method for performing refresh operations on a rank of memory devices is disclosed. After the completion of a memory operation, a determination is made whether or not a refresh backlog count value is less than a predetermined value and the rank of memory devices is being powered down. If the refresh backlog count value is less than the predetermined value and the rank of memory devices is being powered down, an Idle Count threshold value is set to a maximum value such that a refresh operation will be performed after a maximum delay time. If the refresh backlog count value is not less than the predetermined value or the rank of memory devices is not in a powered down state, the Idle Count threshold value is set based on the slope of an Idle Delay Function such that a refresh operation will be performed accordingly. | 05-30-2013 |
| 20130151768 | SYSTEM AND METHOD FOR MANAGING SELF-REFRESH IN A MULTI-RANK MEMORY - Multi-rank memories and methods for self-refreshing multi-rank memories are disclosed. One such multi-rank memory includes a plurality of ranks of memory and self-refresh logic coupled to the plurality of ranks of memory. The self-refresh logic is configured to refresh a first rank of memory in a self-refresh state in response to refreshing a second rank of memory not in a self-refresh state in response to receiving a non-self-refresh refresh command for the second rank of memory. | 06-13-2013 |
| 20130159617 | MEMORY SYSTEM, AND A METHOD OF CONTROLLING AN OPERATION THEREOF - A memory system that includes a memory device and a memory controller. The memory device includes a plurality of memory cells, and a first storage unit configured to store information about a weak cell from among the plurality of memory cells. The memory controller is configured to transmit an operation command signal to the memory device, and control an operation of the memory device by using the information about the weak cell provided from the first storage unit. If the operation command signal is related to an operation to be performed using a first of the memory cells and the first memory cell is the weak cell, the memory device is configured to transmit the information about the weak cell to the memory controller. | 06-20-2013 |
| 20130173858 | Method for Scheduling Memory Refresh Operations Including Power States - A method for performing refresh operations on a rank of memory devices is disclosed. After the completion of a memory operation, a determination is made whether or not a refresh backlog count value is less than a predetermined value and the rank of memory devices is being powered down. If the refresh backlog count value is less than the predetermined value and the rank of memory devices is being powered down, an Idle Count threshold value is set to a maximum value such that a refresh operation will be performed after a maximum delay time. If the refresh backlog count value is not less than the predetermined value or the rank of memory devices is not in a powered down state, the Idle Count threshold value is set based on the slope of an Idle Delay Function such that a refresh operation will be performed accordingly. | 07-04-2013 |
| 20130185498 | PREVENTION OF DATA LOSS DUE TO ADJACENT TRACK INTERFERENCE - For limiting data loss due to ATI or ATE, an apparatus may include a storage module, a tracking module, and a refresh module. The storage module is configured to store a risk value for a tracked storage division. The risk value indicates a risk level of data loss for the tracked storage division. The tracked storage division is one of a plurality of storage divisions of a data storage device. The tracking module is configured to update the risk value to indicate a higher risk level based on a write to a physically proximal storage division. The physically proximal storage division is within an interference range of the tracked storage division. The tracking module is configured to reset the risk value based on a write to the tracked storage division. The refresh module is configured to refresh the tracked storage division based on the risk value meeting a threshold value. | 07-18-2013 |
| 20130185499 | FAST EXIT FROM SELF-REFRESH STATE OF A MEMORY DEVICE - A system provides for a signal to indicate when a memory device exits from self-refresh. Thus, substantially at the same time (before or after) the memory device exits self-refresh, an indicator signal can be triggered to indicate normal operation or standard refresh operation and normal memory access of the memory device. A memory controller can access the indicator signal to determine whether the memory device is in self-refresh. Thus, the memory controller can more carefully manage the timing of sending a command to the memory device while reducing the delay time typically associated with detecting a self-refresh condition. | 07-18-2013 |
| 20130212330 | MEMORY RECORDER QUEUE BIASING PRECEDING HIGH LATENCY OPERATIONS - A memory system and data processing system for controlling memory refresh operations in dynamic random access memories. The memory controller comprises logic that: tracks a time remaining before a scheduled time for performing a high priority, high latency operation a first memory rank of the memory system; responsive to the time remaining reaching a pre-established early notification time before the schedule time for performing the high priority, high latency operation, biases the re-order queue containing memory access operations targeting the plurality of ranks to prioritize scheduling of any first memory access operations that target the first memory rank. The logic further: schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the re-order queue that target other memory ranks; and performs the high priority, high latency operation at the first memory rank at the scheduled time. | 08-15-2013 |
| 20130227212 | REFRESH REQUEST QUEUING CIRCUITRY - An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry to determine a number of queued pending refresh requests for a memory bank based on a comparison of a count from a refresh-request counter to a count from a refresh-address counter; and second circuitry to set a refresh flag in response to a determination that the number of queued pending refresh requests exceeds a predetermined number. Other embodiments may be disclosed and/or claimed. | 08-29-2013 |
| 20130254474 | SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION OF MEMORY - Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable. | 09-26-2013 |
| 20130254475 | MEMORY REFRESH METHOD AND DEVICES - The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict. | 09-26-2013 |
| 20130275665 | DYNAMIC OPERATIONS FOR 3D STACKED MEMORY USING THERMAL DATA - Dynamic operations for operations for 3D stacked memory using thermal data. An embodiment of a memory device includes memory having multiple coupled memory elements and multiple thermal sensors, including a first thermal sensor in a first area of the memory stack and a second thermal sensor in a second area of the memory stack. A memory controller is to provide operations to modify thermal conditions of the memory elements based at least in part on thermal information generated by the thermal sensors. | 10-17-2013 |
| 20130282973 | VOLATILE MEMORY DEVICE AND A MEMORY CONTROLLER - A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows. | 10-24-2013 |
| 20130290621 | DDR CONTROLLER, METHOD FOR IMPLEMENTING THE SAME, AND CHIP - There are provided a DDR controller, a method for implementing the same and a chip, which are applicable to the field of DDR controller technology. The method includes the steps of: parsing a plurality of buffered commands concurrently (S | 10-31-2013 |
| 20130304982 | MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHODS THEREOF - A memory device, a memory system, and operating methods thereof are provided. The method of operating the memory device, which includes a first memory cell and a second memory cell neighboring the first memory cell, includes counting a disturbance value of the second memory cell each time the first memory cell is accessed, updating a disturbance count value of the second memory cell based on the counting, adjusting a refresh schedule based on the disturbance count value of the second memory cell, a desired threshold and a maximum disturbance count value, and resetting the disturbance count value of the second memory cell and the maximum disturbance count value when the second memory cell is refreshed according to the adjusted refresh schedule. | 11-14-2013 |
| 20130318293 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 11-28-2013 |
| 20130332669 | MEMORY CONTROLLER, MEMORY CONTROL METHOD, AND MEMORY CONTROL SYSTEM - The memory controller is provided with a refresh clock generation unit, a control signal generation unit, and a refresh request generation unit. The refresh clock generation unit generates a clock obtained by frequency dividing a system clock, as a refresh clock. The control signal generation unit issues a refresh command to a memory, based on the refresh clock. The refresh request generation unit curtails, based on a specified refresh count in a specified refresh period determined by the memory, a supply to the control signal generation unit of a redundant refresh clock generated exceeding the specified refresh count, the refresh clock being generated within the specified refresh period. | 12-12-2013 |
| 20140006702 | MECHANISM FOR FACILITATING WRITE TRACKING FOR FOLLOWING DATA EYE MOVEMENTS ACROSS CHANGING THERMAL CONDITIONS IN MEMORY SYSTEMS | 01-02-2014 |
| 20140006703 | ROW HAMMER REFRESH COMMAND | 01-02-2014 |
| 20140006704 | ROW HAMMER CONDITION MONITORING | 01-02-2014 |
| 20140006705 | METHOD OF GENERATING MEMORY ADDRESSES AND REFRESH POWER MANAGEMENT CONTROLLER | 01-02-2014 |
| 20140047176 | DRAM ENERGY USE OPTIMIZATION USING APPLICATION INFORMATION - An application program identifies a plurality of least recently accessed constructs of the application program that reside in DRAM memory. The application program causes the aggregation of at least a portion of the identified least recently accessed constructs onto one or more pages of the DRAM memory. The application program then causes the one or more memory pages of the DRAM memory to be put into self-refresh operation mode. | 02-13-2014 |
| 20140059287 | ROW HAMMER REFRESH COMMAND - A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row. | 02-27-2014 |
| 20140068171 | REFRESH CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A refresh control circuit includes an internal chip information unit configured to provide internal chip information related to a retention characteristic of a memory cell, a mode information modification unit configured to output modified mode information based on the internal chip information, wherein the modified mode information represent a number of memory banks for refresh operation, and a selection signal activation unit configured to activate one or more of selection signals for selecting corresponding one or more of the memory banks in response to the modified mode information. | 03-06-2014 |
| 20140068172 | SELECTIVE REFRESH WITH SOFTWARE COMPONENTS - A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria. | 03-06-2014 |
| 20140082272 | Memory Reorder Queue Biasing Preceding High Latency Operations - A method for controlling memory refresh operations in dynamic random access memories. The method includes determining a count of deferred memory refresh operations for a first memory rank. Responsive to the count approaching a high priority threshold, issuing an early high priority refresh notification for the first memory rank, which indicates the pre-determined time for performing a high priority memory refresh operation at the first memory rank. Responsive to the early high priority refresh notification, the behavior of a read reorder queue is dynamically modified to give priority scheduling to at least one read command targeting the first memory rank, and one or more of the at least one read command is executed on the first memory rank according to the priority scheduling. Priority scheduling removes these commands from the re-order queue before the refresh operation is initiated at the first memory rank. | 03-20-2014 |
| 20140089576 | METHOD, APPARATUS AND SYSTEM FOR PROVIDING A MEMORY REFRESH - A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows. | 03-27-2014 |
| 20140089577 | VOLATILE MEMORY DEVICE AND MEMORY CONTROLLER - A volatile memory device includes a memory cell array, a command decoder, a self-refresh circuit, and a register. The command decoder is configured to decode a self-refresh entry command, a self-refresh exit command, and a register read command based on external command signals received from outside the volatile memory device. The self-refresh circuit is configured to automatically refresh the memory cell array during a self-refresh mode which be entered in response to the self-refresh entry command and be exited in response to the self-refresh exit command. The register is configured to store an accessible state in response to the self-refresh exit command, and output the stored accessible state in response to the register read command. The accessible state indicates whether or not the memory cell array is ready to be read or written. | 03-27-2014 |
| 20140115247 | INFORMATION RECORDING DEVICE AND INFORMATION RECORDING METHOD - An information recording device includes a recording medium in which renewal data, which is a target of a data refresh operation, is recorded, a reading module that reads the renewal data recorded in the recording medium, a renewal module that performs updating of a value indicating a state of the data refresh operation, a generation module that generates parity data based on the value and the read renewal data, and a recording module that records the renewal data after recording the generated parity data. | 04-24-2014 |
| 20140115248 | DEVICE, SYSTEM, AND METHOD OF MEMORY ALLOCATION - Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System. | 04-24-2014 |
| 20140122790 | DYNAMIC PRIORITY MANAGEMENT OF MEMORY ACCESS - A system includes multiple master devices and at least one memory refresh scheduler. When a master device needs higher priority for memory access, the master device sends a dynamic priority signal to the memory refresh scheduler and in response, the memory refresh scheduler changes its policy for issuing refresh commands. | 05-01-2014 |
| 20140136774 | MANAGEMENT OF MEMORY REFRESH POWER CONSUMPTION - Embodiments include a system, an apparatus, a device, and a method. The apparatus includes a processor, a dynamic memory, and a hardware-implemented memory control circuit. The hardware-implemented control circuit includes a control circuit for establishing an extended refresh period of the dynamic memory based at least in part on a monitored result that indicates an occurrence of a memory loss in the dynamic memory. The hardware-implemented control circuit also includes a control circuit for causing a refresh of the dynamic memory during each of at least two extended refresh periods. | 05-15-2014 |
| 20140149653 | VARIABLE MAPPING OF MEMORY ACCESSES TO REGIONS WITHIN A MEMORY - An apparatus for processing data | 05-29-2014 |
| 20140149654 | DATA INDEPENDENT PERIODIC CALIBRATION USING PER-PIN VREF CORRECTION TECHNIQUE FOR SINGLE-ENDED SIGNALING - A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver. | 05-29-2014 |
| 20140156923 | ROW HAMMER MONITORING BASED ON STORED ROW HAMMER THRESHOLD VALUE - Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row. | 06-05-2014 |
| 20140164692 | MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING - This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data. | 06-12-2014 |
| 20140173192 | EXECUTION ENGINE FOR EXECUTING SINGLE ASSIGNMENT PROGRAMS WITH AFFINE DEPENDENCIES - The execution engine is a new organization for a digital data processing apparatus, suitable for highly parallel execution of structured fine-grain parallel computations. The execution engine includes a memory for storing data and a domain flow program, a controller for requesting the domain flow program from the memory, and further for translating the program into programming information, a processor fabric for processing the domain flow programming information and a crossbar for sending tokens and the programming information to the processor fabric. | 06-19-2014 |
| 20140189228 | THROTTLING SUPPORT FOR ROW-HAMMER COUNTERS - Throttling of memory access commands. Accesses to rows of a memory device are monitored for a timeframe. The timeframe is divided into at least two sub-frames. If the number of accesses for any of the rows during a first sub-frame exceeds a first threshold throttling accesses to the accessed row at a first rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the first threshold. The first threshold is associated with risk of data corruption on a row physically adjacent to the accessed row. If a number of accesses for the accessed row during a second sub-frame exceeds a second threshold, throttling accesses to the accessed row at a second rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the second threshold. The second threshold is greater than the first threshold. The second throttling rate is greater than the first throttling rate. | 07-03-2014 |
| 20140189229 | REFRESH RATE PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION - A memory subsystem can test a memory device in situ, testing the performance of the device in the system it is built into during production. Thus, the refresh rate can be adjusted specific to the memory device(s) of a specific system, rather than defaulting to a refresh frequency specified by a standard for the memory device(s). A test component embedded within the host memory subsystem can perform a test and identify specific bits or lines of memory that produce errors when a lower frequency refresh rate is used. The system maps out the identified bits or lines to prevent the bits/lines from being used in runtime of the system. The memory subsystem can then set its refresh rate to an adjusted refresh rate at which a threshold number of errors can be removed by mapping out the bits/lines. | 07-03-2014 |
| 20140189230 | MEMORY CONTROLLING DEVICE AND METHOD THEREOF - A memory controlling device and method are disclosed for controlling a memory having a partial array self refresh (PASR) function and a plurality of memory segments. The memory controlling device comprises an address mapper, an address decoder, an address selector, and a PASR configuration register storing a PASR configuration. The address mapper converts an input address set into a mapped address set according to an address offset. The mapped address set comprises a plurality of consecutive mapped addresses or at least one mapped address within a limited range. The address decoder updates the PASR configuration during writing. The address selector generates an updated address set, which is used for setting at least one mode register of the memory, according to the PASR configuration register under a sleep-or-standby mode in order that the memory can self refresh at least one of the memory segments correspondingly. | 07-03-2014 |
| 20140215141 | High-Speed Processor Core Comprising Mapped Auxilliary Component Functionality - A high-speed processor core having a plurality of individual FPGA-based processing elements configured in a synchronous or asynchronous pipeline architecture with direct processor-to-memory interconnectivity and having an auxiliary component functionality mapped into at least one of the processing elements. | 07-31-2014 |
| 20140215142 | DRAM REFRESH METHOD AND SYSTEM - A DRAM refresh method used with a memory system organized into rows of memory cells, each of which has an associated data retention time, with the system arranged to refresh predefined blocks of memory cells simultaneously. For each block of memory cells that are to be refreshed simultaneously, the minimum data retention time for the memory cells in the block is determined. Then, an asymmetric refresh sequence is created which specifies the order in which the blocks of memory cells are refreshed, such that the blocks having the shortest minimum data retention times are refreshed more often than the blocks having longer minimum data retention times. | 07-31-2014 |
| 20140237177 | MEMORY MODULE AND MEMORY SYSTEM HAVING THE SAME - A memory module includes a master memory device and at least one slave memory device. The master memory device may generate a refresh clock signal, and perform a refresh operation in synchronization with the refresh clock signal. The slave memory device may be connected to receive the refresh clock signal, and perform a refresh operation in synchronization with the refresh clock signal. | 08-21-2014 |
| 20140281201 | REFRESH CONTROL DEVICE, WIRELESS RECEIVER, AND SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a refresh control device including: an arbitration operating unit configured to arbitrate (i) a memory access request for accessing a volatile memory that requires a refresh operation for holding data and (ii) a refresh trigger for requesting execution of the refresh operation; and a trigger generating unit configured to generate refresh triggers in a non-constant cycle to satisfy refresh-rate requirements defining the number of refresh operations necessary to be executed per predetermined period for the volatile memory to hold the data. | 09-18-2014 |
| 20140281202 | DRAM CONTROLLER FOR VARIABLE REFRESH OPERATION TIMING - A method for selection of a DRAM refresh timing in a DRAM memory system is disclosed. The method may include running a workload for a first number of refresh intervals using a first DRAM refresh timing and making a first workload throughput measurement for the first number of refresh intervals. The method may also include running the workload for a second number of refresh intervals using a second DRAM refresh timing and making a second workload throughput measurement for the second number of refresh intervals. The method may further include deciding if the first throughput measurement is greater than the second throughput measurement, and then selecting the first DRAM refresh timing as a selected DRAM refresh timing, or deciding if the second throughput measurement is greater than the first throughput measurement, then selecting the second DRAM refresh timing as the selected DRAM refresh timing. | 09-18-2014 |
| 20140281203 | MANAGING DISTURBANCE INDUCED ERRORS - In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells. | 09-18-2014 |
| 20140281204 | FLEXIBLE MEMORY SYSTEM WITH A CONTROLLER AND A STACK OF MEMORY - Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults. | 09-18-2014 |
| 20140281205 | MEMORY CIRCUIT AND METHOD FOR ITS OPERATION - In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be. | 09-18-2014 |
| 20140281206 | Techniques for Probabilistic Dynamic Random Access Memory Row Repair - Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed. | 09-18-2014 |
| 20140281207 | Techniques for Determining Victim Row Addresses in a Volatile Memory - Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed. | 09-18-2014 |
| 20140289461 | INFORMATION PROCESSING SYSTEM INCLUDING SEMICONDUCTOR DEVICE HAVING SELF-REFRESH MODE - Disclosed herein is an information processing system having first and second devices. The second device alternately issues a self-refresh command and a self-refresh exit command to the first device. The first device performs a refresh operation once in response to the self-refresh command and updates a state of a DLL circuit in response to the self-refresh exit command. | 09-25-2014 |
| 20140325137 | MEMORY CONTROLLER AND ASSOCIATED SIGNAL GENERATING METHOD - The invention is directed to a memory controller and an associated signal generating method. By appropriately arranging a sequence according to which command signals are generated and expanding a latching interval of a part of address signals, not only the memory controller is enabled to control the DDR memory modules in a functional manner to further overcome issues of conventionally small latching intervals, but also system stability and access performance are reinforced as the memory access clock speed continue to increase. | 10-30-2014 |
| 20140344513 | METHODS AND SYSTEMS FOR SMART REFRESH OF DYNAMIC RANDOM ACCESS MEMORY - Methods and devices for refreshing a dynamic memory device, (e.g., DRAM) to eliminate unnecessary page refresh operations. A value in a lookup table for the page may indicate whether valid data including all zeros is present in the page. When the page includes valid data of all zeros, the lookup table value may be set so that refresh, memory read, write and clear accesses of the page may be inhibited and a valid value may be returned. A second lookup table may contain a second value indicating whether a page has been accessed by a page read or write during the page refresh interval. A page refresh, by issuing an ACT−PRE command pair, and a page address may be performed according to the page refresh interval when the second value indicates that page access has not occurred. | 11-20-2014 |
| 20140344514 | MEMORY SYSTEM WITH A PROGRAMMABLE REFRESH CYCLE - A memory system with a programmable refresh cycle including a memory device. The memory device includes refresh circuitry in communication with a memory array and with a memory controller. The refresh circuitry is configured for receiving a refresh command from the memory controller and for refreshing a number of memory cells in the memory device in response to receiving the refresh command. A refresh cycle time of the refresh command is programmable. The memory device also includes a programmable refresh cycle mode register in communication with the refresh circuitry. Contents of the programmable refresh cycle mode register indicate the refresh cycle time of the refresh command. | 11-20-2014 |
| 20140359208 | MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A memory includes a plurality of word lines each of which are connected to one or more memory cells, an address detection unit suitable for detecting a target address of a target word line among the plurality of word lines, wherein the target word line has an activation history satisfying a predetermined condition, and a control unit suitable for activating one or more word line among the plurality of word lines each time a refresh command is applied, and activating one or more adjacent word lines in response to a refresh command after detection of the target address, wherein the adjacent word line is adjacent to the target word line and identified by the target address. | 12-04-2014 |
| 20140359209 | WORD SHIFT STATIC RANDOM ACCESS MEMORY (WS-SRAM) - Word shift static random access memory (WS-SRAM) cell, word shift static random access memory (WS-SRAM) and method using the same employ dynamic storage mode switching to shift data. The WS-SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, a dynamic/static (D/S) mode selector to selectably switch the WS-SRAM cell between the dynamic storage mode and a static storage mode, and a column selector to selectably determine whether or not the WS-SRAM cell accepts shifted data. The WS-SRAM includes a plurality of WS-SRAM cells arranged in an array and a controller to shift data. The method includes switching a storage mode and activating a column selector of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected WS-SRAM cell. | 12-04-2014 |
| 20140379978 | REFRESH SCHEME FOR MEMORY CELLS WITH WEAK RETENTION TIME - A memory refresh method within a memory controller includes checking a first retention state corresponding to a first memory address and a second retention state corresponding to a second memory address. The memory refresh method also includes performing a refresh operation on a row corresponding to the second memory address when the second retention state indicates a weak retention state. The first memory address corresponds to a refresh counter address, and the second memory address corresponds to a complementary address of the refresh counter address. | 12-25-2014 |
| 20140379979 | MEMORY ACCESS ALIGNMENT IN A DOUBLE DATA RATE ('DDR') SYSTEM - Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations. | 12-25-2014 |
| 20150019805 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD FOR THE SAME, PROGRAM FOR THE SAME, AND STORAGE MEDIUM - An information processing apparatus according to an aspect of the present invention acquires temperature information for each of a plurality of memories in a wide IO memory device, and when execution of a job is instructed, decides on a memory having a lower temperature as the memory to be used by a functional module that corresponds to a function, based on the memory size to be used by the functional module that corresponds to the function, and on the acquired temperature information for the memories. | 01-15-2015 |
| 20150026399 | Automatic Partial Array Self-Refresh - Methods of configuring dynamic memory associated with a processing system, are described. The dynamic memory is configured in a plurality of blocks, the method comprises: a) receiving information relating to a utilisation status of the memory; b) processing the received information to determine at least one first block of the memory that is currently not in use for information storage; and c) configuring the at least one first block to be excluded from an information refresh process. | 01-22-2015 |
| 20150026400 | Facilitating Communication Between Memory Devices and CPUs - According to one embodiment, an apparatus comprises one or more memory devices and one or more processors coupled to a circuit board. The memory devices are configured according to a second memory technology. The processors are configured to receive messages conforming to a first memory technology, translate the messages from the first memory technology to the second memory technology, and send the translated messages to the memory devices. | 01-22-2015 |
| 20150039822 | MECHANISM FOR ENABLING FULL DATA BUS UTILIZATION WITHOUT INCREASING DATA GRANULARITY - A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity. | 02-05-2015 |
| 20150058549 | DETECTION OF MULTIPLE ACCESSES TO A ROW ADDRESS OF A DYNAMIC MEMORY WITHIN A REFRESH PERIOD - Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory. | 02-26-2015 |
| 20150058550 | INFORMATION RECORDING APPARATUS THAT PERFORMS REFRESH OF MEMORY AND CONTROL METHOD THEREFOR - An information recording apparatus which is capable of preventing data loss due to a decrease in a time period for which data is retained in a memory, and performing refresh of the memory mounted on a main body of the information recording apparatus. When the number of times of data erasure in the memory is updated, a table showing data retention time periods corresponding to the number of times of data erasure in the memory is referred to, and a date and time at which refresh of the memory should be performed within a data retention time period corresponding to the number of times of data erasure is set. Whether it is possible to perform refresh of the memory at the set date and time is judged, and when it is possible to perform refresh of the memory at the set date and time, refresh of the memory is performed. | 02-26-2015 |
| 20150067249 | Memory Scheduling Method and Memory Controller - In a memory scheduling method, a memory controller writes a first group of first row strobe commands (ACTs) into a first memory. The first group of first ACTs includes multiple first ACTs and a periodic interval exists between two adjacent first ACTs written by the memory controller into the first memory. The memory controller writes operation commands that correspond to the first group of first ACTs into the first memory after writing the first group of first ACTs into the first memory. The memory controller writes second ACTs into a second memory in periodic intervals for writing the first group of first ACTs into the first memory and/or in periodic intervals for writing the operation commands that correspond to the first group of first ACTs. The memory controller writes operation commands that correspond to the second ACTs into the second memory. | 03-05-2015 |
| 20150089127 | MEMORY BROADCAST COMMAND - Apparatus, systems, and methods to broadcast a memory command are described. In one embodiment, a memory controller comprising logic to insert a first predetermined value into an all ranks parameter in a memory command, and transmit the memory command to a memory device. Other embodiments are also disclosed and claimed. | 03-26-2015 |
| 20150100723 | DATA PROCESSOR WITH MEMORY CONTROLLER FOR HIGH RELIABILITY OPERATION AND METHOD - A data processor includes a memory accessing agent and a memory controller. The memory accessing agent generates a plurality of accesses to a memory. The memory controller is coupled to the memory accessing agent and schedules the plurality of memory accesses in an order based on characteristics of the memory. The characteristics of the memory include a row cycle page time (t | 04-09-2015 |
| 20150106561 | MEMORY COMPONENT WITH ADJUSTABLE CORE-TO-INTERFACE DATA RATE RATIO - A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation. | 04-16-2015 |
| 20150113213 | RESISTIVE MEMORY DEVICE, OPERATING METHOD THEREOF, AND SYSTEM HAVING THE SAME - A resistive memory device includes a memory cell array including a plurality of resistive memory cells, an address decoder suitable for decoding an address signal and selecting the resistive memory cells, a read/write control circuit suitable for programming data to the memory cell array or reading data from the memory cell array, a voltage generator suitable for generating operation voltages and providing the operation voltages to the address decoder and a controller suitable for controlling the address decoder, the read/write control circuit, and the voltage generator to perform a write operation in response to a write command and a plurality of write data. | 04-23-2015 |
| 20150113214 | FINAL LEVEL CACHE SYSTEM AND CORRESPONDING METHODS - A data access system including a processor and a final level cache module. The processor is configured to generate a request to access a first physical address. The final level cache module includes a dynamic random access memory (DRAM), a final level cache controller, and a DRAM controller. The final level cache controller is configured to (i) receive the request from the processor, and (ii) convert the first physical address to a first virtual address. The DRAM controller is configured to (i) convert the first virtual address to a second physical address, and (ii) access the DRAM based on the second physical address. | 04-23-2015 |
| 20150120998 | METHOD, APPARATUS AND SYSTEM FOR DYNAMICALLY CONTROLLING AN ADDRESSING MODE FOR A CACHE MEMORY - In an embodiment, a first portion of a cache memory is associated with a first core. This first cache memory portion is of a distributed cache memory, and may be dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores (including the first core) according to an addressing mode, which itself is dynamically controllable. Other embodiments are described and claimed. | 04-30-2015 |
| 20150120999 | MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME - A memory system may include a memory including a cell array having a plurality of word lines and an address storage unit that stores an address in response to a capture command, wherein the memory sequentially refreshes the word lines in response to a refresh command at a set cycle, and refreshes a word line corresponding to the stored address in response to the refresh command when the address is stored in the address storage unit; and a memory controller transmitting the refresh command to the memory at the set cycle when a word line satisfying one or more of conditions that the number of activation times is equal to or more than a reference number and an activation frequency is equal to or more than a reference frequency is detected, and transmitting the capture command and an address of the detected word line to the memory. | 04-30-2015 |
| 20150127898 | SYSTEM AND MEMORY CONTROLLER FOR INTERRUPTIBLE MEMORY REFRESH - A refresh command is communicated to a memory device to initiate an interruptible refresh which contains multiple segment refreshes separated by interrupt boundaries. A command is communicated to the memory device before execution of a segment refresh and the segment refresh is delayed at an interrupt boundary. Alternatively, a first number of commands in a queue is determined. A first number of segment refreshes to execute is determined based on the first number of commands. The first number of segment refreshes to execute is communicated to the memory device to cause execution of the first number of segment refreshes. A second number of commands in the queue is determined. A second number of segment refreshes to execute is determined based on the second number of commands. The second number of segment refreshes to execute is communicated to the memory device to cause execution of the second number of segment refreshes. | 05-07-2015 |
| 20150127899 | MEMORY DEVICE FOR INTERRUPTIBLE MEMORY REFRESH - A refresh command is received from a memory controller. An interruptible refresh containing multiple segment refreshes is initiated. The segment refreshes are separated by interrupt boundaries. A command is received before execution of a segment refresh. The first command is executed and execution of the first segment refresh is delayed at a first interrupt boundary. Alternatively, a first number of segment refreshes to execute is received from a memory controller. The received first number of segment refreshes is executed. A second number of segment refreshes to execute is received from a memory controller. The received second number of segment refreshes is executed. No segment refreshes are executed between the execution of the first number of segment refreshes and the execution of the second number of segment refreshes. | 05-07-2015 |
| 20150134897 | METHOD AND APPARATUS FOR REFRESHING A MEMORY CELL - A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory cells of the memory device are to be refreshed by the memory device. | 05-14-2015 |
| 20150149717 | PARTIAL ACCESS MODE FOR DYNAMIC RANDOM ACCESS MEMORY - Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2 | 05-28-2015 |
| 20150149718 | A LOWER ENERGY CONSUMPTION AND HIGH SPEED COMPUTER SYSTEM AND A MARCHING MAIN MEMORY ADAPTED FOR THE COMPUTER SYSTEM, WITHOUT THE MEMORY BOTTLENECK - A computer system encompasses a processor ( | 05-28-2015 |
| 20150294711 | PERFORMING REFRESH OF A MEMORY DEVICE IN RESPONSE TO ACCESS OF DATA - An access of data in a memory device is sampled. In response to the sampled access of data, a refresh operation is performed in the memory device. | 10-15-2015 |
| 20150310899 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. | 10-29-2015 |
| 20150310900 | REQUEST AGGREGATION WITH OPPORTUNISM - Systems, apparatuses, and methods for aggregating memory requests with opportunism in a display pipeline. Memory requests are aggregated for each requestor of a plurality of requestors in the display pipeline. When the number of memory requests for a given requestor reaches a corresponding threshold, memory requests may be issued for the given requestor. In response to determining the given requestor has reached its threshold, other requestors may issue memory requests even if they have not yet aggregated enough memory requests to reach their corresponding thresholds. | 10-29-2015 |
| 20150318030 | MULTIPLEXED SYNCHRONOUS SERIAL PORT COMMUNICATION WITH SKEW CONTROL FOR STORAGE DEVICE - A method is provided, for example, to implement multiplexed communication between a controller and a preamplifier in a storage device. For example, multiplexed communication is implemented by controlling a bidirectional serial data line of a digital bus to selectively transmit digital signals in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller, in response to a direction control signal, and concurrently transmitting a synchronous clock signal over a clock signal line of the digital bus from the controller to the preamplifier to synchronize transfer and processing of the digital signals transmitted on the bidirectional serial data line of the digital bus. The direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus. | 11-05-2015 |
| 20150339245 | Adaptive Scheduling Queue Control For Memory Controllers Based Upon Page Hit Distance Determinations - Methods and systems are disclosed for adaptive scheduling queue control based upon page hit distance determinations. A threshold occupancy value is determined for a window of previous access requests to a memory and used to adaptively control a number of access requests stored in a scheduling queue buffer. For certain embodiments, a page hit distance (PHD) determination for each access request and historical page hit distance data is used to adjust the threshold occupancy value that determines the number (N) of access requests stored in the buffer prior to removing an access request and using it to access the memory. For each access request, the page hit distance represents the number of previously received access requests since the last access request to access the same page of memory. An average PHD can be determined over a number (M) of previous access requests and used to control the threshold occupancy value. | 11-26-2015 |
| 20150347036 | DRAM CONTROLLER FOR VARIABLE REFRESH OPERATION TIMING - A method for selection of a DRAM refresh timing in a DRAM memory system is disclosed. The method may include running a workload for a first number of refresh intervals using a first DRAM refresh timing and making a first workload throughput measurement for the first number of refresh intervals. The method may also include running the workload for a second number of refresh intervals using a second DRAM refresh timing and making a second workload throughput measurement for the second number of refresh intervals. The method may further include deciding if the first throughput measurement is greater than the second throughput measurement, and then selecting the first DRAM refresh timing as a selected DRAM refresh timing, or deciding if the second throughput measurement is greater than the first throughput measurement, then selecting the second DRAM refresh timing as the selected DRAM refresh timing. | 12-03-2015 |
| 20150357025 | DEVICE, SYSTEM, AND METHOD OF MEMORY ALLOCATION - Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System. | 12-10-2015 |
| 20150380066 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device includes a memory device suitable to perform an internal operation; a processor suitable to generate command generation information to command performance of the s internal operation; and a command set processing block suitable to generate a command set, which is provided to the memory device, based on the command generation information, wherein the command set processing block generates a final sequence which configures a pattern included in the command set. | 12-31-2015 |
| 20160055898 | MEMORY ACCESS METHOD AND MEMORY SYSTEM - A first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, a first chip select signal, and a first higher-order address signal, and forwards a memory access instruction and a lower-order address signal received from a memory controller to the target second level buffer chip. The target second level buffer chip determines a target memory module according to a second chip select signal and a delayed address signal obtained by delays a second higher-order address signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. A cascading manner of a system memory is changed to a tree-like topological form, which avoids a protocol conversion problem, reduces the memory access time. | 02-25-2016 |
| 20160055900 | SYSTEM AND METHOD FOR DYNAMIC CACHING - In one embodiment, a computer-implemented method executable by a server system to store data in a data cache and refresh the data based on a dynamic schedule is provided. The method includes: receiving, by a processor, data from a first resource; storing, by the processor, the data in a data cache; determining, by the processor, a type of the data, and an access frequency of the data; determining, by the processor, a dynamic schedule based on the type of the data, and the access frequency of the data; and refreshing the data cache with new data from the first resource based on the dynamic schedule. | 02-25-2016 |
| 20160064066 | MAINTENANCE OPERATIONS IN A DRAM - A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order. | 03-03-2016 |
| 20160071558 | MEMORY MAPPING IN A PROCESSOR HAVING MULTIPLE PROGRAMMABLE UNITS - The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units. | 03-10-2016 |
| 20160085466 | MEMORY ACCESS RATE - A technique includes determining, via an analog circuit, where an access rate of a memory row associated with a memory device exceeds a threshold. In various examples, upon a determination that the access rate exceeds the threshold, the technique may further comprise generating an alert to indicate possible corruption of data stored in an adjacent row to the memory row. | 03-24-2016 |
| 20160099044 | METHOD AND APPARATUS FOR A MEMORY MODULE TO ACCEPT A COMMAND IN MULTIPLE PARTS - Provided are a method and apparatus for a memory module to accept a command in multiple parts. A first half of a command is placed on a bus for a memory module in a first clock cycle. A chip select signal is placed on the bus for the memory module for the first half of the command. A second half of the command is placed on the bus in a second clock cycle following the first clock cycle, wherein the memory module accepts the second half of the command a delay interval from accepting the first half of the command. | 04-07-2016 |
| 20160125921 | INFORMATION PROCESSING APPARATUS, METHOD OF CONTROLLING THE SAME, PROGRAM, AND STORAGE MEDIUM - An information processing apparatus, equipped with a WideIO memory device stacked on an SOC die including a CPU, and a method of controlling the same, are provide. The apparatus obtains temperature information of each of a plurality of memories of the WideIO memory device, and generates temperature distribution information of the WideIO memory device in accordance with respective execution of a plurality of function modules. Then, the apparatus determines a refresh rate of the WideIO memory device based on the maximum temperature of the WideIO memory device, decides a period, at which the refresh rate is determined, based on an operation mode of the information processing apparatus and a change rate of the maximum temperature for a predetermined time interval, and refreshes the WideIO memory device in accordance with the determined refresh rate. | 05-05-2016 |
| 20160155491 | MEMORY PERSISTENCE MANAGEMENT CONTROL | 06-02-2016 |
| 20160172013 | ADDRESS AND CONTROL SIGNAL TRAINING | 06-16-2016 |
| 20160172014 | LEVERAGING INSTRUCTION RAM AS A DATA RAM EXTENSION DURING USE OF A MODIFIED HARVARD ARCHITECTURE PROCESSOR | 06-16-2016 |
| 20160180899 | IMPLEMENTING DRAM ROW HAMMER AVOIDANCE | 06-23-2016 |
| 20160180918 | SEMICONDUCTOR DEVICE, MEMORY ACCESS CONTROL METHOD, AND SEMICONDUCTOR DEVICE SYSTEM | 06-23-2016 |
| 20160189757 | MANAGING DISTURBANCE INDUCED ERRORS - In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells. | 06-30-2016 |
| 20160189766 | Systems and Methods Involving Multi-Bank, Dual- or Multi-Pipe SRAMs - Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank. | 06-30-2016 |
| 20160202926 | REFRESH ROW ADDRESS | 07-14-2016 |
| 20170236569 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM WITH COORDINATED CALIBRATION AND REFRESH OPERATIONS | 08-17-2017 |
| 20170236575 | MEMORY REFRESH OPERATION WITH PAGE OPEN | 08-17-2017 |
| 20180024769 | APPARATUSES AND METHODS FOR WRITE ADDRESS TRACKING | 01-25-2018 |
| 20220137843 | Multi-Modal Refresh of Dynamic, Random-Access Memory - A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data. | 05-05-2022 |
