| Entries |
| Document | Title | Date |
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| 20080201518 | LOG-BASED FTL AND OPERATING METHOD THEREOF - A log-based FTL and an operating method thereof for improving performances of reading and writing operations to increase the lifetime of a flash memory. In the method, when a reading operation for an LBN and an LPN is requested, a PBN and a PPN corresponding to the LBN and the LPN are calculated with reference to a pagemap corresponding to the LBN. A physical page of a physical block corresponding to the PBN and the PPN is accessed so that a reading operation is performed. On the other hand, when a writing operation for the LBN and the LPN is requested, a PBN and a PPN for a free-page of a physical block last assigned for the LBN are calculated with reference to a blockmap. The physical page of the physical block corresponding to the PBN and the PPN is accessed, so that a writing operation is performed. The pagemap stores a PBN and a PPN, and the blockmap stores a PBN list and a PPN. | 08-21-2008 |
| 20080201519 | MEMORY CARD - A memory card is structured to support a variety of applications by dividing a storage region into a plurality of sub storage regions, each sub storage region being assigned a particular data format associated with each of a plurality of application programs stored in a controller of the memory card. The data stored in each of the sub storage regions co-exists compatibly in the memory card. This allows for a multiplicity of applications, which can be made available through the use of a single memory card. | 08-21-2008 |
| 20080201520 | Flash firmware management - A computing host executes a web browser to access a utility application for managing one or more storage devices connected to the computing host. Management of each storage device may include making queries about the storage spaces and contents of the storage device, updating firmware of the storage device, updating programmable hardware of the storage device, erasing the storage device, sanitizing the storage device, logging events occurring in the storage device, and maintaining statistics on operation of the storage device. | 08-21-2008 |
| 20080201521 | Memory controller for controlling memory and method of controlling memory - A memory controller for controlling a memory that operates in synchronization with a clock signal, wherein the memory sequentially outputs data of addresses starting from a target address in synchronization with the clock signal after receiving a read command and the target address, the memory controller includes a supply control module that performs a supply process for supplying data inside the memory corresponding to a request address to an external device, in response to a read request designating the request address which is transmitted from the external device, wherein the supply process includes a supply process using a sequential mode, and wherein the supply process using the sequential mode includes a process for acquiring data to be supplied to the external device from the memory in response to read requests by repeatedly stopping and restarting supply of the clock signal without supplying the read command and the target address to the memory, in a case where a plurality of consecutive request addresses are sequentially designated one after another by a plurality of the consecutive read requests and a process for supplying requested data from among data acquired in response to the plurality of the read requests to the external device. | 08-21-2008 |
| 20080209106 | Memory access - A memory access system including a memory in which data is organized in pages, each page holding a sequence of data elements; means for receiving a requested address including a requested page address and a requested data element address; logic for accessing a current page from the memory using a current page address; logic for reading out data elements of the current page in the sequence in which they are held in memory; logic for comparing the requested page address with the current page address and for issuing a memory access request with the requested page address when they are not the same; and logic operable when the requested page address is the same as the current page address for comparing a requested data element address with the current address of a data element being read out and returning the data element when the requested data element address matches the current data element address. | 08-28-2008 |
| 20080209107 | Apparatus, method, and system of NAND defect management - Various embodiments comprise apparatus, methods, and systems that include an apparatus comprising a memory device configurable as a plurality of erase block groups including a base erase block group, wherein each of the plurality of erase block groups comprises a plurality of erase blocks each identified by a matching unique plurality of erase block numbers unique within the plurality of erase blocks and matching across the plurality of erase block groups; and a mapping table coupled to the plurality of erase block groups to store at least one group address number corresponding to one of the matching unique plurality of erase block numbers identifying a non-defective erase block in the base erase block group, and corresponding to several of the matching unique plurality of erase block numbers identifying a single non-defective erase block in each of the plurality of erase block groups other than the base erase block group. | 08-28-2008 |
| 20080209108 | System and method of page buffer operation for memory devices - Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory. | 08-28-2008 |
| 20080209109 | INTERRUPTIBLE CACHE FLUSHING IN FLASH MEMORY SYSTEMS - Cache flushing is effected for a flash memory by copying, to a block of the memory, first and second portions of cached data, and servicing a host access in-between copying the first portion and the second portion. Either both portions are selected before the copying, or erasing the block is forbidden until after the copying, or a portion of the block left unwritten by the first copying remains unwritten until after the host access is serviced. | 08-28-2008 |
| 20080209110 | APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA - An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements. | 08-28-2008 |
| 20080209111 | OVER-SAMPLING READ OPERATION FOR A FLASH MEMORY DEVICE - A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation. | 08-28-2008 |
| 20080209112 | High Endurance Non-Volatile Memory Devices - High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM. | 08-28-2008 |
| 20080209113 | Method For Increasing Storage Capacity of a Memory Device - A method for increasing memory storage capacity in a memory device having at least two storage cells wherein at least one measurable physical property is associated with each of the storage cells a nominal value of which may be used to assign a data value to the respective storage cell. Differences between at least two storage cells with regard to the respective nominal values of one or more of the respective physical properties associated with a storage cell and its actual value at a given time are used to provide additional storage capacity. | 08-28-2008 |
| 20080209114 | Reliability High Endurance Non-Volatile Memory Device with Zone-Based Non-Volatile Memory File System - Improved reliability high endurance non-volatile memory device with zone-based non-volatile memory file system is described. According to one aspect of the present invention, a zone-based non-volatile memory file system comprises a two-level address mapping scheme: a first level address mapping scheme maps linear or logic address received from a host computer system to a virtual zone address; and a second level address mapping scheme maps the virtual zone address to a physical zone address of a non-volatile memory module. The virtual zone address represents a number of zones each including a plurality of data sectors. Zone is configured as a unit smaller than data blocks and larger than data pages. Each of the data sector consists of 512-byte of data. The ratio between zone and the sectors is predefined by physical characteristics of the non-volatile memory module. A tracking table is used for correlating the virtual zone address with the physical zone address. Data programming and erasing are performed in a zone basis. | 08-28-2008 |
| 20080209115 | SEMICONDUCTOR MEMORY CARD ACCESS APPARATUS, A COMPUTER-READABLE RECORDING MEDIUM, AN INITIALIZATION METHOD, AND A SEMICONDUCTOR MEMORY CARD - A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster. | 08-28-2008 |
| 20080209116 | Multi-Processor Flash Memory Storage Device and Management System - A data storage device has a host controller interface, a plurality of microprocessor units each having a portion of random access memory (RAM) dedicated thereto, a plurality of Flash device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units, and a dataflow controller accessible to the host controller interface for managing access to the Flash device configurations. | 08-28-2008 |
| 20080215798 | Randomizing for suppressing errors in a flash memory - Original data to be stored in a nonvolatile memory are first randomized while preserving the size of the original data, In response for a request for the original data, the randomized data are retrieved, derandomized and exported without authenticating the requesting entity. ECC encoding is applied either before or after randomizing; correspondingly, ECC decoding is applied either after or before derandomizing. | 09-04-2008 |
| 20080215799 | Control Chip of Adapter Interconnecting Pc and Flash Memory Medium and Method of Enabling the Control Chip to Program the Flash Memory Medium to be Accessible by the Pc - In one embodiment an apparatus interconnecting a PC and a flash memory device is provided and includes a control chip including a RAM, a ROM, and a processor. The control chip is adapted to program the flash memory device as a main firmware stored with compatible configuration codes, an auxiliary firmware stored with programs of data encryption, flash memory device activation, and data compression, and a data storage segment so as to enable the PC to access the flash memory device via the control chip. Also, method of enabling the control chip to program the flash memory medium to be accessible by the PC is provided. | 09-04-2008 |
| 20080215800 | Hybrid SSD Using A Combination of SLC and MLC Flash Memory Arrays - Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one aspect of the present invention, a hybrid SSD is built using a combination SLC and MLC flash memory arrays. The SSD also includes a micro-controller to control and coordinate data transfer from a host computing device to either the SLC flash memory array of the MLC flash memory array. A memory selection indicator is determined by triaging data file based on one or more criteria, which include, but is not limited to, storing system files and user directories in the SLC flash memory array and storing user files in the MLC flash memory array; or storing more frequent access files in the SLC flash memory array, while less frequent accessed files in the MLC flash memory array. | 09-04-2008 |
| 20080215801 | Portable Data Storage Using Slc and Mlc Flash Memory - A portable data storage device is disclosed that includes an interface ( | 09-04-2008 |
| 20080215802 | High Integration of Intelligent Non-volatile Memory Device - High integration of a non-volatile memory device (NVMD) is disclosed. According to one aspect of the present invention, a non-volatile memory device comprises an intelligent non-volatile memory (NVM) controller and an intelligent non-volatile memory module. The NVM controller includes a central processing unit (CPU) configured to handle data transfer operations to the NVM module to ensure source synchronous interface, interleaved data operations and block abstracted addressing. The intelligent NVM module includes an interface logic, a block address manager and at least one non-volatile memory array. The interface logic is configured to handle physical block management. The block address manager is configured to ensure a physical address is converted to a transformed address that is accessible to the CPU of the intelligent NVM controller. The transformed address may be an address in blocks, pages, sectors or bytes either logically or physically. | 09-04-2008 |
| 20080215803 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories. | 09-04-2008 |
| 20080222347 | Method and apparatus for protecting flash memory - A method is provided for protecting flash memory residing on a computing device. The method includes: receiving a data file having a digital signature at a main processor; forwarding the data file from the main processor to a secondary processor for signature validation; validating the digital signature associated with the data file at the secondary processor; enabling a write capability of a flash memory upon successful validation of the digital signature; and writing the data file to the flash memory. | 09-11-2008 |
| 20080222348 | File system for managing files according to application - The present invention discloses systems for managing files according to application. A digital storage system including: a storage memory having program code configured: to identify an application identity of an application issuing a storage command to access a file; and to adjust a storage mode of the file according to the application identity; and a processor for executing the program code. Preferably, the identifying is performed using a PID that is an indicator of the application identity. Preferably, the adjusting includes adjusting the storage mode according to the storage command. Preferably, the adjusting is performed using an SAT and/or an AST. A digital storage system including: a storage memory having program code configured: to identify an application scenario associated with a storage command to access a file; and to adjust a storage mode of the file according to the application scenario; and a processor for executing the program code. | 09-11-2008 |
| 20080222349 | IEEE 1394 INTERFACE-BASED FLASH DRIVE USING MULTILEVEL CELL FLASH MEMORY DEVICES - A flash drive and method of transferring data from a system to a flash drive. The flash drive includes a casing, a plurality of flash memory devices within the casing, each of the flash memory devices having multilevel cells, an IEEE 1394 interface controller within the casing, coupled to the flash memory devices, and interfacing with the flash memory devices for interleaved multichannel access to and from at least two of the flash memory devices, and at least one IEEE 1394 interface connector projecting from the casing for interfacing the flash memory devices with a system through the controller. The method entails coupling a plurality of multilevel cell flash memory devices to a system through an IEEE 1394 interface controller and at least one IEEE 1394 interface connector, and performing interleaved multichannel access to and from at least two of the flash memory devices. | 09-11-2008 |
| 20080222350 | Flash memory device for storing data and method thereof - A flash memory device which comprises a controller and one or plurality of flash memories for storing data and method thereof are disclosed. The controller comprises a control interface to accept data access which is from a main board and is managed by a control element of flash memory and a buffer management element. Through a micro-processing element in the controller, the data access from main board is checked for a random access or a serial page access. The random access and serial page access are written to different blocks by different processes in one or plurality of flash memories. The lifetime and processing speed of flash memories are improved for reduced erasure times during writing data. | 09-11-2008 |
| 20080228995 | Portable Data Storage Device Using a Memory Address Mapping Table - A portable data storage device includes a USB controller, a master control unit and a NAND flash memory device. The master control unit receives data to be written to logical addresses, and instructions to read data from logical addresses. It uses a memory address mapping table to associate the logical addresses with the physical addresses in the memory device, and writes data to or reads data from the physical address corresponding to the logical address. The mapping is changed at intervals, so that different ones of the physical address regions are associated at different times with the logical addresses. This increases the speed of the device, and also means that no physical addresses are rapidly worn out by being permanently associated with logical addresses to which data is written relatively often. | 09-18-2008 |
| 20080228996 | Portable Data Storage Device Using Multiple Memory Devices - A portable data storage device includes a USB interface ( | 09-18-2008 |
| 20080228997 | ZONED INITIALIZATION OF A SOLID STATE DRIVE - Zoned initialization of a solid state drive is provided. A solid state memory device includes a controller for controlling storage and retrieval of data to and from the device. A set of solid state memory components electrically coupled to the controller. The set is electrically divided into a first zone and a second zone, wherein the first zone is at least partially initialized independent from the second zone. An interface is coupled between the controller and the set of solid state memory components to facilitate transfer of data between the set of solid state memory components and the controller. | 09-18-2008 |
| 20080228998 | MEMORY STORAGE VIA AN INTERNAL COMPRESSION ALGORITHM - The subject specification discloses flash memory device with the capability of performing both internal compression as well as internal de-compression. Each of these actions takes place through appropriate algorithms. In normal operation, the compression occurs prior to a writing of data in a flash memory device. The compressed data travels to a storage location. The de-compression occurs after the reading of stored data and de-compressed data travels to an external system. | 09-18-2008 |
| 20080228999 | Dual use for data valid signal in non-volatile memory - In some types of non-volatile memory devices, the same signal from a memory device may be used for two purposes: During a read operation, the signal may be used by a memory controller to latch the data that is being received from the memory device. During a block erase operation and/or a block write operation, the signal may be used to notify the memory controller that the operation has been completed by the memory device. | 09-18-2008 |
| 20080229000 | FLASH MEMORY DEVICE AND MEMORY SYSTEM - A memory system comprises a flash memory, a processing unit, and a flash controller including address and control registers, the address and control registers being configured to receive information from the processing unit, wherein the flash controller is configured to control a copy-back program operation of the flash memory in hardware based on information stored in the address and control registers. | 09-18-2008 |
| 20080229001 | Solid memory module with extensible capacity - A solid memory module with extensible capacity includes at least a non-volatile memory module, each of which has at least a memory chip and a first connector, and at least a second connector, which electrically connects the first connector of the volatile memory module, at least a control unit and as a system interface. This control unit obtains external signals by this system interface and then transmits to this non-volatile memory module by the control unit to store or use the memory content. | 09-18-2008 |
| 20080229002 | SEMICONDUCTOR MEMORY AND INFORMATION PROCESSING SYSTEM - A semiconductor memory ( | 09-18-2008 |
| 20080229003 | STORAGE SYSTEM AND METHOD OF PREVENTING DETERIORATION OF WRITE PERFORMANCE IN STORAGE SYSTEM - Provided is a storage system capable of inhibiting the deterioration of its write performance. This storage system includes a flash memory, a cache memory, and a controller for controlling the reading, writing and deletion of data of the flash memory and the reading and writing of data of the cache memory, and detecting the generation of a defective block in the flash memory. When the controller detects the generation of a defective block in the flash memory, it migrates prescribed data stored in the flash memory to the cache memory and, even upon receiving from the host computer a command for updating the migrated data, disables the writing of data in the flash memory based on the command. | 09-18-2008 |
| 20080229004 | PROCESSOR SYSTEM USING SYNCHRONOUS DYNAMIC MEMORY - A processor system including: a processor and controller core connected via an internal bus; and a plurality of synchronous memory chips connected to the processor via an external bus; the controller core including a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips. | 09-18-2008 |
| 20080229005 | Multi Partitioned Storage Device Emulating Dissimilar Storage Media - A digital media. In one embodiment, the digital media devices includes a storage unit/partition that emulates a Compact Disc-Read Only Memory (CD-ROM), and optionally, a second storage unit/partition that acts as a Read/Write storage device. | 09-18-2008 |
| 20080235435 | USE OF A SHUTDOWN OBJECT TO IMPROVE INITIALIZATION PERFORMANCE - According to some embodiments, use of a shutdown object during system initialization is disclosed. The shutdown object may be read from a non-volatile memory device and loaded into a random access memory. A plurality of headers may then be scanned from the non-volatile memory device. The shutdown object may be referenced to determine whether each of the plurality of headers includes valid data. Each of the plurality of headers that includes valid data may be represented in the random access memory. | 09-25-2008 |
| 20080235436 | STORAGE ACCESS CONTROL - A system and device are disclosed. In one embodiment, the system includes a processor, system memory, chipset, flash memory, and flash memory controller. The flash memory controller includes a base address register for a flash memory hidden protected area (HPA) to store a flash memory HPA base address, a size register for a flash memory HPA to store a size of the flash memory HPA, and control logic to allocate a portion of the flash memory as a flash memory HPA using the flash memory HPA base address and the flash memory HPA size address. | 09-25-2008 |
| 20080235437 | Methods for forcing an update block to remain sequential - A method for operating a memory system is provided. In this method, a sequential update block and preexisting data associated with the sequential update block are provided. Here, an option to convert the sequential update block to a chaotic update block also is provided. A write command is received to write data following a previous write command, where the write command and the previous write command have a discontinuity in logical addresses. If a logical address of the write command is different from logical addresses of the preexisting data, then the data are written to the sequential update block. If the logical address of the write command matches one of the logical addresses of the preexisting data, then the sequential update block is converted to a chaotic update block. | 09-25-2008 |
| 20080235438 | System and method for effectively implementing a multiple-channel memory architecture - A system and method for implementing a multiple-channel memory architecture includes a plurality of memory channels that are configured in a parallel manner to store electronic data. In certain embodiments, the memory channels are implemented to include non-volatile flash memory devices. A transfer controller communicates with the memory channels to control concurrent data transfer operations for transferring the electronic data in and out of the memory channels. The transfer controller generates individual channel clock signals to the respective memory channels for triggering corresponding data transfer operations which occur in an overlapping temporal sequence. | 09-25-2008 |
| 20080235439 | Methods for conversion of update blocks based on association with host file management data structures - A method for operating a memory system is provided. In this method, a sequential update block is provided and a write command is received to write data. The write command comprises a logical address associated with the data. If the logical address is associated with a host file management data structure, then the sequential update block is converted to a chaotic update block. After the conversion, the data are written to the chaotic update block. | 09-25-2008 |
| 20080235440 | Memory device - A memory device includes a housing, a memory within the housing, and a first electrical interface accessible on a top surface of the housing and a second electrical interface accessible on a bottom surface of the housing. As such, at least one of the first electrical interface and the second electrical interface is configured to establish electrical connection of the memory device with an electrical interface of another memory device when the memory device and the another memory device are in a stacked configuration. | 09-25-2008 |
| 20080235441 | Reducing power dissipation for solid state disks - A data processing device including a computer, the computer including a solid state disk (SSD), including a primary memory for single level cell storage, and a secondary memory for multi-level cell storage, a limited internal battery for supplying power to the computer, a socket for connecting the computer to an external power supply source, a detector for indicating that the computer is connected to an external power source, a processor for transferring data from the primary memory to the secondary memory, and an SSD controller for deciding whether or not the processor may transfer data from the primary memory to the secondary memory, based on a signal received from said detector. A method for SSD memory management is also described and claimed. | 09-25-2008 |
| 20080235442 | FLASH MEMORY DEVICE CAPABLE OF IMPROVING READ PERFORMANCE - A flash memory device, related system ad method are disclosed. The memory device includes a memory cell array a page buffer receiving read data, wherein the page buffer includes a main register transferring read data to a cache register during an read operation, and a control logic block controlling operation of the page buffer during the read operation, such that initialization of the main register continuously extends beyond a time period during which read data is transferred from the main register to the cache register. | 09-25-2008 |
| 20080235443 | Intelligent Solid-State Non-Volatile Memory Device (NVMD) System With Multi-Level Caching of Multiple Channels - A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security. | 09-25-2008 |
| 20080244162 | METHOD FOR READING NON-VOLATILE STORAGE USING PRE-CONDITIONING WAVEFORMS AND MODIFIED RELIABILITY METRICS - Data stored in non-volatile storage is read using sense operations and associated pre-conditioning waveforms. The pre-conditioning waveform provides a short term history for a non-volatile element which is analogous to the conditions experienced during programming when a programming pulse is applied prior to a verify operation. The pre-conditioning waveform can cause electrons to enter and exit trap sites, for instance, so that the accuracy of a probabilistic decoding process is improved. In one approach, multiple read operations are performed, some with pre-conditioning waveforms and some without. Pre-conditioning waveforms with different characteristics, such as amplitude, shape, duration and time before the associated read pulse, can also be used. For probabilistic decoding, initial reliability metrics can be developed based on multiple reads. Tables which store the reliability metrics can then be prepared for use in subsequent decoding. | 10-02-2008 |
| 20080244163 | PORTABLE DATA ACCESS DEVICE - A portable data access device is applicable to a data processing system. The portable data access device includes at least a first data access sector preset to be a read-only data access sector, for storing at least data and/or application programs executable by the data processing system; at least a second data access sector set to be a general data access sector; and a controller for interfacing with the data processing system and controlling data access to the first data access sector and the second data access sector. The data processing system may execute the application programs and/or access the data through the portable data access device, and the risk of modifying or damaging the data and/or application programs can be reduced by the read-only data access sector. | 10-02-2008 |
| 20080244164 | STORAGE DEVICE EQUIPPED WITH NAND FLASH MEMORY AND METHOD FOR STORING INFORMATION THEREOF - A storage device equipped with NAND flash memory and method for storing information thereof includes a SLC processing structure to provide fast information access and improve processing performance and a MLC processing structure to increase data density of each storage unit and reduce the cost and size of each unit of information. The data storing method includes storing important information such as operating system programs, application programs and information that have been accessed frequently in the SLC processing structure, and storing ordinary information in the MLC processing structure to reduce the cost and size of each unit of information. | 10-02-2008 |
| 20080244165 | Integrated Memory Management Device and Memory Device - An example of a device comprises a first MMU converting a logical address into a physical address for a cache, a controller accessing the cache based on the physical address for the cache, a first storage storing history data showing an access state to a main memory outside a processor, a second storage storing relation data showing a relationship between a logical address and a physical address in the main memory, and a second MMU converting a logical address into a physical address for the main memory based on the history and relation data and accessing the main memory based on the physical address for the main memory. The first and second MMU, controller, first storage, second storage are included in the processor. | 10-02-2008 |
| 20080244166 | System and method for configuration and management of flash memory - A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block. By forming correspondence among the physical erase unit, segment, frame, page, virtual erase unit, area, memory logical block and cluster to control the data access to the flash memory, the present invention achieves the reconfiguration and management of memory consumption and access efficiency for the flash memory. | 10-02-2008 |
| 20080250190 | PORTABLE MEMORY DEVICE OPERATING SYSTEM AND METHOD OF USING SAME - A portable operating system for use by a user on a portable memory device, the system being accessible by the user on a primary host computer having a host graphical user interface. The system includes a portable graphical user interface accessible by the user when the portable memory device is placed into communication with the primary host computer, at least one portable application executable by the user via the portable graphical user interface, and a file system accessible by the user. Dragging at least one file from a host graphical user interface of the primary host computer to the portable graphical user interface activates a file system to transfer files into respective portable file folders corresponding to the respective filetype. | 10-09-2008 |
| 20080250191 | FLEXIBLE, LOW COST APPARATUS AND METHOD TO INTRODUCE AND CHECK ALGORITHM MODIFICATIONS IN A NON-VOLATILE MEMORY - A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface. | 10-09-2008 |
| 20080250192 | Integrating flash memory system - The present invention discloses an integrating data processing system. The system includes a master device with a host interface for processing data, at least one NAND flash memory unit having a unit interface, and a flash memory controller. For controlling access to the NAND flash memory unit, the flash memory controller is provided with a first interface connected with the host interface of the master device, and a second interface connected with the unit interface of the NAND flash memory unit. The first interface is identical to the unit interface of the flash memory and the second interface is identical to the host interface of the master device. The master device can access the NAND flash memory unit via the flash memory controller thereby facilitating to fit in with the development of new flash memory device without upgrading the original master device. | 10-09-2008 |
| 20080250193 | Method to transmit important emergency personal and medical information via portable storage media - This invention presents a way to carry concise, important personal and medical information in a very portable format using information storage media, in a convenient carrying form for universal use by emergency medical or police personnel to assist the person carrying the device. | 10-09-2008 |
| 20080250194 | TWO-DIMENSIONAL WRITING DATA METHOD FOR FLASH MEMORY AND CORRESPONDING STORAGE DEVICE - In a two-dimensional writing data method for a flash memory and a corresponding storage device the storage device includes a plurality of flash modules and a control module. The flash modules are electrically connected to the control module. The control module includes a plurality of buffers and a process unit. The buffers are electrically connected to the respective flash modules and electrically connected to the process unit. The process unit is configured for managing a plurality of memory pages of the flash modules and defining addresses of the memory pages of the flash modules to form a two-dimensional access sequence. The process unit divides data into a plurality of data packets, and transmits the data packets into the buffers in series. The data is written into the corresponding memory pages from the respective buffers, thus the access time of the storage device is decreased. | 10-09-2008 |
| 20080250195 | Multi-Operation Write Aggregator Using a Page Buffer and a Scratch Flash Block in Each of Multiple Channels of a Large Array of Flash Memory to Reduce Block Wear - A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table. | 10-09-2008 |
| 20080256287 | Methods and systems of managing memory addresses in a large capacity multi-level cell (MLC) based flash memory device - Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM. | 10-16-2008 |
| 20080256288 | MICROCOMPUTER, ELECTRONIC INSTRUMENT, AND FLASH MEMORY PROTECTION METHOD - A microcomputer includes a flash memory and a flash controller that controls access to the flash memory, the flash memory including a protection information storage section that stores protection information, the protection information indicating whether or not access to a given area of the flash memory is available; the flash controller including a flash protection section that performs a protection process relating to access to a given area of the flash memory based on the protection information; and the flash protection section performing the protection process relating to access to the flash memory when an access target is data. | 10-16-2008 |
| 20080256289 | MEMORY APPARATUS TO WRITE AND READ DATA, AND METHOD THEREOF - An apparatus and method of reading and writing data from and on a storage medium include receiving at least one of file information and file data from a host, generating a logical block address corresponding to the one of the file information and the file data, and writing the one of the file information and the file data at the generated logical block address | 10-16-2008 |
| 20080263264 | DATA ACCESS CONTROL SYSTEM AND METHOD OF MEMORY DEVICE - A data access control system of a memory includes a micro-processor, having a micro-controller, a command decoder, and a memory interface. The data access control system can be used to control display driving of a display system. The command decoder is used to decode the content of a data access command. A memory unit is configured into a first region for storing a first-type data being stored in a memory manner, and a second region for storing a second-type data being stored in a simulation manner of the memory. A bus is connected between the micro-processor and the memory unit, for performing data transmission. The micro-processor uses the memory interface to write data into the first region of the memory unit, and uses the command decoder to convert the nonvolatile data and write into the second region of the memory unit. | 10-23-2008 |
| 20080263265 | ADAPTIVE DYNAMIC READING OF FLASH MEMORIES - Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. Values of parameters of threshold voltage functions are adjusted in accordance with comparisons of the threshold voltages of some or all of the cells to two or more of m≧2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on the values. Alternatively, the m threshold voltage intervals span the threshold voltage window, and respective threshold voltage states are assigned to the cells based on numbers of cells whose threshold voltages are in the intervals, without re-reading the cells. | 10-23-2008 |
| 20080263266 | ADAPTIVE DYNAMIC READING OF FLASH MEMORIES - Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. A histogram is constructed by determining how many of some or all of the cells have threshold voltages in each of two or more of m≧2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on estimated values of shape parameters of the histogram. Alternatively, the cells are read relative to reference voltages that define m≧2 threshold voltage intervals that span the threshold voltage window, to determine numbers of at least a portion of the cells whose threshold voltages are in each of two or more of the threshold voltage intervals. Respective threshold voltage states are assigned to the cells based on the numbers without re-reading the cells. | 10-23-2008 |
| 20080270677 | Safe software revision for embedded systems - The present invention, in one embodiment includes identifying a first partition of an embedded program memory, reading a description associated with the first partition, identifying a second partition of an embedded program memory, reading a description associated with the second partition, comparing descriptions, selecting an embedded program memory partition using the comparison, and writing program code to the selected program memory partition. | 10-30-2008 |
| 20080270678 | COMMAND RESEQUENCING IN MEMORY OPERATIONS - Systems and processes may include a memory coupled to a memory controller. Command signals for performing memory access operations may be received. Attributes of the command signals, such as type, time lapsed since receipt, and relatedness to other command signals, may be determined. Command signals may be sequenced in a sequence of execution based on the attributes. Command signals may be executed in the sequence of execution. | 10-30-2008 |
| 20080270679 | CONTROL CIRCUIT OF FLASH MEMORY DEVICE AND METHOD OF OPERATING THE FLASH MEMORY DEVICE - Provided is a method of operating a flash memory device having a first area and a second area, in which a programmed state and an erased state of the first area are opposite to that of the second area. The method includes receiving a program command, inverting the program data when the received program command is a command for programming the second area, and programming the inverted program data into the second area. | 10-30-2008 |
| 20080270680 | Controller for Non-Volatile Memories and Methods of Operating the Memory Controller - A non-volatile memory system ( | 10-30-2008 |
| 20080270681 | Non-Volatile Memory with Block Erasable Locations - A main memory ( | 10-30-2008 |
| 20080270682 | METHOD FOR USING A MULTI-BIT CELL FLASH DEVICE IN A SYSTEM NOT DESIGNED FOR THE DEVICE - A computerized system is booted from a flash memory device configured to always operate one or more of its blocks only in a M-bit-per-cell mode and the rest of its blocks in a N>M-bit-per-cell mode. When the system is powered up, an initialization program is retrieved from the M-bit-per-cell block(s), corrected for errors using a first error correction method, and executed. Data accessed subsequently from the N-bit-per-cell blocks are corrected using an error correction method that corrects more errors per block than the first error correction method. | 10-30-2008 |
| 20080276035 | Wear Leveling - A reference memory location can be designated in a memory device. A memory location can be designated in response to storing data in the memory device. If the identified memory location is associated with the reference memory location then an allocated memory location can be designated relative to the reference memory location, and the allocated memory location can be leveled. | 11-06-2008 |
| 20080276036 | Memory with Block-Erasable Location - A non-volatile main memory ( | 11-06-2008 |
| 20080276037 | Method to Access Storage Device Through Universal Serial Bus - A method accessing a flash memory storage device through universal serial bus (USB) of the present invention includes a flash controller and a flash memory, wherein the method includes connecting the storage device to a USB interface of an electronic device; outputting a plurality of accessing instructions to the flash controller via the electronic device; deciding which data is needed to be temporarily saved in a cache memory and a priority of the accessing instructions according to the characteristic of the file system and the content of preceding instructions of the flash controller; and writing the data temporarily saved in the cache memory into the flash memory according to the priority of the flash controller. The objective of the method of the present invention is to enhance the operation efficiency of the storage device. | 11-06-2008 |
| 20080276038 | Storage system using flash memory modules logically grouped for wear-leveling and raid - A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group. | 11-06-2008 |
| 20080282023 | Restoring storage devices based on flash memories and related circuit, system, and method - A solution for restoring operation of a storage device based on a flash memory is proposed. The storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A corresponding method starts by detecting a plurality of conflicting physical blocks for a corrupted logical block (resulting from a breakdown of the storage device). The method continues by determining a plurality of validity indexes (indicative of the number of last versions of the logical sectors of the corrupted logical block that are stored in the conflicting physical blocks). One ore more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded. | 11-13-2008 |
| 20080282024 | Management of erase operations in storage devices based on flash memories - A method of freeing physical memory space in an electrically alterable memory that includes a plurality of physical memory blocks includes a plurality of physical memory pages. Each physical memory block may be individually erased as a whole, and which memory is used to emulate a random access logical memory space including a plurality of logical memory sectors by storing updated versions of a logical memory sector data into different physical memory pages. The method includes causing a most recent version of multiple versions of logical memory sector data, stored in physical pages of at least one physical memory block, to be copied into an unused physical memory block, marking the at least one physical memory block, and when the electrically alterable memory is idle, erasing the marked physical memory block. | 11-13-2008 |
| 20080282025 | Wear leveling in storage devices based on flash memories and related circuit, system, and method - A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased. | 11-13-2008 |
| 20080282026 | Bioprocess data management - A data management system for a biological process, comprising:
| 11-13-2008 |
| 20080288712 | ACCESSING METADATA WITH AN EXTERNAL HOST - Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host. | 11-20-2008 |
| 20080288713 | FLASH-AWARE STORAGE OPTIMIZED FOR MOBILE AND EMBEDDED DBMS ON NAND FLASH MEMORY - Reliable storage for database management systems (DBMS) running on memory devices such as NAND type flash memory utilizes minimum I/O overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the DBMS pages and prevent overwriting or data loss. There is no need for journaling and logging, and performance is increased by reducing the write and erase counts on the flash memory. The logical page numbers of the DBMS are mapped to physical page numbers in the page map, such that the virtual page map allocates an available page from the physical pages when changes to a page occur, and the updated information is stored in the allocated page. The allocated page number is mapped to the logical page number of the original page, thus maintaining a modified page representation while preventing physical in-place updates. | 11-20-2008 |
| 20080288714 | FILE STORAGE IN A COMPUTER SYSTEM WITH DIVERSE STORAGE MEDIA - A method for storing data in a computer having a magnetic hard disk drive (HDD) and an electronic solid-state drive (SSD). The method includes configuring the computer so that the HDD and the SSD are each independently accessible by an operating system of the computer. A plurality of files is received for storage by the computer. A predicted use profile of the computer is defined. A respective one of the HDD and the SDD is selected for the storage of each of the files responsively to the predicted use profile. | 11-20-2008 |
| 20080288715 | Memory Page Size Auto Detection - Methods and apparatuses are presented for memory page size auto detection. A method for automatically determining a page size of a memory device includes receiving page size extents of the memory device, determining a bus width of the memory device, detecting a number of pages having an automatic detection marker, and determining the page size of the memory device based upon the detected number of pages and the received page size extents. An apparatus for automatically determining page size detection includes logic for performing the above presented method. | 11-20-2008 |
| 20080288716 | STORAGE DEVICE - A storage device includes: a binary flash memory that has a first storage area and a capacity of storing two values per each cell; a multivalued flash memory that has a second storage area and a capacity of storing at least three values per each cell; and a controller configured to arrange the first storage area ahead of the second storage area, logically combine the first storage area with the second storage area to form a single combined storage area, and perform data reading and data writing from and into the combined storage area. Data management information is stored in a head of the combined storage area according to a predetermined file system. The storage device of this arrangement has the advantages of both an SLC flash memory and an MLC flash memory. | 11-20-2008 |
| 20080288717 | SINGLE SECTOR WRITE OPERATION IN FLASH MEMORY - A flash storage device having improved write performance is provided. The device includes a storage block having a plurality of physical pages and a controller for mapping the plurality of physical pages to a plurality of logical addresses and for writing data to the plurality of physical pages. When updating data previously written to one of the plurality of logical addresses, the controller is configured to write the updated data to a second physical page which is mapped to the logical address. Each of the logical addresses may be associated with a pointer field, which is for storing a pointer value indicating the invalidity of a physical page and/or the location of another physical page. | 11-20-2008 |
| 20080294834 | SOLID STATE STORAGE SUBSYSTEM FOR EMBEDDED APPLICATIONS - A non-volatile storage subsystem solution is provided for embedded applications. The storage subsystem is preferably designed to communicate with the host system using a signal interface, such as a USB or SATA interface, that uses substantially fewer signal lines than the IDE interface traditionally used for embedded applications. Thus, the amount of board real estate used to carry interface signals in the host system is reduced. To further reduce board real estate, the host system may include a processor that includes an integrated controller (e.g., a USB or SATA controller) corresponding to the host-subsystem signal interface. The storage subsystem may plug into, and lock to, an internal connector on a circuit board of the host system. | 11-27-2008 |
| 20080294835 | SOLID STATE STORAGE SUBSYSTEM FOR EMBEDDED APPLICATIONS - A non-volatile storage subsystem solution is provided for embedded applications. The storage subsystem is preferably designed to communicate with the host system using a signal interface, such as a USB or SATA interface, that uses substantially fewer signal lines than the IDE interface traditionally used for embedded applications. Thus, the amount of board real estate used to carry interface signals in the host system is reduced. To further reduce board real estate, the host system may include a processor that includes an integrated controller (e.g., a USB or SATA controller) corresponding to the host-subsystem signal interface. The storage subsystem may plug into, and lock to, an internal connector on a circuit board of the host system. | 11-27-2008 |
| 20080294836 | NAND flash memory system with programmable connections between a NAND flash memory controller and a plurality of NAND flash memory modules and method thereof - A method and related system for programming connections between a NAND flash memory controller and a plurality of NAND flash memory modules includes the NAND flash memory controller generating a switch signal and a swap signal according to a condition of one of the plurality of NAND flash memory modules, a remap module selectively coupling the plurality of NAND flash memory modules to the NAND flash memory controller according to the switch signal, and a swap module selectively coupling the plurality of NAND flash memory modules to the NAND flash memory controller according to the swap signal. | 11-27-2008 |
| 20080294837 | MEMORY CONTROLLER FOR CONTROLLING A NON-VOLATILE SEMICONDUCTOR MEMORY AND MEMORY SYSTEM - A memory controller includes a host interface, a holding circuit and a control circuit. The memory controller controls a semiconductor memory. The semiconductor memory includes memory blocks. The host interface is connectable to a host apparatus and receivable of write data and an address. The holding circuit is capable of holding the address. The control circuit searches information indicating an existence of a parent directory from the write data, and holds the address in the holding circuit when the information is detected. The control circuit successively writes the write data to the same memory block when a new write access is made with respect to the same address as the address held in the holding circuit. | 11-27-2008 |
| 20080294838 | UNIVERSAL BOOT LOADER USING PROGRAMMABLE ON-CHIP NON-VOLATILE MEMORY - In one embodiment, an IC system includes a system on a chip (SoC) adapted to load boot-up code from an external NAND flash memory, which stores the boot-up code. The SoC has a processor, an internal ROM including boot-loading code, an operating RAM, a NAND flash controller (NFC), and an OTP memory. At some point after SoC manufacture, the OTP memory is programmed with parameters needed for communication between the NFC and the external NAND flash memory. This provides a system designer flexibility in choosing a type of external NAND flash memory for the IC system. During SoC power-up, the NFC is initialized with the communication parameters, thereby allowing the NFC to control the NAND flash memory. The boot-loading code directs the processor to load the boot-up code from the external NAND memory onto the operating RAM. The processor then executes the boot-up code from the operating RAM. | 11-27-2008 |
| 20080301355 | FLASH MEMORY INFORMATION READING/WRITING METHOD AND STORAGE DEVICE USING THE SAME - A flash memory information read/write method in which an external resource such as host, external memory, EEPROM, or external controller is used to read and update new flash memory information after fabrication of a flash memory device, enabling the new flash memory information to be written in a predetermined address in a flash memory module of the flash device by a controller of the flash memory device, so that every flash memory device that has an erroneous or damaged factory data or information is still usable, and the flash memory controller provider needs not to continuously develop new firmware controllers for different flash memories. | 12-04-2008 |
| 20080301356 | FAST WRITING NON-VOLATILE MEMORY - A method writes data in a non-volatile memory comprising memory cells that are erased before being written. The method comprises the steps of providing a main non-volatile memory area comprising target pages, providing an auxiliary non-volatile memory area comprising auxiliary pages, providing a look-up table to associate to an address of invalid target page an address of valid auxiliary page, and, in response to a command for writing a piece of data in a target page writing the piece of data as well as the address of the target page in a first erased auxiliary page, invalidating the target page, and updating the look-up table. | 12-04-2008 |
| 20080301357 | NON-VOLATILE MEMORY WITH AUXILIARY ROTATING SECTORS - A method writes data in a non-volatile memory. The method provides, in the memory, a non-volatile main memory area comprising target pages, a non-volatile auxiliary memory area comprising auxiliary pages, and, in the auxiliary memory area: a current sector comprising erased auxiliary pages usable to write data, a save sector comprising auxiliary pages comprising data linked to target pages to be erased or being erased, a transfer sector comprising auxiliary pages including data to be transferred to erased target pages, and an unavailable sector comprising auxiliary pages to be erased or being erased. The method can be applied in particular to FLASH memories. | 12-04-2008 |
| 20080301358 | Electronic device that Downloads Operational Firmware from an External Host - An electronic device comprises an interface unit, a control circuit and a microprocessor. The interface unit receives a first operational firmware from a host. The control circuit transfers the first operational firmware to a memory. The microprocessor executes the first operational firmware which stored in the memory. The microprocessor controls operations of the electronic device according to the first operational firmware. And the control circuit is electrically coupled to a non-volatile memory which stores a second operational firmware for performing a specific function also performed by the first operational firmware. | 12-04-2008 |
| 20080301359 | Non-Volatile Memory and Method With Multi-Stream Updating - In a memory that is programmable page by page and each page having multiple sectors that are once-programmable, even if successive writes are sequential, the data recorded to an update block may be fragmented and non-sequential. Instead of recording update data to an update block, the data is being recorded in at least two interleaving streams. When a full page of data is available, it is recorded to the update block. Otherwise, it is temporarily recorded to the scratch pad block until a full page of data becomes available to be transferred to the update block. Preferably, a pipeline operation allows the recording to the update block to be set up as soon as the host write command indicates a full page could be written. If the actual write data is incomplete due to interruptions, the setup will be canceled and recording is made to the scratch pad block instead. | 12-04-2008 |
| 20080307154 | System and Method for Dual-Ported I2C Flash Memory - A method for emulating a dual-port I2C device includes monitoring a bus for I2C traffic. A system receives an I2C interrupt on the bus. The system determines whether the received I2C interrupt is one of either a hardware interrupt or a software interrupt. In the event the received I2C interrupt is a hardware interrupt, the system responds to the hardware interrupt, and accesses a flash memory for read/write operation based on the hardware interrupt. In the event the received I2C interrupt is a software interrupt, the system responds to the software interrupt, and accesses a flash memory for read/write operation based on the software interrupt. | 12-11-2008 |
| 20080307155 | Method of Interfacing A Host Operating Through A Logical Address Space With A Direct File STorage Medium - A method and system for interfacing a system operating through a logical address space with a direct file storage (DFS) medium is disclosed. The method includes receiving data associated with addresses in a logical block address (LBA) format from a host system and generating file objects manageable by the DFS medium based on a determination of the correlation of the LBA data to host file data. The memory system includes non-volatile memory using the DFS format, an interface for receiving LBA format data, and a controller configured to communicate with the host via an LBA interface and generate file objects from the LBA format data correlated to the host application files usable by the memory system. | 12-11-2008 |
| 20080307156 | System For Interfacing A Host Operating Through A Logical Address Space With A Direct File Storage Medium - A method and system for interfacing a system operating through a logical address space with a direct file storage (DFS) medium is disclosed. The method includes receiving data associated with addresses in a logical block address (LBA) format from a host system and generating file objects manageable by the DFS medium based on a determination of the correlation of the LBA data to host file data. The memory system includes non-volatile memory using the DFS format, an interface for receiving LBA format data, and a controller configured to communicate with the host via an LBA interface and generate file objects from the LBA format data correlated to the host application files usable by the memory system. | 12-11-2008 |
| 20080307157 | Method and system for updating firmware of microcontroller - A system for updating firmware of a microcontroller includes a serial peripheral interface (SPI), an inter integrated Circuit (I | 12-11-2008 |
| 20080307158 | METHOD AND APPARATUS FOR PROVIDING DATA TYPE AND HOST FILE INFORMATION TO A MASS STORAGE SYSTEM - A method and system for providing advance data type information to a mass storage system is disclosed. The method may include a host system providing host file information, such as a host file identifier and/or a data type, to a memory system in addition to LBA format data. The system may include a processor, a memory system interface and a host file system operative on the processor to identify and provide host file information and/or data type information to the memory system along with LBA format data. | 12-11-2008 |
| 20080307159 | Method and control device for operating a non-volatile memory, in particular for use in motor vehicles - A method for the consecutive writing of performance quantity data to a non-volatile memory, in particular in a control device in a motor vehicle. The method encompasses the operations of determining a write address, which defines an address space for the writing of a performance quantity datum to be written, the address space being directly contiguous with a memory area occupied by a previously written performance quantity datum, and of writing the performance quantity datum to be written, to the address space of the non-volatile memory defined by the write address. In the determination operation, the write address corresponds directly to an address datum assigned to the most recently written performance quantity data, which is stored in a referencing datum in the non-volatile memory, or it is determined therefrom with the aid of an address offset that is independent of the size of the previously written performance quantity data. | 12-11-2008 |
| 20080313387 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF READING DATA RELIABLY - A control unit reads data from a plurality of memory cells connected to one of the word lines in a read operation at a first level CR generated by a voltage generator circuit and in a read operation at a second level CR−x and finds the number of cells included between the first level and the second level from the data and, if the number is equal to or smaller than a specified value, determines the result of the read operation at the first level to be read data. | 12-18-2008 |
| 20080313388 | ELECTRONIC DATA FLASH CARD WITH VARIOUS FLASH MEMORY CELLS - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 12-18-2008 |
| 20080313389 | ELECTRONIC DATA FLASH CARD WITH VARIOUS FLASH MEMORY CELLS - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 12-18-2008 |
| 20080313390 | Method and System for Presenting an Executing Status of a Memory Card - A system and a method for presenting an executing status of a memory card are provided. The system comprises a processing apparatus and an access device. The processing apparatus stores an application program having a plurality of icons. The access device connects the memory card and the processing apparatus. The processing apparatus sends a reading command to the memory card via the access device. The memory card sends executing information in reply after receiving the reading command. Finally, the processing apparatus analyzes the executing information of the memory card and presents a corresponding icon through the application program in association with the analytic result. | 12-18-2008 |
| 20080313391 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region. | 12-18-2008 |
| 20080313392 | Data controlled power supply apparatus - A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit. | 12-18-2008 |
| 20080320206 | Nonvolatile Memory Card and Configuration Conversion Adapter - A nonvolatile memory card, including interface parts for plural kinds of memory cards; interface controllers corresponding to the interface parts for corresponding memory cards; and a switch configured to select a single one of the interface controllers. | 12-25-2008 |
| 20080320207 | MULTI-LEVEL CELL (MLC) DUAL PERSONALITY EXTENDED FIBER OPTIC FLASH MEMORY DEVICE - A multi-level cell (MLC) dual-personality extended fiber optic flash drive includes a MLC dual-personality extended fiber optic Universal Serial Bus (USB) plug connector connected to a dual-personality extended fiber optic flash drive and being removably connectable to a host. The connector is adaptable to receive electrical data and optical data. A transceiver, located on the flash drive, is operative to convert received electrical data to optical data or to convert received optical data to electrical data. | 12-25-2008 |
| 20080320208 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THEREOF - A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area. In the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information. | 12-25-2008 |
| 20080320209 | High Performance and Endurance Non-volatile Memory Based Storage Systems - High performance and endurance non-volatile memory (NVM) based storage systems are disclosed. According to one aspect of the present invention, a NVM based storage system comprises at least one intelligent NVM device. Each intelligent NVM device includes a control interface logic and NVM. Logical-to-physical address conversion is performed within the control interface logic, thereby eliminating the need of address conversion in a storage system level controller. In another aspect, a volatile memory buffer together with corresponding volatile memory controller and phase-locked loop circuit is included in a NVM based storage system. The volatile memory buffer is partitioned to two parts: a command queue; and one or more page buffers. The command queue is configured to hold received data transfer commands by the storage protocol interface bridge, while the page buffers are configured to hold data to be transmitted between the host computer and the at least one NVM device. | 12-25-2008 |
| 20080320210 | Data management systems, methods and computer program products using a phase-change random access memory for selective data maintenance - A data management system includes a data processor configured to provide a file system module configured to store first data in a flash memory in block units and a filter layer module configured to receive second data from the file system module and to store the second data in a phase-change random access memory (PRAM) in sub-block units. The filter layer module may be configured to identify difference data in the second data received from the file system module by comparing the received second data and third data stored in the PRAM, and to write the identified difference data to the PRAM. The second data may include file metadata and the first data may include data other than file metadata. The sub-block units may be byte units. | 12-25-2008 |
| 20080320211 | NONVOLATILE MEMORY CONTROL DEVICE, NONVOLATILE MEMORY CONTROL METHOD, AND STORAGE DEVICE - According to an embodiment of the present invention is to increase the number of arbitrarily available physical blocks in a nonvolatile memory device. The device comprises a file system control section which analyzes a file allocation table (FAT) to identify an unused logical block, a logical/physical block address conversion table management section which uses a table of a logical/physical block address conversion table information section to obtain a first physical block corresponding to the unused logical block and releases the association between the first physical block and the unused logical block, and a physical block address information management section which registers the first physical block in a physical block address information section as an arbitrarily available second physical block. | 12-25-2008 |
| 20080320212 | CONTROL DEVICE AND CONTROL METHOD OF NONVOLATILE MEMORY AND STORAGE DEVICE - According to one embodiment, the control device according to an embodiment of the present invention, facilitates and speeds up averaging processing of the number of erases of a physical block (exchange processing of a physical block) of a nonvolatile memory. The device includes a file system control section that analyzes a file system of a nonvolatile memory and identifies a logical block of a read-only file, a logical/physical block address conversion table management section that obtains a first physical block corresponded to the logical block, and a physical block information management section that selects a second physical block that can be optionally used. Further, the device includes a physical block information modification section that moves data of the first physical block to the second physical block. | 12-25-2008 |
| 20080320213 | CONTROL DEVICE OF NONVOLATILE MEMORY AND CONTROL METHOD THEREOF, AND STORAGE DEVICE - According to one embodiment, the overall information processing time can be shortened. There are provided (1) a logical/physical block address conversion table information section that associates a logical block address of a logical address space with a physical block address of a nonvolatile memory device, (2) a physical block use state management section and a physical block erase count management section to read out erase count information from a physical block of which the logical block address and the physical block address are not associated, and a physical block that satisfies a predetermined condition set related to the erase count information is selected as a selected physical block, and (3) a logical/physical block address conversion table management section that registers a physical block address of the selected physical block in the logical/physical block address conversion table. | 12-25-2008 |
| 20080320214 | Multi-Level Controller with Smart Storage Transfer Manager for Interleaving Multiple Single-Chip Flash Memory Devices - A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device. | 12-25-2008 |
| 20090006718 | SYSTEM AND METHOD FOR PROGRAMMABLE BANK SELECTION FOR BANKED MEMORY SUBSYSTEMS - A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures. | 01-01-2009 |
| 20090006719 | SCHEDULING METHODS OF PHASED GARBAGE COLLECTION AND HOUSE KEEPING OPERATIONS IN A FLASH MEMORY SYSTEM - An embodiment of a non-volatile memory storage system comprises a memory controller, and a flash memory module. The memory controller manages the storage operations of the flash memory module. The memory controller is configured to assign a priority level to one or more types of house keeping operations that may be higher than a priority level of one or more types of commands received by a host coupled to the storage system, and to service all operations required of the flash memory module according to priority. | 01-01-2009 |
| 20090006720 | SCHEDULING PHASED GARBAGE COLLECTION AND HOUSE KEEPING OPERATIONS IN A FLASH MEMORY SYSTEM - An embodiment of a non-volatile memory storage system comprises a memory controller, and a flash memory module. The memory controller manages the storage operations of the flash memory module. The memory controller is configured to assign a priority level to one or more types of house keeping operations that may be higher than a priority level of one or more types of commands received by a host coupled to the storage system, and to service all operations required of the flash memory module according to priority. | 01-01-2009 |
| 20090006721 | METHODS OF AUTO STARTING WITH PORTABLE MASS STORAGE DEVICE - A portable flash memory storage device such as a memory card can configure a host device upon insertion. The configuration may specify applications or other sequences of operations to be executed by the host upon insertion of the card. Files on the card may be associated with an appropriate application and then automatically opened with the appropriate application. A secure configuration may override a more freely modifiable configuration in certain embodiments. | 01-01-2009 |
| 20090006722 | AUTO START CONFIGURATION WITH PORTABLE MASS STORAGE DEVICE - A portable flash memory storage device such as a memory card can configure a host device upon insertion. The configuration may specify applications or other sequences of operations to be executed by the host upon insertion of the card. Files on the card may be associated with an appropriate application and then automatically opened with the appropriate application. A secure configuration may override a more freely modifiable configuration in certain embodiments. | 01-01-2009 |
| 20090006723 | METHOD FOR COMMUNICATING WITH A NON-VOLATILE MEMORY STORAGE DEVICE - Method for a storage device is provided. The method includes interpreting a command from a host system, wherein a command parser module for a storage device interprets the command; and extracting information regarding an operation from the command, wherein the command parser module extracts the information and interfaces with the host system. | 01-01-2009 |
| 20090006724 | Method of Storing and Accessing Header Data From Memory - Methods of storing and accessing data using a header portion of a file are disclosed. In an embodiment, a method of storing content in a non-volatile memory is disclosed. The method includes reading a content file including media content and including a trailer, storing information related to the trailer together with secure data in a header portion of a file, and storing the file to a storage element of the non-volatile memory or a memory area of a host device coupled to the non-volatile memory device. | 01-01-2009 |
| 20090006725 | MEMORY DEVICE - A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer. | 01-01-2009 |
| 20090006726 | MULTIPLE ADAPTER FOR FLASH DRIVE AND ACCESS METHOD FOR SAME - A multiple adapter is used for assembling a plurality of flash drives. The multiple adapter includes a multiple expansion port, a detector, a file manager, and a controller. The multiple expansion port coupled to the flash drives. The detector is coupled to the multiple expansion port for detecting store information of the flash drives. The file manager is coupled to the multiple expansion port and the detector for receiving the store information and calculating total memory capacity and total spare capacity of the flash drives. The controller is used for controlling the detector and the file manager. A writing procedure and a reading procedure of an access method are also provided. | 01-01-2009 |
| 20090006727 | SYSTEM PROGRAMMING PROCESS FOR AT LEAST ONE NON-VOLATILE MEANS OF STORAGE OF A WIRELESS COMMUNICATION DEVICE, CORRESPONDING PROGRAMMING EQUIPMENT AND PACKET TO BE DOWNLOADED - It is proposed an in-system programming process, by programming equipment of at least one non-volatile storage memory of a communication device. The process includes the following steps: transmission, by the programming equipment to the communication device, of at least one extension file; transmission, by at least one of the extension files, called an enlightening extension file, of at least one first item of configuration information for the communication device; selection, by the programming equipment depending on the first item(s) of configuration information for the communication device of at least one data file associated to an internal application of the communication device; and transmission, by the programming equipment to the storage memory, of the selected data file(s). | 01-01-2009 |
| 20090013122 | Transaction Method for Managing the Storing of Persistent Data in a Transaction Stack - A transaction method manages the storing of persistent data to be stored in at least one memory region of a non-volatile memory device before the execution of update operations that involve portions of the persistent data. Values of the persistent data are stored in a transaction stack that includes a plurality of transaction entries before the beginning of the update operations so that the memory regions involved in such an update are restored in a consistent state if an unexpected event occurs. A push extreme instruction reads from the memory cells a remaining portion of the persistent data that is not involved in the update operation, and stores the remaining portion in a subset of the transaction entries. The push extreme instruction is executed instead of a push instruction when the restoring of the portion of persistent data is not required after the unexpected event. The restoring corresponds to the values that the persistent data had before the beginning of the update operations. | 01-08-2009 |
| 20090013123 | Storage Bridge and Storage Device and Method Applying the Storage Bridge - A storage bridge includes a flash memory register unit for temporarily storing data and for storing data of a storage unit when a host unit stores data to the storage unit, and a transmission interface control unit coupled to the flash memory register unit for controlling operations of the flash memory register unit. | 01-08-2009 |
| 20090013124 | ROM CODE PATCH METHOD - The present invention relates to a method of replacing a sequence of one or more commands from a routine in a ROM of a device using a RAM. The method allows replacing part of a routine, for example a single command, while continuing to use the rest of the commands of the routine from the ROM. In an exemplary embodiment of the invention, a single command is replaced by adding only two additional commands or four additional commands as overhead in the replacement process. | 01-08-2009 |
| 20090013125 | MEMORY CARD - A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus. | 01-08-2009 |
| 20090013126 | METHOD AND DEVICES FOR COMPRESSING DELTA LOG USING FLASH TRANSACTIONS - Each received piece of configuration data is added at a next currently free location in a volatile buffer. The contents of the volatile buffer are compressed after adding each received piece of configuration data. The compression result is stored in a non-volatile flash memory. If the compression result was shorter than a limit, it is allowed to be overwritten in the flash memory by a next compression result. If the compression result was longer than the limit, it is stored in the flash memory and the next compression result is directed to a different location in the flash memory. | 01-08-2009 |
| 20090019211 | Establishing A Redundant Array Of Inexpensive Drives - Establishing, with a USB RAID controller connected to a USB hub and with USB mass storage devices connected to the USB hub and the USB RAID controller through USB connectors, the USB hub controlled by a USB host controller, a RAID array including enumerating, by the USB host controller, the USB mass storage devices, including discovering the USB RAID controller; receiving, by the USB RAID controller from a RAID console application program, an instruction to designate USB connectors as RAIDable USB connectors, the instruction including selected USB connectors; designating, by the USB RAID controller, the selected USB connectors as RAIDable USB connectors; enumerating by the USB RAID controller the USB mass storage devices connected to the RAIDable USB connectors; configuring by the USB RAID controller a RAID array, the RAID array including the USB mass storage devices; and storing, through the USB RAID controller, computer data on the RAID array. | 01-15-2009 |
| 20090019212 | Flash disk of phone book - The present invention provides a flash disk of phone book, it comprises an autorun part, a phone book part and a free use part. | 01-15-2009 |
| 20090019213 | Method and control unit for operating a non-volatile memory, in particular for use in motor vehicles - A method for operating a nonvolatile memory, wherein the nonvolatile memory is configured to read out an erased data pattern when reading out a memory area that has not been written in, and performing the operations or tasks of setting a memory area for storing operating variable data that are to be written, providing operating variable data to be written in the nonvolatile memory, checking whether the operating variable data to be written correspond to the erased data pattern of the memory area set, writing the operating variable data in the determined memory area if the operating variable data that are to be written are different from the erased data pattern, and if the operating variable data that are to be written correspond to the erased data pattern, preventing writing the operating variable data in the determined memory area. | 01-15-2009 |
| 20090019214 | REGISTER HAVING SECURITY FUNCTION AND COMPUTER SYSTEM INCLUDING THE SAME - A register having a security function is provided. The register includes: a write security unit and a storage unit. The write security unit outputs a first control signal to control whether a write operation is permissible, in response to a write signal, an address signal, and a write permission signal. The storage unit writes and stores input data, in response to the first control signal. The write permission signal is received from an external source and indicates whether to protect the written data. | 01-15-2009 |
| 20090019215 | Method and device for performing cache reading - Method and device for reading data from a semiconductor device, where tR is a read operation time, tT is a buffer transfer time, and tH is a host transfer time, where at least two of tR, tT, and tH may be overlapped to reduce a total transfer time. | 01-15-2009 |
| 20090019216 | Disk drive device and method for saving a table for managing data in non-volatile semiconductor memory in disk drive device - Embodiments of the present invention help to suppress adverse effects on the host computer operation caused by saving a segment table. According to one embodiment, a hard disk drive (HDD) creates a segment table to associate addresses of user data in a flash memory with LBAs in a magnetic disk. The HDD updates the segment table in a DRAM and saves it to the flash memory at a specific timing. The HDD creates a journal indicating an update of the segment table and saves it to the flash memory. The segment table and the journal in the flash memory enable the latest segment table to be restored. If the HDD receives a predetermined command from a host computer, it saves the segment table in the DRAM into the flash memory. | 01-15-2009 |
| 20090019217 | Non-Volatile Memory And Method With Memory Planes Alignment - A non-volatile memory is constituted from a set of memory planes, each having its own set of read/write circuits so that the memory planes can operate in parallel. The memory is further organized into erasable blocks, each for storing a logical group of logical units of data. In updating a logical unit, all versions of a logical unit are maintained in the same plane as the original. Preferably, all versions of a logical unit are aligned within a plane so that they are all serviced by the same set of sensing circuits. In a subsequent garbage collection operation, the latest version of the logical unit need not be retrieved from a different plane or a different set of sensing circuits, otherwise resulting in reduced performance. In one embodiment, any gaps left after alignment are padded by copying latest versions of logical units in sequential order thereto. | 01-15-2009 |
| 20090019218 | Non-Volatile Memory And Method With Non-Sequential Update Block Management - In a nonvolatile memory with block management system that supports update blocks with non-sequential logical units, an index of the logical units in a non-sequential update block is buffered in RAM and stored periodically into the nonvolatile memory. In one embodiment, the index is stored in a block dedicated for storing indices. In another embodiment, the index is stored in the update block itself. In yet another embodiment, the index is stored in the header of each logical unit. In another aspect, the logical units written after the last index update but before the next have their indexing information stored in the header of each logical unit. In this way, after a power outage, the location of recently written logical units can be determined without having to perform a scanning during initialization. In yet another aspect, a block is managed as partially sequential and partially non-sequential, directed to more than one logical subgroup. | 01-15-2009 |
| 20090024786 | External storage device - An external storage device includes a hard-drive, a flash memory, and a memory arrangement unit. The memory arrangement determines if the tag of the data accessed by a computer stored in the tag list of the memory arrangement unit and controls the hard-drive and the flash memory according to the result of the determination. | 01-22-2009 |
| 20090024787 | Data writing method and apparatus - Provided are a data writing method and apparatus. In the data writing method, data that is to be written to a first storage medium and the address of the first storage medium are received, data is read from the address of the first storage medium, the received data is compared with the read data, and then the received data is stored in either the first storage medium or a second storage medium, depending on the comparison result. Accordingly, it is possible to reduce the time required for data writing and to increase the lifetime of a storage medium. | 01-22-2009 |
| 20090024788 | PORTABLE ELECTRONIC DEVICE AND DATA CONTROL METHOD - A portable electronic device is provided with a storage section which stores various pieces of information and a transmitter/receiver section which transmits and receives data to and from external equipment. It is determined whether or not data paired with write data contained in a write command is stored by the storage section when the write command is received by the transmitter/receiver section, the write data is written to the storage section if it is concluded that the data paired with the write data contained in the write command is stored by the storage section, and the transmitter/receiver section is caused to transmit a result of determination on abnormality to the external equipment if it is concluded that the data paired with the write data contained in the write command is not stored by the storage section. | 01-22-2009 |
| 20090031073 | MULTI-INTERFACE AND MULTI-BUS STRUCTURED SOLID-STATE STORAGE SUBSYSTEM - A solid-state storage subsystem, such as a non-volatile memory card or drive, includes multiple interfaces and a memory area storing information used by a data arbiter to prioritize data commands received through the interfaces. As one example, the information may store a priority ranking of multiple host systems that are connected to the solid-state storage subsystem, such that the data arbiter may process concurrently received data transfer commands serially according to their priority ranking. A host software component may be configured to store and modify the priority control information in solid-state storage subsystem's memory area. | 01-29-2009 |
| 20090031074 | Multi-level Cell Flash Memory and Method of Programming the Same - Provided is a flash memory having a multi-level cell (MLC) and a method of programming the same. The method includes identifying a set of first patterns from input data, determining whether there is a set of second patterns stored within the flash memory that is of a number substantially similar to the number of the first patterns, and programming the input data as a most significant bit (MSB) in a location of the flash memory where the identified set of second patterns is stored when it is determined that there is a set of second patterns stored within the flash memory that is of a number substantially similar to the number of first patterns. | 01-29-2009 |
| 20090031075 | Non-volatile memory device and a method of programming the same - Provided are a non-volatile memory device and a method of programming the same. The method includes: performing a program operation; performing a program verify read operation; and performing a pass/fail determine operation simultaneously with one of a verify recovery operation and a bit line setup operation, after the performing of the program verify read operation. | 01-29-2009 |
| 20090031076 | Method for Managing Flash Memory - A method for managing a flash memory, a method for leveling the wear of blocks in a flash memory, and a method for managing a file system for a flash memory are provided. The method for managing a flash memory includes: if changing of data of a data block recorded in a data area is requested, recording the data block having changed data in an alternative area and recording mapping information of the data block recorded in the alternative area in a mapping area; and if changing of data of the data block recorded in the alternative area is requested, recording a data block having changed data in the data area and deleting the mapping information recorded in the alternative area from the mapping area. | 01-29-2009 |
| 20090037643 | Semiconductor memory device including control means and memory system - A semiconductor memory device includes a first nonvolatile memory which has a first external interface and is capable of recording 1-bit data in one memory cell, a second nonvolatile memory which has a test terminal interface and is capable of recording a plurality of data in one memory cell, and a control unit which has a second external interface and is configured to control a physical state of an inside of the second nonvolatile memory. | 02-05-2009 |
| 20090037644 | System and Method of Storing Reliability Data - Systems and methods of storing error correction data are provided. A method may include storing data at a first memory having a first non-volatile memory type. The method may also include determining error correction data related to the stored data. The method may further include storing the error correction data at a second memory having a second non-volatile memory type. The first non-volatile memory may have a slower random access capability than the second non-volatile memory. | 02-05-2009 |
| 20090037645 | NON-VOLATILE MEMORY DEVICE AND DATA ACCESS CIRCUIT AND DATA ACCESS METHOD - A non-volatile memory device, a data access circuit and a data access method are provided. The non-volatile memory device includes a main controller, a plurality of sub-controllers and a plurality of memory blocks. The sub-controllers are coupled to the main controller and are used to execute the tasks assigned by the main controller. The memory blocks are respectively coupled to the corresponding sub-controllers. The main controller is used to divide a received main data into a plurality of sub-data, and the sub-data are respectively saved in the memory blocks through corresponding sub-controllers. Therefore, the data access speed of the non-volatile memory device is substantially speeded-up. | 02-05-2009 |
| 20090037646 | Method of using a flash memory for a circular buffer - A method of using a FLASH memory for a circular buffer, and the FLASH memory for same, the method including one or more of the following steps in various exemplary embodiments: providing a circular buffer having a plurality of sectors; designating a byte of each of the plurality of sectors of the circular buffer as a binary state indicator; saving data sequentially in the circular buffer; and cycling through a plurality of sectors of the binary state indicators, such as empty or erase, last, middle and first, as the data is sequentially saved in the circular buffer. | 02-05-2009 |
| 20090037647 | SEMICONDUCTOR MEMORY CARD, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory card which can be attached to a host apparatus and can be removed from the host apparatus includes a plurality of data transfer terminals, and an internal circuit transmitting a first signal to at least one first data transfer terminal comprising at least one of the data transfer terminals and transmitting a second signal to at least one second data transfer terminal comprising at least one of the data transfer terminals different from the first data transfer terminals. The second signal is generated by executing a logical operation on the first signal. | 02-05-2009 |
| 20090037648 | INPUT/OUTPUT CONTROL METHOD AND APPARATUS OPTIMIZED FOR FLASH MEMORY - An input/output control method and apparatus optimized for a flash memory, which can improve the performance of the flash memory. The input/output control method optimized for a flash memory includes determining whether a random write operation of data occurs in a flash memory, and successively writing randomly input data in a predetermined surplus region of the flash memory if it is judged that the random write operation occurs. | 02-05-2009 |
| 20090037649 | Methods and Systems for Running Multiple Operating Systems in a Single Mobile Device - Methods and systems for running multiple operating systems in a single embedded or mobile device (include PDA, cellular phone and other devices) are disclosed. The invention allows a mobile device that normally can only run a single operating system to run another operating system while preserving the state and data of the original operating system. Guest OS is packaged into special format recognizable by the host OS that still can be executed in place by the system. The Methods include: Change the memory protection bits for the original OS; Fake a reduced physical memory space for guest OS; Use special memory device driver to claim memories of host OS; Backup whole image of the current OS and data to external memory card. | 02-05-2009 |
| 20090037650 | Function updatable device and an options card therefor - A device such as for example a electronic medical device has a memory that has prestored therein a number of programs or routines for performing various functions. Some of those functions are optional functions that were not enabled when the equipment was put into service. If the user of the equipment desires thereafter to activate any one of those optional functions, an options card that has a number of memory blocks each specifically configured to enable one of the prestored optional functions is sent to the user. The user can then insert the options card into a receptacle integrated into the device and, upon power up of the device, elect a menu for enabling the desired optional function(s) prestored in the device. The options card may be configured to have a count number that indicates the number of devices the card may be used for enabling a particular optional function. The options card may further be configured to include data that may be used to enable or disable multiple optional functions prestored in the device. When returned to the manufacturer, given that the serial numbers of the machines to which the options card was inserted are recorded therein, the manufacturer can easily keep tab of the status of those machines in the field that had had optional functions enabled/disabled. | 02-05-2009 |
| 20090037651 | Non-Volatile Memory and Method with Phased Program Failure Handling - In a memory with block management system, program failure in a block during a time-critical memory operation is handled by continuing the programming operation in a breakout block. Later, at a less critical time, the data recorded in the failed block prior to the interruption is transferred to another block, which could also be the breakout block. The failed block can then be discarded. In this way, when a defective block is encountered during programming, it can be handled without loss of data and without exceeding a specified time limit by having to transfer the stored data in the defective block on the spot. This error handling is especially critical for a garbage collection operation so that the entire operation need not be repeated on a fresh block during a critical time. Subsequently, at an opportune time, the data from the defective block can be salvaged by relocation to another block. | 02-05-2009 |
| 20090037652 | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules - A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands. | 02-05-2009 |
| 20090043947 | MANAGING PROCESSING DELAYS IN AN ISOCHRONOUS SYSTEM - Command cycles incorporate mechanisms to inform a host processor in advance of a need to service the memory so that the host can respond when it suits the host, but in time for the service to be performed before a catastrophic failure. The regular host cycle need not be interrupted for such notification. | 02-12-2009 |
| 20090043948 | Method and System for Storing Logical Data Blocks Into Flash-Blocks in Multiple Non-Volatile Memories Which Are Connected to At Least One Common Data I/0 Bus - For recording or replaying in real-time digital HDTV signals very fast memories are required. For storage of streaming HD video data NAND flash memory based systems can be used. However, NAND flash memories have a slow write access, and they have unmasked production defects. Write or read operations can be carried out on complete physical data blocks only, and defect data blocks must not be used by the file system. Logical file system blocks are used which are larger than the physical data blocks. According to the invention the error reporting mechanism of the NAND flash memories is exploited. The video data is not only written to the non-volatile flash memories, but is also written to corresponding buffer slots (LFSB) of a volatile SRAM or DRAM memory operating in parallel. The video data are kept in the vola- tile memory until the flash memory holding the respective data has reported that its program or write operation succeeded. Once this has taken place, the data within the volatile memory can be overwritten in order to save memory capacity. If the flash memory has reported an error, the respective block (FSBD) of data is marked bad and will not be overwritten until the end of the entire recorded take has been reached. At this time, the marked video data from the volatile memory are copied to spare flash-blocks within the flash memories. | 02-12-2009 |
| 20090043949 | BLOCK DECODER OF A FLASH MEMORY DEVICE - A block decoder increases the integration level of a flash memory device by reducing the number of control signals. Address signals are substituted with existing high voltage switch signals. The block decoder of a flash memory device includes a primary decoding unit and a secondary decoding unit. The primary decoding unit outputs a decoding signal in response to first and second address coding signals of a high voltage and first to third control signals. The secondary decoding unit outputs a control signal to control the potential of a block word line in response to the decoding signal and first and second pre-decoded signals. | 02-12-2009 |
| 20090043950 | SEMICONDUCTOR MEMORY STORAGE APPARATUS AND CONTENT DATA MANAGEMENT METHOD - A semiconductor memory storage apparatus includes a packetization unit receiving content data includes a plurality of variable-length frames, and adding management data showing frame data inherent information to frame data of each variable-length frame, and further, packetizing the content data storing the frame data and the management data in each fixed-length packet for every variable-length frame, a buffer temporarily storing the content data at a fixed-length packet unit in write/read operation of the content data packetized at the fixed-length packet unit, a storage unit using a non-volatile memory as an information storage medium, and storing the content data supplied from the buffer, and a controller writing/reading content data packetized at the fixed-length packet unit with respect to the storage unit at a fixed-length packet unit. | 02-12-2009 |
| 20090043951 | PROGRAMMING SCHEMES FOR MULTI-LEVEL ANALOG MEMORY CELLS - A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits. | 02-12-2009 |
| 20090043952 | MOVING SECTORS WITHIN A BLOCK OF INFORMATION IN A FLASH MEMORY MASS STORAGE ARCHITECTURE - A device is disclosed for storing mapping information for mapping a logical block address identifying a block being accessed by a host to a physical block address, identifying a free area of nonvolatile memory, the block being selectively erasable and having one or more sectors that may be individually moved. The mapping information including a virtual physical block address for identifying an “original” location, within the nonvolatile memory, wherein a block is stored and a moved virtual physical block address for identifying a “moved” location, within the nonvolatile memory, wherein one or more sectors of the stored block are moved. The mapping information further including status information for use of the “original” physical block address and the “moved” physical block address and for providing information regarding “moved” sectors within the block being accessed. | 02-12-2009 |
| 20090049231 | EFFICIENT AND SYSTEMATIC MEASUREMENT FLOW ON DRAIN VOLTAGE FOR DIFFERENT TRIMMING IN FLASH SILICON CHARACTERIZATION - Systems and methods that facilitate characterization of a flash memory device are presented. A characterization component can be associated with a regulator component included in a memory device to facilitate setting and measuring respective drain voltage levels for programming, erase, and soft programming operations at address bit combinations available for the respective operations. The characterization component can utilize external address bits that can be fixed when performing the operations to minimize disruption to the drain voltage measurement flow. The characterization component can detect when a particular operation has already been performed based in part on an applicable portion of the address bit combination associated with such operation, and can bypass such operation at that address bit combination to proceed to the next operation that has yet to be performed thereby efficiently setting and measuring drain voltage levels for various operations and trim settings to characterize the memory device. | 02-19-2009 |
| 20090049232 | EXECUTE-IN-PLACE IMPLEMENTATION FOR A NAND DEVICE - An Execute-In-Place (XIP) implementation in a NAND controller of the kind that controls a NAND flash memory device. A page load command is provided to a predefined block and page address in a NAND device and identifies whether the boot read request received from the processor is a continuation of a previous boot read request. A read enable pin in the NAND device is toggled if the boot read request is a continuation of the previous boot read request. A random data output command sequence is sent to the NAND device and the read enable pin is toggled if the boot read request is not a continuation of the previous boot read address. | 02-19-2009 |
| 20090049233 | Flash Memory, and Method for Operating a Flash Memory - A method for operating a flash memory is provided. The flash memory comprises a controller, a cache, and a plurality of blocks. By using a cache to preload data from the host, the buffer of the controller can be smaller than the capacity of a single block or omitted entirely. Smooth data transmission is still maintained. | 02-19-2009 |
| 20090049234 | SOLID STATE MEMORY (SSM), COMPUTER SYSTEM INCLUDING AN SSM, AND METHOD OF OPERATING AN SSM - In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer. | 02-19-2009 |
| 20090055574 | NAND Flash Memory Device And Related Method Thereof - The NAND flash memory device contains a NAND flash memory, a mirror data area, and a controller. The mirror data area has a size at least to hold a page of data and is usually formed by random access memory. The controller saves a data to be written into the NAND flash memory that occupies a partial number of the sectors of a first page of the NAND flash memory into the sectors of a second page of the mirror data area. When a new data is to be written into the remaining sectors of the first page of the NAND flash memory, the new data is stored instead into the second page's remaining sectors of the mirror data area. When the second page of the mirror data area is full, the entire second page is written into the first page of the NAND flash memory. | 02-26-2009 |
| 20090055575 | Flash memory with small data programming capability - The present invention provides a method featuring receiving a request to access a memory array having one or more memory erase units with a data area of flash array and with a specific amount of memory which offers small data programming capability; and if the memory access request includes programming small data, then providing access to the specific amount of memory, or if the memory access request does not include programming small data, then providing access to the data area of flash array; as well as an apparatus in the form of a flash memory device featuring a memory array having one or more memory erase units with a data area of flash array and with a specific amount of memory which offers small data programming capability, and a memory controller, responsive to a request, for providing access to the specific amount of memory if the request includes programming small data, or for providing access to the data area of flash array if the request does not include programming small data. | 02-26-2009 |
| 20090055576 | MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND DATA WRITING METHOD - A nonvolatile storage device is provided with a nonvolatile main storage memory ( | 02-26-2009 |
| 20090055577 | PROGRAMMING METHODS FOR NONVOLATILE MEMORY - Example embodiments are directed to methods, memory devices, and systems for programming a nonvolatile memory device having a charge storage layer including performing at least one unit programming loop, each unit programming loop including, applying a programming pulse to at least two pages, applying a time delay to the at least two pages, and applying a verifying pulse to the at least two pages. | 02-26-2009 |
| 20090055578 | APPARATUS USING FLASH MEMORY AS STORAGE AND METHOD OF OPERATING THE SAME - An apparatus usable with a flash memory as storage and a method of operating the same are provided, which can provide an optimized architecture to a flash memory through combination of a flash transition layer (FTL) with a database. The apparatus includes a flash memory, a device driver to manage a mapping table between logical addresses and physical addresses in accordance with a data operation in the flash memory, and a control unit to perform data recovery of the flash memory by requesting the mapping table through an interface provided by the device driver. | 02-26-2009 |
| 20090055579 | Semiconductor memory device for simultaneously programming plurality of banks - Provided is a semiconductor memory device for simultaneously programming a plurality of banks. The semiconductor memory device includes: a memory cell array comprising a plurality of banks; a plurality of data buffers storing a plurality of pieces of program data to be programmed in the corresponding banks; and a plurality of scan latches configured to scan the plurality of program data transmitted from the corresponding data buffers, and configured to generate 1 | 02-26-2009 |
| 20090063756 | USING FLASH STORAGE DEVICE TO PREVENT UNAUTHORIZED USE OF SOFTWARE - A flash storage device and a method for using the flash storage device to prevent unauthorized use of a software application are provided. An identifier may be encoded within specific sectors of the flash storage device. One bits of the identifier may be encoded as unusable ones of the specific sectors and zero bits of the identifier may be encoded as usable one of the specific sectors. Alternatively, the zero bits of the identifier may be encoded as the unusable ones of the specific sectors and the one bits of the identifier may be encoded as the usable ones of the specific sectors. The software application may be permitted to execute on a processing device connected to the flash storage device only when the identifier is encoded within the flash storage device. | 03-05-2009 |
| 20090063757 | Memory emulation in an electronic organizer - An electronic organizer using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, FLASH memory, and a non-volatile memory card, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the electronic organizer. At least one of the memory arrays may be in the form of a removable memory card. | 03-05-2009 |
| 20090063758 | PROGRAM AND READ METHOD AND PROGRAM APPARATUS OF NAND FLASH MEMORY - A program method, a read method, and a program apparatus of a NAND flash memory are disclosed. The program method and apparatus of the NAND flash memory provided by the present invention can reduce the programming time of each page and increase the programming speed of the entire NAND flash memory when the data to be programmed in a single operation is less than the storage capacity of all the data storage areas in the page. In addition, the read method of the NAND flash memory provided by the present invention can reduce the number of reading each page and accordingly the number of reading the entire NAND flash memory when the data to be read in a single operation is less than the storage capacity of all the data storage areas in the page. | 03-05-2009 |
| 20090070518 | Adaptive Block List Management - In a nonvolatile memory array, selected blocks are maintained as open blocks that are available to store additional data without being erased first. Nonsequential open blocks are selected from two lists, one list based on recency of the last write operation, and the other list based on frequency of writes to the block. Sequential open blocks are divided into blocks expected to remain sequential and blocks that are not expected to remain sequential. | 03-12-2009 |
| 20090070519 | SYSTEM AND METHOD FOR SECURE DOCUMENT PROCESSING USING REMOVABLE DATA STORAGE - The subject application is directed to a system and method for secure document processing. A removable storage, such as a flash drive, magnetic storage, IC card, is installed in document processing device. A selected document processing operation, such as copying, scanning, and the like, is then performed. Data files resultant from the selected document processing operations are directed to the removable storage for being stored temporary, instead of being sent to the storage inherent to the document processing device. Data files temporary stored in the removable storage are then deleted. | 03-12-2009 |
| 20090070520 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR STORAGE DEVICE - In a semiconductor storage device, a memory controller divides each of blocks in each of chips into a first page set composed of pages and a second page set composed of pages, divides a logical address space into groups, and divides each group into lines. Block units are created each of which is obtained by assembling a predetermined number of blocks from the blocks in each chip. A predetermined number of block units from the block units are managed as standard block units, and the other block units are managed as spare block units. Each standard block unit is made to correspond to one group. The corresponding group data is stored in the pages in the first page set in each block constituting the standard block unit, and unwritten pages for recording update data for the group data are provided to be included in the second page set. | 03-12-2009 |
| 20090070521 | WRITE ABORT AND ERASE ABORT HANDLING - A portion of a nonvolatile memory array that is likely to contain, partially programmed data may be identified from a high sensitivity read, by applying stricter than usual ECC requirements, or using pointers to programmed sectors. The last programmed data may be treated as likely to be partially programmed data. Data in the identified portion may be copied to another location, or left where it is with an indicator to prohibit further programming to the same cells. To avoid compromising previously stored data during subsequent programming, previously stored data may be backed up. Backing up may be done selectively, for example, only for nonsequential data, or only when the previously stored data contains an earlier version of data being programmed. If a backup copy already exists, another backup copy is not created. Sequential commands are treated as a single command if received within a predetermined time period. | 03-12-2009 |
| 20090070522 | METHOD AND APPARATUS FOR CASCADE MEMORY - A system and method of operating a cascade of a plurality of memory devices connected in series is disclosed. In one aspect, there is a memory controller operatively connected to the memory cell and a cascade circuit configured to enable a subsequent memory device in a cascade of memory devices. | 03-12-2009 |
| 20090070523 | Flash memory device storing data with multi-bit and single-bit forms and programming method thereof - A flash memory device may include a memory cell array including a plurality of memory blocks and a partition information block, the partition information block storing partition information that indicates a boundary between multi-bit memory blocks and single-bit memory blocks among the memory blocks. The memory device may include a control logic configured to determining whether a memory block that a block address from the outside indicates has a multi-bit form or a single-bit form based on the partition information and to control program and read operations in a multi-bit form or a single-bit form based on a determination result. The control logic automatically programs data in the partition information block according to whether a fuse connected to the control logic fuse is cut or not, the data being used for preventing the partition information block from being programmed or erased. | 03-12-2009 |
| 20090077301 | PROGRAMMABLE SEQUENCE GENERATOR FOR A FLASH MEMORY CONTROLLER - A programmable sequence generator for controlling a flash memory device. The programmable sequence generator includes a plurality of programmable sequence registers including control phase sequence (CPS) registers and data phase sequence (DPS) registers programmed with phase sequence values corresponding to an operation command sequence of the flash memory device; and logic circuitry in a programmable command sequencer for controlling a set of states of the programmable command sequencer using the plurality of programmable sequence registers. | 03-19-2009 |
| 20090077302 | Storage apparatus and control method thereof - This storage apparatus has a disk-shaped storage device for storing data sent from a host system, and includes a nonvolatile memory device for storing the data, a controller for controlling the reading or writing of the data sent from the host system from or into the disk-shaped storage device, and a device controller for controlling the nonvolatile memory device and the disk-shaped storage device. The device controller replicates data stored in the disk-shaped storage device to the nonvolatile memory device according to the usage of the disk-shaped storage device. The controller reads data from the nonvolatile memory device when the controller receives a data read request from the host system and corresponding data is stored in the nonvolatile memory device. | 03-19-2009 |
| 20090077303 | System for transferring information and method thereof - A system for transferring information and method thereof, the system includes a management processor, a storage processor and a peripheral. Moreover, the management processor connects to the storage processor by I2C bus and GPIO bus, wherein the I2C bus is used for transmitting information from the management processor to the storage processor, and the GPIO bus is used for transmitting acknowledged instruction from the storage processor to the management processor. Moreover, the management processor transmits the information to the storage processor continuously until the management processor receives an acknowledged instruction from the storage processor. Furthermore, the storage processor waits to receive the information from the management processor, and replies the acknowledged instruction to the management processor after the storage processor receives the information correctly. | 03-19-2009 |
| 20090077304 | MEMORY SYSTEM HAVING NONVOLATILE AND BUFFER MEMORIES, AND READING METHOD THEREOF - Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request is allocated to the buffer memory; determining whether a size of requested data is larger than a reference unless the input address is allocated to the buffer memory; and conducting a prefetch reading operation from the nonvolatile memory if the requested data size is larger than the reference. | 03-19-2009 |
| 20090077305 | Flexible Sequencer Design Architecture for Solid State Memory Controller - A method and apparatus for controlling access to solid state memory devices which may allow maximum parallelism on accessing solid state memory devices with minimal interventions from firmware. To reduce the waste of host time, multiple flash memory devices may be connected to each channel. A job/descriptor architecture may be used to increase parallelism by allowing each memory device to operate separately. A job may be used to represent a read, write or erase operation. When firmware wants to assign a job to a device, it may issue a descriptor, which may contain information about the target channel, the target device, the type of operation, etc. The firmware may provide descriptors without waiting for a response from a memory device, and several jobs may be issued continuously to form a job queue. After the firmware finishes programming descriptors, a sequencer may handle the remaining work so that the firmware may concentrate on other tasks. | 03-19-2009 |
| 20090077306 | OPTIMIZING MEMORY OPERATIONS IN AN ELECTRONIC STORAGE DEVICE - To optimize memory operations, a mapping table may be used that includes: logical fields representing a plurality of LBA sets, including first and second logical fields for representing respectively first and second LBA sets, the first and second LBA sets each representing a consecutive LBA set; PBA fields representing PBAs, including a first PBA disposed for representing a first access parameter set and a second PBA disposed for representing a second access parameter set, each PBA associated with a physical memory location in a memory store, and these logical fields and PBA fields disposed to associate the first and second LBA sets with the first and second PBAs; and, upon receiving an I/O transaction request associated with the first and second LBA sets, the mapping table causes optimized memory operations to be performed on memory locations respectively associated with the first and second PBAs. | 03-19-2009 |
| 20090083474 | FILE ALLOCATION TABLE MANAGEMENT - In one embodiment, a storage controller comprises a first port that provides an interface to a host computer, a second port that provides an interface a storage device, a processor, and a flash memory module communicatively connected to the processor and comprising logic instructions which, when executed by the processor, configure the processor to receive, in a file allocation table manager, a signal indicative of a request to perform a first update of a file allocation table stored in a memory module, locate, in the memory module, a first memory sector corresponding to a first entry in the file allocation table having an active status, write, in the memory module, a second file allocation table entry, set a status flag associated with the second entry to an active state, and set a status flag associated with the first entry to a standby state. | 03-26-2009 |
| 20090083475 | APPARATUS AND METHOD FOR UPDATING FIRMWARE STORED IN A MEMORY - The invention provides a method for updating firmware stored in a memory. In one embodiment, the memory is divided into a plurality of blocks, and the firmware to be updated with a new image version. First, a first data block is obtained from the new image version, and a second data block is obtained from a target block selected from the memory. Whether the first data block is different from the second data block is then checked. The first data block is then written into the target block when the first data block is different from the second data block. Finally, the aforementioned steps are repeated until all of the blocks are processed. | 03-26-2009 |
| 20090083476 | SOLID STATE DISK STORAGE SYSTEM WITH PARALLEL ACCESSSING ARCHITECTURE AND SOLID STATE DISCK CONTROLLER - A solid state disk (SSD) storage system with a parallel accessing architecture, including a SSD controller and a plurality of transmission interfaces of a predetermined bit number and bandwidth, and a solid state disk controller thereof are provided. The SD controller forms channels for transmitting control signals and data with one or more flash memories through each of the transmission interfaces. That is, independent transmission channels are constituted between the SSD controller, the transmission interfaces with multiple bits, and the flash memories. In one embodiment, the transmission interfaces are compatible with MMC 4.0 protocol or higher. Moreover, a host controls and accesses the flash memories through a SATA bus interface and the SSD controller, and uses a direct memory access (DMA) engine with a bidirectional connection port in the SSD controller to transmit data. | 03-26-2009 |
| 20090083477 | METHOD AND APPARATUS FOR FORMATTING PORTABLE STORAGE DEVICE - A method and apparatus for formatting a portable storage device, which are capable of performing formatting optimized for a non-volatile memory of the portable storage device. The method includes: detecting whether file system information is initialized when formatting of the non-volatile memory is started; if the initialization of the non-volatile memory is detected, detecting a cluster size and cluster start position of a storage space of the portable storage device; and if the detected cluster size and the cluster start position information do not match a size and a staring position of a minimum recording unit of the storage space, performing a re-formatting operation of the portable storage device. | 03-26-2009 |
| 20090083478 | INTEGRATED MEMORY MANAGEMENT AND MEMORY MANAGEMENT METHOD - An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory. | 03-26-2009 |
| 20090089481 | Leveraging Portable System Power to Enhance Memory Management and Enable Application Level Features - A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window. Additionally, in a data write operations, where the memory device receives data from a host, stores the data in volatile memory, and then writes the data into the non-volatile memory, the memory device sends the host an acknowledgment of the data having been written into the non-volatile memory after it has been store in the volatile memory, but before the write into the non-volatile memory is complete. | 04-02-2009 |
| 20090089482 | DYNAMIC METABLOCKS - A nonvolatile block erasable memory array links erase blocks together for programming with high parallelism as a metablock. Erase blocks are operated in banks, with each bank having a dedicated bus and controller. Sub-metablocks of different metablocks, in different banks, are accessed in parallel allowing different metablocks to be updated at the same time. | 04-02-2009 |
| 20090089483 | Storage device and deduplication method - This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area. | 04-02-2009 |
| 20090089484 | DATA PROTECTION METHOD FOR POWER FAILURE AND CONTROLLER USING THE SAME - A data protection method suitable for a plurality of physical blocks mapped to a logical block in a non-volatile memory is provided. The data protection method includes recording data update information in each of the physical blocks for identifying an update relationship of the physical blocks and re-establishing the update relationship of the physical blocks according to the data update information. The data update information is composed of a plurality of words having a circular relationship, and the number of these words is greater than the number of the physical blocks. The data update information is sequentially recorded in each of the physical blocks according to the update relationship and the circular relationship. | 04-02-2009 |
| 20090089485 | WEAR LEVELING METHOD AND CONTROLLER USING THE SAME - A wear leveling method for a non-volatile memory is provided. The non-volatile memory is substantially divided into a plurality of blocks, and these blocks are grouped into at least a data area, a spare area, a substitute area, and a temporary area. The wear leveling method includes selecting blocks from the spare area according to different purposes and executing a wear leveling procedure. | 04-02-2009 |
| 20090089486 | PORTABLE DATA STORAGE DEVICE INCORPORATING MULTIPLE FLASH MEMORY UNITS - A portable data storage device is disclosed which includes an Interface for enabling the portable data storage device to be used for data transfer with a host Computer, and an Interface controller for controlling the interface. There is also a master control unit for controlling the writing of data to and reading data from a non-volatile memory. The non-volatile memory includes at least one single layer cell flash memory and at least one multiple layer cell flash memory. Upon receiving a write instruction, the master control unit determines which of the memories data contained in the instruction should be written to, and writes the data as appropriate similarly, upon receiving a read instruction, the master control unit reads the data from the appropriate one of the memories and transmits the data out of the device. | 04-02-2009 |
| 20090089487 | MULTIPORT SEMICONDUCTOR MEMORY DEVICE HAVING PROTOCOL-DEFINED AREA AND METHOD OF ACCESSING THE SAME - A multiprocessor system includes a first processor for performing a first task, a second processor for performing a second task, and a multiport semiconductor memory device having a protocol-defined area for defining a specification related to data communication between the first processor and the second processor. The protocol-defined area is located in at least one shared memory area accessible in common by the first processor and the second processor through a first port and a second port, respectively, and is assigned as a predetermined memory capacity to a portion of a memory cell array. | 04-02-2009 |
| 20090089488 | MEMORY SYSTEM, MEMORY READ METHOD AND PROGRAM - According to one embodiment, there is disclosed a memory system comprising a flash memory unit which suspends a write operation to execute a read operation when receiving a suspend command during a write operation, a CPU, an OS which includes a device driver, a TLB which has a page table for conversion from a virtual address to a physical address, and an application program which makes a TLB setting request with respect to the device driver when receiving a read command under the control of the CPU and the OS, acquires address information read from the page table of the TLB by the device driver in response to the setting request, and executes read directly with respect to the flash memory unit using the acquired address information without using the device driver. | 04-02-2009 |
| 20090089489 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM WITH MEMORY CONTROLLER, AND CONTROL METHOD OF FLASH MEMORY - The memory controller updates a count number based on a new assignment of a logical block to a physical block, and writes count information in the physical block to which the logical block is newly assigned. The count information is defined by the count number. The memory controller decides, based on the count number and the count information stored in each physical block, whether or not to transfer stored data in a physical block to another physical block. | 04-02-2009 |
| 20090089490 | MEMORY SYSTEM - A memory system including a nonvolatile memory, a first controller connected to a host equipment, the first controller controlling the entire memory system, a second controller connected to the first controller and also connected to the nonvolatile memory, the second controller controlling an access process to said nonvolatile memory, the second controller receives a command via the first controller and carries out the access process to the nonvolatile memory according to the command, the command being input from the host equipment. | 04-02-2009 |
| 20090089491 | SEMICONDUCTOR MEMORY DEVICE AND DATA MANAGEMENT METHOD USING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a memory part which has a plurality of memory blocks having a memory cell capable of storing a plurality of different kinds of data which require a memory area having different characteristics, and a memory controller which has a function of treating each of the memory blocks as a deletion unit in order to manage the memory part and converting a logic address of the memory part to a physical address identifying the memory block, and which replaces the memory block with a preregistered free block in rewriting the memory block. The memory controller manages the different kinds of data to be stored in the memory part so as to store the same kind of data as before, even after each of the memories and free blocks in the memory part are rewritten. | 04-02-2009 |
| 20090089492 | FLASH MEMORY CONTROLLER - Methods, systems and computer program products for implementing a polling process among one or more flash memory devices are described. In some implementations, the polling process may include sending a read status command to a flash memory device to detect the ready or busy state of the flash memory device. A status register may be included in the flash memory device for storing a status signal indicating an execution state of a write (or erase) operation. A solid state drive system may perform the polling process by reading the status register of the flash memory device. | 04-02-2009 |
| 20090094406 | SCALABLE MASS DATA STORAGE DEVICE - A scalable data storage device which includes non-volatile memory uses a networked bus system which can be employed on a single memory storage chip level or in a multi-chip package (MCP). The scalable data storage device uses data routing modules which are adapted to store incoming data and send outgoing data thereby providing decoupling of the networked buses. This arrangement enables significantly higher data transfer rates, surpassing DRAM SSDs at a fraction of the size and cost, provides increased volumetric density (1 TB in less than 1 cubic inch), and permits concurrency of operations. The scalable data storage device can be engineered to have a rewrite capability of over 500 times that of Flash RAM and can scale down to 8 bits and up to exabytes, yottabytes and beyond. The scalable data storage device may be used in a wide range of applications from large data centers to small consumer electronic products. | 04-09-2009 |
| 20090094407 | Non-volatile memory device having assignable network identification - Memory devices and methods disclosed such as memory devices that include a network identification that uniquely identifies the memory device on a network. The memory device can then receive memory commands that include the network identification. The memory device can also generate memory commands, including the network identification, for broadcast over the network. | 04-09-2009 |
| 20090094408 | MEMORY WRITING DEVICE - After power-on, the start-up of a CPU | 04-09-2009 |
| 20090094409 | WEAR LEVELING METHOD AND CONTROLLER USING THE SAME - A wear leveling method for non-volatile memory is provided, by which the non-volatile memory is substantially divided into a plurality of blocks and the blocks are grouped into a data area and a spare area. The method includes selecting a block based on an erased sequence when getting the block from the spare area. The method also includes performing a wear leveling procedure. | 04-09-2009 |
| 20090094410 | METHOD FOR BLOCK WRITING IN A MEMORY - A method is provided for block writing in an electrically programmable non-volatile memory, in which a block to be written in the memory includes at least one word. The method includes determining a word write time by dividing a fixed block write time by the number of words in the block to be written, and controlling the memory to successively write each word in the memory during the write time. | 04-09-2009 |
| 20090094411 | NAND FLASH CONTROLLER AND DATA EXCHANGE METHOD BETWEEN NAND FLASH MEMORY AND NAND FLASH CONTROLLER - The invention discloses a NAND flash controller, including a command and address data transmission channel adapted to connect the bus timing interface with the channel selector and transmit command and address data, a data buffer region adapted to receive message data from the bus timing interface through system bus, a control register adapted to receive an operation parameter configured through system bus via the bus timing interface, a logic controller adapted to write the data information into or read the data information from the data buffer region according to the operation parameter, a channel selector adapted to connect the DMA data transmission channel or the command and address data transmission channel according to the operation parameter for transmitting data. The invention also discloses a date exchange method between NAND flash controller and NAND flash memory. The invention improves the data transmission efficiency and is compatible with various NAND flash memories. | 04-09-2009 |
| 20090100214 | Management Platform For Extending Lifespan Of Memory In Storage Devices - A management platform for extending lifespan of memory, such as SD, MMC, micro SD, of storage devices is provided. The memory includes a plurality of virtual access units, and a virtual block is defined to include a fixed number of virtual access units. In the management platform, a memory control unit tallies the number of operations performed on a virtual access unit when the virtual access unit is selected to perform on. A processing unit determines whether the data stored in virtual access units should be move to another virtual access unit according to an operation threshold in order to prevent from data loss caused by the memory damage. | 04-16-2009 |
| 20090100215 | IDENTITY-BASED FLASH MANAGEMENT - Methods, apparatus, and computer code for effecting flash policy configuration operations in accordance with an end-user identifier and/or a host-instance identifier are disclosed herein. Exemplary flash policy configuration operations include (i) configuring a flash error-correction policy, (ii) configuring a flash-management table storage policy; (iii) configuring a wear-leveling policy; (iv) configuring a bad-block management policy and (v) configuring a flash-programming voltage parameter. Exemplary end-user identifiers include but are not limited to email account identifiers, logon user names, and International Mobile Subscriber Identities (IMSI). Exemplary host-instance identifiers may include but are not limited to International Mobile EQUIPMENT Identifiers (IMEI). Optionally, the flash policy configuration is contingent on authentication context data—for example, strength of the authentication (e.g. login/password vs. smartcard authentication or biometric authentication), date of the authentication, and identity provider information. | 04-16-2009 |
| 20090100216 | Power saving optimization for disk drives with external cache - A power conservation system implementable in a computer system. The system includes a non-volatile cache memory (NVCM) device for storing information. The NVCM device is operationally coupled to the computer system. The system also includes a data storage device coupled to the NVCM device. The data storage device is for storing said information. The system further includes a controller coupled to the NVCM device. The controller initiates an occurrence of writing the information in the NVCM device to the data storage device. The occurrence of writing causes powering up of the data storage device to which the data is to be written or from which data is to be retrieved. | 04-16-2009 |
| 20090100217 | Portable Data Transfer and Mass Storage Device for Removable Memory Modules - A hand-held battery powered device for transferring data between one or more flash memory modules and a mass storage device. The device includes one or more slots to accept a flash memory module into a housing which includes fixed or removable mass storage device and logic circuitry disposed within the housing for transferring data between the flash memory module and mass storage device. Ports are disclosed for transferring data from the resident mass storage device to the user's computer. | 04-16-2009 |
| 20090100218 | HARD DISK DRIVE WITH REDUCED POWER CONSUMPTION, RELATED DATA PROCESSING APPARATUS, AND I/O METHOD - A hard disk drive is disclosed and related methods of reading/writing data are disclosed. The hard disk drive includes a disk serving as a main data storage medium, and first and second buffers storing data to be stored on the disk, as well as a controller defining a data I/O path in relation to a detected operating state of the hard disk drive. | 04-16-2009 |
| 20090106481 | HYBRID FLASH MEMORY DEVICE - A hybrid memory system is provided that combines the advantages of NAND flash memory devices with the advantages of NOR flashes memory devices. The system includes a NAND flash memory portion to provide mass storage and fast programming/erasure capabilities of conventional NAND flash memory devices. The system further comprises a NOR flash memory portion to provide code storage and fast random reading capabilities of conventional NOR flash memory devices. Accordingly, the hybrid memory system provides both mass storage and code storage. along with fast programming/erasure speeds and fast random access speeds. | 04-23-2009 |
| 20090106482 | MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT - In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes. | 04-23-2009 |
| 20090106483 | SECURE PERSONALIZATION OF MEMORY-BASED ELECTRONIC DEVICES - Systems and/or methods that facilitate programming content to a plurality of nonvolatile memory devices are presented. A wafer program component facilitates programming content to a plurality of memory devices contained on a wafer. The wafer program component can interface with the wafer and can employ parallel processes to program the memory devices on the wafer at substantially the same time. The content programmed to the memory devices can be the same content or different content. A portion of the content can be access-restricted where authentication information is to be provided in order to be granted access to such content, where access-restricted content can include content associated with subscriptions or personal information of a user(s). | 04-23-2009 |
| 20090106484 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME - A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area. | 04-23-2009 |
| 20090106485 | READING ANALOG MEMORY CELLS USING BUILT-IN MULTI-THRESHOLD COMMANDS - A method for data storage includes storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values. The memory has at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number. After storing the data, the first data bits are read from the memory cells by executing at least the second built-in command. | 04-23-2009 |
| 20090106486 | EFFICIENT PREFETCHING AND ASYNCHRONOUS WRITING FOR FLASH MEMORY - Disclosed herein are a flash file system and an address translation method. The flash file system includes a file system, a Flash Translation Layer (FTL), and flash memory. The FTL receives Local Block Addresses (LBAs) from the file system, and translates the LBAs into Physical Block Address (PBAs. The flash memory receives the resulting PBAs. The FTL includes a memory block in which a multi-stage clustered hash table for mapping the LBAs to the PBAs is stored, and performs the address translation using the clustered hash table. | 04-23-2009 |
| 20090106487 | Electronic Device Having a Memory Element and Method of Operation Therefor - An electronic device comprises a processing unit operably coupled to a buffer random access memory, in turn operably coupled to a non-volatile memory configured to emulate an electrically erasable programmable read only memory. The processing unit is arranged to transfer data between the buffer RAM and the non-volatile memory at a first clock frequency. A second RAM is operably coupled between the processing unit and the non-volatile memory and the processing unit sets a Tag bit in the second RAM to identify an address in the buffer RAM that is being written to or read from by the processing unit. | 04-23-2009 |
| 20090113113 | METHOD AND APPARATUS FOR SANITIZING OR MODIFYING FLASH MEMORY CHIP DATA - A method and apparatus is provided for individually checking, sanitizing and/or otherwise altering data bits of a plurality of memory chips via one or more processes where the memory chips being processed at any given time may be of different unformatted memory capacities, may be of different memory types, and may have the process started at different times. The method utilizes a computer based program capable of multithreaded operation whereby a new procedure thread is initiated upon a determination by the main program that a given reader port is in recent initial communication with a memory chip. | 04-30-2009 |
| 20090113114 | Implementation of One Time Programmable Memory with Embedded Flash Memory in a System-on-Chip - System and method for implementing one time programmable (OTP) memory using embedded flash memory. A system-on-chip (SoC) includes a cleared flash memory array that includes an OTP block, including an OTP write inhibit field that is initially deasserted, a flash memory controller, and a controller. Data are written to the OTP block, including setting the OTP write inhibit field to signify prohibition of subsequent writes to the OTP block. The SoC is power cycled, and, in response, at least a portion of the OTP block is latched in a volatile memory, including asserting an OTP write inhibit bit based on the OTP write inhibit field, after which the OTP block is not writeable. In response to each subsequent power cycling, the controller is held in reset, the latching is performed, the controller is released from reset, and the flash array, now write protected, is configured to be controlled by the controller. | 04-30-2009 |
| 20090113115 | NON-VOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI-LEVEL CELLS WITHIN THE SAME MEMORY - A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode. | 04-30-2009 |
| 20090113116 | Digital content kiosk and methods for use therewith - A digital content kiosk and methods for use therewith are disclosed. Various embodiments are disclosed relating to exemplary memory devices, memory architectures, and programming techniques that can be used with a digital content kiosk, exemplary mechanical and electrical components of a digital content kiosk, exemplary security aspects of a digital content kiosk, and exemplary uses of a digital content kiosk. Other embodiments are disclosed, and each of these embodiments can be used alone or in combination with one another. | 04-30-2009 |
| 20090113117 | RE-FLASH PROTECTION FOR FLASH MEMORY - A method for storing data includes providing a memory package including an integrated circuit containing a non-volatile memory and counter circuitry. The data is written to the non-volatile memory. The counter circuitry is operated to maintain a count of write operations performed on the non-volatile memory. The data and the count from the memory package are received at a controller, separate from the memory package, and the data is authenticated in response to the count. | 04-30-2009 |
| 20090113118 | MEMORY MODULE AND CONTROL METHOD OF SERIAL PERIPHERAL INTERFACE USING ADDRESS CACHE - A serial peripheral interface memory module using address cache comprises a flash memory array for storing data, a serial/parallel convertor for receiving serial signals and generating a control command, an address and data, an address register, an address accumulator for accumulating the address in the address register and storing the accumulated address back to the address register, and a flash memory controller for controlling the access to the flash memory array. When the control command is a standard command, the serial/parallel controller first stores the address following the control command into the address register and then the flash memory controller accesses data according to the address in the address register. When the control command is a specific command, the flash memory controller directly accesses data according to the address in the address register without waiting for an address update. | 04-30-2009 |
| 20090113119 | DATA WRITING METHOD - Data are write commanded from a host into a NAND flash memory. The data are saved once in a cache memory before being written into the NAND flash memory. The cache memory includes a physical segment whose size is the product of one page sector size of the NAND flash memory and the m-th power of 2 (m is 0 or a positive integer). A CPU records and manages the data writing status for each physical segment in a sector unit. | 04-30-2009 |
| 20090113120 | States Encoding in Multi-Bit Cell Flash Memory for Optimizing Error Rate - To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to [N/M] memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the [N/M] cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware. | 04-30-2009 |
| 20090113121 | Swappable Sets of Partial-Mapping Tables in a Flash-Memory System With A Command Queue for Combining Flash Writes - A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables. | 04-30-2009 |
| 20090119444 | MULTIPLE WRITE CYCLE MEMORY USING REDUNDANT ADDRESSING - The present invention produces a low-cost reliable non-volatile memory with multiple write cycles. The memory circuit trades full configurability for increased reliability and decreased cost by providing a limited number of write or rewrite cycles utilizing an indirectly accessible register set that writes data into fully configurable memory. The circuit is useful for both providing upgrade capability to electronic computational systems and data robustness to logic storage systems. Less configurable non-volatile memory (NVM) block | 05-07-2009 |
| 20090119445 | COMPUTER MEMORY ACCESSIBLE IN EITHER POWER STATE OF THE COMPUTER - A system on a computer for providing access to data stored on the computer in either power state is provided. The system can include a memory module and an external data interface connector. The system can further include a data interface controller for managing a data interface to the memory module and a data interface to the external data interface connector. The system can further include a multiplexer conductively connecting the data interface controller with the memory module when the computer is powered on, the multiplexer conductively disconnecting the data interface controller from the memory module when the computer is powered off and the multiplexer conductively connecting the external data interface connector with the memory module when the computer is powered on. | 05-07-2009 |
| 20090119446 | DIVIDED BITLINE FLASH MEMORY ARRAY WITH LOCAL SENSE AND SIGNAL TRANSMISSION - A flash memory array and a method for performing read operation therein are disclosed. The flash memory array comprises a plurality of memory segment, a data cache and a plurality of data handlers coupled between a pair of memory segment and between a memory segment and the data cache. A read operation of selected bitlines of a selected memory segment is performed by a segment data handler coupled to the selected memory segment locally and the read data is transmitted to the data cache. A segment data handler is configured to get read data from the selected bitlines by first pre-charging the bitlines and sensing the bitlines. Further, the read data is transmitted to the data cache through all of the segment data handlers in a sequential manner, if present between the selected memory segment and the data cache. | 05-07-2009 |
| 20090119447 | CONTROLLED BIT LINE DISCHARGE FOR CHANNEL ERASES IN NONVOLATILE MEMORY - Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge wherein the gate voltage of the discharge transistor component can be controlled by a discharge controller component. The rate of BL discharge can be determined by the size of discharge transistor component used in the design, the strength and/or size of the y-decoder component, the number of erase errors that occur for a particular memory device, and/or other factors in order to facilitate preventing hot switching from occurring. | 05-07-2009 |
| 20090119448 | Memory Apparatus, and Method of Averagely Using Blocks of a Flash Memory - A flash memory controller for averagely using blocks of a flash memory and the method thereof are provided. The flash memory controller is configured to process wear-leveling by allocating frequently updated data in less-erased blocks, and, allocating less-updated data in frequently erased blocks to achieve dynamic uniformity of times of erasion of blocks. | 05-07-2009 |
| 20090119449 | Apparatus and method for use of redundant array of independent disks on a muticore central processing unit - The invention is based on running the entire RAID stack on a dedicated core of one of the cores of the multi-core CPU. This makes it possible to eliminate the use of a conventional separate RAID controller and replace its function with a special flash memory chip that contains a program, which isolates the dedicated cores from the rest of the operating system and converts it into a powerful RAID engine. A part of the memory of the flash memory chip can also be used for storing data at power failure. This makes it possible to avoid having the battery backup module. The invention of the method of RAID on multi-core CPU may have many useful applications on an enterprise level, e.g., for increased accessibility and preserving critical data. | 05-07-2009 |
| 20090119450 | MEMORY DEVICE, MEMORY MANAGEMENT METHOD, AND PROGRAM - A memory device includes a non-volatile memory which allows data to be written, read, and erased electrically and in which writing and reading are done in units of a page and erasing is done in units of a block including a plurality of pages, and a control section that manages access to the non-volatile memory. The control section performs management of access to the non-volatile memory by performing logical address-physical address translation (logical-physical translation) in translation units (TUs) each being an integer fraction of a size of the block and an integer multiple of a page size. | 05-07-2009 |
| 20090125668 | Management of erased blocks in flash memories - The invention relates to a method for managing the erasure process in a memory system comprising individually erasable memory blocks (SB) that can be addressed with the aid of real memory block addresses (SBA). Said memory blocks are sub-divided into a plurality of writable sectors and can be addressed by means of an address conversion that uses an allocator table (ZT) to convert logical block addresses (LBA) into one of the respective memory block addresses (SBA). According to the invention, the allocator table (ZT) is sub-divided into at least one useful data area (NB) and a buffer block area (BB). The invention is characterised in that a first identifier erased (ER), indicating the physical erasure status and a second identifier content erased (CER), indicating the logical erasure status, is set for each memory block (SB) in the allocator table (ZT). | 05-14-2009 |
| 20090125669 | PREVENTING DATA LOSS IN A STORAGE SYSTEM - Storage servers use a fast, non-volatile or persistent memory to store data until it can be written to slower mass storage devices such as disk drives. If the server crashes before a write can complete, the data remains safely stored in non-volatile memory. If the data cannot be committed to disk when the server reboots (e.g. because the destination mass storage device is unavailable), it is stored in a file. When the disk reappears, the data in the file may be used to restore a file or file system on the disk to a consistent state. | 05-14-2009 |
| 20090125670 | ERASE BLOCK MANAGEMENT - An improved Flash memory device with a distributed erase block management (EBM) scheme is detailed that enhances operation and helps minimize write fatigue of the floating gate memory cells of the Flash memory device. The Flash memory device of the invention combines the EBM data in a user data erase block by placing it in an EBM data field of the control data section of the erase block sectors. Therefore distributing the EBM data within the Flash memory erase block structure. This allows the Flash memory to update and/or erase the user data and the EBM data in a single operation, to reduce overhead and speed operation. The Flash memory also reduces the process of EBM data structure write fatigue by allowing the EBM data fields to be load leveled by rotating them with the erase blocks they describe. | 05-14-2009 |
| 20090125671 | APPARATUS, SYSTEM, AND METHOD FOR STORAGE SPACE RECOVERY AFTER REACHING A READ COUNT LIMIT - An apparatus, system, and method are disclosed for storage space recovery after reaching a read count limit. A read module reads data in a storage division of solid-state storage. A read counter module then increments a read counter corresponding to the storage division. A read counter limit module determines if the read count exceeds a maximum read threshold, and if so, a storage division selection module selects the corresponding storage division for recovery. A data recovery module reads valid data packets from the selected storage division, stores the valid data packets in another storage division of the solid-state storage, and updates a logical index with a new physical address of the valid data. | 05-14-2009 |
| 20090125672 | MEMORY CARD AND HOST DEVICE THEREOF - A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal. | 05-14-2009 |
| 20090125673 | MEMORY CARD AND HOST DEVICE THEREOF - A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal. | 05-14-2009 |
| 20090132752 | Interface for Non-Volatile Memories - A portable storage device for storage of data. The portable storage device comprises a first non-volatile memory of a first character; a second non-volatile memory of a second character, the second character being different to the first character; and a controller for determining to which of the first and second non-volatile memory the data is to be sent. The determining is based on a defined relationship between the first and second non-volatile memories, the defined relationship being buffer or backup. | 05-21-2009 |
| 20090132753 | REPLICATION MANAGEMENT SYSTEM AND METHOD WITH UNDO AND REDO CAPABILITIES - A method for replicating a volume of data including UNDO and REDO data replication commands includes identifying a current state of the database through a point in time (PIT) copy of all volumes to be affected, ensuring that enough storage volume is identified to carry out the point in time copies and if not, the appropriate user warning issued notifying the user that the UNDO or REDO functions will not be available for a particular session. | 05-21-2009 |
| 20090132754 | DATA STORAGE DEVICE WITH HISTOGRAM OF IDLE TIME AND SCHEDULING OF BACKGROUND AND FOREGROUND JOBS - A data storage device includes a cumulative data histogram of lengths of idle times between foreground user service requests. The cumulative data histogram is updated with measured lengths of current idle times between successive user service requests. Background service request are scheduled following a user service request after a time delay that is controlled as a function of the cumulative data histogram and a calculated length of a busy time of the background service request. | 05-21-2009 |
| 20090132755 | FAULT-TOLERANT NON-VOLATILE INTEGRATED CIRCUIT MEMORY - Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread over portions of a plurality of memory devices, rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices. | 05-21-2009 |
| 20090132756 | Portable flash memory storage device that may show its remaining lifetime - A portable flash memory storage device that may show its remaining lifetime according to this invention is provided, in which an average erase count that is stored may be read and, after being processed and converted, is formed into a piece of information on its remaining lifetime that is further shown on a display screen of a display module in the portable flash memory storage device, and an erase is implemented on the portable flash memory storage device for an automatic update of average erase count, allowing a user to decide to replace the device or not depending on a latest remaining lifetime information. | 05-21-2009 |
| 20090132757 | STORAGE SYSTEM FOR IMPROVING EFFICIENCY IN ACCESSING FLASH MEMORY AND METHOD FOR THE SAME - A storage system for improving efficiency in accessing flash memory and method for the same are disclosed. The present invention provides a cache unit for temporarily storing data prior to writing in the flash memory or reading from the flash memory. In reading process, after data stored in a flash memory is accessed by a host, the cache unit holds the data. Upon subsequent read requests to read the same data, the data is cached accordingly, thereby shortening a preparation time for reading the data from the flash memory. In writing process, a host requests write a series of requests to write data into the flash memory, the data is gathered and is stored in the cache unit until the cache unit is full. A cluster of data in the cache unit is accordingly written into the flash memory, so that a preparation time for writing the data into the flash memory is also shortened. | 05-21-2009 |
| 20090132758 | RANK MODULATION FOR FLASH MEMORIES - We investigate a novel storage technology, Rank Modulation, for flash memories. In this scheme, a set of n cells stores information in the permutation induced by the different charge levels of the individual cells. The resulting scheme eliminates the need for discrete cell levels, and overshoot errors when programming cells (a serious problem that reduces the writing speed), as well as mitigate the problem of asymmetric errors. We present schemes for Gray codes, rewriting and joint coding in the rank modulation paradigm. | 05-21-2009 |
| 20090138650 | METHOD AND APPARATUS FOR MANAGING FIRMWARE OF AN OPTICAL STORAGE APPARATUS - A method of managing a firmware includes configuring the firmware to include at least a first firmware portion with a plurality of program codes, and a second firmware portion with a plurality of parameters separately; and storing the first firmware portion and the second firmware portion in a first storage area and a second storage area of a first storage module, respectively. | 05-28-2009 |
| 20090138651 | ENCODING METHOD FOR FLASH MEMORIES - A encoding method for a flash memory is provided, which can be used for reducing the memory wear and extend the endurance of the memory. The encoding method includes the steps as follows: (A) receiving a set of information bits; (B) counting an amount of the information bits needed to be programmed in the set; (C) reversing the set of information bits if the amount of information bits needed to be programmed is less than half of the amount of whole information bits in the set, so that there are more than half of the information bits needed to be programmed in the reversed set; and (D) programming the information bits needed to be programmed in the reversing set, including the reverse flag bit for read out check. | 05-28-2009 |
| 20090138652 | NON-VOLATILE MEMORY GENERATING DIFFERENT READ VOLTAGES - In one aspect, a non-volatile memory is provided which includes a plurality of m-bit non-volatile memory cells and a plurality of n-bit non-volatile memory cells, where 1≦m| 05-28-2009 | |
| 20090138653 | ELECTRONIC APPARATUS AND METHOD OF CONTROLLING A MEMORY UNIT CONNECTED TO THE SAME - An electronic apparatus in which a memory unit containing a memory and a controller to access the memory in response to an externally input command can be installed. The electronic apparatus comprises a first acquiring section which acquires identification information from the memory unit, a second acquiring section which, on the basis of the identification information acquired by the first acquiring section, acquires one from a plurality of control programs to control the controller of the memory unit, and a setting section which sets an operating environment so as to apply the control program acquired by the second acquiring section to the process of inputting and outputting data to and from the memory unit. | 05-28-2009 |
| 20090138654 | FATIGUE MANAGEMENT SYSTEM AND METHOD FOR HYBRID NONVOLATILE SOLID STATE MEMORY SYSTEM - A solid state memory system comprises a first nonvolatile semiconductor memory having a first write cycle lifetime and a first set of physical addresses, and a second nonvolatile semiconductor memory having a second write cycle lifetime and a second set of physical addresses. The first write cycle lifetime is greater than the second write cycle lifetime. The system further comprises a fatigue management module to generate a write frequency ranking for a plurality of logical addresses. The fatigue management module maps each of the plurality of logical addresses to a physical address of the first set of physical addresses or the second set of physical addresses based on the write frequency rankings. | 05-28-2009 |
| 20090144487 | STORAGE EMULATOR AND METHOD THEREOF - A storage emulator and method thereof are disclosed. The storage emulator allows a host system to access a storage unit connected to a storage system as if the storage unit is directly coupled to the host system. The storage emulator includes a virtual storage emulating module, a storage-managing unit, and a communicating module. The virtual storage emulating module emulates at least one virtual storage unit corresponding to the storage unit on the host system and receives a storage accessing command from the host system. The storage-managing unit identifies the storage accessing command as either a self-sustaining type command or a non-self-sustaining type command. The communicating module communicates with the storage unit of the storage system via the network. If the storage accessing generates a self-sustaining command response in accordance with the storage accessing command and returns the self-sustaining command response to the host system directly. If the storage accessing command is identified as the non-self-sustaining type command, the storage-managing unit forwards the storage accessing command to the storage system via the network, receives a command response in accordance with the storage accessing command from the storage system, and returns the command response to the host system. | 06-04-2009 |
| 20090144488 | MEMORY CARD AND METHOD FOR HANDLING DATA UPDATING OF A FLASH MEMORY - The invention provides a method for handling data updating of a flash memory. In one embodiment, the flash memory comprises a mother block comprising a plurality of updated pages to be updated. First, a spare block, recording no data, is popped as a file allocation table (FAT) block corresponding to the mother block. Data for updating the updated pages of the mother block is then written to a plurality of replacing pages of the FAT block. Finally, a plurality of mapping relationships between the replacing pages and the updated pages are recorded in a page mapping table stored in the FAT block. | 06-04-2009 |
| 20090144489 | ELECTRONIC DEVICE AND PROGRAM FOR OPERATING THE SAME - A navigation device realizes such processing as map display and route guidance based on map data stored in a memory card. The data in the memory card tends to be volatilized with an increase in the frequency of reading of data. Therefore, the data that are highly frequently read out are held in a RAM so as to be read from the memory card at a decreased frequency. Further, the passage of time is calculated from the date and hour the data are recorded in the memory card, and the whole data in the memory card are refreshed every time when the passage of time exceeds a threshold value T | 06-04-2009 |
| 20090150594 | METHOD TO MINIMIZE FLASH WRITES ACROSS A RESET - A method and apparatus described herein are for minimizing flash writes across reset. When a commonly accessed variable is to be updated, an erase conscious value is written to minimize erase operations. As an example, the location for the commonly accessed variable holds consecutive values to represent a usable value instead of a binary representation. Furthermore, when the commonly accessed variable is to be read, the stored value is translated into the associated usable value for use by a system. | 06-11-2009 |
| 20090150595 | BALANCED PROGRAMMING RATE FOR MEMORY CELLS - A balanced program rate on NVM cells is achieved by (i) scrambling data bits and user bits; and (ii) shifting ED bits (of data and user bits) according to an incremental shift number, which may be the PBE-counter (which provides an incremental number). ED bits for the LSS may also be shifted, according to an incremental shift number (which may be the PBE-counter). The ED bits of the shift-niumber inherently have an evenly balanced distribution The ED bits of the PBE-counter inherently have an evenly balanced distribution. | 06-11-2009 |
| 20090150596 | DEVICE IDENTIFIERS FOR NONVOLATILE MEMORY MODULES - A memory card has a data scrambler that performs a data scrambling operation on data stored in the memory card according to a device ID associated with the memory card. The device ID is either set at the factory and permanently stored in the card, or configurable by a user or a host system. | 06-11-2009 |
| 20090150597 | DATA WRITING METHOD FOR FLASH MEMORY AND CONTROLLER USING THE SAME - A data writing method for a flash memory is provided. The data writing method includes: dividing a new data into at lease one sub-data by the length of a writing unit; selecting one of a plurality of spare blocks from the flash memory as a substitute block for substituting a data block, wherein the new data is to be written into the data block; sequentially writing the sub-data having the length of the writing unit into the substitute block in the writing unit; and storing the sub-data not having the length of the writing unit into a temporary area. The writing efficiency of the flash memory can be improved by temporarily storing the sub-data not having the length of the writing unit into the temporary area and then writing the sub-data not having the length of the writing unit with subsequent data into the substitute block. | 06-11-2009 |
| 20090150598 | APPARATUS AND METHOD OF MIRRORING FIRMWARE AND DATA OF EMBEDDED SYSTEM - Disclosed is an apparatus and method of mirroring firmware and data of an embedded system. The embedded system mirrors a boot loader image, a kernel image, a RAM disk image and data that are stored on a main flash memory to be operated onto a secondary flash memory. Therefore, when a main flash memory does not normally work, the firmware and data that are stored on the main flash memory to be operated is mirrored onto the secondary flash memory, which prevents the loss of data and maintains the operation of the embedded system. As a result, it is possible to secure the reliability and operability of the system. | 06-11-2009 |
| 20090150599 | METHOD AND SYSTEM FOR STORAGE OF DATA IN NON-VOLATILE MEDIA - A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data. | 06-11-2009 |
| 20090150600 | MEMORY SYSTEM - A memory system includes a nonvolatile memory having a plurality of data blocks each of which is a unit of data erase and has a plurality of pages, each of the pages being a unit of data write, and a controller which checks whether or not the nonvolatile memory has been affected by power interruption at power-on time and, if the nonvolatile memory has been affected by power interruption, writes data to that first page in a first data block which has not been affected by power interruption. | 06-11-2009 |
| 20090150601 | Partial Block Data Programming And Reading Operations In A Non-Volatile Memory - Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units. | 06-11-2009 |
| 20090157946 | MEMORY HAVING IMPROVED READ CAPABILITY - In the present invention, a memory, and in particular, a NOR emulating memory comprises a memory controller having a non-volatile memory for storing program code to initiate the operation of the memory controller. The controller has a first bus for receiving address signals from a host device and a second bus for interfacing with a RAM memory, and a third bus for interfacing with a NAND memory. A volatile RAM memory is connected to the second bus. A NAND memory is connected to the third bus. The controller receives commands and a first address from the first bus, and maps the first address to a second address in the NAND memory, and operates the NAND memory in response thereto. The RAM memory serves as cache for data to or from the NAND memory. The controller also maintains data coherence between the data stored in the RAM memory as cache and the data in the NAND memory. The invention further has a first buffer for storing data from the NAND memory in response to a read command to be written to the RAM memory, and a second buffer for storing data from the RAM memory to be written to the NAND memory. In the event of a read operation, if the data from the specified address is in the RAM memory, then the data is read from the RAM memory completing the read operation. In the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is sufficient space in the RAM memory to store an entire page of data from the NAND memory, then the entire page is read from the NAND memory, stored in the first buffer and then stored in the RAM memory, and from the specified address is read out, completing the read operation. Finally, in the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is insufficient space in the RAM memory to store an entire page of data from the NAND memory, then an entire page from the RAM memory is first stored in the second buffer, then an entire page is read from the NAND memory, stored in the first buffer, and from the first buffer, stored in the now freed RAM memory and data from the specified address is read out, completing the read operation. The page of data from the second buffer is subsequently stored back into the NAND memory after the completion of the read operation thereby reducing read latency. | 06-18-2009 |
| 20090157947 | Memory Apparatus and Method of Evenly Using the Blocks of a Flash Memory - A memory apparatus and a method of evenly using the blocks of a flash memory are provided. The memory apparatus comprises a flash memory and a controller. The flash memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks. The controller is configured to receive data corresponding to the first data block, select a spare block, program data into the spare block when the erase count corresponding to the spare block is less than the predetermined value or to select a second data block and program data stored in the second data block into the spare block when the erased count corresponding to the spare block reaches the predetermined value. As a result, the blocks of the flash memory are used evenly. | 06-18-2009 |
| 20090157948 | INTELLIGENT MEMORY DATA MANAGEMENT - Systems and/or methods that facilitate data management on a memory device are presented. A data management component can log and tag data creating data tags. The data tags can comprise static metadata, dynamic metadata or a combination thereof. The data management component can perform file management to allocate placement of data and data tags to the memory or to erase data from the memory. Allocation and erasure are based in part on the characteristics of the data tags, and can follow embedded rules, an intelligent component or a combination thereof. The data management component can provide a search activity that can utilize the characteristics of the data tags and an intelligent component. The data management component can thereby optimize the useful life, increase operating speed, improve accuracy and precision, improve efficiency of non-volatile (e.g., flash) memory and provide improved functionality to memory devices. | 06-18-2009 |
| 20090157949 | ADDRESS TRANSLATION BETWEEN A MEMORY CONTROLLER AND AN EXTERNAL MEMORY DEVICE - In one or more embodiments, address translation is performed over a dedicated serial bus between a non-volatile memory controller and a memory device that is external from the non-volatile memory device. The memory controller accesses memory address translation data in the external memory device to determine a physical address that corresponds to a logical memory address. The controller can then use the physical memory address to generate memory signals for the non-volatile memory array. | 06-18-2009 |
| 20090157950 | NAND flash module replacement for DRAM module - An electronic memory module according to the invention provides non-volatile memory that can be used in place of a DRAM module without battery backup. An embodiment of the invention includes an embedded microprocessor with microcode that translates the FB-DIMM address and control signals from the system into appropriate address and control signals for NAND flash memory. Wear-leveling, bad block management, garbage collection are preferably implemented by microcode executed by the microprocessor. The microprocessor, additional logic, and embedded memory provides the functions of a flash memory controller. The microprocessor memory preferably contains address mapping tables, free page queue, and garbage collection information. | 06-18-2009 |
| 20090157951 | INFORMATION RECORDING DEVICE AND INFORMATION RECORDING METHOD - An information recording device includes a table showing a physical address in first and second areas and a number of rewriting at the physical address in a correspondence manner, the first area being a writing destination in a recording medium configured to be consumed by rewriting, the second area being not a writing destination in the recording medium, an instructor configured to instruct to change the first and second tables based on the first table and the physical address of the writing destination, a changer configured to change the table based on the instruction, and a writer configured to write data to the recording medium based on the physical address in the first area. | 06-18-2009 |
| 20090157952 | Semiconductor memory system and wear-leveling method thereof - Disclosed is a semiconductor memory system and wear-leveling method thereof. The semiconductor memory system is comprised of a nonvolatile memory including a plurality of logic blocks each of which is divided into a plurality of entries, a file system detecting a type of data to be stored and allocating the logic block or the entry for storing the data in accordance with the data type, and a translation layer leveling wearing degrees over the logic blocks or the entries in accordance with the data type. The semiconductor memory system is improved in performance and lifetime by managing wearing degrees over the logic block or the entries in accordance with the data type. | 06-18-2009 |
| 20090157953 | Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein - A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer. | 06-18-2009 |
| 20090164700 | EFFICIENT MEMORY HIERARCHY IN SOLID STATE DRIVE DESIGN - Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one (“L1”) cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component. | 06-25-2009 |
| 20090164701 | PORTABLE IMAGE INDEXING DEVICE - A portable image-indexing device that includes a port adapter for connecting to a personal computer and a port adapter for receiving a camera card. The device includes memory for storing a plurality of image and video files and for storing image indexing application programs. A processor performs image indexing on images and/or videos and includes a power source. | 06-25-2009 |
| 20090164702 | FREQUENCY DISTRIBUTED FLASH MEMORY ALLOCATION BASED ON FREE PAGE TABLES - Systems and/or methods that provide for frequency distributed flash memory allocation are disclosed. The systems and methods determine the rate at which a system address is being written and the current erase cycle state of each data block in the non-volatile memory device and assigns a physical address to the write operation based on the determined system address rate and the current erase state of each data block in the non-volatile system. In this regard, system addresses that are assigned more frequently are assigned physical page addresses from data blocks which have a low erase cycle state (i.e., greater cycle endurance remaining) and system addresses that assigned less frequently are assigned physical page addresses from data blocks which have a high erase cycle state (i.e., lesser cycle endurance remaining). The result is a more robust non-volatile device having increased erase/initialization cycle endurance, which adds to the overall reliability of the device over time. | 06-25-2009 |
| 20090164703 | FLEXIBLE FLASH INTERFACE - Systems and methods that can facilitate providing a flexible flash interface component that can accommodate communicating with almost any flash memory component (e.g., Open NAND Flash Interface (ONFI) compliant and ONFI noncompliant flash memory). A micro-operations component can contain one or more micro-operation that can be used to execute commands within the flash interface component. To facilitate a flexible flash interface, the micro-operations can include such commands as, but are not limited to, sending a command to the flash memory, sending a row address, sending a column address, transmit data (TXD), receive data (RXD), have the flash interface wait for a ready signal from the flash memory, read a status register from a flash memory, and/or provide an end of sequence (EOS) indication to the flash interface, for example. | 06-25-2009 |
| 20090164704 | HIGH PERFORMANCE FLASH CHANNEL INTERFACE - Systems and/or methods that facilitate high performance flash channel interface techniques are presented. Integrated error correction code (ECC) engine and buffer sets facilitate bypassing error correction of data being written to or read from memory, such as flash memory, in addition to single ECC mode or multiple ECC mode. The integrated ECC engines and buffers can quickly analyze data, and provide error correction information or correct error, significantly increasing throughput. In addition, the programmable flash channel interface can provide more rapid development of flash products by accommodating both Open NAND Flash Interface (ONFI) standard flash and legacy flash devices, by using a configurable micro-code engine in the flash interface. | 06-25-2009 |
| 20090164705 | System and Method for Implementing Extensions to Intelligently Manage Resources of a Mass Storage System - Systems and methods for implementing extensions to intelligently manage resources of a mass storage system are disclosed. Generally, a host sends an extension of an enabled set of extensions to a mass storage system that includes at least one of command sequence information, command information or file attribute information. The host additionally sends a host application command to the mass storage system that includes logical block address information associated with the at least one of command sequence information, command information or file attribute information of the extension. Based on the received extension, the mass storage system intelligently performs operations that efficiently manage the resources of the mass storage system to reduce the frequency of operations such as data consolidation operations, data collection operations, and data copy operations, thereby increasing the data programming and reading performance of the mass storage system. | 06-25-2009 |
| 20090164706 | Emulation of a NAND memory system - A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example. | 06-25-2009 |
| 20090164707 | Method and system for accessing non-volatile memory - Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data. | 06-25-2009 |
| 20090164708 | MEMORY CHIP WITH EXTENDED INPUT/OUTPUT INTERFACE - A memory chip ( | 06-25-2009 |
| 20090164709 | SECURE STORAGE DEVICES AND METHODS OF MANAGING SECURE STORAGE DEVICES - Methods of managing a secure area in a secure storage device include conducting an authentication process between a host and the secure storage device while modifying a size of the secure area, backing up secure data to the host from the secure area after completing the authentication process, updating management information to modify a size of the secure area, and storing the secure data, which has been backed up to the host, into the secure area that is modified in size. Related storage devices are also disclosed. | 06-25-2009 |
| 20090164710 | SEMICONDUCTOR MEMORY SYSTEM AND ACCESS METHOD THEREOF - A semiconductor memory system and access method thereof. The semiconductor memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores monitoring data in one or more of plural memory cells. The memory controller controls the nonvolatile memory. The memory controller detects the monitoring data and adjusts a bias voltage, which is provided to the plural memory cells, in accordance with a result of the detection. | 06-25-2009 |
| 20090164711 | SEMICONDUCTOR MEMORY CONTROLLER, SEMICONDUCTOR MEMORY, AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY CONTROLLER - A semiconductor memory controller, which outputs data to be stored in a memory unit to the memory unit via a bus of N-bit width (N is an even number), executes a duplexing process on the data to generate duplicated data, simultaneously outputs the respective duplicated data to two different sections of the memory unit using N/2 bit width for each duplicated data, and stores the duplicated data in the two sections of the memory unit, respectively. | 06-25-2009 |
| 20090164712 | FLASH MEMORY - A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal. | 06-25-2009 |
| 20090172246 | DEVICE AND METHOD FOR MANAGING INITIALIZATION THEREOF - A host may initialize itself faster by enabling an associated storage device to respond to host access commands under specified conditions before the storage device has completed its own initialization. Embodiments of the invention include a storage device, a controller, a method of servicing commands, and a method of using a host that sends access commands to a storage device. Access commands to a flash memory use logical addresses to reference the memory contents. A controller translates the logical addresses to physical addresses using a mapping table that the controller constructs in volatile memory during initialization based on data retrieved from the flash memory. An access command satisfying a predefined condition is serviced before the controller completes the construction of the mapping table. | 07-02-2009 |
| 20090172247 | CONTROLLER FOR ONE TYPE OF NAND FLASH MEMORY FOR EMULATING ANOTHER TYPE OF NAND FLASH MEMORY - A controller for one type of NAND flash memory device that emulates another type of NAND flash memory device. The controller may include a host NAND interface to receive host data from a NAND host device, and a data aggregator for aggregating the host data with complementary data, to thereby create device data that is storable in a device page of an array of NAND flash memory cells of the NAND flash memory device. After creating the device data the controller writes the device data into a device page of the NAND flash memory cells. The controller also includes a data parser to parse host data from device data when data read operations are executed by the controller. If required, the controller uses the data parser to parse complementary data from device data to create device data when data writing operations are executed by the controller. | 07-02-2009 |
| 20090172248 | MANAGEMENT OF A FLASH MEMORY DEVICE - Methods, computing devices and machine readable medium to manage sector based file system accesses to block erasable flash memory devices are disclosed. One disclosed method includes allocating erasable blocks of a flash memory device to a volume and formatting the volume of a flash memory device with a file system designed to access the flash memory device via sectors that are each smaller than an erasable block. The method also includes writing a data unit to a special block of the erasable blocks and writing a sector mapping table unit to the special block to associate the data unit with a sector of the file system. The method further includes allocating a spare block of erasable blocks to support a reclaim process. | 07-02-2009 |
| 20090172249 | DYNAMICALLY ADJUSTING CACHE POLICY BASED ON DEVICE LOAD IN A MASS STORAGE SYSTEM - A dynamic cache policy manager for a mass memory may be used to decide whether a data request is to be routed to the cache or directly to the mass memory, based on estimated delays in processing the request. The choice may be based, at least partially, on the size of the respectively queues for the cache and mass memory. For write requests, the choice may be based on how many erase blocks are available in the cache. | 07-02-2009 |
| 20090172250 | RELOCATING DATA IN A MEMORY DEVICE - Systems and methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others. | 07-02-2009 |
| 20090172251 | Memory Sanitization - Apparatus and method for memory sanitization is disclosed, including a memory, the memory including—in whole or in part—multiple layers of memory, and control logic configured to perform a sanitize operation on a portion of the memory. In one example, a third dimensional memory array can constitute at least a portion of the multiple layers of memory. The multiple layers of memory may include non-volatile two-terminal cross-point memory arrays. Each non-volatile two-terminal cross-point memory array can include a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the terminals of the two-terminal memory element. The two-terminal memory elements retain stored data in the absence of power. The non-volatile two-terminal cross-point memory arrays can be vertically stacked upon one another and may be positioned on top of a logic plane that includes active circuitry. | 07-02-2009 |
| 20090172252 | Memory device and method for performing a write-abort-safe firmware update - A memory device and method for performing a write-abort-safe firmware update are disclosed. In one embodiment, a location in a memory of a memory device for a firmware update is allocated. The firmware update is written into the allocated location in the memory. A pointer is written to the firmware update in a directory, and a pointer is written to the directory in a location in the memory that is read during boot-up. In another embodiment, a block in a memory of a memory device is allocated for updated file system data comprising a firmware update and a directory. The updated file system data is written into the allocated location in the memory. A pointer is written to the firmware update in the directory, and a pointer is written to the updated file system data in a boot block in the memory, wherein the boot block is read during boot-up. | 07-02-2009 |
| 20090172253 | Methods and apparatuses for nonvolatile memory wear leveling - Apparatuses, systems, and computer program products that enable wear leveling of nonvolatile memory devices, such as flash memory devices, are disclosed. One or more embodiments an apparatus that has a receiver and a wear leveling module. The receiver may receive low-level write requests to update direct-mapped values of nonvolatile memory. The wear leveling module may determine physical locations of the nonvolatile memory that correspond to logical locations of the write requests. Alternative embodiments may comprise systems or apparatuses that include one or more various types of additional modules, such as low-level driver modules, error correction code modules, queue modules, bad block management modules, and flash translation layer modules. Other embodiments comprise computer program products that receive a direct-mapped low-level write request, determine a physical write location of nonvolatile memory that corresponds to a logical write location of the low-level write request. | 07-02-2009 |
| 20090172254 | METHOD FOR PREVENTING READ-DISTURB HAPPENED IN NON-VOLATILE MEMORY AND CONTROLLER THEREOF - A method for preventing read-disturb happened in non-volatile memory and a controller thereof are disclosed. The non-volatile memory includes a plurality of blocks, and the blocks are grouped into at least a data group and a spare group, each block includes a plurality of pages. The method includes recording read times of at least a first block of the blocks within the data group and then renewing the original data stored in the first block when the read times of the first block is greater than a predetermined value. | 07-02-2009 |
| 20090172255 | WEAR LEVELING METHOD AND CONTROLLER USING THE SAME - A wear leveling method for a multi level cell (MLC) NAND flash memory is provided. The flash memory includes a first zone and a second zone respectively having a plurality of blocks, wherein each of the blocks includes an upper page and a lower page. The wear leveling method includes: respectively determining whether to start a block swapping operation of a wear leveling process in the first zone and the second zone of the flash memory according to different start-up conditions; and respectively performing the block swapping operation in the first zone and the second zone, wherein the blocks in the first zone are accessed by using only the lower pages, and the blocks in the second zone are accessed by using both the upper pages and the lower pages. Thereby, the lifespan of the flash memory is effectively prolonged and meaningless consumption of system resources is avoided. | 07-02-2009 |
| 20090172256 | DATA WRITING METHOD FOR FLASH MEMORY, AND FLASH MEMORY CONTROLLER AND STORAGE DEVICE THEREOF - A data writing method for a block of a multi level cell NAND flash memory including upper page addresses and lower page addresses is provided, wherein a writing speed at the lower page addresses is higher than that at the upper page addresses. The data writing method includes receiving a writing command and determining whether an address to be written with new data in the writing command is the upper page address of the block. The method also includes copying old data previously recorded on the lower page addresses of the block as an old data backup when the address to be written in the writing command is the upper page address of the block and then writing the new data to the address to be written. Thus, old data may be protected while writing data to the upper page address of the multi level cell NAND flash memory. | 07-02-2009 |
| 20090172257 | System and method for performing host initiated mass storage commands using a hierarchy of data structures - Disclosed is a mass storage system and method for breaking a host command into a hierarchy of data structures. Different types of data structures are designed to handle different phases of tasks required by the host command, and multiple data structures may be used to handle portions of the host command in parallel, thereby allowing increased performance. The disclosed embodiments include a flash memory controller designed to allow a high degree of pipelining and parallelism. | 07-02-2009 |
| 20090172258 | Flash memory controller garbage collection operations performed independently in multiple flash memory groups - A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold. | 07-02-2009 |
| 20090172259 | Mass storage controller volatile memory containing metadata related to flash memory storage - A volatile memory associated with a mass storage controller and a flash memory module. The volatile memory includes a number of tables containing information related to the flash memory storage, including a table storing physical flash memory addresses and a plurality of tables containing metadata. | 07-02-2009 |
| 20090172260 | Flash memory controller and system including data pipelines incorporating multiple buffers - A storage controller connected to a flash memory storage module, the controller and module including multiple sets of buffers. The buffers are part of one or more pipelines through which data is moved between the storage module and one or more hosts. | 07-02-2009 |
| 20090172261 | Multiprocessor storage controller - A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In one embodiment, the storage controller operates with a flash memory module, and includes multiple parallel pipelines that allow plural host commands to be handled simultaneously. | 07-02-2009 |
| 20090172262 | Metadata rebuild in a flash memory controller following a loss of power - A method of rebuilding metadata in a flash memory controller following a loss of power. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area is valid. | 07-02-2009 |
| 20090172263 | Flash storage controller execute loop - In a storage controller connected to a flash memory module, an execute loop used to carry out tasks related to reading or writing data from the module. The loop includes reading a data structure from a queue and carrying out a task specified by the data structure, unless resources required by the task are not available, in which event the loop moves on to another data structure stored in another queue. Data structures bypassed by the loop are periodically revisited, until all tasks required are completed. Data structures store state information that is updated when tasks are completed. | 07-02-2009 |
| 20090172264 | SYSTEM AND METHOD OF INTEGRATING DATA ACCESSING COMMANDS - A data accessing command integration method includes the following steps. Firstly, M data accessing commands are sequentially received through a bus, wherein N data accessing commands contained in the M data accessing commands have the same command type and comply with a sequential address relationship. Next, the N data accessing commands are re-ordered according to the addressing sequence, so that a first data corresponding to the re-ordered N data accessing commands are sequentially accessed in the data memory. | 07-02-2009 |
| 20090172265 | FLASH MEMORY DEVICE HAVING SECURE FILE DELETION FUNCTION AND METHOD FOR SECURELY DELETING FLASH FILE - Disclosed is a flash memory device having a secure flash file deletion function and a method for securely deleting a flash file. Data and object headers as actual contents of the flash file are separately stored in data blocks and header blocks. At this time, the data is encrypted and stored, and a decryption key is included in an object header and stored in a header block. When the flash file is deleted, the object header is deleted by searching the header block where the object header including the decryption key is stored. In order to search the header block, a binary tree structure is used in which a terminal node indicates an LSB of a file ID. Disclosed may be applied to an embedded system where a flash memory is used as a storage medium. In particular, disclosed is suitable for a NAND flash memory device. | 07-02-2009 |
| 20090172266 | MEMORY SYSTEM - A memory system includes a NAND flash memory including a memory block containing a plurality of pages, and a controller which controls write of data to the flash memory, and includes a scrambling circuit which converts the data into a pseudo random number, wherein the scrambling circuit includes an initial value generator which generates an initial value for every segment, an initial value shifter which shifts the initial value by N bits for every page address, a pseudo random number generator which generates a pseudo random number sequence by an M-sequence by using the initial value shifted N bits, and a random number adder which adds the pseudo random number sequence to the data. | 07-02-2009 |
| 20090172267 | REFRESH METHOD OF A FLASH MEMORY - A flash memory device includes a flash memory that stores many physical data blocks, a refresh management table that stores indications of the number of times each individual physical data block has been read, and a controller responsive to read and erase control signals from a source external to the flash memory device, and to the stored indications of the refresh management table for controlling reading, erasing and refreshing of the individual physical data blocks. In response to the number of times each individual physical data block has been read being equal to or exceeding a limit value, the controller refreshes the individual physical data block associated with the indication equaling or exceeding the limit value. | 07-02-2009 |
| 20090172268 | METHOD FOR SECURING A MICROPROCESSOR, CORRESPONDING COMPUTER PROGRAM AND DEVICE - A method is provided for securing a microprocessor containing at least one main program, which operates with at least one memory. The method includes implementing counter-measures, during which additional operations, that are not required for the main program, are implemented so as to modify the consumption of current and/or the processing time of the microprocessor. The method also includes: identification of at least one address or one memory zone of the memory(ies), called critical addresses, and which contain, or which may contain, critical data for said main program; monitoring the addressing ports of the memory(ies), so as to detect the access to the critical address(es); and activation of the step of implementing counter-measures, when an access to the critical address(es) is detected. | 07-02-2009 |
| 20090172269 | NONVOLATILE MEMORY DEVICE AND ASSOCIATED DATA MERGE METHOD - A memory system is disclosed with a nonvolatile memory adapted to store a file system containing file system information, and a controller adapted to read the file system information and perform a merge operation. | 07-02-2009 |
| 20090177833 | Buffering systems methods for accessing multiple layers of memory in integrated circuits - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 07-09-2009 |
| 20090177834 | METHOD FOR MANAGING DATA INTENDED TO BE WRITTEN TO AND READ FROM A MEMORY - The invention relates to a method for managing data intended to be written to and read from a memory of FLASHPROM type organized into pages. Several data are stored per page and the method consists:
| 07-09-2009 |
| 20090177835 | Flash Drive With Spring-Loaded Retractable Connector - A pen-type computer peripheral device includes an elongated housing containing a PCBA having a plug connector. The PCBA is secured to a positioning member that is actuated by way of a press-push button that is exposed through a slot defined in a wall of the housing. A spring-loaded mechanism includes a spring and a locking mechanism that locks the connector in a retracted position and a deployed position, and the spring biases the connector from the retracted position to the deployed position, or vice versa. | 07-09-2009 |
| 20090182933 | DURABLE DATA STORAGE SYSTEM AND METHOD - A method of operating a storage system, comprising: issuing a first command to write a first data to a first nonvolatile storage device; writing the first data to a second nonvolatile storage device if write condition is unstable; retrieving the first data from the second nonvolatile storage device; and writing the first data to the first nonvolatile storage device during a stable write condition, wherein whether write condition is stable is determined based on one of a sensor output or a memory access status signal, and wherein the memory access status signal is one of a predetermined value of retries, idling, access commands, or any combination thereof. | 07-16-2009 |
| 20090182934 | Memory device and method of multi-bit programming - Memory devices and multi-bit programming methods are provided. A memory device may include a plurality of memory units; a data separator that separates data into a plurality of groups; a selector that rotates each of the plurality of groups and transmits each of the groups to at least one of the plurality of memory units. The plurality of memory units may include page buffers that may program the transmitted group in a plurality of multi-bit cell arrays using a different order of a page programming operation. Through this, evenly reliable data pages may be generated. | 07-16-2009 |
| 20090182935 | MASS STORAGE DEVICE, IN PARTICULAR OF THE USB TYPE, AND RELATED METHOD FOR TRANSFERRING DATA - A mass storage device of the present invention includes one or more memory elements and a logic module adapted to interface the one or more memory elements for exchanging data according to a data exchange protocol, in particular of the USB type, through a first port. The mass storage device has a module for detecting the presence of a power voltage associated with a first connector of the first port, and the logic module can set the storage device to either a Host or a Function device configuration depending on the detection carried out by the module for detecting the presence of a power voltage. The device also includes a second port adapted to implement a direct data exchange with further storage devices. The device additionally offers the possibility of communicating with radio or optical wireless ports exchanging data through a data bus, e.g. of the USB type. | 07-16-2009 |
| 20090182936 | SEMICONDUCTOR MEMORY DEVICE AND WEAR LEVELING METHOD - Disclosed is a semiconductor memory device and wear leveling method thereof. The semiconductor memory device including: a nonvolatile memory having pluralities of memory blocks, at least one of the memory blocks storing erasing counts of the memory blocks; and a memory controller managing wear leveling of the nonvolatile memory. The memory controller adjusts a period of managing the wear leveling with reference to the erasing counts. | 07-16-2009 |
| 20090182937 | SEMICONDUCTOR MEMORY CARD, AND PROGRAM FOR CONTROLLING THE SAME - A semiconductor memory card that has a sufficient storage capacity when an EC application writes data to a storage is provided. A usage area for the EC application in an EEPROM | 07-16-2009 |
| 20090187700 | RETARGETING OF A WRITE OPERATION RETRY IN THE EVENT OF A WRITE OPERATION FAILURE - Methods and systems are herein disclosed for write operation retry using the data stored and retained in an internal buffer within the non-volatile memory device. By using the data stored in the internal buffer, the systems and method of the present invention eliminate the need to include a dedicated retry buffer at the system level. Thereby, reducing the system cost, minimizing space consumption on a board within the system and, in some instance, limiting the latency attributed to a retry that relies on retrying the write based on re-transferring of the data contents to the internal non-volatile memory buffer. | 07-23-2009 |
| 20090187701 | Nand flash memory access with relaxed timing constraints - Timing constraints on data transfers during access of a NAND flash memory can be relaxed by providing a plurality of data paths that couple the NAND flash memory to a buffer that provides external access to the memory. The buffer defines a bit width associated with the external access, and each of the data paths accommodates that bit width. | 07-23-2009 |
| 20090187702 | NONVOLATILE MEMORY - For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series. | 07-23-2009 |
| 20090187703 | MEMORY CARD AND ITS INITIAL SETTING METHOD - In the initial setting of a memory card | 07-23-2009 |
| 20090193176 | Data storage device having a built-in display - A data storage device for an electronic device includes a hard disk for storing a plurality of pieces of data, a nonvolatile memory for storing a plurality of file names corresponding to the pieces of data, a display, and a controller connected electrically to the hard disk, the nonvolatile memory and the display unit, and operable so as to permit viewing of the file names stored in the nonvolatile memory by displaying a viewing result including a viewed one of the file names on the display. | 07-30-2009 |
| 20090193177 | Virtual Processor Based Security For On-Chip Memory, and Applications Thereof - A processor-based method, system and apparatus to comprise a method, system and apparatus to access a memory location in an on-chip memory based on a virtual processing element identification associated with an instruction. The system comprises multiple virtual processing elements, an access list and a comparator coupled to the memory and the access list. In response to an instruction from a virtual processing element to access a memory location in the memory, the comparator compares a first virtual processing identification associated with the instruction to a second virtual processing identification stored in the access list and grants access to the virtual processing element to read from or write to the memory location if the first virtual processing element identification is equal to the second virtual processing element identification. The data in the memory is allocated and de-allocated by software. In one embodiment, the access list is instantiated in hardware and cannot be read from or written to by software. A virtual processing element comprises multiple hardware thread contexts with each thread context being associated with a distinct register file. | 07-30-2009 |
| 20090193178 | SYSTEMS AND METHODS FOR POWER MANAGEMENT IN RELATION TO A WIRELESS STORAGE DEVICE - Various embodiments of the present invention provide systems and methods for reducing power consumption in a device including a memory system. As one example, a system may include a memory system with a hard disk drive and a flash memory. The flash memory maintains a menu file that includes a list of content objects available on the hard disk drive. In addition, the system includes a processor that executes software maintained on the memory system to update the menu file when a previously unavailable content object becomes available on the hard disk drive. Further, in some cases, the processor executes software that is operable to update the menu file when a previously available content object becomes unavailable on the hard disk drive. Additionally, the systems may include instructions executable by the processor to receive a play list, and to copy a first content object identified on the play list from the hard disk drive to the flash memory, and to copy a second content object identified on the play list from the hard disk drive to the flash memory. With the content objects thus moved to the flash memory, they can be uploaded to either the application device that supplied the play list, or to another application device designated as the recipient of the content objects. | 07-30-2009 |
| 20090193179 | Information processing apparatus - A main memory and a hard disk include predetermined serial numbers. A flash memory registers the main memory and hard disk together with their serial numbers. A BIOS reads the serial numbers from the main memory and hard disk. When a read-out serial number is not registered in the flash memory, the BIOS places the information processing apparatus in an unusable state. | 07-30-2009 |
| 20090193180 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD FOR SEMICONDUCTOR MEMORY DEVICE - A memory card capable of connecting to a host device includes a flash memory, a host interface unit which transfers data between a host device and the memory card, and a transfer mode control unit which changes a data transfer mode based on a command from the host device. The transfer mode control unit outputs status data containing an error code to the host device if a transfer mode change command is inputted from the host device, instructing the memory card to change to a transfer mode not supported by the host interface unit of the memory card. | 07-30-2009 |
| 20090193181 | Control Unit, Image Processing Apparatus and Computer-Readable Storage Medium - A memory information storage control method is executed by a control unit which carries out a memory information storage process to generate memory information related to a program being executed by the control unit and to store the memory information. The memory information storage control method includes an interface process to register a storage location of the memory information generated by the memory information storage process, a registering process to register a portable storage device as the storage location of the memory information using the interface process, and an executing process to confirm coupling of the portable storage device to the control unit and to register the storage location of the memory information in the detachably coupled portable storage device by the registering process. | 07-30-2009 |
| 20090193182 | INFORMATION STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, an information storage device includes a non-volatile storage medium, a non-volatile memory configured to store specific data blocks to be read for a host device and write data to be written to the non-volatile storage medium, a buffer configured to temporarily store write data transmitted from the host device, and a controller. The controller is configured to delete synchronized data the same data block as which exists on the non-volatile storage medium among the specific data blocks stored in the non-volatile memory if the free space of the non-volatile memory is smaller than a given data size, and to write the write data stored in the buffer to the non-volatile memory. | 07-30-2009 |
| 20090193183 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 07-30-2009 |
| 20090193184 | Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System - A hybrid solid-state disk (SSD) has multi-level-cell (MLC) or single-level-cell (SLC) flash memory, or both. SLC flash may be emulated by MLC that uses fewer cell states. A NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Most data is block-mapped and stored in MLC flash, but some critical or high-frequency data is page-mapped to reduce block-relocation copying. A hybrid mapping table has a first-level and a second level. Only the first level is used for block-mapped data, but both levels are used for page-mapped data. The first level contains a block-page bit that indicates if the data is block-mapped or page-mapped. A PBA field in the first-level table maps block-mapped data, while a virtual field points to the second-level table where the PBA and page number is stored for page-mapped data. Page-mapped data is identified by a frequency counter or sector count. SRAM space is reduced. | 07-30-2009 |
| 20090198869 | ERASE COUNT RECOVERY - An erase count of a flash memory block which is lost, e.g., due to power failure is updated or replaced by using known erase counts of other blocks of the flash memory. A flash management algorithm assigns a new erase count value instead of the lost one based on either a maximum value, an average value or a value combining the maximum value of the known erase counts and some tolerance value. The known values may be obtained from wear leveling data or from a stored erase history. | 08-06-2009 |
| 20090198870 | Methods and Media for Writing Data to Flash Memory - A method for writing bytes to flash memory is disclosed herein whereby the method comprising includes counting bytes from a data source, the bytes associated with a first value and a second value and comparing a number of bytes associated with the first value with a number of bytes associated with the second value. The method may further include inverting the bytes in the case where the number of bytes associated with the first value is greater than the number of bytes associated with the second value and transferring the bytes not associated with the second value to the flash memory. | 08-06-2009 |
| 20090198871 | EXPANSION SLOTS FOR FLASH MEMORY BASED MEMORY SUBSYSTEM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-06-2009 |
| 20090198872 | HARDWARE BASED WEAR LEVELING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-06-2009 |
| 20090198873 | PARTIAL ALLOCATE PAGING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-06-2009 |
| 20090198874 | MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-06-2009 |
| 20090198875 | DATA WRITING METHOD FOR FLASH MEMORY, AND CONTROLLER AND SYSTEM USING THE SAME - A data writing method for a flash memory is provided. The data writing method includes following steps. First, a block is selected as a substitute block from a spare area of the flash memory, wherein the substitute block is used for substituting a data block in a data area for writing a new data. Next, the new data is directly written into the substitute block starting from a start page, wherein there is valid data in the data block before the address for writing the new data. Thereby, meaningless data moving can be reduced, system performance can be improved, and overlong waiting time for writing the new data can be prevented. | 08-06-2009 |
| 20090198876 | Programmable Command Sequencer - An embedded subsystem IC which provides simple procedures for an external CPU IC to invoke one or more functions provided by modules of the subsystem is disclosed. The embedded subsystem comprises at least one module to perform at least one function, a first memory, and a sequence controller. Each module is controlled by values stored in local registers of the module. The first memory stores at least one predefined sequence of instructions. Each instruction sequence controls a module to perform a function. The sequence controller comprises a second memory to store a vector table and a state machine. In response to receiving a command the CPU, the sequence controller obtains a start address in the first memory of an instruction sequence corresponding with the command. The state machine programs one or more registers of a module that performs the function identified by the command according to the instruction sequence that begins with the start address. | 08-06-2009 |
| 20090198877 | SYSTEM, CONTROLLER, AND METHOD FOR DATA STORAGE - A system, a controller, and a method for data storage are provided. The system includes a first storage unit, a second storage unit, and a controller. The first storage unit comprises a single-layer structure for storing data, and the second storage unit comprises a multi-layer structure for storing data. The controller is coupled to the first storage unit, the second storage unit, and a host and controls the host to set the first storage unit as a master storage device and set the second storage unit as a slave storage device. As a result, the host can recognize the first storage unit and the second storage unit as two independent storage devices for storing data. Thereby, the data storage process can be simplified. | 08-06-2009 |
| 20090198878 | INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD - The information processing system is comprised of: a first nonvolatile storage device in which a plurality of first programs for initiating the information processing system, and duplications of the plural first programs have been stored in blocks different from each other; a second volatile storage device to which the plurality of first programs are transferred; a third nonvolatile storage device into which a second program for executing the plural first programs is stored; and a CPU (Central Processing Unit) for executing the plural first programs. While an instruction has been contained in the second program, the instruction instructs that the plurality of first programs are transferred from the first storage device to the second storage device, contents of the plurality of first programs transferred to the second storage devices are compared with each other; and if the contents of the plurality of first programs are not made coincident with each other, then a normal program is judged from the plurality of first programs based upon a majority decision. The CPU executes the first program judged as the normal program so as to initially initiate the information processing system. | 08-06-2009 |
| 20090198879 | MEMORY SYSTEM AND METHOD OF CONTROLLING THE SAME - A memory system has a memory unit composed of a plurality of memory cells, a memory controller for controlling to read out and write data from and to the memory unit, and a host processor connected to the memory controller for reading out and writing data from and to the memory unit through the memory controller. The memory controller has a refresh controller for rewriting the data stored in the memory unit. The host processor has a determination unit for determining whether or not a refresh operation can be executed to the memory unit and a permission signal transmission unit for transmitting a refresh permission signal when it is determined that the refresh operation can be executed to the memory unit by the determination unit. The refresh controller controls the start of the refresh operation to the memory unit based on the refresh permission signal transmitted from the host processor. | 08-06-2009 |
| 20090198880 | READ STROBE FEEDBACK IN A MEMORY SYSTEM - A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed back to the controller circuit that then uses the fed back signal to read the data from the data/IO bus. | 08-06-2009 |
| 20090204744 | METHODS AND SYSTEMS FOR RECONFIGURING DATA MEMORY OF EMBEDDED CONTROLLER MANAGED FLASH MEMORY DEVICES - Methods and systems for reconfiguring data memory of an embedded controller managed flash memory device are disclosed. According to one method, using a controller managed flash memory device reconfiguration module configured to execute on a general purpose computing platform separate from a computing platform in which an embedded controller managed flash memory device is located, reconfiguration data to be written to a data memory of the embedded controller managed flash memory device is received from a user and I/O commands for writing the reconfiguration data to an external device are generated. Flash device commands corresponding to the I/O commands are generated. The reconfiguration data is communicated to the data memory of the embedded controller managed flash memory device by sending the flash device commands and the reconfiguration data over a flash device interface of the embedded controller managed flash memory device. | 08-13-2009 |
| 20090204745 | Programming device for non-volatile memory and programming method thereof - The invention presents a programming method for a non-volatile memory with a bit signal to be programmed unidirectionally. The method includes the steps of a) providing first data each having a first number of sequential bits of first status in a data page in a non-volatile memory, b) decoding the first number of sequential bits of the first status in the first data into a second number of sequential bits of second status, and c) programming second data in a portion of the data page where the first status has been decoded to the second status. | 08-13-2009 |
| 20090204746 | FLASH MEMORY STORAGE DEVICE FOR ADJUSTING EFFICIENCY IN ACCESSING FLASH MEMORY - A flash memory storage device for boosting efficiency in accessing flash memory is disclosed. The flash memory storage device provides a Multi-level cell (MLC) flash memory for storing data, a single-level cell (SLC) flash memory for storing data, and a control unit for determining whether to store a file into the MLC NAND flash memory or a SLC NAND flash memory based on the file's data characteristics. | 08-13-2009 |
| 20090204747 | Non binary flash array architecture and method of operation - A Flash memory array comprises a plurality of Erase Sectors (Esecs) arranged in a plurality of Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs), and there is a non-binary number of at least one of the Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs). A user address is translated into a physical address using modular arithmetic to determine pointers (ysel, esg, psec) for specifying a given Erase Sector (ESec) within a given Erase Sector Group (ESG); a given Erase Sector Group (ESG) within a given Physical Sector (Psec); and a given Physical Sector (PSec) within the array. | 08-13-2009 |
| 20090204748 | MULTI-CHANNEL FLASH MEMORY SYSTEM AND ACCESS METHOD - Disclosed is a multi-channel flash memory system formed by flash memories having pages divided into sectors and accessed by corresponding channels. An interface device is configured to access the flash memories via the channels by a unit of at least one sector, wherein the interface device divides an address into a plurality of addresses of sector unit and controls the divided addresses so as to be jumped by a given size. | 08-13-2009 |
| 20090204749 | Redimdamt purge for flash storage device - A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command, by writing a pattern of data to the flash storage unit, such that the flash storage units are purged substantially in parallel with each other. | 08-13-2009 |
| 20090204750 | DIRECT LOGICAL BLOCK ADDRESSING FLASH MEMORY MASS STORAGE ARCHITECTURE - A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address. | 08-13-2009 |
| 20090210611 | STORAGE SYSTEM AND DATA WRITE METHOD - The size of a memory management unit in a low-performance non-volatile memory device is maintained, and the size of write data is compared with the size of the memory management unit. If the size of the write data is smaller than that of the memory management unit, the write data is cached by the high-performance non-volatile memory device; or if the size of the write data is not smaller, the write data is written to the low-performance device. Subsequently, a plurality of address values for the write data cached by the high-performance device are referred to; an address segment that is equal to the size of the memory management unit and in which the cached address values are consecutive; and data contained in that address segment is copied from the high-performance device to the low-performance device. | 08-20-2009 |
| 20090210612 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND NONVOLATILE MEMORY SYSTEM - In rewriting processing of logical sectors, data of the transferred logical sectors are temporarily stored in a memory buffer. When the buffer memory has been full filled with data, the data is written into a flash memory. In rewriting processing for the flash memory including a writing unit (page) having a capacity larger than a minimum writing unit (sector) from outside, the number of executions of the evacuation processing can be reduced and the fast data rewriting can be performed. Thus, it is possible to rationalize the evacuation processing for old data caused in the rewriting in units of sectors and to improve the data rewriting speed. | 08-20-2009 |
| 20090210613 | Method for Programming a Controller in a Motor Vehicle - A method and apparatus are provided for programming of a control device of a motor vehicle, in which the control device includes at least one program-controlled processor and at least two individually addressable memory areas, in particular at least two physically separated memory components. In order to accelerate the inputting of memory contents the invention suggests that the processor carries out or brings about the following two steps at least intermittently largely simultaneously. On the one hand, checking whether programs, program parts and/or data already written into the first memory area correspond to the data to be written into the first memory area, and on the other hand, writing a program, a program part and/or data into the second memory area. | 08-20-2009 |
| 20090210614 | Non-Volatile Memories With Versions of File Data Identified By Identical File ID and File Offset Stored in Identical Location Within a Memory Page - In the file storage system, each portion belonging to a data file is identified by its file ID and an offset along the data file, where the offset is a constant for the file and every file data portion is always kept at the same position within a memory page to be read or programmed in parallel. In this way, every time a page containing a file portion is read and copy to another page, the data in it is always page-aligned, and each bit within the file portion can always be manipulated by the same sense amplifier and same set data latches within the same memory column. In a preferred implementation, the page alignment is such that (offset within a page)=(data offset within a file) MOD (page size). Any gaps that may exist in page can be padded with any existing page-aligned valid data. | 08-20-2009 |
| 20090216935 | Memory device for a user profile - A memory device for a user profile of a plurality of electronic devices or functional units in a motor vehicle is used for providing data corresponding to the user profile in the vehicle without a user having to make corresponding settings. As a result of being stored in the memory device, the user profile can be used in different vehicles. | 08-27-2009 |
| 20090216936 | DATA READING METHOD FOR FLASH MEMORY AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data reading method suitable for a flash memory storage system having a flash memory is provided, wherein the flash memory is substantially divided into a plurality of blocks and these blocks are grouped into at least a data area and a spare area. The data reading method includes: respectively determining whether the blocks in the data area are frequently read blocks; allocating a buffer storage area corresponding to the frequently read block and copying data stored in the frequently read block to the buffer storage area; and reading the data from the buffer storage area corresponding to the frequently read block when the data stored in the frequently read block is to be read. As described above, data loss caused by read disturb can be effectively prevented. | 08-27-2009 |
| 20090216937 | MEMORY CONTROLLER, MEMORY SYSTEM, AND ACCESS CONTROL METHOD OF FLASH MEMORY - A memory controller adds dummy data to write data by referring to instruction information about a descriptor transfer of the write data if a size of the write data to be written according to a data-write request information does not match a page size unit, thereby adjusting the size of the write data to the page size unit and then outputs the write data. | 08-27-2009 |
| 20090216938 | Management Of Non-Volatile Memory Systems Having Large Erase Blocks - A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages are written into another block provided for this purpose. The valid original and updated data are then combined at a later time, when doing so does not impact on the performance of the memory. If the data of a large number of pages of a block are to be updated, however, the updated pages are written into an unused erased block and the unchanged pages are also written to the same unused block. By handling the updating of a few pages differently, memory performance is improved when small updates are being made. | 08-27-2009 |
| 20090222612 | Programmable Food Service Systems - A data key, for use with a programmable food service device, comprises: an insertion portion, for insertion into a key aperture in the programmable food service device; a data memory for storing data relating to the operation of the programmable food service device; and a data connection portion for connecting directly with a data port on a computer, to allow the computer to access the data memory. | 09-03-2009 |
| 20090222613 | INFORMATION PROCESSING APPARATUS AND NONVOLATILE SEMICONDUCTOR MEMORY DRIVE - According to one embodiment, an information processing apparatus includes an information processing apparatus main body, and a nonvolatile semiconductor memory drive which is accommodated in the information processing apparatus main body. The nonvolatile semiconductor memory drive includes a nonvolatile semiconductor memory, an address management table which is indicative of a correspondency between logical block addresses and physical addresses of the nonvolatile semiconductor memory, and a control module. The control module refers to the address management table in response to reception of a read request from the information processing apparatus main body, and outputs data of a predetermined value to the information processing apparatus main body in a case where the physical address corresponding to the logical block address, which is included in the read request, is not stored in the address management table. | 09-03-2009 |
| 20090222614 | INFORMATION PROCESSING APPARATUS AND NONVOLATILE SEMICONDUCTOR MEMORY DRIVE - According to one embodiment, an information processing apparatus includes an information processing apparatus main body, and a nonvolatile semiconductor memory drive which is accommodated in the information processing apparatus main body. The nonvolatile semiconductor memory drive includes a nonvolatile semiconductor memory, and a control module configured to control, in accordance with a command from the information processing apparatus main body, a write operation, a read operation and an erase operation of the nonvolatile semiconductor memory, to generate, in every predetermined time period, statistical information relating to the write operation, the read operation and the erase operation of the nonvolatile semiconductor memory, and to store the statistical information, which corresponds to each of a plurality of time periods each having a time length corresponding to the predetermined time period, in a memory area of the nonvolatile semiconductor memory. | 09-03-2009 |
| 20090222615 | Information Processing Apparatus and Nonvolatile Semiconductor Memory Drive - According to one embodiment, a nonvolatile semiconductor memory includes a first memory area which is formed of a fixed area to which a predetermined physical address range is allocated, and which stores management information including an address management table indicative of a correspondency between logical block address and physical addresses of the nonvolatile semiconductor memory, and a second memory area to which a first logical address range is allocated and which stores log data indicative of an operation condition of the nonvolatile semiconductor memory drive. A control module accesses the first memory area by using the physical address belonging to the predetermined physical address range in a case of reading or writing the management information, and accesses the second memory area by using the physical address corresponding to the logical block address belonging to the first logical address range, which is obtained by referring to the address management table. | 09-03-2009 |
| 20090222616 | MEMORY SYSTEM - A controller includes an identification information management table that manages identification information indicating, for each of addresses in second-management unit, whether one or more data in first management unit belonging to the addresses is stored in the second or the third storing area. When the controller executes a process of flushing data from the first storing area to the second storing area or the third storing area, the controller updates the identification information in the identification information management table. The controller executes a process of reading data from the second storing area or the third storing area by referring to the identification information. As a result, the speed of searches conducted in the management table is increased. | 09-03-2009 |
| 20090222617 | MEMORY SYSTEM - A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus. | 09-03-2009 |
| 20090222618 | MEMORY SYSTEM AND BLOCK MERGE METHOD - In one embodiment, the invention provides a memory system including a flash memory device including a plurality of memory blocks implementing a plurality of data blocks, a plurality of log blocks, and a plurality of free blocks. The memory system further includes a flash translation layer maintaining the number of the free blocks to be at least equal to a reference number by converting selected memory blocks among the data and log blocks into free blocks via at least one merge operation during a background period. Additionally, the flash translation layer converts selected ones of the free blocks into data and log blocks, respectively. | 09-03-2009 |
| 20090222619 | Electronic Flash Memory External Storage Method and Device - An electronic flash memory external storage method and device for data processing system includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores data by flash memory and access control circuit with the cooperation of the firmware and the driver with the operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in static state and is driven by software. It is plug-and-play and adapted to data processing system. | 09-03-2009 |
| 20090228633 | Data processor - A data processor ( | 09-10-2009 |
| 20090240868 | MANAGEMENT METHOD, MANAGEMENT APPARATUS, AND CONTROLLER FOR MEMORY DATA ACCESS - A management method, a management apparatus, and a controller for memory data access are provided. The management apparatus is disposed between a host and a device for managing the data transmitted between the host and the device, wherein the management apparatus includes a control unit and a storage unit. When the control unit receives a data writing command from the host, it searches for a set mapped to the data in the storage unit and updates the data in the set. Then, the control unit collects the other parts of the data in the storage unit and the device, integrates all parts of the data, and writes the integrated data into the device. Accordingly, the efficiency in data transmission can be improved, and the number of data writing operations can be reduced so that the lifespan of the device can be prolonged. | 09-24-2009 |
| 20090240869 | Sharing Data Fabric for Coherent-Distributed Caching of Multi-Node Shared-Distributed Flash Memory - A Sharing Data Fabric (SDF) causes flash memory attached to multiple compute nodes to appear to be a single large memory space that is global yet shared by many applications running on the many compute nodes. Flash objects stored in flash memory of a home node are copied to an object cache in DRAM at an action node by SDF threads executing on the nodes. The home node has a flash object map locating flash objects in the home node's flash memory, and a global cache directory that locates copies of the object in other sharing nodes. Application programs use an applications-programming interface (API) into the SDF to transparently get and put objects without regard to the object's location on any of the many compute nodes. SDF threads and tables control coherency of objects in flash and DRAM. | 09-24-2009 |
| 20090240870 | STORAGE APPARATUS WITH A PLURALITY OF NONVOLATILE MEMORY DEVICES - According to one embodiment, a counter counts bits having a predetermined logical value contained in accessed data to be written or read in an access process of accessing any of the physical blocks provided in a selected one of the nonvolatile memory devices. A timer measures an access busy period in the access process. A control module updates an access busy period data item stored in a busy period storage module and concerning the selected one, in accordance with a count value of the counter, whereby the access busy period data item represents the access busy period measured. | 09-24-2009 |
| 20090240871 | MEMORY SYSTEM - A system includes: a first input buffer that functions as an input buffer for a third storing area; and a second input buffer that functions as an input buffer for the third storing area and that separately stores data with a high update frequency for the third storing area. In the system, a plurality of data written in a first storing area or a second storing area are flushed to the first input buffer in units of logical blocks. Also, a plurality of data written in the first input buffer are relocated to the third storing area in units of logical blocks. | 09-24-2009 |
| 20090240872 | MEMORY DEVICE WITH MULTIPLE-ACCURACY READ COMMANDS - A method for data storage includes defining at least first and second read commands for reading storage values from analog memory cells. The first read command reads the storage values at a first accuracy, and the second read command reads the storage values at a second accuracy, which is finer than the first accuracy. A condition is evaluated with respect to a read operation that is to be performed over a given group of the memory cells. One of the first and second read commands is selected responsively to the evaluated condition. The storage values are read from the given group of the memory cells using the selected read command. | 09-24-2009 |
| 20090240873 | Multi-Level Striping and Truncation Channel-Equalization for Flash-Memory System - Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers. | 09-24-2009 |
| 20090248956 | Apparatus for Storing Management Information in a Computer System - An apparatus for providing management storage via a USB port of a computer system is disclosed. The apparatus includes a flash memory, a first and second switches, a first and second inverters, a designated port, and a controller. Coupled to the flash memory, the first and second switches are controlled by a main power of a computer system in a complementary manner. The first and second inverters, which are powered by a standby power of the computer system, are coupled to a respective control input of the first and second switches. The designated port, which is coupled to the flash memory via the first switch, allows data to be read from and written to the flash memory without booting up the computer system. On the other hand, the controller, which is coupled to the flash memory via the second switch, allows data to be read from and written to the flash memory by the computer system only after the computer system has been booted up. | 10-01-2009 |
| 20090248957 | MEMORY RESOURCE MANAGEMENT FOR A FLASH AWARE KERNEL - A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices. | 10-01-2009 |
| 20090248958 | FLASH MEMORY USABILITY ENHANCEMENTS IN MAIN MEMORY APPLICATION - A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices. | 10-01-2009 |
| 20090248959 | FLASH MEMORY AND OPERATING SYSTEM KERNEL - A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices. | 10-01-2009 |
| 20090248960 | METHODS AND SYSTEMS FOR CREATING AND USING VIRTUAL FLASH CARDS - Creating and using virtual flash cards is disclosed. A disclosed method includes receiving an input of sets of flash data into a portable handheld device, associating related sets of the flash data based on manual inputs that define the relationship between the related sets of flash data, presenting one of the related sets of flash data via the handheld device and prompting a selection of a set of flash data that is associated with the presented set of flash data. Feedback is provided that indicates whether or not a selected set of flash data is correct. | 10-01-2009 |
| 20090248961 | MEMORY MANAGEMENT METHOD AND CONTROLLER FOR NON-VOLATILE MEMORY STORAGE DEVICE - A memory management method and a controller for a non-volatile memory storage device are provided. The memor management method and the controller are adapted for establishing a logical-to-physical mapping table of each block in a memory buffer of the controller by merely reading the data stored in a system management area within a start page of each block, so as to promote the management efficiency of the non-volatile memory storage device. In addition, the method and the controller of the present invention integrate all of or a part of the system management areas within the start page for efficiently managing and using the memory capacity of all the system management areas within the start page. | 10-01-2009 |
| 20090248962 | Memory system and wear leveling method thereof - A memory system includes a variable resistance memory configured to input and output data by a first unit and a translation layer for managing the degree of wear of the variable resistance memory by a second unit, different from the first unit. | 10-01-2009 |
| 20090248963 | MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME - A memory system includes a memory system includes a nonvolatile memory including a memory space which is formatted from outside by an additional-write type file system, and a memory controller controlling the nonvolatile memory, the memory controller transmitting a write protect error when the memory controller is instructed to write data in an address which is equal to or smaller than an address of previously written data in an address area of the memory space. | 10-01-2009 |
| 20090248964 | MEMORY SYSTEM AND METHOD FOR CONTROLLING A NONVOLATILE SEMICONDUCTOR MEMORY - A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management tablet the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated. | 10-01-2009 |
| 20090248965 | HYBRID FLASH MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A hybrid flash memory device and a control method of the hybrid flash memory device are provided. The hybrid flash memory device includes a micro controller connected to a host bus for receiving data to be written in the hybrid flash memory device from a host via the host bus; and a memory module coupled to the micro controller. The flash module includes a first type of flash memory and a second type of flash memory. The data are determined to be written in a first log block of the first type of flash memory when the data size is not greater than a predetermined data size. On the contrary, the data are determined to be written in a second log block of the second type of flash memory when the data size is greater than the predetermined data size. | 10-01-2009 |
| 20090248966 | FLASH DRIVE WITH USER UPGRADEABLE CAPACITY VIA REMOVABLE FLASH - An exemplary data storage device includes a fixed storage medium, an expansion socket configured to selectively receive at least one removable memory card, and a controller configured to interface the fixed storage medium and the at least one removable memory card with a host device. An exemplary method includes verifying credentials with verification data stored on the fixed storage medium of the data storage unit, and protecting data on the removable storage medium removably attached to the data storage unit. | 10-01-2009 |
| 20090248967 | PORTABLE ALARM CONFIGURATION/UPDATE TOOL - A stand-alone portable alarm update tool includes a memory interface for receiving a computer readable memory; a serial port for interconnection to a security alarm panel, by way of a complementary port; a processor; and processor readable memory in communication with the processor, storing software adapting the processor to upload and download configuration files from a removable memory received by the memory port, to the alarm panel, by way of the serial port. Conveniently, the tool may be packaged in a hand-held casing, and which may also house a battery. In this way, the tool may be readily transported by an installer, without being unnecessary heavy or bulky. | 10-01-2009 |
| 20090254696 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATION FOR SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor IC has a nonvolatile memory including twin cells, a selector, and a sense circuit. When complementary data are written into a pair of nonvolatile memory cells of each twin cell, the pair of nonvolatile memory cells is set to be in a written state where one cell of the pair is set to one of low and high threshold voltages, and the other is set to the other threshold voltage. When non-complementary data are written into a pair of nonvolatile memory cells, for example, the memory cells both take the low threshold voltage and are made blank. The selector includes switching elements. During the blank-check action, switching elements of the selector are controlled to ON state. Then, the first total current of the twin cells forced to flow into the first input terminal of the sense circuit commonly is compared with the reference signal on the second input terminal, whereby whether the twin cells have been written or blank can be detected at a high speed. As to a semiconductor nonvolatile memory such that complementary data are written into memory cells in memory cell pairs, the blank-check time can be shortened. | 10-08-2009 |
| 20090259797 | METHOD, APPARATUS AND COMPUTER READABLE MEDIUM FOR STORING DATA ON A FLASH DEVICE USING MULTIPLE WRITING MODES - Methods, apparatus and computer readable medium for writing data into a flash memory device are disclosed. In some embodiments, the data is written in a writing mode selected in accordance with an extent to which the flash memory storage device or a flash die thereof is full of previously-stored data. The presently disclosed techniques may be implemented on the “device-side” (for example, by a device controller of the flash device) and/or on the “host-side.” In some embodiments, the selected writing mode is a bits-per-cell density mode. In some embodiments, the selected writing mode is a “slower” or “faster” writing mode. The presently disclosed techniques relate to SBC as well as MBC devices. | 10-15-2009 |
| 20090259798 | Method And System For Accessing A Storage System With Multiple File Systems - In order to write data to a storage system accessible with a first and second file system, a manager receives a data write request associated with a file. The manager determines if a function supported by the second file system is needed to complete the write request. If so, the file is opened and extended with the first file system. The file is then opened and written to by the second file system. The file is truncated by the first file system, and closed by both file systems. If the second file system function is not needed, the file is opened, written, and closed by the first file system. In order to read data from a storage system using a function supported by the second file system, the second file system's cached storage system index is updated, then the file is opened, read, and closed by the second file system. | 10-15-2009 |
| 20090259799 | METHOD AND APPARATUS FOR A VOLUME MANAGEMENT SYSTEM IN A NON-VOLATILE MEMORY DEVICE - Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks for storing different types of data. The memory system is partitioned to include a second addressable range of memory blocks capable of storing data indicating attributes of the first addressable range of memory blocks. The second addressable range of memory blocks may also be periodically updated such that the capacities of the first addressable range of memory blocks may be dynamically adjusted depending on application needs and changes to the non-volatile memory device over time. In some embodiments, one partition of a memory device may be configured for high reliability data storage while a second partition is configured for normal reliability storage. | 10-15-2009 |
| 20090259800 | FLASH MANAGEMENT USING SEQUENTIAL TECHNIQUES - Disclosed are techniques for flash memory management, including receiving data from a host, writing the data to a flash memory device in the order it was received from the host, and providing at least one data structure configured to locate the data written to the flash memory device. | 10-15-2009 |
| 20090259801 | CIRCULAR WEAR LEVELING - A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory. | 10-15-2009 |
| 20090259802 | SMART DEVICE RECORDATION - Valuable information can be retained upon a storage device, such as a flash memory unit. Due to the portable nature of the memory, there can be increased likelihood of theft, less back up of important files not a reliable medium, legal physical transfer of the device between parties, and the like. When an operation is requested to take place related to the device, a check can take place if the operation should be allowed based upon device metadata, such as physical location of the device, device history, and so forth. A determination can be made on if the operation should automatically occur based upon a result of the check. If it is determination that the operation should not automatically occur, then the operation can be denied or a request can be made to an owner of the device on if the operation should be allowed to occur. | 10-15-2009 |
| 20090259803 | SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR ENCODING DATA TO BE WRITTEN TO A NONVOLATILE MEMORY BASED ON WEAR-LEVELING INFORMATION - A nonvolatile memory system is operated by providing data to be written to a nonvolatile memory, logically combining the data to be written to the nonvolatile memory with a random pattern to generate encoded data; and programming the encoded data in the nonvolatile memory. | 10-15-2009 |
| 20090259804 | CALIBRATED TRANSFER RATE - Methods, systems, and devices are described for the implementation of a novel architecture to support a calibrated rate for the transfer of circuit configuration data. Sets of configuration data from a memory may be transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Upon system power-up, there may be a default speed for the transfer of the configuration data. Techniques are described to first transfer calibration data upon power-up; the transferred calibration data may then be used to set an accelerated speed for a remaining portion of the transfer. | 10-15-2009 |
| 20090259805 | FLASH MANAGEMENT USING LOGICAL PAGE SIZE - Disclosed are techniques for flash memory management, including tracking payload data via one or more data structures configured to define the size of logical pages in a flash memory. In various embodiments, the logical page size may be larger than, equal to, or smaller than a physical page size of a flash memory chip. | 10-15-2009 |
| 20090259806 | FLASH MANAGEMENT USING BAD PAGE TRACKING AND HIGH DEFECT FLASH MEMORY - Disclosed are techniques for flash memory management, including utilizing defect information corresponding to a granularity smaller than a physical erase block size of a flash memory chip. | 10-15-2009 |
| 20090259807 | FLASH MEMORY ARCHITECTURE WITH SEPARATE STORAGE OF OVERHEAD AND USER DATA - A memory device has a plurality of dedicated data blocks for storing only user data and a plurality of dedicated overhead blocks for storing only overhead data. Current overhead segments of a dedicated overhead block can be consolidated and moved to a new dedicated overhead block. | 10-15-2009 |
| 20090259808 | Methods of Sanitizing a Flash-Based Data Storage Device - A data storage device includes one or more non-volatile, blockwise erasable data storage media and a mechanism for sanitizing the media in response to a single external stimulus or in response to a predetermined physical or logical condition. Optionally, only part of the media is sanitized, at a granularity finer than the blocks of the medium. Setting a flag in an auxiliary nonvolatile memory enables an interrupted sanitize to be detected and restarted. Optionally, a “death certificate” verifying the sanitizing is issued. Preferably, the media are configured in a manner that allows atomic operations of the sanitizing to be effected in parallel. | 10-15-2009 |
| 20090265505 | DATA WRITING METHOD, AND FLASH STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data writing method, and a flash storage system and a controller using the same are provided. The method includes grouping the physical blocks of a flash memory into the physical blocks of a data area, a spare area and a special area. The method also includes writing the update data into the corresponding physical block of the special area when the update data is the single accessing unit. The method may include moving a part of valid data in a physical block mapping a logical block where the update data is belonged into a physical block of the spare area during each data writing command. Accordingly, it is possible to reduce the response time for each data writing command, thereby preventing a time-out problem caused by a flash memory having a large erasing unit configured at the flash storage system. | 10-22-2009 |
| 20090265506 | STORAGE DEVICE - A computing system and a storage device are provided. A computing system includes a first storage media, a second storage media having an input/output speed slower than that of the first storage media, and a hybrid file system management unit to manage a first physical file system and second physical file system, and provide a virtual file system manager with a virtual file system converted from the first physical file system and second physical file system. The first physical file system controls the first storage media and the second physical file system controls the second storage media. | 10-22-2009 |
| 20090265507 | SYSTEM TO REDUCE DRIVE OVERHEAD USING A MIRRORED CACHE VOLUME IN A STORAGE ARRAY - A system comprising a host, a solid state device, and an abstract layer. The host may be configured to generate a plurality of input/output (IO) requests. The solid state device may comprise a write cache region and a read cache region. The read cache region may be a mirror of the write cache region. The abstract layer may be configured to (i) receive the plurality of IO requests, (ii) process the IO requests, and (iii) map the plurality of IO requests to the write cache region and the read cache region. | 10-22-2009 |
| 20090265508 | Scheduling of Housekeeping Operations in Flash Memory Systems - A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming. | 10-22-2009 |
| 20090271559 | Method for Storing Individual Data Items of a Low-Voltage Switch - A method is disclosed for storing individual data items of a low-voltage switch provided with a microcontroller triggering unit. According to an embodiment, the ROM cells of a dead microcontroller ROM which are not occupied by a program code memory cells are occupied by the individual data items of the low-voltage switch. | 10-29-2009 |
| 20090271560 | Dynamic Fix-Up of Global Variables During System BIOS Execution - A method is described for preserving the flexibility associated with relative memory addressing in programs designed to be stored in read-only memory. | 10-29-2009 |
| 20090271561 | MEDIUM FOR INTEGRATING STORING CAPACITIES OF MULTIPLE STORAGE DEVICES - A medium for integrating storing capacities of multiple storage devices has multiple memory card connectors, a memory card interface management module, a control module and a communication interface. Each memory card connector is used to connect to a memory card. The memory card interface management module is connected to the memory card connectors. The control module is connected to the memory card interface management module and stores a mount and unmount management process. The control module executes the mount and unmount management process to integrate storing capacities of all connected memory cards into a single storing capacity and unintegrate the storing capacity of the impendingly removed memory cards from the storing capacity of all connected memory cards. The communication interface is used to connect to a computer. Therefore, it is convenient for users to change the storing capacity of the medium based on different requirements. | 10-29-2009 |
| 20090271562 | Method and system for storage address re-mapping for a multi-bank memory device - A method and system for storage address re-mapping in a multi-bank memory is disclosed. The method includes allocating logical addresses in blocks of clusters and re-mapping logical addresses into storage address space, where short runs of host data dispersed in logical address space are mapped in a contiguous manner into megablocks in storage address space. Independently in each bank, valid data is flushed within each respective bank from blocks having both valid and obsolete data to make new blocks available for receiving data in each bank of the multi-bank memory when an available number of new blocks falls below a desired threshold within a particular bank. | 10-29-2009 |
| 20090271563 | FLASH MEMORY TRANSACTIONING - Providing for improved transactioning for Flash memory is described herein. By way of example, transactioning operations associated with abstract data structures can be bundled into a common layer of a Flash management protocol stack, to reduce transaction redundancy at abstracted layers. In some aspects, the common layer can be a block level layer providing relatively direct access to low level Flash. Thus, a file system or database application, operating at a higher, abstracted layer of the Flash management protocol stack, can offload transactioning operations to a block level process that has access to underlying Flash memory. As a result, increased efficiency, throughput, and added flexibility can be achieved for storage system transactioning. | 10-29-2009 |
| 20090271564 | STORAGE SYSTEM - A storage system has a storage controller and a flash memory module that is coupled to the storage controller. The storage controller manages the status of a storage area in a flash memory chip of the flash memory module. When a portion of the storage area in the flash memory chip becomes unwritable, the storage controller carries out control so as to use a free storage area as an alternate area for the unwritable storage area, and to store data that has been stored in the unwritable storage area, in the alternate area. | 10-29-2009 |
| 20090271565 | METHOD OF PROCESSING HARD DISK DRIVE - A method of processing a hard disk drive. The method can include downloading at least two process codes and a main code to a first storage area of the hard disk drive, sequentially performing processes based on the at least two process codes, and installing the main code in a second storage area. | 10-29-2009 |
| 20090271566 | METHOD FOR CONFIGURING OR RE-CONFIGURING PROGRAMMABLE DEVICE AND APPARATUS ASSOCIATED THEREWITH - A method of configuring a programmable device may include connecting an electronic storage medium to a configuration system with user-friendly input/output capabilities to establish configuration information for the programmable device, which may have limited input/output capabilities. The configuration information may be applied to the programmable device when the electronic storage medium is connected to the programmable device. Additional programmable devices may be configured when connected to the electronic storage medium. Further embodiments of the method and apparatus to provide the programmable device configuration service are also provided. | 10-29-2009 |
| 20090271567 | METHODS FOR MANAGING BLOCKS IN FLASH MEMORIES - A method for managing blocks in a flash memory is provided, which includes dynamic and static block managing methods. In the dynamic block managing method, a blank block is selected as a swap block for write operation. During each write operation, new data and/or original data in an object block to be operated are written into the swap block, and the object block is erased. Then, a logical address of the object block is changed to be a logical address of the swap block, so that the object block served as the swap block for a next write operation. In the static block managing method, a variable seed parameter is set. Different values of the seed parameter are each associated with a logical address of a respective flash memory block. When the value of the seed parameter varies, data in the flash memory block and the swap block associated to the value of the seed parameter are exchanged, so that the flash memory block associated to the value of the seed parameter becomes the swap block for the next write operation. | 10-29-2009 |
| 20090271568 | FLASH MEMORY SYSTEM AND DATA WRITING METHOD THEREOF - Provided are a flash memory system and a data reading method thereof, the method including serially reading groups of data and parity codes corresponding to each of the respective groups from a page buffer; calculating the parity for each serially read group; checking for errors in each serially read group by comparing each calculated parity with a corresponding serially read parity code, respectively; and providing an output signal indicative of any comparative parity errors detected, wherein the reading of each group of data is followed by the reading of the parity code for the group, and the checking for errors in each group of data is done during the serial reading operation. | 10-29-2009 |
| 20090276561 | SPI NAND PROTECTED MODE ENTRY METHODOLOGY - One or more techniques are provided for restricting access to protected modes of operation in a memory device. In one embodiment, detection circuitry is provided and configured to receive and evaluate a protected mode entry sequence for accessing a protected mode of operation. The detection circuitry may be further configured to temporarily enable an output pin on a serial interface between the memory device and a master device to receive inputs, such that a entry sequence may be entered on both the input and output pins. In another embodiment, the detection circuitry may be enabled only if a security code is first provided, thus requiring both the correct security code and entry sequence before protected mode access is allowed. The memory device may also include a parallel NAND memory array, and detection logic may be further configured to enable a serial-to-parallel NAND translator once protected mode access is allowed. | 11-05-2009 |
| 20090276562 | Flash cache flushing method and system - A flash memory system that uses repeated writing of the data to achieve stable storage, is adapted for efficient cache flushing operations by utilizing a part of the non-volatile flash memory array as a designated buffer for the data, in which data integrity is retained until all repeat writing thereof is complete. Repeated writing is carried out from the designated buffer directly to the final storage locations in the flash memory array, for example using simple internal copy back operations. | 11-05-2009 |
| 20090282184 | COMPENSATING NON-VOLATILE STORAGE USING DIFFERENT PASS VOLTAGES DURING PROGRAM-VERIFY AND READ - Optimized verify and read pass voltages are obtained to improve read accuracy in a non-volatile storage device. The optimized voltages account for changes in unselected storage element resistance when the storage elements become programmed. This change in resistance is referred to as a front pattern effect. In one approach, the verify pass voltage is higher than the read pass voltage, and a common verify voltage is applied on the source and drain sides of a selected word line. In other approaches, different verify pass voltages are applied on the source and drain sides of the selected word line. An optimization process can include determining a metric for different sets of verify and read pass voltages. The metric can indicate threshold voltage width, read errors or a decoding time or number of iterations of an ECC decoding engine. | 11-12-2009 |
| 20090282185 | FLASH MEMORY DEVICE AND A METHOD FOR USING THE SAME - A flash memory device is presented. The device includes a flash memory, which has a temporary storage portion, a main storage portion and a controller. The temporary storage portion is provided for buffering data and addresses. The buffered addresses are indicative of the destination of the buffered data in the main storage portion. The controller is configured for selectively accessing the main storage portion or the temporary storage portion or a combination thereof for receiving and/or outputting the data from the memory. The controller is further configured for enabling communication of data between the two portions. Because non-volatile flash memory is used for the temporary storage, no other memory components are needed and, in case of an unexpected power failure, the data in the temporary area is not lost. | 11-12-2009 |
| 20090282186 | DYNAMIC AND ADAPTIVE OPTIMIZATION OF READ COMPARE LEVELS BASED ON MEMORY CELL THRESHOLD VOLTAGE DISTRIBUTION - A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage distribution data using a weighting function to create an interim set of data, determining a derivative of the interim set of data, and identifying and storing negative to positive zero crossings of the derivative as read compare points. | 11-12-2009 |
| 20090282187 | FLASH MEMORY DEVICE CAPABLE OF PREVENTING READ DISTURBANCE - A storage has a first cache area temporarily storing one page data read from a flash memory, and a second cache area to which data of the first cache area is transferred. A controller stores data of the first cache area in the second cache area, and reads and outputs the data stored in the second cache area when data having the same address as data read from the first cache area is read. | 11-12-2009 |
| 20090282188 | MEMORY DEVICE AND CONTROL METHOD - A memory device includes a first controller and a second controller. The first controller receives a first command from a host and stores the first command in a first command queue, and transmits the first command to the second controller relating to the first command stored in the first command queue. The second controller transmits the first command stored in the second command queue to a flash memory. | 11-12-2009 |
| 20090287873 | SEMICONDUCTOR INTEGRATED CIRCUIT, SYSTEM DEVICE INCLUDING SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT CONTROL METHOD - A disclosed semiconductor integrated circuit interfaces an external circuit and a host for controlling the external circuit and obtains data used to interface the external circuit and the host from a rewritable external memory. The disclosed semiconductor integrated circuit includes external terminals to which an external signal line group is connected, the external signal line group including signal lines connecting the external circuit and the external memory in parallel; an external terminal interface circuit configured to interface the semiconductor integrated circuit and the external circuit or the external memory connected via the external signal line group; and a control circuit configured to activate or deactivate the external circuit and the external memory. The control circuit is configured to activate either the external circuit or the external memory that is to be accessed via the external terminal interface circuit. | 11-19-2009 |
| 20090287874 | Flash Recovery Employing Transaction Log - A transaction log for flash recovery includes a chained sequence of blocks specifying the operations that have been performed, such as a write to a sector or an erase to a block. Checkpoints are performed writing the entire flash state to flash. Once a checkpoint is performed, all of the log entries prior to the checkpoint are deleted and the log processing on recovery begins with the latest checkpoint. If the system is able to safely shutdown, then a checkpoint may be performed before the driver unloads, and on initialization, the entire persisted flash state may be loaded into the flash memory with a minimal amount of flash scanning. If a power failure occurs during system operation, then on the next boot-up, only the sectors or blocks specified in the log entries after the latest checkpoint have to be scanned, rather than all the sectors on the part. | 11-19-2009 |
| 20090287875 | MEMORY MODULE AND METHOD FOR PERFORMING WEAR-LEVELING OF MEMORY MODULE - The invention comprises a memory module capable of wear-leveling. In one embodiment, the memory module comprises a flash memory and a controller. The flash memory comprises a plurality of management units, wherein each of the management units comprises a plurality of blocks. The controller receives new data with a logical address managed by a first management unit selected from the management units, pops a first spare block from a spare area of the first management unit, determines whether an erase count of the first spare block is greater than a first threshold value, searches a second management unit selected from the management units for a replacing block with an erase count lower than a second threshold value when the erase count of the first spare block is greater than the first threshold value, and directs the first management unit and the second management unit to exchange the first spare block with the replacing block. | 11-19-2009 |
| 20090287876 | METHOD, APPARATUS AND CONTROLLER FOR MANAGING MEMORIES - A method, an apparatus and a controller for managing memories are provided. In the present invention, a data accessing format of each of the memories is adjusted such that the accessing units for each data accessing operation are unified. A mapping table is then established for recording the adjusted data accessing format. When a data accessing command is received from a host, the mapping table is inquired so as to execute the data accessing command. Accordingly, incompatibility of hardware structures can be resolved, and management of different types of flash memory can be achieved. | 11-19-2009 |
| 20090287877 | MULTI NON-VOLATILE MEMORY CHIP PACKAGED STORAGE SYSTEM AND CONTROLLER AND ACCESS METHOD THEREOF - A multi non-volatile memory chip packaged storage system having a memory module, a controller, a first and a second control buses and a first and a second I/O buses is provided. The memory module at least includes a first and a second non-volatile memory chips which are both enabled by receiving a chip enabled signal via a chip enabled pin, wherein the memory module and the controller are stacked and packaged as a single chip. After the first and the second non-volatile memory chips are enabled by the chip enable signal via the chip enabled pin, the controller may active the first and second control buses and the first and second I/O buses to access the first and the second non-volatile memory chips, or only active the first control and I/O buses or the second control and I/O buses to access the corresponding first or second non-volatile memory chip. | 11-19-2009 |
| 20090287878 | STORAGE APPARATUS USING FLASH MEMORY - For a storage apparatus in which flash memory disks and hard disks coexist, high-density mounting of flash memory modules is achieved. A storage apparatus in accordance with the present invention includes flash memories and a storage controller. A second storage apparatus including magnetic disks is connected to the storage apparatus. For creation of a logical volume, the storage controller can form a storage area using a flash memory or a magnetic disk. When an input/output request is issued from a host computer, if a storage area is formed with a flash memory, the storage controller directly accesses the flash memory to handle the input/output request. When the storage apparatus defines a storage area formed with a flash memory, the storage apparatus defines the storage area by adding up the capacity of a storage area to be provided for the host computer and a substitute area capacity determined in consideration of restrictions imposed on the number of times of deletion of the flash memory. | 11-19-2009 |
| 20090287879 | NAND FLASH MEMORY DEVICE AND METHOD OF MAKING SAME - An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device. | 11-19-2009 |
| 20090292860 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE - The present invention relates to a method of programming a non-volatile memory device. A method of programming an non-volatile memory device in accordance with an aspect of the present invention includes inputting n page of data, storing a single page of data in each of page buffer units of a plurality of memory cell units, programming a first page of data stored in a page buffer unit of a first memory cell unit, transferring a second page of data, stored in a page buffer unit of a second memory cell unit, to the page buffer unit of the first memory cell unit, and programming the transferred second page of data into the first memory cell unit. | 11-26-2009 |
| 20090292861 | USE OF RDMA TO ACCESS NON-VOLATILE SOLID-STATE MEMORY IN A NETWORK STORAGE SYSTEM - A network storage controller uses a non-volatile solid-state memory (NVSSM) subsystem which includes raw flash memory as stable storage for data, and uses remote direct memory access (RDMA) to access the NVSSM subsystem, including to access the flash memory. Storage of data in the NVSSM subsystem is controlled by an external storage operating system in the storage controller. The storage operating system uses scatter-gather lists to specify the RDMA read and write operations. Multiple client-initiated reads or writes can be combined in the storage controller into a single RDMA read or write, respectively, which can then be decomposed and executed as multiple reads or writes, respectively, in the NVSSM subsystem. Memory accesses generated by a single RDMA read or write may be directed to different memory devices in the NVSSM subsystem, which may include different forms of non-volatile solid-state memory. | 11-26-2009 |
| 20090292862 | FLASH MEMORY MODULE AND STORAGE SYSTEM - A storage controller manages address conversion information denoting the correspondence relationship between a logical address and a physical address of storage area (for example, a physical block) inside a flash memory. The storage controller uses the above-mentioned address conversion information to specify a physical address corresponding to a logical address specified by an I/O request from a higher-level device, and sends an I/O command including I/O-destination information based on the specified physical address to a memory controller inside a flash memory module. The memory controller carries out the I/O with respect to a storage area inside a flash memory specified from the I/O-destination information of the I/O command from the storage controller. | 11-26-2009 |
| 20090292863 | MEMORY SYSTEM WITH A SEMICONDUCTOR MEMORY DEVICE - A memory system with a semiconductor memory device, in which a physical block of n-bits serves as an erase unit, wherein the address management of the memory device is performed by a logical block with m-bits, “m” being larger than “n” and expressed by a power of two, and wherein a n-bit portion continued from the head address in the logical block is defined as a first management unit corresponding to one physical block of the memory device, and a number of the remaining fraction portions each defined as a second management unit are gathered so as to correspond to one physical block of the memory device. | 11-26-2009 |
| 20090292864 | IDENTIFICATION INFORMATION MANAGEMENT SYSTEM AND METHOD FOR MICROCOMPUTER - An exemplary object of the present invention is to facilitate the management of identification information in a microcomputer having a flash memory. A system | 11-26-2009 |
| 20090292865 | SYSTEMS AND METHODS FOR SCHEDULING A MEMORY COMMAND FOR EXECUTION BASED ON A HISTORY OF PREVIOUSLY EXECUTED MEMORY COMMANDS - A memory system is operated by maintaining a queue of memory commands to be executed, maintaining a list of previously executed memory commands, comparing local information associated with the commands to be executed with local information associated with the list of previously executed commands, and selecting one of the commands for execution from the queue of memory commands to be executed based on a result of the comparison. | 11-26-2009 |
| 20090300269 | HYBRID MEMORY MANAGEMENT - Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage. | 12-03-2009 |
| 20090300270 | Dynamoelectric machine assemblies having memory for use by external devices - A method is provided for storing data from an external device in a dynamoelectric machine assembly (i.e., an electric motor or generator). The dynamoelectric machine assembly includes a memory device and a processor for controlling operation of the dynamoelectric machine assembly in response to commands from an external device. The method includes receiving a command from the external device to store data in the memory device of the dynamoelectric machine assembly, and storing the data in the memory device in response to the command. Dynamoelectric machine assemblies, external devices and systems suitable for use in the provided method are also disclosed. | 12-03-2009 |
| 20090300271 | STORAGE SYSTEM HAVING MULTIPLE NON-VOLATILE MEMORIES, AND CONTROLLER AND ACCESS METHOD THEREOF - A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enabled by receiving a chip enable signal from the controller via a chip enable pin. When the controller performs a multichannel access, the controller provides an access instruction to the first and second non-volatile memory chip, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. When the controller performs a single channel access, the controller provides the access signal to one of the first and second non-volatile memory chips, and provides a non-access instruction to the other one, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. | 12-03-2009 |
| 20090300272 | Method for increasing reliability of data accessing for a multi-level cell type non-volatile memory - A method for increasing reliability of data accessing for a multi-level cell type non-volatile memory, wherein a plurality of data storage blocks are taken for data accessing of a computer system in accordance with the structure of storage of the multi-level cell type non-volatile memory; and a page jumper is provided to select at least a set of data storage pages in corresponding to a physical page of same storage cell, by jump connecting of the page jumper which jumps over another data storage page in corresponding to the physical page of the same storage cell, then the data storage page selected is accessed for at least a data storage block. the frequency of erasing of flash memory blocks can thus be reduced to elongate the life of use of the multi-level cell type non-volatile memory, this can assure integrity of the data in accessing during abnormal system power breaking. | 12-03-2009 |
| 20090300273 | Flash memory apparatus with automatic interface mode switching - A flash memory controller with automatic interface mode switching is applied to a flash memory apparatus with a plurality of flash memories and the controller contains: a memory interface, a microprocessor, and an interface mode controller. The microprocessor recognizes the supported interface mode of every flash memory connected with the memory interface in an initial setting process, and individually sets the corresponding interface mode setting value into the interface mode controller. Thus, when the flash memory apparatus is operating in a normal operation state, the interface mode controller can output the corresponding interface mode setting value according to the present enabled flash memory, and the memory interface can adjust and switch the interface mode according to the interface mode setting value outputted by the interface mode controller. Thereby, the present invention can achieve the purpose whereby the flash memory apparatus can speed up accessing and increase efficiency. | 12-03-2009 |
| 20090300274 | SSD WITH DISTRIBUTED PROCESSORS - In one embodiment, a system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus. | 12-03-2009 |
| 20090300275 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - A semiconductor device includes: a first sector ( | 12-03-2009 |
| 20090300276 | ENHANCED DATA ACCESS IN A STORAGE DEVICE - A flash storage device having improved write performance is provided. The device includes a storage block having a plurality of physical pages and a controller configured to allocate subsets of the plurality of physical pages to a plurality of logical addresses, respectively, and to write data to the plurality of physical pages. Each of the subsets of physical pages includes more than one physical page. Upon receiving a first write request for one of the logical addresses, data from the first write request is written to a first physical page of the physical pages allocated to the logical address. Upon receiving a second write request for one of the logical address, the data from the second write request is written to a second physical page allocated to the logical address and the first physical page allocated to the logical address is invalidated. | 12-03-2009 |
| 20090307411 | METHOD AND APPARATUS FOR SECURING DIGITAL INFORMATION ON AN INTEGRATED CIRCUIT DURING TEST OPERATING MODES - The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode. | 12-10-2009 |
| 20090307412 | MEMORY MANAGEMENT METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME - A memory management method for a non-volatile memory and a controller using the same are provided. The non-volatile memory is substantially divided into a plurality of blocks. First, non-erasing information of a plurality of memory units comprising at least one block is recoded and used as a reference to establish an evaluation value. Then, whether to move data of at least one block on the memory units to another memory unit according to the evaluation value is determined. Accordingly, problems of read disturb and data retention due to excessive reading times can be resolved. | 12-10-2009 |
| 20090307413 | DATA WRITING METHOD FOR FLASH MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data writing method for a multi-level cell (MLC) NAND flash memory and a storage system and a controller using the same are provided. The flash memory includes a plurality of blocks. Each of the blocks includes a plurality of page addresses. The page addresses are categorized into a plurality of upper page addresses and a plurality of lower page addresses. The writing speed of the lower page addresses is faster than that of the upper page addresses. The data writing method includes receiving a writing command and data and writing the data into a page address. The page address is skipped when it is an upper page address and a corresponding lower page address stores a valid data written by a previous writing command. Thereby, the accuracy of the data written by the previous writing command is ensured when a programming error occurs to the flash memory. | 12-10-2009 |
| 20090307414 | MEMORY SYSTEM, MEMORY SYSTEM CONTROL METHOD, AND DRIVE RECORDER APPARATUS - A memory system includes a NAND-type flash memory which includes a plurality of memory cells and can store one-bit, two-bit or more data in one memory cell, and a duplicating-converting circuit configured to duplicate input data by assigning the input data to a predetermined threshold level and another threshold level different from the predetermined threshold level. Moreover, the memory system includes a controller configured to control to store the data duplicated by the duplicating-converting circuit, in the NAND-type flash memory. | 12-10-2009 |
| 20090307415 | Memory device having multi-layer structure and driving method thereof - A memory device having a multi-layer structure, the memory device includes a first semiconductor layer including at least one memory cell array. The memory cell array includes a plurality of memory cells. A second semiconductor layer is on the first semiconductor layer. The second semiconductor layer includes a bit line and a page buffer connected to the bit line corresponding to the memory cell array. The memory device also includes a contact between the first semiconductor substrate and the second semiconductor substrate to connect the page buffer with the memory cell array. | 12-10-2009 |
| 20090307416 | SSD WITH A CONTROLLER ACCELERATOR - In one embodiment, a data storage system includes a solid state data storage device and a memory controller in signal communication with the solid state data storage device. The memory controller includes a processor, a local memory, and an accelerator coupled between the processor and the local memory. The accelerator includes logic circuitry configured to perform data management for the local memory. | 12-10-2009 |
| 20090313417 | Methods for Data Management in a Flash Memory Medium - A method for data management in a flash memory medium is provided in the present invention, The method comprises the following steps: dividing a plurality of blocks of the flash memory medium into two or more sections; generating a section-address-mapping table by scanning logic addresses in the blocks in each section; storing the section-address-mapping table into a backup block in each section; and performing an operation of writing/reading by reading the section-address-mapping table, storing the section-address-mapping table to a RAM, and performing a conversion between a physical address and a logic address based on the section-address-mapping table stored in the RAM. Since the section-address-mapping tables are stored in the backup block in respective sections, when an operation of writing/reading is performed and it is necessary to switch to a section-address-mapping table for a next section, data stored in the next section can be read out based on the section-address-mapping table stored in the backup block in the next section, without needing to scan each block in the next section for generating a new section-address-mapping table dynamically. Therefore, the method of the present invention can save the time for operation and thus achieve effective management on data in the flash memory medium. | 12-17-2009 |
| 20090313418 | Using asymmetric memory - In one illustrative embodiment, a computer implemented method using asymmetric memory management is provided. The computer implemented method receives a request, containing a search key, to access an array of records in the asymmetric memory, wherein the array has a sorted prefix portion and an unsorted append portion, the append portion alternatively comprising a linked-list, and responsive to a determination that the request is an insert request, inserts the record in the request in arrival order in the unsorted append portion to form a newly inserted record. Responsive to a determination that the newly inserted record completes the group of records, stores an index, in sorted order, for the group of records. | 12-17-2009 |
| 20090313419 | METHOD OF STORING DATA ON A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure. | 12-17-2009 |
| 20090313420 | Method for saving an address map in a memory device - A method for saving an address map in a memory device is provided. In one embodiment, a logical-to-physical address map is stored in a volatile memory of a memory device. The memory device receives a command from a host device to perform an operation that is associated with a power-down sequence of the host device, such as a flush cache command. In response to receiving the command, the memory device performs the operation and saves the logical-to-physical address map in a non-volatile memory of the memory device. In this way, the command triggers both the performance of the operation and the saving of the logical-to-physical address map in the non-volatile memory of the memory device. | 12-17-2009 |
| 20090313421 | Data Update Method and Electronic Device Using Such Data Update Method - A data update method is provided for updating the data stored in a memory unit of an electronic device. The data update method includes the following steps. In response to a data update request, a data content indexing table is read from the memory unit. According to the data content indexing table, position information associated with the portion of the data to be updated is computed. According to the position information, the portion of the data to be updated is updated. | 12-17-2009 |
| 20090313422 | FLASH MEMORY CONTROL APPARATUS HAVING SEQUENTIAL WRITING PROCEDURE AND METHOD THEREOF - A flash memory control apparatus having a sequential writing procedure and method thereof are described. The flash memory control apparatus includes primary controller, a command module, an address module, a data buffer, a status unit, a counting device and a secondary controller. The primary controller generates a predetermined value which represents the amount of a plurality of pages in the flash memory. The command module stores a writing command during the writing procedure. The address module stores a current address for addressing a current page of the pages based on the current address and the writing command via a control bus. The data buffer stores the data for allowing the command module to write the data to the current page based on the current address via the control bus while the writing command is executed on the flash memory. The status unit determines that the flash memory is either ready or busy in writing the data to the current page of the flash memory. If the command module correctly writes the data to the current page according to the determination result, the address module generates at least one next address. The address module addresses at least one next page of the pages based on the at least one next address and the writing command. The command module sequentially writes the data to the at least one next page during the writing procedure until the pages are written successively. | 12-17-2009 |
| 20090313423 | MULTI-BIT FLASH MEMORY DEVICE AND METHOD OF ANALYZING FLAG CELLS OF THE SAME - Disclosed is a multi-bit flash memory device which includes a memory cell array and a control circuit. The memory cell array has multiple memory cells and multiple flag cells. The control circuit determines whether the flag cells are programmed, based on a reference corresponding to a read margin of the flag cells, and controls a program operation of the memory cells in response to the determination. | 12-17-2009 |
| 20090313424 | MEMORY DEVICE AND METHOD FOR SECURE READOUT OF PROTECTED DATA - The invention relates to a memory device, preferably a non-volatile memory device, comprising a memory array ( | 12-17-2009 |
| 20090313425 | MEMORY CONTROL APPARATUS, CONTENT PLAYBACK APPARATUS, CONTROL METHOD AND RECORDING MEDIUM - A data storage apparatus is provided that realizes a measure against deterioration of a flash memory in which integrity check data is stored. A content playback apparatus ( | 12-17-2009 |
| 20090319720 | SYSTEM AND METHOD OF GARBAGE COLLECTION IN A MEMORY DEVICE - In a particular embodiment, a controller is adapted to perform a garbage collection operation to remove redundant data, to predict a performance parameter associated with performance of the garbage collection operation, and to abort the garbage collection operation when the predicted performance parameter exceeds a threshold. | 12-24-2009 |
| 20090319721 | FLASH MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME - The invention provides a method for operating a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a single-level-cell memory and a multiple-level-cell memory. First, new data for updating a logical block address is received from a host. An update count corresponding to the logical block address is then compared with a threshold value. When the update count is greater than the threshold value, it is determined whether a first physical block address corresponding to the logical block address is pointing to a multiple-level-cell block of the multiple-level-cell memory. When the first physical block address is pointing to the multiple-level-cell block, a target single-level-cell block is then selected from the single-level-cell memory. A corresponding relationship between the logical block address and a second physical block address of the target single-level-cell block is then built. The new data is then written to the target single-level-cell block with the second physical block address. | 12-24-2009 |
| 20090319722 | AD HOC FLASH MEMORY REFERENCE CELLS - In a nonvolatile memory, that includes cells organized in a plurality of bit lines and a plurality of word lines, user data are stored in respective portions of each of two of the word lines. Control information is stored in a cell that is common to one of the bit lines and one of the two word lines. A cell that is common to the bit line and the other word line is used as a reference cell. A flash memory, that includes a plurality of primary cells and a plurality of spare cells, is interrogated to determine which spare cells have been used to replace respective primary cells. At least some of the other spare cells are used as reference cells. | 12-24-2009 |
| 20090319723 | METHOD AND DEVICE FOR BINDING A NON-VOLATILE STORAGE DEVICE WITH A CONSUMER PRODUCT - A method is disclosed for binding a non-volatile storage device ( | 12-24-2009 |
| 20090327578 | Flash Sector Seeding to Reduce Program Times - A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location of the data byte in an address translation table so the data byte may be accessed. | 12-31-2009 |
| 20090327579 | LIMITED MEMORY POWER - Storage devices can retain information through application of a charge upon the storage device. However, applying the charge upon the storage device can be change physical characteristics of the charge and ultimately increase a likelihood of device failure. Therefore, a determination can be made on how to apply the charge based upon analysis of the device, of data for retention, and the like. Raw data can be analyzed and/or estimations can be made to determine the charge. | 12-31-2009 |
| 20090327580 | OPTIMIZATION OF NON-VOLATILE SOLID-STATE MEMORY BY MOVING DATA BASED ON DATA GENERATION AND MEMORY WEAR - An exemplary method includes writing data to locations in non-volatile solid-state memory and deciding whether to move data written to one location in the memory to another location in the memory based on generation of the data and wear of the other location. Such a method may be used for non-volatile random access memory (NVRAM). Various other methods, devices, systems, etc., are also disclosed. | 12-31-2009 |
| 20090327581 | NAND MEMORY - Disclosed herein is a method and apparatus to refresh/rewrite the data in a NAND solid state storage device (“SSD”) only when it needs to be re-written. Upon power-up, the SSD assumes that it may have been a long time since some of its data was last written, and a background task to scan through all the data is started in the SSD. During idle periods, the entire contents of the drive is read. If a location is read and it has more than “bit error threshold” bits (for example three (3) bits if there is capability to correct eight (8) bits) in error before error correction is applied, it is assumed that this memory location is retaining the data only marginally, and the corrected data should be re-written to a new location, or alternatively re-written in the same location. The corrected data is then re-written to a new location or the same location. | 12-31-2009 |
| 20090327582 | Banded Indirection for Nonvolatile Memory Devices - Methods, apparatuses, and computer program products that enable banded indirection for nonvolatile memory devices, such as flash memory devices, are disclosed. One or more embodiments comprise a method for performing banded indirection when accessing data of a nonvolatile device. The methods comprise tracking fragmentation of a band of physical addresses of the nonvolatile memory device, storing a physical address of the band, and accessing data of a logical address of the band via the stored physical address based on the fragmentation of the band. Some embodiments comprise apparatuses for accessing data of nonvolatile devices using banded indirection. The embodiments comprise a nonvolatile memory element to store data, wherein the nonvolatile memory element has bands of physical addresses, a fragmentation detector to detect fragmentation of a band of the nonvolatile memory, and a data access module to access data of the band via a physical address based on the fragmentation. | 12-31-2009 |
| 20090327583 | Seek Time Emulation for Solid State Drives - Methods and apparatuses for delaying execution of input/output (I/O) requests for solid state drives are contemplated. Some embodiments comprise receiving I/O requests for a solid state drive and calculating amounts of time based on characteristics of the requests, such as differences of the logical block addresses (LBAs) of the requests. The embodiments may then delay responses by the solid state drive for the requests. Calculating the amounts of time and delaying the responses by the amounts of time may allow the solid state drives to emulate the responses of various types of hard disk drives. Some embodiments comprise an apparatus for delaying execution of the I/O requests for solid state drives. The apparatuses may have numerous modules, such as a request receiver to receive the I/O requests, a calculation module to calculate the amounts of delay times, and a delay module to delay the responses of the I/O requests. | 12-31-2009 |
| 20090327584 | Apparatus and method for multi-level cache utilization - In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed. | 12-31-2009 |
| 20090327585 | DATA MANAGEMENT METHOD FOR FLASH MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data management method a flash memory storage system and a controller using the same are provided. The data management method is used for accessing a flash memory of the flash memory storage system, wherein the flash memory includes a plurality of physical blocks and the physical blocks are grouped into a data area and a spare area. The data management method includes configuring a plurality of logical blocks for be accessed by a host. The data management method also includes dividing each physical block into a plurality of physical parts and mapping the logical blocks to the physical parts. The data management method further includes accessing the mapped physical parts according to the physical blocks to be accessed by the host. Accordingly, it is possible to increase the usage and the accessing speed of the physical blocks in the flash memory storage system. | 12-31-2009 |
| 20090327586 | MEMORY DEVICE AND DATA STORING METHOD - A memory device is provided, comprising a single-level memory unit, a multi-level memory unit and a control unit. The single-level memory unit comprises a first link table and stores data according to the first link table. The multi-level memory unit comprises a second link table and stores data according to the second link table. The control unit directs data which normally belongs to the single-level memory unit to the multi-level memory unit or directs data which normally belongs to the multi-level memory unit to the single-level memory unit according to a control signal. | 12-31-2009 |
| 20090327587 | PERSONALIZATION OF PORTABLE DATA STORAGE MEDIA - In a method for the personalization of portable data carriers ( | 12-31-2009 |
| 20090327588 | SOLID-STATE DISK WITH WIRELESS FUNCTIONALITY - A solid-state disk (SSD) controller includes a first integrated circuit (IC) that includes an interface module, a memory control module, and a wireless network interface module. The interface module externally interfaces the SSD controller to a computing device. The memory control module controls solid-state memory, receives data from the computing device via the interface module, and caches the data in the solid-state memory. The wireless network interface module communicates with the computing device via the interface module and allows the computing device to connect to a wireless network. | 12-31-2009 |
| 20090327589 | TABLE JOURNALING IN FLASH STORAGE DEVICES - A method of table journaling in a flash storage device comprising a volatile memory and a plurality of non-volatile data blocks is provided. The method comprises the steps of creating a first copy in a first one or more of the plurality of non-volatile data blocks of an addressing table stored in the volatile memory, writing transaction log data to a second one or more of the plurality of non-volatile data blocks, and updating the first copy of the addressing table based on changes to the addressing table stored in the volatile memory after the second one or more of the plurality of non-volatile data blocks have been filled with transaction log data. | 12-31-2009 |
| 20090327590 | ENHANCED MLC SOLID STATE DEVICE - Flash memory drives and related methods are disclosed that operate to keep frequently written data, which results in frequently erased blocks, in SLC-mimicking MLC flash, and relatively static data in normal MLC flash. A flash drive according to the present disclosure keeps track of the number of times that data for each logical block address (LBA) has been written to the flash memory, and determines whether to store newly received data associated with a particular LBA in SLC-mimicking MLC flash or in normal MLC flash depending on the number of writes that have occurred for that particular LBA. Dynamic allocation can occur between the two types of MLC. Related methods and software are also described. | 12-31-2009 |
| 20090327591 | SLC-MLC COMBINATION FLASH STORAGE DEVICE - Flash memory drives and related methods are disclosed that operate to keep frequently written data, which results in frequently erased blocks, in SLC flash, and relatively static data in MLC flash. A flash drive according to the present disclosure keeps track of the number of times that data for each logical block address (LBA) has been written to the flash memory, and determines whether to store newly received data associated with a particular LBA in SLC flash or in MLC flash depending on the number of writes that have occurred for that particular LBA. For each logical block sent to the flash drive, a comparison is made of the write count of the associated LBA to a threshold. If the write count is above the threshold, the logical block is written to SLC flash. If the write count is below the threshold, the logical block is written to MLC flash. | 12-31-2009 |
| 20090327592 | CLUSTERING DEVICE FOR FLASH MEMORY AND METHOD THEREOF - Disclosed are a clustering device for a flash memory and a method thereof. The clustering device for a flash memory in accordance with an embodiment of the present invention can gather pages having similar update times and perform a write operation of the pages in a same block. Accordingly, the writing performance of the flash memory can be improved and the lifetime of the flash memory can be increased. | 12-31-2009 |
| 20090327593 | READ-ONLY MEMORY DEVICE WITH SECURING FUNCTION AND ACCESSING METHOD THEREOF - The present invention provides a memory device and a method for accessing the memory device thereof. The memory device comprises an address encoding selector for selecting one of plurality of encoding circuits which encodes a first address into a second address, and a data decoding selector for selecting one of plurality of decoding circuits which decodes a first data corresponding to the second address into a second data and a non-volatile memory, coupled to address encoding selector and the data decoding selector, for storing the first data. The method for accessing the memory device comprises encoding a first address into a second address by an address encoding selector, and decoding a first data corresponding to the second address into a second data by a data decoding selector, wherein the first data being stored in the non-volatile memory. | 12-31-2009 |
| 20090327594 | APPARATUS AND METHODS FOR PROGRAMMING MULTILEVEL-CELL NAND MEMORY DEVICES - Methods and apparatus are provided. A first data value is read from a first memory cell and is stored. An attempt is made to add a second data value to the first memory cell. If the attempt to add the second data value to the first memory cell is unsuccessful, the first data value and the second data value are written to one or more other memory cells. | 12-31-2009 |
| 20090327595 | STORAGE CAPACITY STATUS - In one embodiment of the present invention, a memory device is disclosed to include memory organized into blocks, each block having a status associated therewith and all of the blocks of the nonvolatile memory having collectively a capacity status associated therewith and a display for showing the capacity status even when no power is being applied to the display. | 12-31-2009 |
| 20100005224 | Foldable USB flash memory device that can be manufactured in any desired shape and size suitable for different types of host devices - An enhanced design for the USB flash memory devices implemented with the USB specifications. The main idea in this design is to create two-section USB flash memory devices and both the sections be joined together with the help of rotating hinges and pivots so that both the sections can rotate with respect to each other. In this design, one section contains the USB connector that is used to connect the USB device with the host device and the other section contains the USB controller, memory controller, and flash memory components of a standard USB device. This arrangement provides the ability to both the sections in the device to rotate against each other and adjust at any desired angle and be folded together. While the rotating hinges are required at both the end sides of two sections where both the sections join together to be able to rotate around each other, rotating hinges or ribbon cables are used between the two sections to provide path for the data flow and the required power between the USB flash memory device and the USB host. | 01-07-2010 |
| 20100005225 | NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND HOST DEVICE - A nonvolatile memory device has a file system manager and manages the file system of a file to be recorded. The nonvolatile memory device measures time by obtaining time information from outside in each writing file data or based on time information preliminarily obtained. At the time of writing file data, management information of the file system is configured based on the time information at the time. Thus, the time information can be stored in a file entry table, and the time information can be used as file management information. The nonvolatile memory system with high user's convenience can be provided. | 01-07-2010 |
| 20100005226 | NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - An access device | 01-07-2010 |
| 20100005227 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - A file to be read or written is designated and accessed from an access device side to a nonvolatile memory device. In an initialization after start-up of the power source, an empty capacity detector detects empty capacity parameters of a nonvolatile memory with dividing the memory into a plurality of regions. An empty capacity parameter notification part notifies the access device of the empty capacity parameters in a stepwise fashion whenever the empty capacity detector detects an empty capacity. With this, at the time when the empty capacity becomes not less than a capacity required to write file data, the data can be written to the nonvolatile memory without waiting for completion of the initialization, resulting in improvement of a response in the recording. | 01-07-2010 |
| 20100005228 | DATA CONTROL APPARATUS, STORAGE SYSTEM, AND COMPUTER PROGRAM PRODUCT - A data control apparatus includes a mapping-table managing unit that manages a mapping table that is associated with a corrupted-data recovery function of recording data and error correcting code data as redundant data that is given separately from the data, distributed and stored in units of stripe blocks in the plural nonvolatile semiconductor memory devices, the mapping table containing arrangement information of the data and the error correcting code data; a determining unit that determines whether to differentiate frequencies of writing the data into the semiconductor memory devices; and a changing unit that changes the arrangement information by switching the data stored in units of the stripe blocks managed using the mapping table to differentiate the frequencies of writing the data into the semiconductor memory devices, when the determining unit determines that the frequencies of writing the data into the semiconductor memory devices are to be differentiated. | 01-07-2010 |
| 20100005229 | FLASH MEMORY APPARATUS AND METHOD FOR SECURING A FLASH MEMORY FROM DATA DAMAGE - A method for securing a flash memory from data damage is provided. After writing of data to a plurality of written pages of a first block of a flash memory is completed, a last weak page of the written pages is determined. A first strong page corresponding to the last weak page is then determined. A plurality of strong pages between the first strong page and the last weak page are then determined. Data of the plurality of strong pages is the coped to a backup area of the flash memory for data recovery. | 01-07-2010 |
| 20100005230 | DATA STORING METHODS AND APPARATUS THEREOF - A data storing method for non-volatile memory is provided, wherein the non-volatile memory includes at least one memory block having a plurality of strong pages and weak pages. A logic block writing command is received for storing the corresponding writing data into the memory block. It is then determined whether the writing data is larger than one page. The writing data is divided into a plurality of page data according to the memory size of the page when the writing data is larger than one page. Next, a first storing page for each page data is determined according to a starting writing page according to the logic block writing command. And, the page data are sequentially written into the first storing pages. Note that each first storing page is a strong page within the memory block. | 01-07-2010 |
| 20100005231 | METHOD AND SYSTEM FOR HARDWARE IMPLEMENTATION OF RESETTING AN EXTERNAL TWO-WIRED EEPROM - Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without initiation by a central processing unit (CPU). The resetting may occur via a virtual CPU. The CPU and the virtual CPU may be integrated on a single chip. The signal generation and EEPROM resetting may occur via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM. | 01-07-2010 |
| 20100005232 | MEMORY CONTROLLER INTERFACE - A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and SRAM memory devices to instead operate using NAND flash and SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor. | 01-07-2010 |
| 20100011149 | Data Storage Devices Accepting Queued Commands Having Deadlines - A data storage device accepts queued read and write commands that have deadlines. The queued read and write commands are requests to access the data storage device. The deadlines of the queued read and write commands can be advisory deadlines or mandatory deadlines. | 01-14-2010 |
| 20100011150 | DATA COLLECTION AND COMPRESSION IN A SOLID STATE STORAGE DEVICE - Methods for programming compressed data to a memory array, memory devices, and memory systems are disclosed. In one such method, memory pages or blocks that are partially programmed with valid data are found. The data is collected from these partially programmed pages or blocks and the data is compressed. The compressed data is then programmed back to different locations in the memory array of the memory device. | 01-14-2010 |
| 20100011151 | DATA ACCESSING METHOD, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module. | 01-14-2010 |
| 20100011152 | DATA PROGRAMMING METHODS AND DEVICES - A data programming device is provided and comprises a non-volatile memory, a volatile memory, and a memory control unit. The non-volatile memory is arranged for programming data. The volatile memory is arranged for temporarily storing data. The memory control unit is arranged for receiving data and determining whether the data is programmed into the non-volatile memory or stored into the volatile memory. If the data exceeds one page, the memory control unit programs a first portion of the data into the non-volatile memory and stores a second portion of the data, which is insufficient for one page, into the volatile memory. | 01-14-2010 |
| 20100011153 | BLOCK MANAGEMENT METHOD, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for managing a multi level cell (MLC) NAND flash memory is provided, wherein the MLC NAND flash memory has a plurality of physical blocks grouped into at least a data area and a spare area, each of the physical blocks has a plurality of pages divided into a plurality of upper pages, and a plurality of lower pages with a writing speed thereof being greater than that of the upper pages. The block management method includes configuring a plurality of logical blocks for being accessed by a host, recording the logical block belonged to a frequently accessed block and executing a special mode to use the lower pages of at least two physical blocks of the MLC NAND flash memory for storing data of one logical block belonged to the frequently accessed block. Accordingly, it is possible to increase the access speed of a storage system. | 01-14-2010 |
| 20100011154 | DATA ACCESSING METHOD FOR FLASH MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data accessing method for a flash memory and a storage system and a controller using the same are provided. The data accessing method includes grouping a plurality of physical blocks of the flash memory into a data area, a spare area, and a random area and when a write command and a new data to be written are received from a host, determining whether the new data is a continuous data, wherein the new data is written temporarily into the physical blocks in the random area if the new data is not a continuous data. Thereby, the number of data moving and physical block erasing is reduced and accordingly the data accessing speed in a random writing mode is increased. | 01-14-2010 |
| 20100011155 | Data processor with flash memory, and method for accessing flash memory - A data processor includes a flash memory that stores a plurality of types of data therein, a random access memory that stores record data information therein, and a controller that can access the flash memory and the RAM. The record data information indicates a head address in the flash memory and a data length corresponding to latest data of each of the plurality of types of data. The controller reads, from the flash memory, the latest data of a type of a reading target among the plurality of types of data, with reference to the record data information. | 01-14-2010 |
| 20100011156 | MEMORY DEVICE AND MANAGEMENT METHOD OF MEMORY DEVICE - A memory device includes a plurality of blocks, and the plurality of blocks may include a plurality of pages. The memory device may translate an external physical address into internal physical address using a non-volatile address translation memory. The memory device may access one page of a plurality of pages using the internal physical address. | 01-14-2010 |
| 20100011157 | DEVICE AND METHOD FOR BACKING UP DATA ON NON- VOLATILE MEMORY MEDIA, OF THE NAND FLASH TYPE, DESIGNED FOR ONBOARD COMPUTERS - The present invention relates to a device making it possible to manage a flash memory component designed for onboard computers notably in the aviation field. In particular, the invention makes it possible to use NAND flash memory media in fields such as aviation, by virtue of its judicious organisation and management of the flash memory components. On the one hand it makes it possible to optimise and on the other hand to control the lifetime of the flash memories. | 01-14-2010 |
| 20100011158 | MEMORY CONTROLLER, MEMORY SYSTEM, AND CONTROL METHOD FOR MEMORY SYSTEM - A memory controller for performing processing for writing data in an interleaved manner and in units of pages in a semiconductor memory section made up of chip | 01-14-2010 |
| 20100011159 | COMBINED MOBILE DEVICE AND SOLID STATE DISK WITH A SHARED MEMORY ARCHITECTURE - A mobile device includes a system-on-chip (SOC) that includes a mobile device control module, a solid state disk (SSD) control module, and a random access memory (RAM) control module. The mobile device control module executes application programs for the mobile device. The solid-state disk (SSD) control module controls SSD operations. The RAM control module communicates with the mobile device control module and the SSD control module and stores both SSD-related data and mobile device-related data in a single RAM. | 01-14-2010 |
| 20100011160 | Method and system for providing security to processors - There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to the processor, to determine whether or not accesses to external memory are allowed. Other changes to the external address enable pin are thereafter ignored. In addition, if it is determined that an internal memory access is occurring, the contents of such an access can be masked to prevent unauthorized viewing of the memory contents via an external memory bus. In addition, a programmable security bit may be set to disable the dumping of flash memory contents, allowing only the erasing of the flash memory. | 01-14-2010 |
| 20100011161 | Memory emulation using resistivity sensitive memory - Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as HDD, DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another. | 01-14-2010 |
| 20100017554 | SYSTEM AND METHOD FOR MANAGING A PLUGGED DEVICE - An electronic device is provided including a non-volatile memory, a connection interface, a processor and at least one resource. The at least one resource has at least one configuration. The non-volatile memory stores the configuration for the resource. The processor generates the configuration for the resource. When plugged into the host device through the connection interface, the electronic device receives a request from the host device and performs an operation in the resource using the configuration. | 01-21-2010 |
| 20100017555 | Memory storage device and control method thereof - A control method of a memory storage device for writing an updated data from a host to the memory storage device is provided. The memory storage device provides storage space which is divided into a plurality of physical blocks to access the updated data. The control method includes the following steps: first, determining whether the updated data is a hot data or not; finally, storing the less updated data which is not the hot data into the physical block which has the higher erase counts according to the result of above determination. | 01-21-2010 |
| 20100017556 | NON-VOLATILE MEMORY STORAGE SYSTEM WITH TWO-STAGE CONTROLLER ARCHITECTURE - The present invention discloses a non-volatile memory storage system with two-stage controller, comprising: a plurality of flash memory devices; a plurality of first stage controllers coupled to the plurality of flash memory devices, respectively, wherein each of the first stage controllers performs data integrity management as well as writes and reads data to and from a corresponding flash memory device; and a storage adapter communicating with the plurality of first stage controllers through one or more internal interfaces. | 01-21-2010 |
| 20100017557 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE,ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - A nonvolatile memory device reads and writes file data according to a file ID designated by an access device. The nonvolatile memory device includes a capacity parameter decision part | 01-21-2010 |
| 20100017558 | Memory device operable in read-only and re-writable modes of operation - A one-time programmable (OTP) memory device and methods for use therewith are provided. These embodiments can be used to provide compatibility between a memory device that uses an OTP (or few-time programmable (FTP)) memory array and host devices that use a file system, such as the DOS FAT file system, that expects to be able to rewrite to a memory address in the memory device. | 01-21-2010 |
| 20100017559 | Memory device operable in read-only and write-once, read-many (WORM) modes of operation - One-time programmable (OTP) and write-once read-many (WORM) memory devices and methods for use therewith are provided. These embodiments can be used to provide compatibility between a memory device that uses an OTP (or few-time programmable (FTP)) memory array and host devices that use a file system, such as the DOS FAT file system, that expects to be able to rewrite to a memory address in the memory device. These embodiments can also be used to prevent accidental or deliberate overwrites, changes, or deletions to existing data in a WORM memory device. | 01-21-2010 |
| 20100017560 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - It has been difficult for an access device to obtain a remaining capacity of a memory from a nonvolatile memory device having a plurality of interfaces. A capacity parameter generation part | 01-21-2010 |
| 20100017561 | SELECTIVELY ACCESSING MEMORY - Devices, systems, methods, and other embodiments associated with selectively accessing memory are described. In one embodiment, a method detects an indication indicative of whether to program fast access pages or slow access pages of a flash memory. In response to the detected indication, data is programmed from a volatile memory: (1) to the fast access pages of the flash memory while skipping the slow access pages, or (2) to the slow access pages while skipping the fast access pages. | 01-21-2010 |
| 20100017562 | MEMORY SYSTEM - To provide a memory system that can store data smaller than a block size and data larger than the block size without deteriorating writing efficiency, and can dynamically change a parallelism according to the data. The memory system according to an embodiment of the present invention comprises a DRAM | 01-21-2010 |
| 20100017563 | MICROCONTROLLER BASED FLASH MEMORY DIGITAL CONTROLLER SYSTEM - Some embodiments includes a digital control system having a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control, and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug. Other embodiments are described. | 01-21-2010 |
| 20100023672 | Method And System For Virtual Fast Access Non-Volatile RAM - A method of writing data to a non-volatile memory with minimum units of erase of a block, a page being a unit of programming of a block, may read a page of stored data addressable in a first increment of address from the memory into a page buffer, the page of stored data comprising an allocated data space addressable in a second increment of address, pointed to by an address pointer, and comprising obsolete data. The first increment of address is greater than the second increment of address. A portion of stored data in the page buffer may be updated with the data to form an updated page of data. Storage space for the updated page of data may be allocated. The updated page of data may be written to the allocated storage space. The address pointer may be updated with a location of the allocated storage space. | 01-28-2010 |
| 20100023673 | AVOIDANCE OF SELF EVICTION CAUSED BY DYNAMIC MEMORY ALLOCATION IN A FLASH MEMORY STORAGE DEVICE - The operating firmware of a portable flash memory storage device is stored in the relatively large file storage memory, which is non executable. It is logically parsed into overlays to fit into an executable memory. The overlays can be of differing sizes to organize function calls efficiently while minimizing dead space or unnecessarily separating functions that should be within one or a group of frequently accessed overlays. For an overlay having functions that require data allocation, the data allocation can cause eviction. This self eviction is avoided altogether or after initial runtime. | 01-28-2010 |
| 20100023674 | Flash DIMM in a Standalone Cache Appliance System and Methodology - A method, system and program are disclosed for accelerating data storage in a cache appliance cluster that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files in a multi-rank flash DIMM cache memory by pipelining multiple page write and page program operations to different flash memory ranks, thereby improving write speeds to the flash DIMM cache memory. | 01-28-2010 |
| 20100023675 | WEAR LEVELING METHOD, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A wear leveling method for a flash is provided, wherein the flash memory includes a plurality of physical blocks grouped into at least a data area and a spare area. The method includes setting a first predetermined threshold value as a wear-leveling start value and randomly generating a random number as a memory erased count, wherein the random number is smaller than the wear-leveling start value. The method also includes counting the memory erased count each time when the physical blocks are erased and determining whether the memory erased count is smaller than the wear-leveling start value, wherein a physical blocks switching is performed between the data area and the spare area when the memory erased count is not smaller then the wear-leveling start value. Accordingly, it is possible to uniformly use the physical blocks, so as to effectively prolong a lifetime of the store system. | 01-28-2010 |
| 20100023676 | SOLID STATE STORAGE SYSTEM FOR DATA MERGING AND METHOD OF CONTROLLING THE SAME ACCORDING TO BOTH IN-PLACE METHOD AND OUT-OF-PLACE METHOD - A solid state storage system includes a controller configured to divide memory blocks of a flash memory area into first blocks and second blocks corresponding to the first blocks, newly allocates pages of the second blocks when an external write command is requested. The controller is also configured to allocate selected sectors in the allocated pages according to sector addresses and execute a write command. | 01-28-2010 |
| 20100023677 | SOLID STATE STORAGE SYSTEM THAT EVENLY ALLOCATES DATA WRITING/ERASING OPERATIONS AMONG BLOCKS AND METHOD OF CONTROLLING THE SAME - A solid state storage system that evenly allocates data writing/erasing operations among blocks is presented. The solid state storage system includes a controller. The controller is configured to set a representative value that becomes a block allocation reference in accordance with predetermined information of blocks in a flash memory area. The controller is also configured to calculate a data value that becomes life time information according to the predetermined information in a current state for each block. The controller is also configured to determine a block where a deviation is generated between the representative value and the data value. The controller is also configured to allocate block where the deviation is generated as a new block where data is written. | 01-28-2010 |
| 20100023678 | NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND ACCESS DEVICE - When an access device accesses a nonvolatile memory device, the nonvolatile memory device or the access device detects or calculates a temperature T of the nonvolatile memory device. A temperature-adaptive control part of the nonvolatile memory device controls an access rate to a nonvolatile memory on the basis of the temperature T. Accordingly, the control part controls the rate so that the temperature T of the nonvolatile memory devices cannot exceed a limit temperature Trisk. In this manner, a nonvolatile memory system can eliminate a risk of a burn when ejecting the semiconductor memory device and can read and write data at a high speed. | 01-28-2010 |
| 20100023679 | SYSTEMS AND TECHNIQUES FOR NON-VOLATILE MEMORY BUFFERING - An apparatus, system, method, and article for non-volatile memory buffering are described. The apparatus may include a data storage manager to store a data item in a rewritable non-volatile memory buffer. The data item may have a file size less than or equal to a threshold value. The rewritable non-volatile memory buffer may include one or more rewritable memory regions configured to store the data item. Other embodiments are described and claimed. | 01-28-2010 |
| 20100023680 | Method for Controlling Non-Volatile Semiconductor Memory System - In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system. | 01-28-2010 |
| 20100023681 | Hybrid Non-Volatile Memory System - The present invention presents a hybrid non-volatile system that uses non-volatile memories based on two or more different non-volatile memory technologies in order to exploit the relative advantages of each these technology with respect to the others. In an exemplary embodiment, the memory system includes a controller and a flash memory, where the controller has a non-volatile RAM based on an alternate technology such as FeRAM. The flash memory is used for the storage of user data and the non-volatile RAM in the controller is used for system control data used by the control to manage the storage of host data in the flash memory. The use of an alternate non-volatile memory technology in the controller allows for a non-volatile copy of the most recent control data to be accessed more quickly as it can be updated on a bit by bit basis. In another exemplary embodiment, the alternate non-volatile memory is used as a cache where data can safely be staged prior to its being written to the to the memory or read back to the host. | 01-28-2010 |
| 20100023682 | Flash-Memory System with Enhanced Smart-Storage Switch and Packed Meta-Data Cache for Mitigating Write Amplification by Delaying and Merging Writes until a Host Read - A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash. | 01-28-2010 |
| 20100030943 | Semiconductor Memory - A semiconductor memory having a burst mode reading function in synchronization with a clock signal comprises a memory array composed of a plurality of memory cells, a sync read control circuit for releasing an upper group of the received address as a memory access address and a lower group of the received address as a burst address in synchronization with the clock signal, a sense amplifier for releasing an output data from each of the memory cells selected by the memory address, a decoder for decoding the burst address, a address latch for latching the decoded burst address in synchronization with the clock signal, a page selector for holding the output data and selecting corresponding one of the output data determined by the burst address of the address latch, and an output latch for latching the output data in synchronization with the clock signal. | 02-04-2010 |
| 20100030944 | Method and Apparatus for Storing Data in Solid State Memory - A method and a storage device for storing data in a flash memory drive are disclosed. In order to increase data throughput, the drive includes a cache memory including a tag memory and a plurality of flash devices coupled via a plurality of channels to the cache memory. | 02-04-2010 |
| 20100030945 | FLASH MEMORY ALLOCATING METHOD - An allocating method for a flash memory is disclosed. The allocating method includes the following steps: adjusting a preliminary data storage capacity corresponding to the flash memory for determining a real data storage capacity of the flash memory; adjusting a preliminary spare area capacity corresponding to the flash memory for determining a real spare area capacity of the flash memory, wherein a total capacity of the preliminary data storage capacity and the preliminary spare area capacity is equal to the total capacity of the real data storage capacity and the real spare area capacity; and allocating the real data storage capacity and the real spare area capacity to the flash memory, wherein the real data storage capacity stores data, and the real spare area capacity stores parity codes generated by an error codes correction algorithm performed upon the stored data in the real data storage capacity. | 02-04-2010 |
| 20100030946 | STORAGE APPARATUS, MEMORY AREA MANAGING METHOD THEREOF, AND FLASH MEMORY PACKAGE - A storage device is provided, which allows a write area associated with a data area of interest to be allocated according to write performance of a host computer. The storage apparatus includes one or more flash memory packages having a plurality of flash memories and stores data transmitted from one or more host computers. A storage area provided by the one or more flash memory packages includes a first area that is an area for storing actual data formed by one or more logical devices and a second area that is an area for storing a write instruction from the host computer to the logical device. The first and second areas are provided in each of the one or more flash memory packages. The apparatus further includes a monitoring section monitoring the frequency of write instructions from the host computer and a changing section for changing the size of the second area according to the frequency of write instructions. | 02-04-2010 |
| 20100030947 | HIGH-SPEED SOLID STATE STORAGE SYSTEM - A solid state storage device includes a main memory cell array and a sub-memory area. The main memory cell array stores data in a flash memory, whereas the sub-memory includes a non-volatile random access memory for storing data. The data storage speed of the non-volatile random access memory of the sub-memory area is faster than the data storage speed of the flash memory of the main memory cell area. The sub-memory area of the solid state storage device also stores address mapping information therein, so that the address mapping information does not have to be transferred to the main memory cell area and a portion of the main memory cell area does not have to be designated for a non-volatile memory for storing the address mapping information. | 02-04-2010 |
| 20100030948 | SOLID STATE STORAGE SYSTEM WITH DATA ATTRIBUTE WEAR LEVELING AND METHOD OF CONTROLLING THE SOLID STATE STORAGE SYSTEM - A solid state storage system is disclosed capable of performing wear leveling utilizing attributes of different types of data. The solid state storage system performs a control operation such that logical addresses are configured to be mapped to physical addresses of pages in multiple planes of a memory area. In addition, the continuous logical addresses are mapped to the physical addresses of the pages of the different planes. The logical addresses are subsequently grouped so as to define multiple data areas for programming data having different attributes. Accordingly, the data is allocated so as to reduce a life time deviation between planes. | 02-04-2010 |
| 20100030949 | Non-volatile memory devices and control and operation thereof - An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement. | 02-04-2010 |
| 20100030950 | CYCLIC BUFFER MECHANISM FOR RECEIVING WIRELESS DATA UNDER VARYING DATA TRAFFIC CONDITIONS - A method of ensuring that data sent to a handheld wireless communications device is written to non-volatile memory is disclosed. In a device, where data is initially written to a first volatile memory and then written to a second volatile memory before being written from the second volatile memory to a non-volatile memory, software code is implemented that causes the writing of the data to non-volatile memory concurrently with the writing of the data to the second volatile memory. The software code may incorporate operating system commands (such as Windows OS). | 02-04-2010 |
| 20100030951 | NONVOLATILE MEMORY SYSTEM - A Flash memory system is implemented in a system-in-package (SIP) enclosure, the system comprising a Flash memory controller and a plurality Flash memory devices. An SIP relates to a single package or module comprising a number of integrated circuits (chips). The Flash memory controller is configured to interface with an external system and a plurality of memory devices within the SIP. The memory devices are configured in a daisy chain cascade arrangement, controlled by the Flash memory controller through commands transmitted through the daisy chain cascade. | 02-04-2010 |
| 20100030952 | Memory Module, Memory System, and Information Device - A memory system including large-capacity ROM and RAM in which high-speed reading and writing are enabled is provided. | 02-04-2010 |
| 20100036999 | NOVEL METHOD OF FLASH MEMORY CONNECTION TOPOLOGY IN A SOLID STATE DRIVE TO IMPROVE THE DRIVE PERFORMANCE AND CAPACITY - The present invention provides a novel flash memory connection method between a flash controller and flash devices such that the controller can manage two or more flash devices concurrently. It provides the ability to efficiently manage a large array of non-volatile flash devices in a solid state drive (SSD) and allocate flash memory usage in such a way that at least doubles the SSD bandwidth and the total storage capacity. | 02-11-2010 |
| 20100037000 | ONE-TIME-PROGRAMMABLE MEMORY EMULATION - This document discloses one-time-programmable (“OTP”) memory emulation and methods of performing the same. OTP memory can be emulated by managing reads and writes to a memory array in response to an instruction to write data to a OTP memory location and selectively setting a security flag that corresponds to the memory locations. The memory array can be a NAND Flash memory array that includes multiple pages of memory. The memory array can be defined by memory blocks that can include multiple pages of memory. When an OTP write instruction is received, previously stored data can be read from a first page of memory, combined with the new data and stored to a target page of memory. A security flag can be set to prevent the target page from being reprogrammed prior to an erase. | 02-11-2010 |
| 20100037001 | Flash memory based storage devices utilizing magnetoresistive random access memory (MRAM) - A flash memory based storage device may utilize magnetoresistive random access memory (MRAM) as at least one of a device memory, a buffer, or high write volume storage. In some embodiments, a processor of the storage device may compare a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table and causes the data file to be written to the high write volume MRAM when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table. In other embodiments, upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller. | 02-11-2010 |
| 20100037002 | MIXED TECHNOLOGY STORAGE DEVICE - A mixed storage device includes a set of storage units, each potentially based on a different storage technology, such as NAND flash drive, NOR flash drive, magnetic hard drive, magneto-optical drives, optical drives, etc. The mixed storage device comprises a host bus connector that is used to connect to a peripheral bus that facilitates communication to a processor of a device (such as a PC) and a controller. The controller manages a NAND flash storage device, a NOR flash storage device, an optical storage device, a hard drive and other storage components plugged into or integrated with the mixed storage device. | 02-11-2010 |
| 20100037003 | FLASH MEMORY CONTROL APPARATUS HAVING SIGNAL-CONVERTING MODULE - A flash memory control apparatus having a signal-converting module is described. The signal-converting module includes a primary controller, a signal-converting module, a data buffer, and a secondary controller. The primary controller generates a plurality of control signals based on a first control interface. The signal-converting module receiving a reading enable signal and a writing enable signal of the control signals and converts the reading enable signal and the writing enable signal into a writing/reading signal based on a second control interface. The data buffer stores the data from the primary controller according to the first control interface and stores the data from the flash memory according to the second control interface. The secondary controller transmits the writing/reading signal, a clock signal and a data strobe signal to the flash memory based on the second control interface. | 02-11-2010 |
| 20100037004 | STORAGE SYSTEM FOR BACKUP DATA OF FLASH MEMORY AND METHOD FOR THE SAME - A storage system for backup data of a flash memory includes a flash memory for storing a first file, a detector for detecting a number of accesses to the first file, and a driving unit coupled to the detector. The driving unit is used for duplicating the first file as one or more second files when the number of accesses to the first file exceeds a predetermined value, and storing the one or more first files into the flash memory. If the access number is higher than the predetermined value, which indicates this file is more likely to be accessed, the invention automatically backups this file and accesses the backup file at the next access request for fear that the file is damaged by multiple access to the same file. | 02-11-2010 |
| 20100037005 | COMPUTING SYSTEM INCLUDING PHASE-CHANGE MEMORY - A computing system, more particularly, a computing system including a phase-change memory is provided. The computing system includes a flash memory configured to store data and a phase-change memory configured to store address mapping information for converting a logical address into a physical address. The phase-change memory is configured to store the address mapping information while the computing system is in a power-off state. The computing system may store an address mapping table to manage the flash memory in the phase-change memory. | 02-11-2010 |
| 20100037006 | NON-VOLATILE MEMORY AND CONTROLLING METHOD THEREOF - A non-volatile memory of present invention includes a number of memory blocks and a static wear leveling device. The static wear leveling device includes a memory unit for storing the erase counts of the memory blocks and a controlling unit for getting the erase counts from the memory unit, and calculating the standard deviation based on the EC, and deciding the way of the static wear leveling cycle according to the standard deviation. The controlling unit deciding the way of the static wear leveling cycle include the steps of setting at least one predetermined threshold point and judging whether the standard deviation of the erase counts is smaller than the predetermined threshold point. If the standard deviation of the erase counts is smaller than the predetermined threshold point, the static wear leveling cycle starts for a first amount of cycles and moves the static data stored a first number of memory blocks. If the standard deviation of the erase counts is bigger than the predetermined threshold point, starts for a second amount of cycles and moves the static data stored a second number of memory blocks. | 02-11-2010 |
| 20100037007 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell array in which memory cells having an electrically rewritable charge accumulation layer are arranged, a data writing/reading circuit that writes/reads data to/from the memory cell array in units of pages, a write state information storage circuit for nonvolatile storage of write state information indicating a data write state to the memory cell array by the data writing/reading circuit, and a control circuit that controls the data writing/reading circuit based on an access page address indicating a page from which data is about to be read by the data writing/reading circuit and write state information stored in the write state information storage circuit. | 02-11-2010 |
| 20100037008 | APPARATUS WITH A FLASH MEMORY AND METHOD FOR WRITING DATA TO THE FLASH MEMORY THEREOF - An apparatus | 02-11-2010 |
| 20100037009 | SEMICONDUCTOR STORAGE DEVICE, METHOD OF CONTROLLING THE SAME, CONTROLLER AND INFORMATION PROCESSING APPARATUS - A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area. | 02-11-2010 |
| 20100037010 | SEMICONDUCTOR STORAGE DEVICE, METHOD OF CONTROLLING THE SAME, CONTROLLER AND INFORMATION PROCESSING APPARATUS - A semiconductor storage device includes first, second, third, fourth and fifth memory areas and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the fifth memory area, a fourth processing for moving an area of the third unit to the second memory area, a fifth processing for selecting and copying data to an empty area of the third unit in the second memory area, a sixth processing for moving an area of the third unit to the third memory area, and a seventh processing for selecting and copying data to an empty area of the third unit in the third memory area. | 02-11-2010 |
| 20100037011 | Semiconductor Storage Device, Method of Controlling The Same, Controller and Information Processing Apparatus - A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second, third, and fourth memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the third memory area, a fourth processing for moving an area of the third unit having the oldest allocation order in the fourth memory area to the second memory area, and a fifth processing for selecting data in the second memory area and copying the selected data to an empty area of the third unit in the second memory area. | 02-11-2010 |
| 20100037012 | Semiconductor Storage Device, Method of Controlling the Same, Controller and Information Processing Apparatus - A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second, third and fourth memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the third memory area, a fourth processing for moving an area of the third unit from the fourth memory area to the second memory area, a fifth processing for copying data to an area of the third unit and allocating the area to the second memory area, and a sixth processing for copying data to an empty area of the third unit in the second memory area. | 02-11-2010 |
| 20100042772 | Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cells - One or more multi-level NAND flash cells are operated so as to store only single-level data, and these operations achieve an increased level of charge separation between the data states of the single-level operation by requiring a write to both the upper and lower pages, even though only one bit of data is being stored. That is, the second write operation increases the difference in floating gate charge between the erased state and the programmed state of the first write operation without changing the data in the flash memory cell. In one embodiment, a controller instructs the flash memory to perform two write operations for storing a single bit of data in an MLC flash cell. In another embodiment, the flash memory recognizes that a single write operation is directed a high reliability memory area and internally generates the required plurality of programming steps to place at least a predetermined amount of charge on the specified floating gate. | 02-18-2010 |
| 20100042773 | FLASH MEMORY STORAGE SYSTEM AND DATA WRITING METHOD THEREOF - A flash memory storage system and a data writing method thereof are provided. The flash memory storage system includes a controller, a connector, a cache memory, a SLC NAND flash memory and a MLC NAND flash memory. When the controller receives data to be written into the MLC NAND flash memory from a host system, the data is temporarily stored in the cache memory first and then is written into the MLC NAND flash memory from the cache memory. And, the controller may backup the data stored in the cache memory to the SLC NAND flash memory. Accordingly, it is possible to reduce a response time for a flush command, thereby improving a performance of the flash memory storage system. | 02-18-2010 |
| 20100042774 | BLOCK MANAGEMENT METHOD FOR FLASH MEMORY, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for a flash memory chip having multiple planes is provided, wherein each plane has a plurality of physical blocks. The method includes disposing a plurality of physical units, wherein each physical unit includes a physical block of each plane, and the physical blocks in the physical unit have a simultaneously-operable relationship. The method also includes writing data in a single plane access mode when a host system does not update all the physical blocks in an updated the physical unit. The method further includes writing the data in a multi-planes access mode when the host system updates all the physical blocks in the updated physical unit, wherein the physical blocks for writing the data have the simultaneously-operable relationship. | 02-18-2010 |
| 20100042775 | BLOCK MANAGEMENT METHOD FOR FLASH MEMORY, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for managing a flash memory is provided. The method includes dividing the flash memory into a cache area and a storage area and dividing the cache area into a plurality of cache sub-areas, wherein the storage area has a plurality of physical blocks and each cache sub-area contains at least one physical block. The method also includes configuring a plurality of logical blocks for mapping the physical blocks of the storage area, and allocating one of the cache sub-areas for each logical block, wherein when the host writes the data into the logical blocks, the data may be temporarily stored in the cache sub-areas allocated for the logical blocks. Accordingly, it is possible to increase efficiency of the flash storage system and avoid wearing of the physical blocks, so as to prolong a lifetime of the flash storage system. | 02-18-2010 |
| 20100042776 | Method and apparatus for providing enhanced write performance using a buffer cache management scheme based on a buffer replacement rule - An approach is provided for improving write performance using a buffer cache based on a buffer replacement policy. A buffer cache manager is configured to improve address mapping scheme associated with write performance between an application system and a storage device system. The manager selects a victim page to be evicted from a victim block of a buffer cache according to a recently-evicted-first rule. And the victim block is selected associated with a log block of a memory. | 02-18-2010 |
| 20100042777 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND DATA WRITE METHOD FOR THE SAME - A semiconductor device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a first memory block configured to hold at least 2 bits data, and a second memory block configured to hold 1-bit data. The data is programmed into the first and second memory blocks in units of page. Each of the pages in the first memory block is assigned to a corresponding bit of the held data. Time required for write varies depending on the bit. The controller instructs the nonvolatile semiconductor memory to program the write data into the first memory block or the second memory block. The controller instructs the nonvolatile semiconductor memory to program the data on any of the pages in the second memory block if a final page of the write data corresponds to the bit requiring the longest time for the write. | 02-18-2010 |
| 20100049900 | MEMORY CARD AND NON-VOLATILE MEMORY CONTROLLER THEREOF - A memory card and a non-volatile memory controller thereof are provided. The non-volatile memory controller provides a process interface to allow a host to access a non-volatile memory. The non-volatile memory controller includes a mode setting port group, a firmware download port group, a host access port group, a memory port group, a control unit, a processing unit, an interface unit, and a switch unit. When a firmware in the non-volatile memory is to be updated, the switch unit switches to the firmware download port group and then connects it to a fixture to obtain a new firmware. The control unit writes the new firmware into the non-volatile memory directly on a printed circuit board according to an instruction of the process unit. Thereby, in the present invention, firmware updating can be carried out directly on a printed circuit board therefore is made more convenient. | 02-25-2010 |
| 20100049901 | MEMORY CARD AND NON-VOLATILE MEMORY CONTROLLER THEREOF - A memory card and a non-volatile memory controller thereof are provided. The non-volatile memory controller includes a firmware download port group, a memory interface unit, a processing unit, and a host interface unit. The firmware download port group is used for coupled to a firmware update fixture. The memory interface unit includes at least one tri-state buffer component, and the memory interface unit is coupled to a non-volatile memory and the firmware download port group through the tri-state buffer component, wherein the tri-state buffer component determines whether to operate in a high-impedance mode or a normal mode according to a mode single. The processing unit accesses the non-volatile memory through the memory interface unit. When the tri-state buffer component operates in the high-impedance mode according to the mode single, the firmware update fixture writes a new firmware into the non-volatile memory through the firmware download port group. | 02-25-2010 |
| 20100049902 | STORAGE SUBSYSTEM AND STORAGE SYSTEM INCLUDING STORAGE SUBSYSTEM - To provide a storage subsystem in which, even when plural types of storage devices are provided, write processing from a cache memory to the plural types of storage devices is not delayed. Even when there are relative merits in writing performance of write data from the cache memory to the HDD and the SSD, the cache memories | 02-25-2010 |
| 20100049903 | RECORDING SYSTEM AND DATA RECORDING METHOD - A recording method for writing data into an electrically erasable programmable read-only memory is disclosed, in which the memory has already been electrically connected to a controller through a logic device. The method sets the logic devices for the first time to disconnect the memory from the controller, and set the logic devices for the second time to write setting data required by the controller into the memory. After that, the method reads out the setting data stored in the memory to confirm the writing of the setting data, and connects the memory to the controller again. | 02-25-2010 |
| 20100049904 | STORAGE DEVICE USING A MULTI-LEVEL FLASH MEMORY AS A SINGLE FLASH MEMORY AND METHOD FOR THE SAME - A storage device includes a multi-level cell flash memory having a plurality of physical memory cells, a read controller, and a write controller. The physical memory cells form a first page and a second page. The write controller in response to a first request is used for writing first data into the first page, duplicating the first data as a second data and writing the second data into the second page. The read controller is used for adjusting the stored data value complying with a desired storing value. Each physical memory cell comprises four threshold voltage ranges indicative of two-bit logical values. The two-bit data is assigned as a first logical value accordingly in response to a two-bit data corresponding to a first and second threshold voltage ranges in a first physical memory cell. The two-bit data is assigned as a second logical value accordingly in response to a two-bit data corresponding to a third and fourth threshold voltage ranges in a second physical memory cell. | 02-25-2010 |
| 20100049905 | Flash memory-mounted storage apparatus - In a data center, there is a limit in power capacity supplied to a storage apparatus, and the rated power consumption of the storage apparatus may exceed the power supply capacity by addition of storage capacity. A storage apparatus according to the invention includes one or plural packages mounting plural flash memories and a circuit controlling the flash memories as well as information of power supply capacity. The number of flash memories performing writing, erasing or reading at the same time is designated with respect to each package based on the information of power supply capacity. | 02-25-2010 |
| 20100049906 | SECURE NON-VOLATILE MEMORY DEVICE AND METHOD OF PROTECTING DATA THEREIN - The invention relates to a non-volatile memory device comprising: an input for providing external data (D) to be stored on the non-volatile memory device; a first non-volatile memory block ( | 02-25-2010 |
| 20100049907 | Memory System and Control Method Thereof - A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest. | 02-25-2010 |
| 20100049908 | Adaptive Mode Switching of Flash Memory Address Mapping Based on Host Usage Characteristics - In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism. | 02-25-2010 |
| 20100049909 | NAND Flash Memory Controller Exporting a NAND Interface - A NAND controller for interfacing between a host device and a flash memory device (e.g. a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed. | 02-25-2010 |
| 20100049910 | Flash EEprom System With Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks - A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell. | 02-25-2010 |
| 20100057976 | MULTIPLE PERFORMANCE MODE MEMORY SYSTEM - A method and system for controlling a write performance level of a memory is disclosed. The method includes receiving an input at the memory, and configuring the memory to an operation mode providing a write performance level and a storage capacity. The input may specify a storage capacity, a working area capacity, a write performance level, and/or a ratio of the storage capacity to the working area capacity. A desired write performance level may be set by receiving a software command or hardware setting. The storage capacity may be varied depending on whether the memory device has been formatted. As the storage capacity decreases, working area capacity of the memory device increases and write performance increases. Conversely, as the storage capacity increases, working area capacity decreases and write performance decreases. | 03-04-2010 |
| 20100057977 | REDUCED-POWER PROGRAMMING OF MULTI-LEVEL CELL (MLC) MEMORY - In one embodiment, a mobile electronic device has a host controller, an energy-saving encoder, an energy-saving decoder, and a multi-level cell (MLC) NAND flash memory. The host controller provides raw user data to the energy-saving encoder in k-bit segments. The energy-saving encoder encodes each k-bit segment into an n-bit segment of encoded user data for programming the MLC NAND flash memory as a p-symbol codeword, where (i) k is smaller than n (ii) p(=n/log | 03-04-2010 |
| 20100057978 | Storage system and data guarantee method - A system according to the invention reads/writes data by using a memory device performing a wear leveling. A host | 03-04-2010 |
| 20100057979 | DATA TRANSMISSION METHOD FOR FLASH MEMORY AND FLASH MEMORY STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data transmission method suitable for transmitting data from a cache to a plurality of flash memory groups through a single data bus in a flash memory storage system is provided. The data transmission method includes sequentially sorting and grouping data to be written at continuous logical addresses in the cache in unit of logical blocks. The data transmission method further includes respectively transmitting the grouped sector data into the flash memory groups through the data bus in an interleaving manner, wherein data in the same logical block is transmitted and written into physical blocks of the same flash memory group. Thereby, the data is prevented from being written into different physical blocks, and accordingly the lifespan of the flash memory storage system is prolonged. | 03-04-2010 |
| 20100057980 | DATA MEMORY DEVICE WITH AUXILIARY FUNCTION - The invention relates to a method, a data storage device, and a system with a data storage device having an additional module ( | 03-04-2010 |
| 20100064092 | INTERFACE FOR WRITING TO MEMORIES HAVING DIFFERENT WRITE TIMES - An interface between memories having different write times is described. The interface includes a latch for capturing address and data information during a memory access by a processor of a first memory device. The interface also includes an index counter for providing frame management. The interface also includes a variable identity array logic for determining what data is to be written into a second memory device and address generation logic to determine where the data is to be stored in the second memory device. Additionally, the interface includes data validity logic to ensure that the data being written into the second memory device is valid. As a result, the processor can operate in substantially real time and can restore itself after detecting an event upset using the data stored in the second memory device. | 03-11-2010 |
| 20100064093 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONVERTING DATA IN A BINARY REPRESENTATION TO A NON-POWER OF TWO REPRESENTATION - A system, method, and computer program product are provided for converting data in a binary representation to a non-power of two representation. In operation, data in a binary representation is identified. Additionally, the data in the binary representation is converted to a non-power of two representation having a non-power of two number of voltage levels. | 03-11-2010 |
| 20100064094 | Memory managing method for non-volatile memory and controller using the same - A memory managing method for a non-volatile memory and a controller using the same are disclosed. The controller includes a system wear leveling member for performing a first wear leveling process in a non-volatile memory for choosing a memory unit; and a subsystem wear leveling member for performing a second wear leveling process in the chosen memory unit for selecting a block from the chosen memory unit for data programming; whereby uneven use of the blocks of the chosen memory unit is avoided. | 03-11-2010 |
| 20100064095 | Flash memory system and operation method - The present invention discloses a flash memory system comprising: a cache memory, a cache memory interface, a host interface, a flash memory interface, and a microprocessor The cache memory interface contains an arbitrator for performing data bus bandwidth time sharing process to access the cache memory The host interface is used for receiving data from a host system, and storing the data into the cache memory to form ready data The flash memory interface reads the ready data from the cache memory and stores it into at least one flash memory The microprocessor is used for controlling the host interface and the flash memory interface to access the cache memory Hence, the present invention can achieve the purpose of enhancing the access efficiency and increasing the life of the flash memory | 03-11-2010 |
| 20100064096 | SYSTEMS AND METHODS FOR TEMPORARILY RETIRING MEMORY PORTIONS - Flash memory apparatus including a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain portions from among said plurality of memory portions including allocating data, during the first duration of time, only to the certain portions, thereby to define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for the first duration of time. | 03-11-2010 |
| 20100064097 | FLASH MEMORY STORAGE SYSTEM - A flash memory storage system has a plurality of flash memory devices comprising a plurality of flash memories, and a controller having an I/O processing control unit for accessing a flash memory device specified by a designated access destination in an I/O request received from an external device from among the plurality of flash memory devices. A parity group can be configured of flash memory devices having identical internal configuration. | 03-11-2010 |
| 20100064098 | Device and Method for Controlling Solid-State Memory System - A memory system includes an array of solid state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon. A reserved predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system. | 03-11-2010 |
| 20100070681 | METHOD FOR SCRAMBLING DATA IN WHICH SCRAMBLING DATA AND SCRAMBLED DATA ARE STORED IN CORRESPONDING NON-VOLATILE MEMORY LOCATIONS - A method in which data is randomized before being stored in a non-volatile memory to minimize data pattern-related read failures. Predetermined randomized non-user data is stored in a block or other location of a memory array, and accessed as needed by a memory device controller to randomize user data before it is stored in other blocks of the array. Each portion of the user data which is stored in a block is randomized using a portion of the non-user data which is stored in the same relative location in another block. | 03-18-2010 |
| 20100070682 | BUILT IN ON-CHIP DATA SCRAMBLER FOR NON-VOLATILE MEMORY - A non-volatile memory in which data is randomized before being stored in the non-volatile memory to minimize data pattern-related read failures. Randomizing is performed using circuitry on the memory die so that the memory die is portable relative to an external, off-chip controller. Circuitry on the memory die scrambles user data based on a key which is generated using a seed which is shifted according to a write address. Corresponding on-chip descrambling is also provided. | 03-18-2010 |
| 20100070683 | METHOD TO MONITOR READ/WRITE STATUS OF FLASH MEMORY DEVICES - A method and flash memory device employing the method includes a flash memory device having a logic routine saved on the flash memory being a computer readable medium. The flash memory device generates a plurality of memory inputs and outputs. The logic routine determines a memory input and/or memory output operation, and incrementally counts memory inputs and memory outputs using a counter function of the logic routine. The logic routine determines the total number of the plurality of memory inputs and outputs using the counter function. Additionally, the logic routine generates an alert signal when the total number of the memory inputs and outputs exceeds a predetermined value programmed in the logic routine. | 03-18-2010 |
| 20100070684 | MEMORY DEVICE AND OPERATING METHOD THEREOF - A memory device preloads a command file and a plurality of response files. Whenever a host sends a command to the memory apparatus, the command assigns one of the response files; thereby the host can receive response of the memory apparatus by reading the assigned response file. | 03-18-2010 |
| 20100070685 | METHOD FOR OPERATING MEMORY CARD - A method is used for operating a memory card, which comprises following steps: (1) a file is preloaded in the first sector of the file allocation table and the second sectors of the description block, wherein the file at least including first data, second data and third data, wherein the first sector is filled up with the first data, only one of the second sectors is not filled up with the second data and the other second sectors are filled up with the third data. (2) A command is received, where the command is capable of updating the file. (3) The command for the first sector is ignored. (4) The only one of the second sectors is updated according to the command. (5) The command for the other second sectors is ignored. (6) The second data of the only one of the second sectors are recovered. | 03-18-2010 |
| 20100070686 | METHOD AND DEVICE FOR RECONFIGURATION OF RELIABILITY DATA IN FLASH EEPROM STORAGE PAGES - A data processing system comprises a Flash memory ( | 03-18-2010 |
| 20100070687 | PROCEDURE FOR ACCESSING A NON-VOLATILE WATCH MEMORY - The invention relates to a procedure for accessing a non-volatile watch memory, the watch comprising two supply terminals accessible from the outside that define a potential difference corresponding to a standard supply voltage, and a control circuit of the non-volatile memory produced using a technology supporting a predefined maximum supply voltage, the access procedure consisting of transmitting the following to the control circuit of the non-volatile memory by means of a supply terminal of the watch: a) an opening key to authorise access to the non-volatile memory; b) an instruction for access to the non-volatile memory; the procedure being characterised in that the opening key is a predefined instruction transmitted by modulation of the standard supply voltage such that this does not exceed the predefined maximum supply voltage. | 03-18-2010 |
| 20100070688 | FLASH MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO - The invention provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and comprises a multiple-level-cell (MLC) flash memory and a controller. The MLC flash memory comprises a turbo area and a normal area, wherein the turbo area comprises a plurality of first blocks, the normal area comprises a plurality of second blocks, and each of the first blocks and the second blocks comprises a plurality of pages, wherein the pages of the first blocks and the second blocks are divided into strong pages with high data endurance and weak pages with low data endurance. The controller receives data to be written to the MLC flash memory from the host, determines whether the data is important data, and writes the data to the strong pages of the first blocks of the turbo area when the data is important data. | 03-18-2010 |
| 20100070689 | HYBRID HARD DISK DRIVE TO RAPIDLY READ FILES HAVING SPECIFIED CONDITIONS, METHOD OF CONTROLLING THE HYBRID HARD DISK DRIVE, AND RECORDING MEDIUM FOR THE HYBRID HARD DISK DRIVE - A method of controlling a hybrid hard disk drive. The method includes receiving a read command from a host; searching metadata of a file to be read; determining whether the metadata satisfies a predetermined setup condition; and if the metadata satisfies the setup conditions, copying the file to be read, from a first storage device and storing the file in a second storage device. | 03-18-2010 |
| 20100070690 | LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR PROGRAMMING THE SAME - A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM. | 03-18-2010 |
| 20100070691 | Multiprocessor system having multiport semiconductor memory device and nonvolatile memory with shared bus - A multiprocessor system employing a multiport semiconductor memory device and a nonvolatile memory having a shared bus is provided. The multiprocessor system includes a first processor; a second processor; a semiconductor memory device including a shared memory area accessed in common by the first and second processors through different ports and assigned within a memory cell array, and an internal register positioned outside the memory cell array, the internal register being configured to provide an access authority for a shared bus to the first and second processors; and a nonvolatile semiconductor memory device having first and second nonvolatile memory areas coupled corresponding to the first and second processors through the shared bus, the first and second nonvolatile memory areas being accessed by and corresponding to the first and second processors according to the access authority for the shared bus. | 03-18-2010 |
| 20100070692 | MULTI-BIT-PER-CELL FLASH MEMORY DEVICE WITH NON-BIJECTIVE MAPPING - To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits. | 03-18-2010 |
| 20100070693 | INITIALIZATION OF FLASH STORAGE VIA AN EMBEDDED CONTROLLER - A digital system including flash memory, coupled to a system-on-a-chip within which a flash memory subsystem controller is embedded, is disclosed. The system-on-a-chip includes support for a standard external interface, such as a Universal Serial Bus (USB) or IEEE 1394 interface, to which a host system such as flash memory test equipment can connect. Initialization of the flash memory is effected by opening a communications channel between the host system and the embedded flash memory subsystem controller. The host system can then effect initialization of the flash memory subsystem, including formatting of the flash memory arrays, loading application programs, and the like, over the communications channel. | 03-18-2010 |
| 20100077131 | UPDATING CONTROL INFORMATION IN NON-VOLATILE MEMORY TO CONTROL SELECTION OF CONTENT - To control selection of content in a non-volatile memory, control information is stored in the non-volatile memory, where the control information is to control selection of content in the non-volatile memory. An algorithm is used to update the control information in the non-volatile memory to cause different content in the non-volatile memory to be selected, wherein the algorithm sets the control information to an initial value that enhances use of programming of the non-volatile memory to update the control information, and reduces use of erasing of the non-volatile memory to update control information. | 03-25-2010 |
| 20100077132 | MEMORY DEVICES AND ACCESS METHODS THEREOF - Methods and devices capable of erasing a flash memory evenly are provided, in which a flash memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks, and a controller retrieves a corresponding data with a check code from a first data block of the flash memory according to a read command from a host, performs a predetermined check to the corresponding data by the check code, determines whether an error is correctable when a check result of the predetermined check represents that the error has occurred, and increases an erase count of the first data block by a predetermined value when the error is correctable. | 03-25-2010 |
| 20100077133 | Flash Memory Integrated Circuit with Compression/Decompression CODEC - Provided is a flash memory integrated circuit with a compression codec. The flash memory integrated circuit may simultaneously include a memory block and a compression codec circuit. The compression codec circuit may compress input data. A controller circuit may store the compressed input data in at least one page that is included in the memory block. Through this, it is possible to enhance a usage efficiency of a flash memory. | 03-25-2010 |
| 20100077134 | FLASH DEVICE AND METHOD FOR IMPROVING PERFORMANCE OF FLASH DEVICE - The invention provides a flash device. In one embodiment, the flash device comprises a first NAND flash integrated circuit, a second NAND flash integrated circuit, and a control integrated circuit. The control integrated circuit generates a plurality of first access signals with first timings to access the first NAND flash IC, and generates a plurality of second access signals with second timings to access the second NAND flash IC, wherein the first timings are different from the second timings. The first NAND flash integrated circuit then accesses data stored therein according to the first access signals. The second NAND flash integrated circuit then accesses data stored therein according to the second access signals. | 03-25-2010 |
| 20100077135 | MEMORY WEAR LEVELING METHOD, SYSTEM AND DEVICE - A wear leveling method for a non-volatile memory is provided. The non-volatile memory includes a plurality of data blocks, each corresponding to a time value. The data blocks are arranged according to a sequence of the time values corresponding thereto. The arranged blocks form a key table. An erase operation is determined whether to be executed for the data blocks. When the erase operation is executed for the data blocks, the corresponding data block is erased according to a sequence of the time values of the data blocks in the key table. | 03-25-2010 |
| 20100077136 | Memory System Supporting Nonvolatile Physical Memory - A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory. | 03-25-2010 |
| 20100077137 | METHOD FOR CATALOGING AND STORING DATA IN A CONTROL SYSTEM - A method includes receiving a data input file, the data input file defining a first set of data fields to be included in a database and including a set of data elements to be included in the database. The method also includes identifying a second set of data fields in the data input file that are designated to contain a Boolean element, said second set of data fields being a subset of the first set of data fields. The method further includes defining at least one new data field, each new data field collectively storing a plurality of the Boolean elements. The first set of data fields are modified to eliminate the second set of data fields. The method also includes storing in a catalog data that defines an arrangement of the first set of data fields, wherein the arrangement includes the at least one new data field for collectively storing the Boolean elements. | 03-25-2010 |
| 20100082878 | MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND DATA WRITING METHOD - Used is a nonvolatile memory such as a multi-level NAND flash memory having memory cells for holding data of a plurality of pages. When the data is to be written in the nonvolatile memory | 04-01-2010 |
| 20100082879 | PRIORITY COMMAND QUEUES FOR LOW LATENCY SOLID STATE DRIVES - A method, apparatus, and system of a priority command queues for low latency solid state drives are disclosed. In one embodiment, a system of a storage system includes a command sorter to determine a target storage device for at least one of a solid state drive (SSD) command and a hard disk drive (HDD) command and to place the command in a SSD ready queue if the SSD command is targeted to a SSD storage device of the storage system and to place the HDD command to a HDD ready queue if the HDD command is targeted to an HDD storage device of the storage system, a SSD ready queue to queue the SSD command targeted to the SSD storage device, and a HDD ready queue to queue the HDD command targeted to the HDD storage device. | 04-01-2010 |
| 20100082880 | PRE-CODE DEVICE, AND PRE-CODE SYSTEM AND PRE-CODING METHOD THEREROF - A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block. | 04-01-2010 |
| 20100082881 | SOLID STATE STORAGE DEVICE CONTROLLER WITH EXPANSION MODE - Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device. | 04-01-2010 |
| 20100082882 | SEMICONDUCTOR DISK DEVICES AND RELATED METHODS OF RANDOMLY ACCESSING DATA - A computing system includes a host, a data source device, and a controller. The controller is configured to respond to a random access command from the host by setting information in a register that selects what data is to be accessed in the data source device. The controller then successively accesses the data in the data source device using the information that was set in the register. | 04-01-2010 |
| 20100082883 | Hybrid density memory system and control method thereof - A control method of a memory system for accessing an updated data between a host and the memory system is provided. The host has storage space which is divided into a plurality of logical segments to access the data. The system includes a high density memory and a low density memory, and the high density memory includes a plurality of physical segments to access the data. The control method includes the following steps: first, providing a LDM table in the memory system to indicate the allocation information of the low density memory; finally, deciding where the data is written to is according to its properties and the LDM table. | 04-01-2010 |
| 20100082884 | MEMORY CELL OPERATION - The present disclosure includes memory devices and systems having memory cells, as well as methods for operating the memory cells. One or more methods for operating memory cells includes determining age information for a portion of the memory cells and communicating a command set for the portion of the memory cells, the command set including the age information. | 04-01-2010 |
| 20100082885 | METHOD AND SYSTEM FOR ADAPTIVE CODING IN FLASH MEMORIES - Bits are stored by attempting to set parameter value(s) of (a) cell(s) to represent some of the bits. In accordance with the attempt, an adaptive mapping of the bits to value ranges is provided and the value(s) is/are adjusted accordingly as needed. Or, to store (a) bit(s) in (a) cell(s), a default mapping of the bit(s) to a predetermined set of value ranges is provided and an attempt is made to set the cell value(s) accordingly. If, for one of the cells, the attempt sets the value such that the desired range is inaccessible, an adaptive mapping is provided such that the desired range is accessible. Or, to store (a) bit(s) in (a) cell(s), several mappings of the bit(s) to a predetermined set of ranges is provided. Responsive to an attempt to set the cell value(s) according to one of the mappings, the mapping to actually use is selected. | 04-01-2010 |
| 20100082886 | VARIABLE SPACE PAGE MAPPING METHOD AND APPARATUS FOR FLASH MEMORY DEVICE - Disclosed is a method and apparatus embodying a flash translation layer (FTL) in a storage device including a flash memory. The FTL may classify a block into a sequential group and a fusion group based on a locality of a write request. The FTL may store data in blocks of the fusion group by using a page mapping scheme, and sequentially store data by using a block mapping scheme. The FTL may improve efficiency of garbage collection operation that is performed by using limited redundant blocks and also may increase efficiency of a non-sequential reference operation. | 04-01-2010 |
| 20100082887 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY - The memory controller forms temporary virtual blocks each composed of a plurality of physical blocks, whose physical addresses are the same value, each of which is included in each of flash memories, extracts temporary virtual block to which at least one defective block belongs from the temporary virtual blocks, generates a second temporary virtual block to which a defective block does not belong by replacing a defective block belonging to one temporary virtual block with a normal block belonging to another temporary virtual block among temporary virtual blocks extracted, and allocates temporary virtual blocks not extracted and second temporary virtual blocks generated to available virtual blocks. | 04-01-2010 |
| 20100082888 | Memory controller, flash memory system with memory controller, and method of controlling flash memory - In a case where at least one of physical blocks composing the virtual block becomes a defective block, use of the virtual block to which the defective block belongs is forbidden and the virtual block of which use is forbidden is managed as a defective virtual block. Replacing the defective block with a normal block is performed among the defective virtual blocks so as to generate the virtual block to which the defective block does not belong. Then use of the virtual block generated is allowed. | 04-01-2010 |
| 20100082889 | Memory controller, flash memory system with memory controller, and method of controlling flash memory - First operations and second operations are performed in parallel. The first operations are operations to write first data to a first unit area which is any one of unit areas. The second operations are operations to read second data corresponding to the same logical page as first data from one or more flash memories and write the second data to a second unit area which is any one of the unit areas and different from the first unit area. Data transfer is performed between the first unit area and the second unit area so as to form data composed of the first data and a portion of the second data which is not replaced with the first data. | 04-01-2010 |
| 20100082890 | Method of managing a solid state drive, associated systems and implementations - A solid state drive may include one or more memory cell arrays divided into a plurality of blocks. A first portion of the blocks may be designated for storing user data and a second portion of the blocks may be designated as reserved blocks for replacing defective blocks in the first portion. In one embodiment, the method includes reformatting, by a memory controller, the solid state drive to convert one or more blocks in the first portion into reserved blocks. | 04-01-2010 |
| 20100082891 | APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE DEVICES - A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface. | 04-01-2010 |
| 20100082892 | Flash Memory Controller For Electronic Data Flash Card - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input— output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 04-01-2010 |
| 20100082893 | Flash Memory Controller For Electronic Data Flash Card - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 04-01-2010 |
| 20100088458 | OPERATION METHOD OF MEMORY - An operation method of a memory includes the steps of calculating an offset of sequential write commands and the beginning of pages of a block of a non-volatile memory; shifting the block by the offset; and directly writing data from a host to the pages except the first and last pages of the block by the sequential write commands. In an embodiment, the pages are logical pages providing optimal writing efficiency and are determined before calculating the offset. The step of shifting the block by the offset is to increase corresponding logical block addresses (LBA) in the pages by the offset. | 04-08-2010 |
| 20100088459 | Improved Hybrid Drive - A non-volatile storage system comprises a hard disk drive (HDD) having a first capacity for storing information therein in a plurality of blocks. The storage system also comprises a non-volatile solid state memory (SSD) having a second capacity, less than the first capacity, for storing information therein. Finally, the storage system comprises a controller having a volatile memory and for controlling the read operation of the HDD and the read/write operation of the SSD. The controller stores in the volatile memory the address of read blocks from the HDD in a first period of time and determines a plurality of the most frequently read blocks in the first period of time, The controller then causes the SSD to store information from the most frequently read blocks from the HDD, and thereafter causes information to be read from the SSD when the storage system is requested to access information from the most frequently read blocks. The controller resets the identity of the most frequently read blocks in the volatile memory after a second period of time, where the second period of time is longer than said first period of time. | 04-08-2010 |
| 20100088460 | MEMORY APPARATUS, SYSTEMS, AND METHODS - Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed. | 04-08-2010 |
| 20100088461 | SOLID STATE STORAGE SYSTEM USING GLOBAL WEAR LEVELING AND METHOD OF CONTROLLING THE SOLID STATE STORAGE SYSTEM - A solid state storage system is disclosed including a memory area having a plurality of chips. The solid state storage system includes a micro controller unit (MCU) configured to utilize the number of deletions for logical blocks corresponding to logical block addresses when performing wear leveling on the memory area. The allocation of the logical block addresses can be performed using an interleaving process and a multi-plane method. The solid state storage system performs global wear leveling by which the lifespan of the cells of the chips can be uniformly managed. | 04-08-2010 |
| 20100088462 | METHODS FOR HANDLING DATA UPDATING OF FLASH MEMORY AND RELATED MEMORY CARDS - A method for handling data updating of a flash memory is disclosed, in which the flash memory comprises a mother block with a plurality of pages to be updated, and each page comprises a plurality of sectors. In such method, a first data for updating a target page in the mother block is obtained, and then whether the first data comprises data for updating an ending sector in the target page is determined. The first data is written into a replacing page in a first FAT block when the first data does not comprise data for updating the ending sector in the target page. The first data is written into a corresponding page in a second FAT block when the first data comprises the data for updating the ending sector, in which the corresponding page in the second FAT block and the target page in the mother block have the same page indexes. | 04-08-2010 |
| 20100088463 | NONVOLATILE MEMORY SYSTEM AND DATA PROCESSING METHOD - A solid-state disk device exchanging data with a host includes a nonvolatile memory device, a buffer memory configured to temporarily store data exchanged between the host and the nonvolatile memory, and a buffer manager configured to control transfer of data to/from the buffer memory, wherein the transfer of data between the nonvolatile memory device and the host during a streaming mode of operation begins immediately when a defined unit data is input to the buffer memory. | 04-08-2010 |
| 20100088464 | Compression Based Wear Leveling for Non-Volatile Memory - The present disclosure includes systems and techniques relating to non-volatile memory. Systems and techniques can include obtaining information to store in a non-volatile memory, the information including a data segment, compressing data within the data segment, including pad data in one or more portions of the data segment based on a compression result attained by the compression, and writing data of the data segment. | 04-08-2010 |
| 20100088465 | CONTROL DEVICE OF A STORAGE SYSTEM COMPRISING STORAGE DEVICES OF A PLURALITY OF TYPES - A control device of a storage system including a CPU which receives input information including at least a size and an archive deadline of data which is stored in storage devices; wherein data management information includes a write threshold value regarding one type of storage devices, the write threshold value indicating a write limit number to the one type of storage devices, wherein the CPU: selects a storage device which stores data corresponding to the information which is input to an input device, based on the information which is input to the input device and the data management information which is stored in the memory; CPU stores to the selected storage device, the data corresponding to the information which is input to the input device; and, registers to the data management information in the memory, at least one of the information which is input to the input device. | 04-08-2010 |
| 20100088466 | STORAGE DEVICE, STORAGE CONTROL DEVICE, AND CONTROL METHOD - According to one embodiment, a storage device includes an actuator to move a head to a position on a disk medium; a module to record or reproduce data to or from the disk medium using the head; a memory controller to write or read to or from a non-volatile memory; a buffer controller to write or read to or from a buffer memory; an interface controller to transmit and receive to or from an upper device; a switching module to switch data transfer paths among the module, the memory controller, and the interface controller; and an access controller to control the switching module to transfer data read from the non-volatile memory to the upper device concurrently with transferring and storing the read data in a cache region of the buffer memory, upon receiving from the upper device a command to read the data from the non-volatile memory. | 04-08-2010 |
| 20100095048 | SELF-CONTAINED DENSELY PACKED SOLID-STATE STORAGE SUBSYSTEM - A rack mountable solid-state storage subsystem includes a plurality of interface units and a plurality of data storage modules to implement a mass storage device. Each of the interface units may be coupled to a plurality of communication ports for connection to a host server and to other interface units. Each data storage module may be detachably mated to a corresponding connector mounted to a motherboard. Each data storage module may also include a non-volatile flash memory storage and a volatile storage. The data storage modules may be partitioned into a plurality of portions, each coupled to a respective interface unit via the motherboard. Each portion of the data storage modules and the respective interface unit to which each portion is coupled may form a separate storage domain that is isolated from each other domain. The storage subsystem may also include redundant power supplies and backup power supplies. | 04-15-2010 |
| 20100095049 | HOT MEMORY BLOCK TABLE IN A SOLID STATE STORAGE DEVICE - Solid state storage devices and methods for populating a hot memory block look-up table (HBLT) are disclosed. In one such method, an indication to an accessed page table or memory map of a non-volatile memory block is stored in the HBLT. If the page table or memory map is already present in the HBLT, the priority location of the page table or memory map is increased to the next priority location. If the page table or memory map is not already stored in the HBLT, the page table or memory map is stored in the HBLT at some priority location, such as the mid-point, and the priority location is incremented with each subsequent access to that page table or memory map. | 04-15-2010 |
| 20100095050 | COMPUTER MEMORY DEVICE WITH STATUS REGISTER - Method and apparatus for operating a memory device with a status register. In some embodiments, the memory device has a plurality of individually programmable non-volatile memory cells comprised of at least a resistive sense memory. The memory device engages an interface and maintains a status register in some embodiments by logging at least an error or busy signal during data transfer operations. | 04-15-2010 |
| 20100095051 | Memory system and a control method thereof - A control method for the memory system is suitable for a memory system to process the user data from a host. The control unit divides the address of the storage space of the host into a plurality of logical segments for accessing data. The memory system provides a storage space with a plurality of physical segments to access data. The control method comprises the following steps. Firstly, a master table is provided in the physical memory for recording the mapping relation between the addresses of the logical units and the addresses of the physical units. When the data is written, the mapping relation between the addresses of the logical units and the addresses of the physical units is adjusted according to the wear of the physical units. Finally, the data is written into the physical segment according to the master table. | 04-15-2010 |
| 20100095052 | DATA UPDATING IN NON-VOLATILE MEMORY - Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector. | 04-15-2010 |
| 20100095053 | HYBRID MULTI-TIERED CACHING STORAGE SYSTEM - A hybrid storage system comprising mechanical disk drive means, flash memory means, SDRAM memory means, and SRAM memory means is described. IO processor means and DMA controller means are devised to eliminate host intervention. Multi-tiered caching system and novel data structure for mapping logical address to physical address results in a configurable and scalable high performance computer data storage solution. | 04-15-2010 |
| 20100095054 | Memory controller, flash memory system with memory controller, and method of controlling flash memory - The memory controller comprises a data holding unit which is composed of plural unit areas each for holding data corresponding to one logical page among logical pages each composed of plural logical sectors each assigned a logical address provided from a host system. The memory controller writes data held in a unit area which holds large amounts of write data, to the flash memories, in preference to data held in a unit area which holds small amounts of write data. | 04-15-2010 |
| 20100095055 | MEMORY SYSTEM FOR DATA STORAGE AND RETRIEVAL - According to a first aspect of an embodiment of the invention, there is provided a method of data storage and retrieval for use in a solid state memory system, having a non-volatile memory, wherein data is written to the non-volatile memory in the form of at least one logical sector the method comprising: monitoring the logical sector data which is to be written to the non-volatile memory, detecting the presence of a pattern in the logical sector data, upon detecting a repetitive pattern recording the repetitive pattern of the logical sector in a sector address table in the non-volatile memory without making a record of the logical sector data in the nonvolatile memory. | 04-15-2010 |
| 20100100663 | Method of Performing Wear Leveling with Variable Threshold - A wear leveling limit and/or an overall erase count threshold used for activating wear leveling in a non-volatile memory may be adjusted by determining a stage according to a highest erase count, and determining the wear leveling limit and/or the overall erase count threshold corresponding to the stage. Wear leveling may then be performed according to the wear leveling limit and/or the overall erase count threshold. | 04-22-2010 |
| 20100100664 | STORAGE SYSTEM - Increase in read-access response time is avoided in a RAID storage system loaded with SSD. A process or is configured such that the processor sets SSD to a write-enable state, and sets different SSD, from which the same data can be acquired, to a write-disable state; allows predetermined data in CM to be written into the SSD in the write-enable state; receives a read request of data from a host computer; acquires object data of the read request from the different SSD in the case that a storage location of the data is the SSD being set to the write-enable state and transmits the acquired data to the host computer. | 04-22-2010 |
| 20100100665 | DATA UPDATE METHOD AND FLASH MEMORY APPARATUS UTILIZING THE SAME - The invention discloses a flash memory apparatus, including a plurality of blocks and a memory controller. The blocks include a first block, wherein the first block includes a first page. The memory controller receives a first data to be written into the first page of the first block. When the first page has already been written to, the memory controller further selects one of the blocks as a first cache block, writes the first data into a first cache page of the first cache block and records the number of the first block and the number of the first page into the first cache page. The memory controller further updates the first block according to the number of the first block and the number of the first page recorded in the first cache page when receiving an update command. | 04-22-2010 |
| 20100100666 | SYSTEM AND METHOD FOR CONTROLLING FLASH MEMORY USING DESCRIPTOR ARRAY - Disclosed are a system and method for controlling a flash memory using a descriptor array, which may maximize a performance of a flash memory based-storage system. The system includes a descriptor array receipt unit for receiving, from a processor, a descriptor array including, at least one descriptor corresponding to at least one operation; and a flash memory control unit for verifying the descriptor included in the descriptor array and executing a flash memory control command included in the verified descriptor, wherein the flash memory control unit executes the flash memory control command independent from the operation of the processor. | 04-22-2010 |
| 20100100667 | Flash memory system and designing method of flash translation layer thereof - The method of designing a flash translation layer includes receiving a logical address according to an external request and mapping a physical address that corresponds to the logical address. The mapping manages continuous logical addresses and physical addresses corresponding to the logical addresses as one mapping unit. | 04-22-2010 |
| 20100100668 | CONTROL METHOD FOR LOGICAL STRIPS BASED ON MULTI-CHANNEL SOLID-STATE NON-VOLATILE STORAGE DEVICE - A control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following processing steps. In Step 1, a storage space of every channel is partitioned into a plurality of storage units of equal size. In Step 2, at least one logical strip is set by which the storage units with discrete physical addresses across a plurality of channels are organized into a continuous logical space. In Step 3, during data reading/writing operation, the data is divided according to a size of each local strip, the divided data is mapped to the storage units of every channel, and a parallel reading/writing operation is performed across the channels. This method may increase the efficiency of reading and writing operations of the storage device and prolong the operating life span of the device. | 04-22-2010 |
| 20100100669 | SELF-ADAPTIVE CONTROL METHOD FOR LOGICAL STRIPS BASED ON MULTI-CHANNEL SOLID-STATE NON-VOLATILE STORAGE DEVICE - A self-adaptive control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following steps. Storage space of every channel is divided into a plurality of storage units of equal size. At least one logical strip is set by which the storage units with discrete physical addresses across the channels are organized into a continuous logical space, and a logical strip variable is set for determining the storage units organized by the logical strip. Historical operation information of the storage device is obtained statistically, and the logical strip variable is dynamically adjusted according to the obtained operation information. During data interaction, the data is divided according to the logical strip variable, the divided data is mapped to the storage units of every channel, and parallel reading and writing operations are performed among the channels. | 04-22-2010 |
| 20100106887 | FLASH PRESENTATION (FLAPRE) AUTHORING TOOL THAT CREATES FLASH PRESENTATIONS INDEPENDENT OF A FLASH SPECIFICATION - A system for authoring a FLASH presentation can include a FLASH-based FLASH presentation (FLAPRE) authoring tool and a launching application. The FLAPRE authoring tool can be configured to create a specialized FLAPRE code file containing a user-created FLASH presentation. The specialized FLAPRE code file can be created without the use of a FLASH specification. The launching application can be configured to present the FLASH-based FLAPRE authoring tool. The launching application can also support the use of FLASH animation. | 04-29-2010 |
| 20100106888 | Method and System For Device Independence In Storage Device Wear Algorithms - A device, methods and systems that provide device independence in storage device wear algorithms are disclosed. A storage device that provides such device independence includes a device-specific wear algorithm, and may also include an integrated wear algorithm. The device-specific wear algorithm is configured to be loaded into a wear algorithm space and is at least a portion of a wear algorithm. The device-specific wear algorithm is stored in the storage device. The integrated wear algorithm, if employed, is resident in the storage device. A method that provides such device independence is also disclosed. The method includes loading a device-specific wear algorithm from a storage device into a wear algorithm space. The device-specific wear algorithm is configured to be stored in the storage device and loaded into the wear algorithm space. The device-specific wear algorithm is at least a portion of a wear algorithm. | 04-29-2010 |
| 20100106889 | SOLID STATE DRIVE OPERATION - The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming operation is programmed to two or more locations in memory of the solid state drive. The method also includes ceasing to mirror programming operations upon an occurrence of a particular event. | 04-29-2010 |
| 20100106890 | METHOD AND APPARATUS FOR ENFORCING A FLASH MEMORY CACHING POLICY - Methods, apparatus and computer medium for enforcing one or more cache management policies are disclosed herein. In some embodiments, a flash memory of a storage device includes a plurality of flash memory dies each flash memory die including a respective cache storage area and a respective main storage area. A determination is made, for data that is received from an external host device to which main storage area the received data is addressed thereby specifying one of the plurality of flash memory dies as a target die for the received data. Whenever the received data is written into a cache storage area before being written into a main storage area, the received data is written into the cache storage area of the specified target die. | 04-29-2010 |
| 20100106891 | Preventing Unintended Permanent Write-Protection - An input voltage range may be established between different voltage levels used for different programming functions of an integrated circuit device, thus implementing a protection zone (“safe zone”) of non-operation to facilitate prevention of an unintended irreversible programming operation, e.g., permanent write protection. | 04-29-2010 |
| 20100106892 | Access Methods For Memory Devices And Memory Devices Thereof - An access method for use in a memory device is provided. The memory device comprises a data area having a plurality of data blocks and a spare area having a plurality of spare blocks. First, data from a host is received. A spare block is popped from the spare area and the received data is programmed into the popped spare block accordingly. A data block corresponding to the data is pushed to the spare area. The pushed data block is erased when the memory device is waiting for a specific instruction to be issued from the host. | 04-29-2010 |
| 20100106893 | PAGE BUFFER PROGRAM COMMAND AND METHODS TO REPROGRAM PAGES WITHOUT RE-INPUTTING DATA TO A MEMORY DEVICE - A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place. | 04-29-2010 |
| 20100106894 | Method of storing and accessing error correcting code in NAND Flash - A method of storing and accessing an error correcting code in NAND Flash, includes utilizing n pages of a block of the NAND Flash as an extended space of a spare area, n≦1, wherein when writing data, the data is stored in a data area of a sector, and when the error correcting code needs a space which has correcting capability larger than 16 bytes, first 16 bytes of the error correcting code is stored in the 16 bytes spare area, and the remaining of the error correcting code is stored in the extended space of the spare area corresponding to the sector. Therefore, the method develops new storing space for the error correcting code, arranges the error correcting code in sequence of data blocks in sub-space, and loads the error correcting code into system memory for the decoder before reading original data. | 04-29-2010 |
| 20100106895 | Hardware and Operating System Support For Persistent Memory On A Memory Bus - Implementations of a file system that is supported by a non-volatile memory that is directly connected to a memory bus, and placed side by side with a dynamic random access memory (DRAM), are described. | 04-29-2010 |
| 20100106896 | METHOD FOR WRITING AND READING DATA IN AN ELECTRICALLY ERASABLE AND PROGRAMMABLE NONVOLATILE MEMORY - A method for writing and reading data in a main nonvolatile memory having target pages in which data are to be written and read, the method including providing a nonvolatile buffer having an erased area, providing a volatile cache memory, and receiving a write command to update a target page with updating data the length of which can be lower than the length of a page. The method also includes, in response to the write command, writing the updating data into the erased area of the nonvolatile buffer, together with management data of a first type, and recording an updated version of the target page in the cache memory or updating in the cache memory a previously updated version of the target page. | 04-29-2010 |
| 20100106897 | STORAGE DEVICE, DISK DEVICE, WRITE DETERMINING METHOD, AND CONTROL DEVICE - According to one embodiment, a storage device divides and writes into pages a management information table for managing addresses at which data are written. The storage device includes: a writing module configured to write a duplicate of a last page of the management information table after writing the management information table divided into the pages; an acquiring module configured to acquire the last page and the duplicate of the last page written by the writing module; and a determining module configured to determine whether the writing of the management information table has been successful, by comparing the last page and the duplicate of the last page acquired by the acquiring module with each other, or by checking whether the duplicate of the last page has been written by the writing module. | 04-29-2010 |
| 20100106898 | STORAGE AND REPRODUCTION APPARATUS - The storage and reproducing apparatus includes a signal processing block, a memory, a reproduction block, an operation block, and a control block. The signal processing block converts a sound signal entered, into a digital signal. The memory stores a digital signal outputted form the signal processing block and a management data of the digital data. The reproduction block at least converts a digital signal read out from the memory, into a hearable sound for reproduction output. The operation block is provided on an apparatus main body and includes a rotary operation block provided on the apparatus main body in such a manner that the rotary operation block can be rotated around a rotation center and shifted along plane which almost orthogonally intersects the rotation center. The control block, according to an input from the operation block, writes a digital signal and a management data into the memory and reads out a digital signal and a management data stored in the memory. The control block, according to a rotation direction of the rotary operation block, reads out a management data from the memory. When the rotary operation block is shifted along the plane, the control block reads out a digital signal from the memory according to a management information which is being read out from the memory. | 04-29-2010 |
| 20100115175 | Method of managing a large array of non-volatile memories - The present invention provides a non-volatile flash memory management system and method that provides the ability to efficiently manage a large array of flash devices and allocate flash memory use in a way that improves reliability and longevity, while maintaining excellent performance. The invention mainly comprises of a processor, an array of flash memories that are modularly organized, an array of module flash controllers and DRAM caching. The processor manages the above mention large array of flash devices with caching memory through mainly two tables: Virtual Zone Table and Physical Zone Table, a number of queues: Cache Line Queue, Evict Queue, Erase Queue, Free Block Queue, and a number of lists: Spare Block List and Bad Block List. | 05-06-2010 |
| 20100115176 | DATA TRANSFER AND PROGRAMMING IN A MEMORY DEVICE - Methods for data transfer and/or programming a memory device, memory devices and memory systems are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example. | 05-06-2010 |
| 20100115177 | DATA STORAGE DEVICES - A data storage device includes a non-volatile memory array, a user input device, and a host interface adapted to connect the data storage device to a host device and convey data to the host device. In response to a first operation of the user input device, application configuration data is communicated from the data storage device to the host device. The application configuration data is configured to trigger execution by the host device of a configuration application that includes a listing of a plurality of applications for display by the host device allowing a user to identify a selected application. In response to selection of an application, application designation data is generated and stored in the non-volatile memory array. In response to a second operation of the user input device, the application designation data is communicated to the host device to trigger automatic execution by the host device of the selected application. | 05-06-2010 |
| 20100115178 | System and Method for Hierarchical Wear Leveling in Storage Devices - Systems and methods for reducing problems and disadvantages associated with wear leveling in storage devices are disclosed. A method may include maintaining module usage data associated with each of a plurality of storage device modules communicatively coupled to a channel. The method may also include maintaining device usage data associated with each of the plurality of storage devices associated with the storage device module for each of the plurality of storage device modules. The method may additionally include determining a particular storage device module of the plurality of storage device modules to which to store data associated with a write request based at least on the module usage data. The method may further include determining a particular storage device of the particular storage device module to which to store data associated with a write request based at least on the device usage data associated with the particular storage device module. | 05-06-2010 |
| 20100115179 | MEMORY MODULE INCLUDING VOLTAGE SENSE MONITORING INTERFACE - Memory devices and systems include a voltage sense line for addressing voltage tolerances across variable loadings. The memory devices and systems comprise a memory module connector with a first plurality of pins coupled to circuitry on a memory module, and a second plurality of pins coupled to power rails on the memory module that enable monitoring of the power rails from external to the memory module. | 05-06-2010 |
| 20100115180 | MEMORY MODULE INCLUDING ENVIRONMENTAL OPTIMIZATION - A memory apparatus enable operation which is adapted to environmental conditions. The memory apparatus includes a memory module that can store and incorporate environment-dependent optimal operating parameters. The memory module comprises a plurality of volatile memory devices and one or more non-volatile memory devices that store a plurality of environment-dependent device parameters for a device selected from the plurality of volatile memory devices. The stored parameters enable the selected device to function optimally in multiple environmental conditions. | 05-06-2010 |
| 20100115181 | MEMORY DEVICE AND METHOD - A memory device may include a volatile memory and a non-volatile memory which are arranged to be accessed via a common bus. The memory device may include a controller that is arranged as an interface between the common bus and the volatile and non-volatile computer memories, the controller to transmit read/write commands from the common bus to either the volatile memory or the non-volatile memory. | 05-06-2010 |
| 20100115182 | FLASH MEMORY OPERATION - An embodiment is a technique to improve operations of flash memory devices. A plurality of logical block numbers is mapped to a plurality of physical block numbers using a mapper. The physical block numbers are associated with blocks in a flash memory device. A plurality of block statuses of the plurality of free physical block numbers is stored in a replacement table. Each of the block statuses is one of a ready, dirty, and broken status. A destination block in the blocks is written to. The destination block has the ready status. The mapper and the replacement table are updated. | 05-06-2010 |
| 20100115183 | Storage Apparatus and Method of Managing Data Storage Area - Disclosed is a storage apparatus that extends endurance and reduces bit cost. A storage apparatus includes a controller and a semiconductor storage media that has a plurality of storage devices. The plurality of storage devices include a first storage device and a second storage device having an upper limit of an erase count of data smaller than that of the first storage device. Area conversion information includes correspondence of a first address to be specified as a data storage destination and a second address of an area in which data is to be stored. A rewrite frequency of stored data is recorded for each area. The controller selects an area corresponding to the first address, determines whether or not the rewrite frequency of the selected area is equal to or larger than a first threshold value, when the rewrite frequency is equal to or larger than the threshold value, selects an area to be provided by the first storage device, and when the rewrite frequency is smaller than the threshold value, selects an area to be provided by the second storage device and maps the address of the selected area to the first address. | 05-06-2010 |
| 20100115184 | FLASH MEMORY STORAGE SYSTEM AND CONTROLLER AND DATA PROTECTION METHOD THEREOF - A flash memory storage system including a controller and a flash memory chip is provided, wherein the controller is disposed with a rewritable non-volatile memory. When the controller writes a security data into the flash memory chip, the controller randomly generates a data token and generates a message digest according to the security data and the data token by using a one-way hash function, wherein the data token and the message digest are respectively stored in the rewritable non-volatile memory and the flash memory chip. Subsequently, when the controller reads the security data from the flash memory chip, the controller determinates whether the security data is falsified according to the data token and the message digest respectively stored in the rewritable non-volatile memory and the flash memory chip. Thereby, the security data in the flash memory chip can be effectively protected. | 05-06-2010 |
| 20100115185 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - Without corresponding to different address spaces between an access device ( | 05-06-2010 |
| 20100115186 | FLASH MEMORY DEVICE WITH WEAR-LEVELING MECHANISM AND CONTROLLING METHOD THEREOF - A flash memory device with a wear-levelining mechanism includes at least one flash memory, a hot list, a bitmap, a source pointer, and a controller. The controller obtains a physical memory block with high erase count through the hot list, an erase count of the physical memory block, and an overall average erase count of the flash memory device. The controller further finds out a physical memory block which stores static data through managing the bitmap and the source pointer. The controller moves the static data to the physical memory block with high erase count, and releases the physical memory block which stores the static data to avoid the physical memory block with high erase count being worn down increasingly more seriously. | 05-06-2010 |
| 20100115187 | NON-VOLATILE DATA STORAGE SYSTEM AND METHOD THEREOF - A non-volatile data storage system including a first non-volatile storage medium, a second non-volatile storage medium, and a microprocessor is provided. The first non-volatile storage medium includes a popular data address recording area for recording logic addresses of popular data in the first non-volatile storage medium. The microprocessor is coupled to the first non-volatile storage medium and the second non-volatile storage medium. When the non-volatile data storage system boots up, the microprocessor copies the popular data from the first non-volatile storage medium to the second non-volatile storage medium according to the popular data address recording area. The popular data is accessed in the second non-volatile storage medium instead of the first non-volatile storage medium. | 05-06-2010 |
| 20100115188 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording usage information of at least one block during accessing pages of the block; and determining whether to erase a portion of the blocks according to the usage information. For example, the usage information includes a valid page count table for recording valid page counts of the blocks, respectively; and the ranking of a field of the valid page count table represents a physical block address, and the content of the field represents an associated valid page count. In another example, the usage information includes an invalid page count table for recording invalid page counts of the blocks, respectively; and the ranking of a field of the invalid page count table represents a physical block address, and the content of the field represents an associated invalid page count. | 05-06-2010 |
| 20100115189 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the local page address linking table comprises linking relationships between physical page addresses and logical page addresses of a plurality of pages; and building a global page address linking table of the memory apparatus according to the local page address linking table. | 05-06-2010 |
| 20100115190 | SYSTEM AND METHOD FOR PROCESSING READ REQUEST - A system for processing a read request for maximizing host read performance in a flash memory-based storage device is provided. The system for processing the read request solves a bottleneck phenomenon caused by a processor by adding an independent automatic read request processor, different from a conventional system in which a processor of a storage device processes the read request. Also, when processing the read request, a storage device using a write buffer may control a process of merging data of the write buffer and a flash memory and transmitting the data to a host based on a descriptor array, thereby minimizing processor overhead. | 05-06-2010 |
| 20100115191 | System Including Hierarchical Memory Modules Having Different Types Of Integrated Circuit Memory Devices - A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy. | 05-06-2010 |
| 20100115192 | WEAR LEVELING METHOD FOR NON-VOLATILE MEMORY DEVICE HAVING SINGLE AND MULTI LEVEL MEMORY CELL BLOCKS - A method of executing a wear leveling operation within a non-volatile memory including a single-level memory cell block (SLC) and a multi-level memory cell block (MLC) is disclosed. The method includes calculating an average erase point in relation to a number of programming/erase (P/E) operations applied to a logical block address (LBA), a SLC mode usage point in relation to a number of the P/E operations applied to the SLC, a MLC mode usage point in relation to a number of the P/E operations applied to the MLC, and a wear value in relation to the average erase point, the SLC mode usage point, and the MLC mode usage point; and then if the wear value exceeds a defined threshold value, performing the wear leveling operation. | 05-06-2010 |
| 20100115193 | SYSTEM AND METHOD FOR IMPROVING DATA INTEGRITY AND MEMORY PERFORMANCE USING NON-VOLATILE MEDIA - A system and computer system for improving data integrity and memory performance using non-volatile media. A system includes a non-volatile mass storage unit, e.g., a flash memory device and/or a hard drive unit for instance. A memory device is used as a high speed data buffer and/or cache for the non-volatile storage unit. The memory device may be non-volatile, e.g., magnetic random access memory (MRAM) or volatile memory, e.g., static dynamic random access memory (SDRAM). By buffering and/or caching the write data, fewer accesses are required to the mass storage device thereby increasing system performance. Additionally, mechanical and electrical degradation of the mass storage device is reduced. Certain trigger events can be programmed to cause data from the memory device to be written to the mass storage device. In one embodiment, the write buffer contents are preserved across reset or power loss events. In one embodiment, the mass storage unit may be a data transport layer, e.g., Ethernet, USB, Bluetooth, etc. | 05-06-2010 |
| 20100115194 | SEMICONDUCTOR MEMORY INFORMATION STORAGE APPARATUS AND METHOD OF CONTROLLING WRITING - A semiconductor memory information storage apparatus includes a storage unit using a nonvolatile memory, a write number manager counting each of numbers of times of writing of all blocks, a list manager classifying the blocks in the nonvolatile memory by in-use/unused, managing in an in-use list a block of the in-use, managing in a first unused list a block with the number of times of writing equal to a maximum value, and managing in a second unused list a block with the number of times of writing less than the maximum value, and a controller writing and erasing information data to and from the storage unit. | 05-06-2010 |
| 20100122014 | Method For Protecting Memory Proprietary Commands - A method for protecting memory proprietary command is provided. By using the logic block area (LBA) address in the header of the LBA mode, the device end can determine whether the data sector in the LBA mode includes a proprietary command. Also, by using the pre-defined computation function to establish a relation among the values stored in a plurality of characteristic point addresses and a specific point address so that he device end can determine whether a proprietary command is received. As the operating system will not filter out the proprietary command wrapped in this manner, the proprietary command can pass the operating system and be executed by the device end. | 05-13-2010 |
| 20100122015 | SOFTWARE ADAPTED WEAR LEVELING - A subset of software objects stored in a first segment of non-volatile memory are identified as requiring frequent write operations or otherwise associated with a high endurance requirement. The subset of software objects are move to a second segment of non-volatile memory with a high endurance capacity, due to the application of wear leveling techniques to the second segment of non-volatile memory. The first and second segments of memory can be located in the same memory device or different memory devices. | 05-13-2010 |
| 20100122016 | DYNAMIC SLC/MLC BLOCKS ALLOCATIONS FOR NON-VOLATILE MEMORY - Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode. | 05-13-2010 |
| 20100122017 | MEMORY CONTROLLER, NON-VOLATILE MEMORY SYSTEM, AND HOST DEVICE - Provided is a nonvolatile memory system which can be used for a boot program storage and easily controlled by a host device. At the time of reading a boot code | 05-13-2010 |
| 20100122018 | BACKUP METHOD, BACKUP DEVICE, AND VEHICLE CONTROLLER - A backup method includes the following processes. Backup data is temporarily stored in a volatile memory. An erased area is saved in a flash memory for the backup data. The erased area is free of data. The backup data is written in the erased area. | 05-13-2010 |
| 20100122019 | APPARATUS, SYSTEM, AND METHOD FOR MANAGING PHYSICAL REGIONS IN A SOLID-STATE STORAGE DEVICE - An apparatus, system, and method are disclosed for managing physical regions in a solid-state storage device. The definition module defines a physical storage region on solid-state storage media of a solid-state storage device. The physical storage region includes a subset of total physical storage capacity on the solid-state storage media. The storage controller performs memory operations within the physical storage region such that the memory operations are bounded to the physical storage region. The implementation module implements the physical storage region definition with respect to the storage controller for the solid-state storage media. | 05-13-2010 |
| 20100122020 | DYNAMIC PERFORMANCE VIRTUALIZATION FOR DISK ACCESS - A storage control system includes performance monitor logic configured to track performance parameters for different volumes in a storage array. Service level enforcement logic is configured to assign target performance parameters to the different volumes and generate metrics for each of the different volumes identifying how much the performance parameters change for the different volumes responsive to changes in the amounts of tiering media allocated to the different volumes. Resource allocation logic is configured to allocate the tiering media to the different volumes according to the performance parameters, target performance parameters, and metrics for the different volumes. | 05-13-2010 |
| 20100122021 | USB-Attached-SCSI Flash-Memory System with Additional Command, Status, and Control Pipes to a Smart-Storage Switch - An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access. | 05-13-2010 |
| 20100122022 | SSD WITH IMPROVED BAD BLOCK MANAGMENT - In some embodiments, a memory controller includes a plurality of processors of a first type and a processor of a second type coupled to the processors of the first type. Each of the plurality of processors of the first type is configured to determine a bad block rate of a memory channel of a solid state memory device to which it is configured to be coupled. The processor of the second type is configured to receive the bad block data rates from each of the plurality of processors of the first type and to report one of a total capacity or a bad block rate of the solid state memory device to a host device. The total capacity and the bad block rate of the solid state memory device are based on the bad block rates received from each of the plurality of processors of the first type. | 05-13-2010 |
| 20100125695 | NON-VOLATILE MEMORY STORAGE SYSTEM - The present invention discloses a flash memory storage system, comprising at least one RAID controller; a plurality of flash memory cards electrically connected with the RAID controller; and a cache memory electrically connected with the RAID controller and shared by the RAID controller and the flash memory cards. The cache memory efficiently enhances the system performance. The storage system may comprise more RAID controllers to construct a nested RAID architecture. | 05-20-2010 |
| 20100125696 | Memory Controller For Controlling The Wear In A Non-volatile Memory Device And A Method Of Operation Therefor - A memory controller controls the operation of a non-volatile memory device. The memory device has a data storage section and an erased storage section. The data storage section has a first plurality of blocks and the erased storage section has a second plurality of blocks. Each of the first and second plurality of blocks has a plurality of non-volatile memory bits that are erased together. Further, each block has an associated counter for storing the number of times the block has been erased. The memory controller has program instructions which are to scan the counters associated with the blocks of the first plurality of blocks based upon the count contained in each of the counters associated therewith to select a third block, and to scan the counters associated with the blocks of the second plurality of blocks based upon the count contained in each of the counters associated therewith to select a fourth block. The program instructions are further configured to transfer data from the third block to the fourth block, and associating said fourth block with said first plurality of blocks. Finally the program instructions are configured to erase said third block and incrementing the counter associated with said third block, and associating said third block with said second plurality of blocks. The present invention is also a method of operating a non-volatile memory device in accordance with the above described steps. | 05-20-2010 |
| 20100125697 | COMPUTING DEVICE HAVING STORAGE, APPARATUS AND METHOD OF MANAGING STORAGE, AND FILE SYSTEM RECORDED RECORDING MEDIUM - A storage management apparatus and a file system for a storage device are provided. The storage management apparatus allocates a portion of storage for writing a file to the storage, including a table storing unit storing an allocation unit table that includes information of a unit of allocation of the storage according to a file extension of a file to be written. A storage management unit manages the storage based on the allocation unit table. | 05-20-2010 |
| 20100125698 | RECORDABLE MEMORY DEVICE - A recordable memory device includes a nonvolatile semiconductor memory, and a controller controlling the nonvolatile semiconductor memory based on a recordable system. The nonvolatile semiconductor memory has a user area capable of directly making an access from a host, and a system area managed by the controller. A data writing to the reformatted user area of the nonvolatile semiconductor memory executes from a start point which is an unused area after the final physical address of old recordable data recorded in the user area before the reformat. The data writing executes from a start point which is a top physical address in the user area, when the start point exceeds the final physical address in the user area. | 05-20-2010 |
| 20100125699 | Flash memory device and reading method thereof - Provided are a flash memory device and a reading method of the flash memory device. A multi-level cell flash memory device includes: a memory cell array comprising main memory cells storing main data, and indicator cells storing indicate data indicating one of a first mode and a second mode in which the main data of the main memory cell, to which the indicate cells correspond, is written; and an output unit outputting in response to a control signal corresponding to the indicate data, one of main data read from the memory cell array and forced data forcing some bit values of the main data to bit values of mode specific data, as reading data. | 05-20-2010 |
| 20100125700 | DISK DRIVE AND METHOD OF CHANGING A PROGRAM THEREFOR - A method of changing a program for controlling a disk drive that includes an EEPROM. The method includes storing a program block to a disk area such that the program block is associated with a second area for storing the program block that is not utilized for a read operation from the disk area. The method also includes storing a program block that is associated with a first area to an area that includes at least a portion of the second area in the EEPROM such that the first area contained a program block that is utilized for a read operation from the disk area. In addition, the method includes changing the program block in the first area after storing to the second area. Moreover, the method includes storing to the second area the program block that is not utilized for a read operation from the disk area after storing to the first area. | 05-20-2010 |
| 20100125701 | Multi-Level Non-Volatile Memory Device, Memory System Including the Same, and Method of Operating the Same - Methods of programming nonvolatile memory devices include programming a plurality of nonvolatile multi-state memory cells in the non-volatile memory device with state-converted data derived from non-state-converted data. This state-converted data may be associated with a greater number of erased states relative to the non-state-converted data, when programmed into the plurality of nonvolatile memory cells. The methods also include generating a flag having a value that indicates which ones of the plurality of nonvolatile memory cells have been programmed with data that is swapped with data in other ones of the plurality of nonvolatile memory cells. This flag may also be programmed into the nonvolatile memory device. Operations may also be performed to read the state-converted data (and flag) from the plurality of nonvolatile memory cells and then decode the state-converted data into the non-state-converted data, based on the value of the flag. | 05-20-2010 |
| 20100125702 | Non-Volatile Memory System and Access Method Thereof - Disclosed is a method for accessing a non-volatile memory device using a flash translation layer. The method includes receiving a write request for data from a file system and recording the data in the non-volatile memory device in response to the write request. The flash translation layer is informed whether a confirm mark for the data is recorded or not from the file system. | 05-20-2010 |
| 20100131695 | Method for Utilizing a Memory Interface to Control Partitioning of a Memory Module - Apparatuses and methods for implementing partitioning in memory cards and modules where conventional memory cards or modules have only a single partition. A representative memory card/module in accordance with the invention includes a memory devices), and a memory interface which includes a data bus, a command line and a clock line. The memory card/module further includes a memory controller coupled to the memory device(s) and to the memory interface. The memory card/module includes means for controlling the partitioning of the memory device(s), and the memory controller is configured to operate the memory device(s) in accordance with the partition information. | 05-27-2010 |
| 20100131696 | System and Method for Information Handling System Data Redundancy - Flash memory integrated in a hard disk drive chassis maintains a back-up copy of data stored on the hard disk drive between back-ups of the hard disk drive data to separate storage devices. If the hard disk drive fails, the data on the flash memory provides a back-up of changes made since the previous hard disk drive back-up. When a back-up is made of data stored on the hard disk drive to an external storage device, the back-up on the flash memory device is erased to make room for subsequent back-up data. If back-up data stored on the flash memory approaches the capacity of the flash memory, a notice is provided to an end user that a back-up is needed. | 05-27-2010 |
| 20100131697 | METHODS FOR TAG-GROUPING OF BLOCKS IN STORAGE DEVICES - Embodiments described herein disclose methods, devices, and media for storing data. Methods including the steps of: receiving data to be stored in a memory that includes at least three blocks, wherein each block, for storing the data, has at least one metadata value, associated with each block, that is dependent upon a writing time of each block; grouping at least three blocks into at least two block groups, wherein at least one block group contains at least two blocks; associating a respective metadata value with each block group; and associating the respective metadata value of a respective block group with each block storing the data contained in the respective block group, without storing a dedicated copy of at least one metadata value for each block. In some embodiments, at least one metadata value is stored in a block-group table. | 05-27-2010 |
| 20100131698 | MEMORY SHARING METHOD FOR FLASH DRIVER - A memory sharing method for flash driver includes determining a target memory size corresponding to a target flash driver, and loading a target flash program included in the target flash driver into a stack memory allocated in a specific memory device when an unused size of the stack memory available for data storage is greater than the target memory size. Additionally, the step of determining the target memory size includes determining a specific flash program having a maximum size among a plurality of flash programs included in the target flash driver, and setting the target memory size equal to the maximum size of the specific flash program. | 05-27-2010 |
| 20100131699 | METHODS, APPARATUSES, AND COMPUTER PROGRAM PRODUCTS FOR ENHANCING MEMORY ERASE FUNCTIONALITY - A method, apparatus, and computer program product are provided for enhancing memory erase functionality. An apparatus may include a block-based mass memory and a controller configured to receive an erase command from a host device comprising an indication of a location of a block in the mass memory storing memory allocation data. The controller may be further configured to access the memory allocation data based at least in part upon the indicated location. The controller may additionally be configured to determine, based at least in part upon the memory allocation data, blocks within the mass memory that have been freed by the host device. The controller may also be configured to erase the freed blocks. Corresponding methods and computer program products are also provided. | 05-27-2010 |
| 20100131700 | MEMORY INDEXING SYSTEM AND PROCESS - The invention relates to a memory index management system. The said system comprises an indexed storage memory, a memory zone containing the index and a microprocessor. The index is built in the form of a hierarchical tree structure and comprises at least two nodes. A node contains an identifier associated with a pointer that references either a node of the index or a memory zone in the storage memory. The content of a node is distributed over a first and a second memory zone that are separate in the memory zone. The first space has a first specific pointer that points to the second space and the second space has a second specific pointer whose value has a blank state. | 05-27-2010 |
| 20100131701 | NONVOLATILE MEMORY DEVICE WITH PREPARATION/STRESS SEQUENCE CONTROL - Provided is a nonvolatile memory device which includes a command buffer configured to receive and store a sequence of first and second commands, a memory including an array of nonvolatile memory cells, and an operation controller configured to control the execution of first and second operations in the memory as respectively defined by the first and second commands, wherein each one of the first and second operations comprises a preparation sequence followed by a stress sequence, and execution of the preparation sequence for the second operation is parallel with the stress sequence of the first operation. | 05-27-2010 |
| 20100131702 | SINGLE SEGMENT DATA OBJECT MANAGEMENT - A single segment data structure and method for storing data objects employing a single segment data object having a header and a data record. The header includes a segment length field describing the length of memory reserved for the data record and the data record contains at least one data instance object. Each of the data instance objects has a data instance header and data field. The header includes a data instance state field and a data instance length field. The data instance length field contains data representing the length of the data instance data field allowing for variable length “in place” updating. The data instance state field contains data representing an object state of the instance data. Only one of the data instance objects of the data record of the single segment data object has a valid object state. The state field facilitates a power loss recovery process. | 05-27-2010 |
| 20100138588 | MEMORY CONTROLLER AND A METHOD OF OPERATING AN ELECTRICALLY ALTERABLE NON-VOLATILE MEMORY DEVICE - A controller operates a NAND non-volatile memory device which has an array of non-volatile memory cells. The array of non-volatile memory cells is susceptible to suffering loss of data stored in one or more memory cells of the array. The controller interfaces with a host device and receives from the host device a time-stamp signal. The controller comprises a processor, and a memory having program code stored therein for execution by the processor. The program code is configured to receive by the controller the time stamp signal from the host device; to compare the received time stamp signal with a stored signal wherein the stored signal is a time stamp signal received earlier in time by the controller from the host device; and to determine when to perform a data retention and refresh operation for data stored in the memory array based upon the comparing step. | 06-03-2010 |
| 20100138589 | STORAGE OPTIMIZATIONS BY DIRECTORY COMPACTION IN A FAT FILE SYSTEM - Storage optimizations by directory compaction in a file allocation table (FAT) file system. The method comprises determining if a cluster comprises a deleted content, indicating that the deleted content is deleted, and updating an entry of a FAT associated with the cluster to indicate that the cluster is free. The method may also comprise indicating that the deleted content is deleted and modifying a metadata of at least one of a file of the cluster and a directory of the cluster according to a specified protocol. | 06-03-2010 |
| 20100138590 | CONTROL APPARATUS FOR CONTROLLING PERIPHERAL DEVICE, NON-VOLATILE STORAGE ELEMENT, AND METHOD THEREOF - A control apparatus for controlling at least one peripheral device includes a non-volatile storage element and a controller. The non-volatile storage element is used for storing at least one control information set. The controller is externally coupled to the non-volatile storage element and includes a read-only storage element which stores a segment of program code. The controller loads the segment of program code to execute the segment of program code for reading at least one portion of the control information set from the non-volatile storage element to control the operation of the peripheral device. | 06-03-2010 |
| 20100138591 | MEMORY SYSTEM - A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller stores management information of data stored in the second storing unit during a startup operation into the first storing unit and performs data management while updating the management information. The management information in a latest state stored into the first storing unit is also stored in the second storing unit. The management information includes a pre-log before and after change generated before a change occurs in the management information and a post-log, which is generated after the change occurs in the management information, concerning the change in the management information. The pre-log and the post-log are stored in the same areas of different blocks. | 06-03-2010 |
| 20100138592 | Memory device, memory system and mapping information recovering method - Disclosed is a memory device which comprises a data storing part having plural physical storage spaces; and a control part for storing data in the data storing part, wherein each of the physical storage spaces comprises a main area for storing user data at a write operation and a spare area for storing additional data other than the user data, the additional data including a logical address corresponding to a physical storage space and a link value indicating a physical storage space to be accessed next. | 06-03-2010 |
| 20100138593 | MEMORY CONTROLLER, SEMICONDUCTOR RECORDING DEVICE, AND METHOD FOR NOTIFYING THE NUMBER OF TIMES OF REWRITING - User data transferred from a host apparatus and a first information table | 06-03-2010 |
| 20100138594 | FLASH MEMORY DATA READ/WRITE PROCESSING METHOD - A flash memory data read/write processing method is provided. The method includes the following steps. An encoding process is performed on the data to be written so that a number of a specific value in the encoded data is reduced compared with that in the original data, and the encoded data is written into a flash memory chip. The encoded data in the flash memory chip is read out, then a decoding process corresponding to the encoding process in Step 1 is performed on the read data, and finally, the decoded data is output. This method may reduce the consumption of a flash memory chip due to writing and erasing operations, thereby prolonging the operating life span of the flash memory chip. This method may also increase the efficiency of writing and erasing operations, reduce the operating time, as well as reduce the power consumption of flash memory operations. | 06-03-2010 |
| 20100138595 | SEMICONDUCTOR DEVICE COMPRISING FLASH MEMORY AND ADDRESS MAPPING METHOD - A semiconductor device with flash memory includes; a log type determining unit configured to select log type from among a plurality of log types with respect to a log block storing program data requested to be programmed in the flash memory and generate a control signal indicating information indicating the selected log type, and a plurality of log units configured to store program data in the log block having a corresponding log type in response to the control signal, wherein the log type determining unit converts a first type log block formed by a first log type and included in a first type log unit from among the plurality of log units into second type log block formed by a second log type and converts the log block included in a second type log unit from among the plurality of log units into the first type log blocks, the first loge type being different from the second log type. | 06-03-2010 |
| 20100146186 | Program Control of a non-volatile memory - A method of storing data onto a non-volatile memory includes receiving, from a host, first data that is originally assigned to a first storage area, programming the first data to a second storage area, receiving second data from the host, and while receiving the second data from the host, programming, to the first storage area, the first data that has been programmed to the second storage area, wherein the second data is received from the host simultaneously with the first data being programmed to the first storage area. The second storage area is capable of having data stored thereon faster than the first storage area. | 06-10-2010 |
| 20100146187 | ENDURANCE MANAGEMENT TECHNIQUE - According to embodiments of the present invention, endurance management techniques are disclosures. Adherence to endurance and data retention ratings are ensured by managing write accesses to a memory device. | 06-10-2010 |
| 20100146188 | REPLICATED FILE SYSTEM FOR ELECTRONIC DEVICES - Disclosed is a method, system, and computer readable medium for correcting corrupted data in an embedded file system (EFS) within a non-volatile memory (NVM) system. The NVM System further includes a replicated file system (RFS). A memory comparison is performed between EFS memory sectors and corresponding RFS memory sectors to identify any RFS memory sectors that are out of sync with their corresponding EFS memory sectors. Those memory sectors that are out of sync are then erased and rewritten. | 06-10-2010 |
| 20100146189 | Programming Non Volatile Memories - Non volatile memories and methods of programming thereof are disclosed. In one embodiment, the method of programming a memory array includes receiving a series of data blocks, each data block having a number of bits that are to be programmed, determining the number of bits that are to be programmed in a first data block, determining the number of bits that are to be programmed in a second data block, and writing the first and the second data blocks into a memory array in parallel if the sum of the number of bits that are to be programmed in the first data block and the second data block is not greater than a maximum value. | 06-10-2010 |
| 20100146190 | FLASH MEMORY STORAGE SYSTEM, AND CONTROLLER AND METHOD FOR ANTI-FALSIFYING DATA THEREOF - A flash memory storage system is provided. The flash memory storage system includes a controller having a rewritable non-volatile memory and a flash memory chip. The rewritable non-volatile memory stores a data token and the flash memory chip stores a security data and a message digest. When the security data in the flash memory chip is updated, the controller updates the data token and generates an eigenvalue, and updates the message digest according to the updated data token and the updated eigenvalue by using a one-way hash function, respectively. When the security data in the flash memory chip is processed by the controller, the controller determinates whether the security data is falsified according to the data token, the eigenvalue and the message digest. In such a way, the security data stored in the flash memory storage system can be effectively protected. | 06-10-2010 |
| 20100146191 | SYSTEM AND METHODS EMPLOYING MOCK THRESHOLDS TO GENERATE ACTUAL READING THRESHOLDS IN FLASH MEMORY DEVICES - A method for reading at least one page within an erase sector of a flash memory device, the method comprising computing at least one mock reading threshold; using the at least one mock reading threshold to perform at least one mock read operation of at least a portion of at least one page within the erase sector, thereby to generate a plurality of logical values; defining a set of reading thresholds based at least partly on the plurality of logical values; and reading at least one page in the erase sector using the set of reading thresholds. | 06-10-2010 |
| 20100146192 | METHODS FOR ADAPTIVELY PROGRAMMING FLASH MEMORY DEVICES AND FLASH MEMORY SYSTEMS INCORPORATING SAME - A method for programming a plurality of data sequences into a corresponding plurality of flash memory functional units using a programming process having at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, the method comprising providing at least one indication of at least one varying situational characteristic and determining a value for said at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, for each flash memory functional unit, depending at least partly on said indication of said varying characteristic; and, for each individual flash memory functional unit from among said plurality of flash memory functional units, programming a sequence of bits into said individual flash memory functional unit using a programming process having at least one selectable parameter, said at least one selectable parameter being set at said value determined for said individual flash memory functional unit. | 06-10-2010 |
| 20100146193 | SYSTEM AND METHOD FOR CACHE SYNCHRONIZATION - A system for cache synchronization includes a data managing unit and a storage medium. The data managing unit is configured to control storing of data of a buffer cache of the storage medium, in response to an event signal received from a host, by classifying the data of the buffer cache into random data and sequential data. The storage medium includes a first area and a second area, and is configured to store the random data and an address information map in the first area, and to store the sequential data in the second area. | 06-10-2010 |
| 20100146194 | Storage Device And Data Management Method - A storage device includes two flash memories of different flash memory types, and respectively including multiple data blocks. Each data block corresponds to a physical and a logical block address. The storage device further includes a processing module including a controller, which is capable of accessing two mapping tables respectively corresponding to the two flash memories and respectively recording the physical block addresses and the logical block addresses that correspond to the data blocks of the two flash memories. The controller is configured to determine, upon receipt of a command that contains a target logical block address therein, a selected one of the flash memories according to the target logical block address, and to locate a selected one of the physical block addresses by searching one of the mapping tables that corresponds to the selected one of the flash memories with reference to the target logical block address. | 06-10-2010 |
| 20100146195 | Defragmentation Method For A Machine-Readable Storage Device - A defragmentation method includes the steps of: a) configuring a processor to determine a type of a target machine-readable storage device coupled electrically to the processor; b) configuring the processor to select, from among a plurality of pre-established defragmentation algorithms respectively for performing defragmentation on different types of machine-readable storage devices, a defragmentation algorithm that corresponds to the type of the target machine-readable storage device as determined in step a); and c) configuring the processor to perform defragmentation on the target machine-readable storage device according to the defragmentation algorithm as selected in step b). | 06-10-2010 |
| 20100146196 | MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS - A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system. | 06-10-2010 |
| 20100146197 | Non-Volatile Memory And Method With Memory Allocation For A Directly Mapped File Storage System - In a memory system with a file storage system, a scheme for allocating memory locations for a write operation is to write the files substantially contiguously in a memory block one after another rather than to start a new file in a new block. In this way, they are more efficiently packed into the blocks by being written contiguously one after another. In a preferred embodiment, an incrementing write pointer points to the write location in memory for the next data for a file, which is independent of the offset address of the data within the file. When a current write block becomes filled with file data, an erased block is allocated, and the write pointer is moved to this block. Similarly a relocation pointer is used for data relocation during garbage collection or data compaction operations. | 06-10-2010 |
| 20100153620 | Storage system snapshot assisted by SSD technology - A method and apparatus for taking a snapshot of a storage system employing a solid state disk (SSD). A plurality of mapping tables in the SSD store data needed to create a one or more point in time snapshots and a current view of the SSD. In response to a write command, the SSD executes its normal write process and updates its mapping tables to indicate the current view of the SSD and additionally retains the original data in a table of pointers to the original data, as the snapshot of an earlier state of the SSD. In the preferred embodiment, the innate ability of SSDs to write data to a new location is used to perform a point-in-time copy with little or no loss in performance in performing the snapshot. | 06-17-2010 |
| 20100153621 | METHODS, COMPUTER PROGRAM PRODUCTS, AND SYSTEMS FOR PROVIDING AN UPGRADEABLE HARD DISK - Methods, computer program products and systems for providing an upgradeable hard disk. The system includes a plurality of memory card slots and a controller. The controller includes a host interface in communication with a host computer, a memory card interface in communication with one or more memory cards located in one or more of the memory card slots, and a detection mechanism. The detection mechanism monitors the memory card slots for newly added memory cards; and in response to detecting a newly added memory card determines characteristics of the newly added memory card and updates the data placement strategy in response to the characteristics of the newly added memory card. The data placement strategy is utilized by the controller to determine write locations for write data received from the host computer via the host interface. | 06-17-2010 |
| 20100153622 | Data Access Controller and Data Accessing Method - A data access controller and data accessing method is provided. The data access controller includes: a flash memory configuration register unit for storing information used for data access in a flash memory; a flash memory control unit for generating a control signal for data access to a block and a page in the flash memory according to the information used for data access stored in the flash memory configuration register unit; and a temporary memory control unit under the control of the flash memory control unit, adapted to generate a control signal for temporary storage of data. In the inventive solution, data access in the flash memory is under the control of the data access controller, thereby reducing CPU workload, improving operation speed and generality of the control on the data access in flash memory by storing the information for data access for at least one type of flash memory. | 06-17-2010 |
| 20100153623 | Data Managing Method for Flash Memory and Flash Memory Device Using the Same - A data management method for a flash memory apparatus, entailing a step for handling a plurality of flash chips, a step for enabling the flash chips in sequence, and a step for updating the first data in the first block on the first flash chip among the flash chips. Additionally there is a step for updating f writing of the first new data corresponding to the first data into a second block in a second flash chip among the flash chips, and a step merging the first block and the second block, wherein both of the first new data and the first data are corresponding to a first logical block address. | 06-17-2010 |
| 20100153624 | DATA MANAGING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY DEVICE USING THE SAME - A data managing method for non-volatile memory which comprises a step for receiving a first logical block address and updated data, and a step for merging data in a plurality of physical blocks which have lowest usage rates according to usage parameters in a reference table when the first logical address doesn't exist in the reference table in a buffer memory and a number of pair blocks reaches a determined number. | 06-17-2010 |
| 20100153625 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device including a plurality of flash memories, a connector for establishing connection with a host apparatus, a cache memory for data transmission between the flash memories and the host apparatus, a drive control circuit that controls the data transmission between the flash memories and the host apparatus, and a power supply circuit that converts an external power supply voltage into an internal power supply voltage, all mounted on a substrate. A fuse that protects at least the flash memories from an overcurrent is also provided on the substrate. | 06-17-2010 |
| 20100153626 | MEMORY SYSTEM - To provide a memory system that can surely restore management information even when a program error occurs during data writing. After “log writing ( | 06-17-2010 |
| 20100153627 | SYSTEM AND METHOD FOR MANAGING FILES IN FLASH MEMORY - A system and method for managing files in a flash memory. The flash memory has a first storage area and a second storage area for storing files. Each of the files has a file header and a data block. The method includes writing the file header of each of the files into the first storage area and setting the first storage area as a first mode, writing the data block of each of the files into the second storage area and setting the second area as a second mode. Responding to the data block of one of the files being completely written into the second storage area, a memory address of the data block stored in the second storage area is written to a corresponding file header. | 06-17-2010 |
| 20100153628 | METHOD OF FABRICATING SYSTEMS INCLUDING HEAT-SENSITIVE MEMORY DEVICES - A system code is stored in a first nonvolatile memory. The first nonvolatile memory and a second nonvolatile memory are heated during assembly of an electronic device including the first nonvolatile memory and a second nonvolatile memory. The heating is to a temperature sufficient to change a state of at least some memory cells in the second nonvolatile memory device. After the heating, the system code stored in the first nonvolatile memory is copied into the second nonvolatile memory. The first nonvolatile memory may he less vulnerable to temperature-related data alteration than the second nonvolatile memory. For example, the first nonvolatile memory may include a NAND flash memory and the second nonvolatile memory may include a variable resistance memory. | 06-17-2010 |
| 20100153629 | SEMICONDUCTOR MEMORY DEVICE - A command analyzer | 06-17-2010 |
| 20100153630 | Data storage system with complex memory and method of operating the same - A data storage system and a data storing method for the data storage system are provided. The data storage system includes a host unit, a storage unit, and a first input/output bus functioning as an interface between the host unit and the storage unit. The storage unit includes a non-volatile memory buffer unit and a flash memory unit. The non-volatile memory buffer unit includes a plurality of buffers arranged in parallel. The flash memory unit includes a plurality of data storage devices arranged in parallel to input and output data using a parallel method. In the method, a writing request is first classified into one of a plurality of grades according to a writing request frequency when there is a writing request and the writing requested data is stored in one of the non-volatile memory buffer unit and the flash memory unit according to the writing request frequency. | 06-17-2010 |
| 20100153631 | Method and data storage device for processing commands - A data storage device for processing a command includes a host interface and a controller. The host interface stores program information sent within the command from a host. The controller decodes the program information that indicates a memory type to be accessed for the command. In addition, the controller determines whether the specified memory type can be accessed according to the command. The controller performs the command by accessing the memory type when the memory type specified by the program information is available for access. | 06-17-2010 |
| 20100153632 | NON-VOLATILE MEMORY SYSTEM STORING DATA IN SINGLE-LEVEL CELL OR MULTI-LEVEL CELL ACCORDING TO DATA CHARACTERISTICS - Provided is a system storing data received from an application or file system in a non-volatile memory system of single-level cells and multi-level cells in accordance with one or more data characteristics. The non-volatile memory system includes a non-volatile memory cell array having a plurality of multi-level cells forming a MLC area and a plurality of single-level cells forming a SLC area, and an interface unit analyzing a characteristic of the write data and generating a corresponding data characteristic signal. A flash transition layer receives the data characteristic signal, and determines whether the write data should be stored in the MLC area or the SLC area based on whether or not the write data will be accessed by the file, or whether the address associated with the write data is frequently updated or not. | 06-17-2010 |
| 20100161877 | DEVICE AND METHOD FOR TRANSFERRING DATA TO A NON-VOLATILE MEMORY DEVICE - A semiconductor device for transferring input data to a non-volatile memory device. The semiconductor device comprises a virtual page buffer including a plurality of data elements; a mask buffer including a corresponding plurality of data elements; control logic circuitry for (i) setting each of the mask buffer data elements to a first logic state upon receipt of a trigger; (ii) causing input data to be written to selected virtual page buffer data elements; and (iii) causing those mask buffer data elements corresponding to the selected virtual page buffer data elements to be set to a different logic state; mask logic circuitry configured to generate masked output data by combining, for each of the virtual page buffer data elements, data read therefrom together with the logic state of the corresponding mask buffer data element; and an output interface configured to release the masked output data towards the non-volatile memory device. | 06-24-2010 |
| 20100161878 | METHOD OF UNLOCKING PORTABLE MEMORY DEVICE - A method of unlocking usable memory space of a portable memory device, such as a flash drive, includes connecting the portable memory device to a network access device, such as a computer. The network access device executes a control program and accesses a website through the network access device by execution of the control program. A specific task is executed at the website, which sends an unlocking code upon completion of the task. The usable memory space of the portable memory device is unlocked in response to receiving the unlocking code at the network access device. | 06-24-2010 |
| 20100161879 | Efficient and Secure Main Memory Sharing Across Multiple Processors - Various embodiments of the present invention provide systems and methods for using providing memory access across multiple virtual machines. For example, various embodiments of the present invention provide computing systems that include at least two processors each communicably coupled to a network switch via network interfaces. The computing systems further include a memory appliance communicably coupled to the network switch, and configured to operate as a main memory for the two or more processors. | 06-24-2010 |
| 20100161880 | FLASH INITIATIVE WEAR LEVELING ALGORITHM - A method and apparatus for initiative wear leveling for non-volatile memory. An embodiment of a method includes counting erase cycles for each of a set of multiple memory blocks of a non-volatile memory, the counting of erase cycles for each memory block including incrementing a first count for a physical block address of the memory block, and if the memory block is not a spare memory block, incrementing a second count for a logical block address of the memory block. The method also includes determining whether the non-volatile memory has uneven wear of memory blocks based at least in part on the counting of the erase cycles of the plurality of memory blocks. | 06-24-2010 |
| 20100161881 | MEMORY SYSTEM - A memory system ( | 06-24-2010 |
| 20100161882 | Methods for Executing a Command to Write Data from a Source Location to a Destination Location in a Memory Device - The embodiments described herein provide methods for executing a command to write data from a source location to a destination location in a memory device. In one embodiment, a memory device receives, from a host device, a command to write data from a source location to a destination location in the memory device. The memory device executes the command by changing the memory device's logical-to-physical address map without reading the data from the source location and writing the data to the destination location and without a need of further involvement of the host device after the host device sends the command to the memory device. | 06-24-2010 |
| 20100161883 | Nonvolatile Semiconductor Memory Drive and Data Management Method of Nonvolatile Semiconductor Memory Drive - According to one embodiment, a nonvolatile semiconductor memory drive includes a nonvolatile semiconductor memory, and a controller which controls a process of writing and reading data with respect to the nonvolatile semiconductor memory. The controller includes a logical address storage module which stores logical address information containing logical addresses indicating storage positions in a logical address space of the nonvolatile semiconductor memory in a redundant area of a page, and a data management module which creates parity data used to restore one logical address information items among n-1 logical address information items stored in redundant areas of n-1 pages based on the other n-2 logical address information items and writes the created second parity data to the redundant area of the n | 06-24-2010 |
| 20100161884 | Nonvolatile Semiconductor Memory Drive, Information Processing Apparatus and Management Method of Storage Area in Nonvolatile Semiconductor Memory Drive - According to one embodiment, a nonvolatile semiconductor memory drive includes a nonvolatile semiconductor memory, and a controller which controls a process of writing and reading data with respect to the nonvolatile semiconductor memory. The controller includes a compaction control module which acquires free groups set in an unused state by rearranging valid data scattered in n groups in groups of a number not larger than n−1 when the number of free groups remaining in a plurality of groups formed as a storage area management unit of the nonvolatile semiconductor memory becomes not larger than a predetermined number, and a compression control module which acquires free groups by compressing stored data in m groups in which access to stored valid data has not been made for a period longer than a predetermined period and rearranging the compressed data in groups of a number not larger than m−1. | 06-24-2010 |
| 20100161885 | SEMICONDUCTOR STORAGE DEVICE AND STORAGE CONTROLLING METHOD - A semiconductor storage device includes a first storage unit having a plurality of first blocks as data write regions; an instructing unit that issues a write instruction of writing data into the first blocks; a converting unit that converts an external address of input data to a memory position in the first block with reference to a conversion table in which external addresses of the data are associated with the memory positions of the data in the first blocks; and a judging unit that judges whether any of the first blocks store valid data associated with the external address based on the memory positions of the input data, wherein the instructing unit issues the write instruction of writing the data into the first block in which the valid data is not stored, when any of the first blocks does not store the valid data. | 06-24-2010 |
| 20100161886 | Architecture for Address Mapping of Managed Non-Volatile Memory - The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture. | 06-24-2010 |
| 20100161887 | STORAGE DEVICE, CONTROL METHOD THEREOF, AND ELECTRONIC DEVICE USING STORAGE DEVICE - According to one embodiment, a storage device includes a physical address specifying module, a logical address group specifying module, a data writer, and a storage controller. The physical address specifying module specifies a physical address of write destination of data received together with a logical address among physical addresses each representing a block group including a block of each of flash memories connected in parallel the storage area of which is divided into a plurality of blocks for each sector. The logical address group specifying module specifies a logical address group including logical addresses based on the logical address. The data writer writes data of the logical addresses to blocks in the physical address. The storage controller stores the physical address where the data is written and the logical address group from which the data is written in an address conversion map in association with each other. | 06-24-2010 |
| 20100161888 | Data storage system with non-volatile memory using both page write and block program and block erase - An optimized data storage system including non-volatile re-writeable memory having both block program and erase and full or partial page write is disclosed. A memory controller of the system can use block data operations for large data transfers, and page data operations for small data transfers. Page data operations in the non-volatile re-writeable memory do not require block rewrites. One or more layers of the non-volatile re-writeable memory can be fabricated BEOL as two-terminal cross-point memory arrays that are fabricated over a substrate including active circuitry fabricated FEOL. Some or all of the active circuitry can be electrically coupled with the one or more layers of two-terminal cross-point memory arrays to perform data operations on the arrays, such as the block program and block erase and/or full or partial page writes. The arrays can include a plurality of two-terminal memory cells. | 06-24-2010 |
| 20100161889 | Delivering secured media using a portable memory device - In some embodiments an interface of a portable memory device is used to store content information in a hidden memory region of the portable memory device. The interface is also used to store information in a visible memory region of the portable memory device. The information stored in the visible memory region allows the content information stored in the hidden memory region to be accessed. Other embodiments are described and claimed. | 06-24-2010 |
| 20100161890 | CACHE MANAGEMENT METHOD AND CACHE DEVICE USING SECTOR SET - A cache management method and a cache device using a sector sets, are provided. The cache management method includes receiving at least one of a write request and a read request for predetermined data, from a host device. The cache determines whether a cache memory is allocated to a sector set including the predetermined sector, and selectively allocates the cache memory to the sector set based on the result of determination. The cache may store the data in the cache memory allocated to the sector set. | 06-24-2010 |
| 20100161891 | METHOD OF CONTROLLING CARD-SHAPED MEMORY DEVICE - Each of a plurality of memory areas includes a plurality of blocks. Each of the blocks includes a plurality of pages. Each of the memory areas also includes a data cache and a page buffer. A control unit controls a lower-limit value of the number of empty blocks in each of the plurality of memory areas. | 06-24-2010 |
| 20100169540 | METHOD AND APPARATUS FOR RELOCATING SELECTED DATA BETWEEN FLASH PARTITIONS IN A MEMORY DEVICE - A method and system for relocating selected groups of data in a storage device having a non-volatile memory consisting partitions with different types of non-volatile memory. The method may include determining whether data received a first partition meets one or more heightened read probability criteria and/or heightened delete probability criteria. If the criteria are not met, the received data is moved to a second partition, where the first partition has a higher endurance than the second partition. The system may include a first non-volatile memory partition and a second non-volatile memory partition having a lower endurance than the first, where a controller in communication with the first and second partitions determines if a heightened read probability and/or a heightened delete probability are present in received data. | 07-01-2010 |
| 20100169541 | METHOD AND APPARATUS FOR RETROACTIVE ADAPTATION OF DATA LOCATION - A method and system for organizing groups of data in a storage device having a non-volatile memory consisting of higher performance or endurance portion and a lower performance or endurance portion are disclosed. The method may include steps of determining a data usage status for a group of data in only one of the two portions, and if a data usage criterion is met, moving the group of data to the other of the two portions of the non-volatile memory. In another implementation, the method may include determining a data usage status of groups of data in both portions of the non-volatile memory and moving a group of data from one portion to the other if an appropriate data usage criterion is met so that groups of data may be maintained in a portion of the non-volatile memory most suited to their usage patterns. | 07-01-2010 |
| 20100169542 | DYNAMIC MAPPING OF LOGICAL RANGES TO WRITE BLOCKS - A method and system writes data to a memory device including dynamic assignment of logical block addresses (LBAs) to physical write blocks. The method includes receiving a request to write data for a logical block address within an LBA range to the memory device. The method assigns the LBA range to a particular write block exclusively or non-exclusively, depending on the existence of previously assigned write blocks and the availability of unwritten blocks. A data structure may be utilized to record the recent usage of blocks for assigning non-exclusive write blocks. An intermediate storage area may be included that implements the dynamic assignment of LBA ranges to physical write blocks. Data in the intermediate storage area may be consolidated and written to the main storage area. Lower fragmentation and write amplification ratios may result by using this method and system. | 07-01-2010 |
| 20100169543 | RECOVERY FOR NON-VOLATILE MEMORY AFTER POWER LOSS - Non-volatile memory array can be recovered after a power loss. In one example, pages of a memory array are scanned to find a first free page after the power loss. The first free page is marked as available, and the page marked as available is written to with the next write cycle | 07-01-2010 |
| 20100169544 | METHODS FOR DISTRIBUTING LOG BLOCK ASSOCIATIVITY FOR REAL-TIME SYSTEM AND FLASH MEMORY DEVICES PERFORMING THE SAME - A method for distributing log block associativity in log buffer-based flash translation layer (FTL) includes, if write request on page p is generated, checking whether log block associated with corresponding data block that write request is generated exists or not by checking log block mapping table storing mapping information between data blocks and log blocks, wherein the associativity of each log block to data block is set to equal to or less than predetermined value K in advance, and K is a natural number, if log block associated with corresponding data block that write request is generated exists, checking whether associated log block is random log block or sequential log block, and if associated log block is random log block, writing data that write request is generated in first free page of random log block. | 07-01-2010 |
| 20100169545 | HOST SYSTEM AND OPERATING METHOD THEREOF - The prevent invention provides a host system and an operating method thereof. The host system comprises: a peripheral device control circuit, for controlling operation of at least a peripheral device, the peripheral device comprising an embedded micro processor; and a host control circuit, coupled to the peripheral device control circuit via a transmission interface, the host control circuit comprising: a storage module, at least storing a firmware of the embedded micro processor; and a control module, coupled to the storage module, for controlling operation of the host control circuit, and the control module transmitting the firmware to the peripheral device control circuit via the transmission interface. The embedded micro processor executes the firmware provided by the host control circuit to control operation of the peripheral device control circuit. | 07-01-2010 |
| 20100169546 | FLASH MEMORY ACCESS CIRCUIT - A system comprises an instruction processor ( | 07-01-2010 |
| 20100169547 | METHOD FOR PREVENTING DATA LOSS DURING SOLDER REFLOW PROCESS AND MEMORY DEVICE USING THE SAME - The invention provides a method for preventing data loss in a flash memory during a solder reflow process. The flash memory includes a plurality of memory blocks and each memory block includes a plurality of strong pages and weak pages. Preloading data is first received and stored into the strong pages of at least one of first memory block within the flash memory. Then, the flash memory is heated for the solder reflow process. Next, the preloading data is reorganized according to a trigger signal and the strong pages and weak pages of at least one of second memory block within the flash memory are provided for storing the reorganized preloading data. | 07-01-2010 |
| 20100169548 | MEMORY CARD AND METHOD FOR CONTROLLING MEMORY CARD - According to one embodiment, a memory card configured to be installed in and removed from a card slot formed in an electronic apparatus, the memory card includes a memory section configured store at least one file, a close-proximity wireless transfer section configured to perform close-proximity wireless transfer, and a controller configured, every time communication between the close-proximity wireless transfer section and a different close-proximity wireless transfer device is enabled, to execute a process for using the close-proximity wireless transfer section to transmit the files stored in the memory section to the different close-proximity wireless transfer device. | 07-01-2010 |
| 20100169549 | MEMORY SYSTEM AND CONTROLLER - A controller sets, out of a data range that is specified in a read request from a host device, a predetermined size of a first data range that follows a top portion of the data range and a predetermined size of a second data range that follows the first data range, and after transfer, to the host device, of data corresponding to the first data range from a second storage unit or a third storage unit having smaller data output latency than the first storage unit in which read/write of data is performed is started, the controller searches for data corresponding to the second data range in the second storage unit or the third storage unit. | 07-01-2010 |
| 20100169550 | SEMICONDUCTOR MEMORY DEVICE, DATA TRANSFER DEVICE, AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY DEVICE - To provide a semiconductor memory device including a first controller that controls a first data transfer in which data are transferred from the first memory to a second memory in predetermined transfer units; a second controller that controls a second data transfer in which data are transferred from the second memory to a host device; and a control unit that outputs to the first controller a read instruction in which an address in the second memory is specified for each of the predetermined transfer units and creates a descriptor in which the addresses in the second memory are specified in order of transfer. The first controller outputs an end notification at each end of the first data transfer, and the second controller executes the second data transfer according to the specification in the descriptor after receiving the end notification. | 07-01-2010 |
| 20100169551 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - A forward lookup address translation table and a reverse lookup address translation table stored in a nonvolatile second storing unit are transferred as a master table to a volatile first storing unit at a time of start-up. When an event occurs so that the master table needs to be updated, difference information before and after update of any one of the forward lookup address translation table and the reverse lookup address translation table is recorded in the first storing unit as a log, thereby reducing an amount of the log. | 07-01-2010 |
| 20100169552 | REMOVALBLE MULTIMEDIA MEMORY CARD AND METHOD OF USE - A method and system is disclosed for distributing multimedia information. The system and method comprises sending a plurality of multimedia files to at least one server; and recording the plurality of multimedia files on a removable memory device. The removable memory device has a format that includes a predetermined information set that is described and physically stored thereon. The method and system is a complete solution for the commercial multimedia (audio, video, picture, text) distribution. Also, the method and system can be used for commercial distribution of any kind digital data (programs, bank data, documents, control etc). The method and system uses individual unique keycode for customized access to internet and any other electronic devices. All multimedia data files are stored on a removable memory device as a physical, hardware device. | 07-01-2010 |
| 20100169553 | MEMORY SYSTEM, CONTROLLER, AND METHOD OF CONTROLLING MEMORY SYSTEM - A memory system according to an embodiment of the present invention includes a volatile first storing unit, a nonvolatile second storing unit, a controller that transfers data between a host apparatus and the second storing unit via the first storing unit. The memory system monitors whether data written from the host apparatus in the first storing unit has a specific pattern in management units. When data to be flushed to the second storing unit has the specific pattern, the memory system set an invalid address value that is not in use in the second storing unit to the data. | 07-01-2010 |
| 20100169554 | TERMINAL APPARATUS - A terminal apparatus acquires setting information for controlling whether a storage area held by the non-volatile storage medium is to be used or not, from an external apparatus connected via a network, when the terminal apparatus is activated. The terminal apparatus updates area definition information defining the structure of storage areas in the non-volatile storage medium so that the storage area the use of which is restricted is in a state which cannot be recognized by the operating system, if the acquired setting information indicates that the use of the storage area is restricted. The terminal apparatus performs activation processing of the operating system after the update processing of the area definition information ends, if the acquired setting information indicates that the use of the storage area is restricted. | 07-01-2010 |
| 20100169555 | METHOD OF WRITING DATA INTO FLASH MEMORY BASED ON FILE SYSTEM - A method of writing data into flash memory based on OS file system is provided. The method includes steps of: obtaining a data start position of a data area in a first partition of a flash memory; converting the data start position into a first block number and a first page number; calculating an offset and adding the offset to the first page number to be an updated first page number when the first page number is not an integer; and, setting the first block number and the updated first page number as a new data start position of the data area and writing a first data according to the new data start position. | 07-01-2010 |
| 20100169556 | NONVOLATILE STORAGE DEVICE, INFORMATION RECORDING SYSTEM, AND INFORMATION RECORDING METHOD - A nonvolatile storage device includes a nonvolatile memory configured to store user data and management information used to manage the user data on a file system, and a medium controller configured to determine whether a command input from a host device is used for the user data or the management information, the command describing content of processing performed for the user data or the management information, and switch between control methods used for the nonvolatile memory on the basis of the determination result. | 07-01-2010 |
| 20100169557 | USING NON-VOLATILE STORAGE TO TRACK STATUS CHANGES IN OBJECTS - A non-volatile storage device is used to track status changes in one or more items, where it is less costly to set bits in the non-volatile storage device than to reset bits. For each of the items to be tracked, at least two bits of storage space are allocated in the non-volatile storage device. One of the bits is set when the item changes status, and another of the bits is set when the item changes status again. | 07-01-2010 |
| 20100169558 | NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM - A nonvolatile storage device includes a controller and a nonvolatile memory. The controller has: a logical-physical address conversion part for converting a logical address designated by a host device into a physical address; and a boot code address conversion part for converting boot code address information designated by the host device into a physical address. After the power-on and before the logical-physical address conversion part becomes usable, a boot code is read from a part of region which can be accessed by designating a logical address from the host device by designating the boot code address information from the outside. Thus, it is possible to rapidly start the nonvolatile memory system after the power-on. In the state where the logical-physical address conversion part can be used, data-reading and data-writing are carried out by designating a logical address from the host device. | 07-01-2010 |
| 20100169559 | Removable Mother/Daughter Peripheral Card - A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features. | 07-01-2010 |
| 20100169560 | Methods for Selectively Copying Data Files to Networked Storage and Devices for Initiating the Same - A data backup system comprises a USB flash drive that includes an emulation component and a flash memory. The emulation component is configured to represent the flash memory as if it were an auto-launch device. Accordingly, a data source, such as a personal computer, will interact with the flash memory as if it were the auto-launch device. As some operating systems are configured to recognize auto-launch devices upon connection and automatically execute applications stored thereon, merely connecting the USB flash drive to a data source running such an operating system will cause a backup application stored by the flash memory to automatically execute on the data source. Here, the backup application is configured to selectively back up data files from the data source to a networked storage such as a server of a commercial service provider. | 07-01-2010 |
| 20100169561 | Removable Mother/Daughter Peripheral Card - A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features. | 07-01-2010 |
| 20100174845 | Wear Leveling for Non-Volatile Memories: Maintenance of Experience Count and Passive Techniques - Wear leveling techniques for re-programmable non-volatile memory systems, such as a flash EEPROM system, are described. One set of techniques uses “passive” arrangements, where, when a blocks are selected for writing, blocks with relatively low experience count are selected. This can be done by ordering the list of available free blocks based on experience count, with the “coldest” blocks placed at the front of the list, or by searching the free blocks to find a block that is “cold enough”. In another, complementary set of techniques, usable for more standard wear leveling operations as well as for “passive” techniques and other applications where the experience count is needed, the experience count of a block or meta-block is maintained as a block's attribute along its address in the data management structures, such as address tables. | 07-08-2010 |
| 20100174846 | Nonvolatile Memory With Write Cache Having Flush/Eviction Methods - A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion. | 07-08-2010 |
| 20100174847 | Non-Volatile Memory and Method With Write Cache Partition Management Methods - A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache. | 07-08-2010 |
| 20100174848 | DATA PROCESSING APPARATUS - A data processing apparatus comprises a monolithic integrated circuit having a data processor, a non-volatile memory storing at least one security code, and at least one interface at the boundary of the integrated circuit via which communication with the data processor can occur. Processing by the data processor of data received at the at least one interface is controlled by the at least one security code. | 07-08-2010 |
| 20100174849 | SYSTEMS AND METHODS FOR IMPROVING THE PERFORMANCE OF NON-VOLATILE MEMORY OPERATIONS - Disclosed herein are systems and methods that recognize and recapture potentially unused processing time in typical page program and block erase operations in non-volatile memory (NVM) devices. In one embodiment, a characterization module within a controller executes a characterization procedure by performing page program and block erase operations on one or more NVM devices in an array and storing execution time data of the operations in a calibration table. The procedure may be executed at start-up and/or periodically so that the time values are reflective of the actual physical condition of the individual NVM devices. A task manager uses the stored time values to estimate the time needed for completing certain memory operations in its task table. Based on the estimated time for completion, the task manager assigns tasks to be executed during page program and/or block erase cycles, so that otherwise unused processing time can be utilized. | 07-08-2010 |
| 20100174850 | DATA MOVING METHOD AND SYSTEM UTILIZING THE SAME - A data moving method includes: detecting if data to be written from at least first source data unit of a storage unit includes a specific pattern or not; and simplifying writing operation while writing the data from a second source data unit to a first target data unit if the data includes a specific pattern, wherein the second source data unit includes at least one first source data unit, and the first target data unit includes at least one second target data unit. | 07-08-2010 |
| 20100174851 | MEMORY SYSTEM CONTROLLER - The present disclosure includes methods and devices for a memory system controller. In one or more embodiments, a memory system controller includes a host interface communicatively coupled to a system controller. The system controller has a number of memory interfaces, and is configured for controlling a plurality of intelligent storage nodes communicatively coupled to the number of memory interfaces. The system controller includes logic configured to map between physical and logical memory addresses, and logic configured to manage wear level across the plurality of intelligent storage nodes. | 07-08-2010 |
| 20100174852 | METHOD FOR OPERATING NON-VOLATILE MEMORY AND DATA STORAGE SYSTEM USING THE SAME - A method for operating a non-volatile memory is provided. The non-volatile memory includes a plurality of physical blocks haing a plurality of data blocks and spare blocks. An index is obtained by comparing an average erase count of selected physical blocks with a first threshold. Each erase count for each physical block is the total number of the erase operations performed thereon. A performance capability status for the memory is determined according to the index. The performance capability status is set to a first status when the average erase count exceeds the first threshold. An indication is generated based on the performance capability status. A limp function is performed in response to the first status for configuring a minimum number of the at least some spare blocks reserved and used for data update operations. | 07-08-2010 |
| 20100174853 | USER DEVICE INCLUDING FLASH AND RANDOM WRITE CACHE AND METHOD WRITING DATA - A method of writing data to a flash memory in a system includes; receiving write data to be written in the flash memory, determining whether the received write data is random write data or sequential write data, if the received write data is sequential write data, then directly writing the received write data to the flash memory, and if the received write data is random write data, then writing the received write data to the random write cache, and flushing the random write data from the random write cache to the flash memory during idle periods for the flash memory. | 07-08-2010 |
| 20100174854 | NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION - A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device. | 07-08-2010 |
| 20100174855 | MEMORY DEVICE CONTROLLER - A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register. | 07-08-2010 |
| 20100174856 | MULTI-INTERFACE AND MULTI-BUS STRUCTURED SOLID-STATE STORAGE SUBSYSTEM - A solid-state storage subsystem, such as a non-volatile memory card or drive, includes multiple interfaces and a memory area storing information used by a data arbiter to prioritize data commands received through the interfaces. As one example, the information may store a priority ranking of multiple host systems that are connected to the solid-state storage subsystem, such that the data arbiter may process concurrently received data transfer commands serially according to their priority ranking. A host software component may be configured to store and modify the priority control information in solid-state storage subsystem's memory area. | 07-08-2010 |
| 20100174857 | DATA PROCESSOR - A data processor ( | 07-08-2010 |
| 20100180065 | Systems And Methods For Non-Volatile Cache Control - In some embodiments, a method for controlling a cache having a volatile memory and a non-volatile memory during a power up sequence is provided. The method includes receiving, at a controller configured to control the cache and a storage device associated with the cache, a signal indicating whether the non-volatile memory includes dirty data copied from the volatile memory to the non-volatile memory during a power down sequence, the dirty data including data that has not been stored in the storage device. In response to the received signal, the dirty data is restored from the non-volatile memory to the volatile memory, and flushed from the volatile memory to the storage device. | 07-15-2010 |
| 20100180066 | ELECTRONICALLY ADDRESSED NON-VOLATILE MEMORY-BASED KERNEL DATA CACHE - An operating system on a computer system can comprise a user space, which can comprise a persistent data store, and a kernel space, which can be extended by loading kernel modules. As provided herein, the kernel space can utilize kernel designated electronically addressed non-volatile memory (e.g., flash memory) to cache data from the user space persistent store, for example, upon a boot event. The kernel space can further comprise a cache controller that can be used to populate the kernel electronically addressed non-volatile memory with kernel in-memory data caches that comprise user space persistently stored data. In one embodiment, the kernel space can further comprise kernel designated volatile main memory (e.g., RAM), which can be used in conjunction with the kernel electronically addressed non-volatile memory to cache user space persistently stored data. In this way, kernel modules may access user space persistent store data from the RAM and/or electronically addressed non-volatile kernel cache. | 07-15-2010 |
| 20100180067 | SYSTEM FOR EMULATING AND EXPANDING A SPI CONFIGURATION ROM FOR IO ENCLOSURE - The present disclosure is directed to a method for providing serial peripheral interface (SPI) access in an IO enclosure. The method may comprise receiving a SPI access request at a bus interface unit; sending the SPI access request to a register bus, the register bus connecting an internal ROM, at least one status register, and at least one control register; fetching from the internal ROM when the SPI access request is a read request for configuration information; reading from the at least one status register when the SPI access request is a read request for at least one of an indicator, a sensor, or a controller within the IO enclosure; and writing to the at least one control register when the SPI access request is a write request for at least one of the indicator, the sensor, or the controller within the IO enclosure. | 07-15-2010 |
| 20100180068 | STORAGE DEVICE - A storage device realizing an improvement in rewrite endurance of a nonvolatile memory and an improvement in data transfer rate of write and read is provided including a nonvolatile memory | 07-15-2010 |
| 20100180069 | BLOCK MANAGEMENT METHOD FOR FLASH MEMORY, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for a flash memory of a storage system is provided, wherein the flash memory includes a plurality of physical blocks. The block management method includes grouping the physical blocks into a plurality of physical units, and grouping the physical units into a data area, a spare area, and a replacement area. The block management method further includes performing a first physical unit switch which switches the physical units between the data area and the spare area, and performing a second physical unit switch which switches the physical units between the spare area and the replacement area. Therefore, the block management method can uniformly use the physical blocks and thereby effectively prolong a lifespan of the storage system. | 07-15-2010 |
| 20100180070 | METHOD OF HANDLING I/O REQUEST AND SOLID STATE DRIVE USING THE SAME - A solid state drive (SSD) including a storage that includes a plurality of flash memories configured to be independently drivable and a controller to receive an input/output (I/O) request from a host, to split the I/O request into a plurality of sub-requests each having a size configured to be capable of being processed independently by each flash memory, and to process the I/O request based on the sub-requests. | 07-15-2010 |
| 20100180071 | METHOD FOR PROCESSING DATA OF FLASH MEMORY BY SEPARATING LEVELS AND FLASH MEMORY DEVICE THEREOF - The present invention discloses a method for processing data of a flash memory by differentiating levels, which includes steps of separating the communication between a host and a flash memory by a high-level translation layer (HTL) and a low-level abstraction layer (LAL). The HTL receives commands and logical addresses from the host and translates the received logical addresses to the physical addresses of the flash memory. The LAL executes data processing to the corresponding memory cells according to the commands and the physical addresses from the HTL. Since the LAL is disposed between the HTL and the flash memory, the HTL is irrelevant to the structure of the flash memory, and does not have to re-designed with the flash memory which is replaced with another new flash memory. | 07-15-2010 |
| 20100180072 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, FILE SYSTEM, NONVOLATILE MEMORY SYSTEM, DATA WRITING METHOD AND DATA WRITING PROGRAM - A file system ( | 07-15-2010 |
| 20100180073 | FLASH MEMORY DEVICE WITH PHYSICAL CELL VALUE DETERIORATION ACCOMMODATION AND METHODS USEFUL IN CONJUNCTION THEREWITH - A method for determining thresholds useful for converting cell physical levels into cell logical values in an array of digital memory cells storing physical levels which diminish over time, the method comprising determining extent of deterioration of the physical levels and determining thresholds accordingly for at least an individual cell in said array; and reading the individual cell including reading a physical level in the cell and converting the physical level into a logical value using the thresholds, wherein the determining comprises storing predefined physical levels rather than data-determined physical levels in each of a plurality of cells and computing extent of deterioration by determining deterioration of the predefined physical levels. | 07-15-2010 |
| 20100185802 | SOLID STATE MEMORY FORMATTING - The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary. | 07-22-2010 |
| 20100185803 | METHOD AND APPARATUS FOR ADAPTIVE DATA CHUNK TRANSFER - A block memory device and method of transferring data to a block memory device are described. Various embodiments provide methods for transferring data to a block memory device by adaptive chunking. The data transfer method comprises receiving data in a data chunk. The data transfer method then determines that the data chunk is ready to be transferred to a block memory and transfers the data chunk to the block memory. The transfer occurs over duration, repeating the above steps until the transfer is complete. The data transfer method determines that the data chunk is ready to be transferred to the block memory based on at least in part on a duration of a previous transfer. | 07-22-2010 |
| 20100185804 | INFORMATION PROCESSING DEVICE THAT ACCESSES MEMORY, PROCESSOR AND MEMORY MANAGEMENT METHOD - An information processing device of an example of the invention comprises an address generation section that generates a write address indicating a write position in a nonvolatile memory so that the write position is shifted in order to suppress each number of times of overlapped writing for each position of the nonvolatile memory when a write operation to the nonvolatile memory from a processor is performed, an order generation section that generates order information indicating a generation order of the writing operation, and a write control section that stores write information to the write address, and stores the order information to the nonvolatile memory so that the order information is related to at least one of the stored write information and the write address. | 07-22-2010 |
| 20100185805 | Method And Apparatus For Performing Wear Leveling In Memory - The embodiment of the solution provides a method for performing wear leveling in a memory. The method includes: dividing the lifecycle of the memory which includes more than one physical blocks into at least one sampling interval; for each sampling interval, getting the first physical block by taking statistics of the degree of the wear leveling of each physical block in the memory in the current sampling interval; getting the second physical block by taking statistics of the updating times of each logical address in the current sampling interval; exchanging the logical addresses and data of the first physical block and the second physical block. The embodiment of the solution also provides an apparatus corresponding the method | 07-22-2010 |
| 20100185806 | CACHING SYSTEMS AND METHODS USING A SOLID STATE DISK - A system includes a control module, a location description module, and a page invalidation module. The control module is configured to write data received from a host to a storage medium, read data from the storage medium, and cache data from at least one of the host and the storage medium in a flash memory. The location description module is configured to map one of a valid and invalid state to a physical location of a subset of data in the flash memory. The page invalidation module is configured to receive a command from one of the host and the control module that includes an address corresponding to the subset and an instruction to set a state of the physical location to the invalid state. The page invalidation module is further configured to set the state of the physical location to the invalid state in response to the command. | 07-22-2010 |
| 20100185807 | DATA STORAGE PROCESSING METHOD, DATA SEARCHING METHOD AND DEVICES THEREOF - A data storage processing method, a data searching method, and devices thereof are provided. The data storage processing method includes: sequentially writing data to a data recording area in a flash; generating log information according to a physical address of the data in the data recording area and an identifier (ID) of the data, and sequentially writing the log information to a log area in the flash; and constructing a Bloom filter data for the log information in the log area, and sequentially writing the Bloom filter data to a log digest area in the flash. A flash storage structure including the data recording area, the log area, and the log digest area is adopted, thereby reducing the occupied storage space of the flash. In addition, since all the areas adopt a sequential storage mode, the data maintenance is quite simple. | 07-22-2010 |
| 20100185808 | METHODS AND SYSTEMS FOR STORING AND ACCESSING DATA IN UAS BASED FLASH-MEMORY DEVICE - Methods and systems for storing and accessing data in UAS based flash memory device are disclosed. UAS based flash memory device comprises a controller and a plurality of non-volatile memories (e.g., flash memory) it controls. Controller is configured for connecting to a UAS host via a physical layer (e.g., plug and wire based on USB 3.0) and for conducting data transfer operations via two sets of logical pipes. Controller further comprises a random-access-memory (RAM) buffer configured for enabling parallel and duplex data transfer operations through the sets of logical pipes. In addition, a Smart Storage Switch configured for connecting multiple non-volatile memory devices is included in the controller. Finally, a security module/engine/unit is provided for data security via user authentication data encryption/decryption of the device. Furthermore, the flash memory device includes an optical transceiver configured for optical connection to a host also configured with an optical transceiver. | 07-22-2010 |
| 20100191896 | Solid state drive controller with fast NVRAM buffer and non-volatile tables - Systems and methods for a SSD controller enabling data transfer between a host and flash memories have been achieved. A major component of the SSD controller is a non-volatile buffer memory, which interfaces fast disk drive protocols and slow write and read cycles of NAND flash. Preferably MRAM or Phase Change RAM can be used for the buffer memory. Non-volatile tables can also be implemented for storing dynamic logical to physical address translation, defective sector information and their spare sectors and/or SSD configuration parameters. data are kept in a buffer memory when the buffer memory is not powered | 07-29-2010 |
| 20100191897 | SYSTEM AND METHOD FOR WEAR LEVELING IN A DATA STORAGE DEVICE - The present disclosure provides a system and method for wear leveling. In one example, the method includes receiving first data to be stored to a first data storage medium and storing the first data to a first storage location in a nonvolatile data store of a second data storage medium comprising a solid-state memory. The method also includes setting a pointer to enable writing second data that is received to a next storage location in the nonvolatile data store. The next storage location comprises an address of the nonvolatile data store that is sequentially after an address of the first storage location. When the address of the first storage location is a last addressed location of the nonvolatile data store the pointer is set to enable writing the second data to a first addressed location of the nonvolatile data store. The method also includes writing the first data stored in the nonvolatile data store to the first data storage medium when a trigger occurs and preserving the pointer during the writing from the nonvolatile data store to the first data storage device such that the pointer enables writing the second data to the next storage location. | 07-29-2010 |
| 20100191898 | COMPLEX MEMORY DEVICE AND I/O PROCESSING METHOD USING THE SAME - A non-volatile mass storage memory and an input/output processing method using the memory are provided. The memory device includes a storage unit including a non-volatile random access memory and a flash memory and a controller to control the storage to process an input/output request. Accordingly, system memories having different purposes and functionalities, such as a flash memory and a dynamic random access memory (DRAM), may be integrated with each other. | 07-29-2010 |
| 20100191899 | Information Processing Apparatus and Data Storage Apparatus - According to one embodiment, an information processing apparatus includes an storage apparatus including a first storage and a second storage. The storage apparatus includes a first data management module which stores data which is required to be read in a the predetermined period in the second storage so that the data requested to be read in the predetermined period is distinguishable. The storage apparatus further includes a second data management module which performs replacement of the data in the second storage so that data should be stored in the second storage, in an order reverse to that in which the data is requested to be read, while retaining the data stored in the second storage by the first data management module. | 07-29-2010 |
| 20100191900 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes memory chips driven in response to respective chip enable signals, and each of the memory chips includes a controller configured to generate and output information about an operation state, and a state information processor configured to calculate an expected consumption current when a target operation is performed based on the information about the operation states for the memory chips, and to output a control signal regarding whether to suspend or perform the target operation. | 07-29-2010 |
| 20100191901 | NON-VOLATILE STORAGE DEVICE, HOST DEVICE, NON-VOLATILE STORAGE SYSTEM, DATA RECORDING METHOD, AND PROGRAM - A memory controller, a non-volatile storage device, a host device, and a non-volatile storage system capable of performing real-time recording even in the case where normal data and file management information/auxiliary information are written in alternating manner are provided. The host device ( | 07-29-2010 |
| 20100191902 | STORAGE DEVICE EMPLOYING A FLASH MEMORY - A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased. | 07-29-2010 |
| 20100199019 | LOGICAL MEMORY BLOCKS - The present disclosure includes methods and devices for logical memory blocks. One method for operating a memory device includes receiving a command to operate X pages of the memory device, X being greater than Y, and executing the command by executing multiple subcommands, each subcommand operating on a logical memory block portion of the X pages, each logical memory block including at most Y pages. T is a timeout limit, N is a number of pages comprising a block of memory, and Y is number of pages that can be operated within time T. | 08-05-2010 |
| 20100199020 | NON-VOLATILE MEMORY SUBSYSTEM AND A MEMORY CONTROLLER THEREFOR - In the present invention a non-volatile memory subsystem comprises a non-volatile memory device and a memory controller. The memory controller controls the operation of the non-volatile memory device with the memory controller having a processor for executing computer program instructions for partitioning the non-volatile memory device into a plurality of partitions, with each partition having adjustable parameters for wear level and data retention. The memory subsystem also comprises a clock for supplying timing signals to the memory controller. | 08-05-2010 |
| 20100199021 | Firehose Dump of SRAM Write Cache Data to Non-Volatile Memory Using a Supercap - A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down. | 08-05-2010 |
| 20100199022 | INFORMATION ACCESS METHOD WITH SHARING MECHANISM AND COMPUTER SYSTEM - An information access method and a computer system are provided. The computer system includes a system management bus (SMBus), a non-volatile memory, a plurality of hardware devices, a chipset, and a CPU. The hardware devices have a plurality of specific recognition information. The CPU performs a configuration process on the hardware devices through the chipset according to the standard for a SMBus protocol, so as to distribute a plurality of memory spaces in the non-volatile memory to the hardware devices. The hardware devices share the SMBus for accessing the plurality of specific recognition information in the memory spaces. | 08-05-2010 |
| 20100199023 | APPARATUS AND METHOD FOR MANAGING MEMORY - A memory management method and apparatus are disclosed. The memory management apparatus may compute a remaining storage capacity of a flash memory based on a number of bad blocks in a flash memory or a number of block-erases of each of a plurality of blocks, and may display the computed remaining storage capacity of the flash memory. | 08-05-2010 |
| 20100199024 | METHOD AND APPARATUS FOR MANAGING DATA OF FLASH MEMORY VIA ADDRESS MAPPING - A method of managing data of a flash memory is provided. The method comprises: assigning a logical area of the flash memory as a user block area in which user storage data is stored, and a free block area in which the user storage data is temporarily stored when changing the user storage data; and, when a first data unit of user storage data received from a host is different from a second data unit used while mapping a physical address and a logical address of the flash memory where the user storage data is stored, assigning a predetermined logical area of the flash memory as a cache block area in which the user storage data received from the host is temporarily stored. | 08-05-2010 |
| 20100199025 | MEMORY SYSTEM AND INTERLEAVING CONTROL METHOD OF MEMORY SYSTEM - A memory system comprising: a plurality of nonvolatile memory areas capable of operating individually; and a memory controller connected to each of the memory areas individually via a ready/busy signal for interleaving an operation in the memory areas by changing a memory area as a target of an operation command, every time the operation command is transmitted, wherein the memory controller includes a priority-level managing unit that manages a level of selection priority for each memory area, so that after transmission of an operation command, the memory controller selects a memory area with a highest level of selection priority from memory areas in a ready state, to change the selected memory area to a target of a next operation command, and shifts the level of selection priority of the selected memory area at a time of next selection to a lowest level by the priority-level managing unit. | 08-05-2010 |
| 20100199026 | Flash File System and Driving Method Thereof - The present invention discloses a flash file system and drive method thereof, characterized in that, after reception of an access function, it verifies the parameters in the access function and analyzes the file name of the file to be accessed included therein, then queries the starting position of the file to be accessed, and finally controls a physical driver module to access data from the flash according to the starting position and such parameters. The flash file system according to the present invention does not require FAT (File Allocation Table) file system and block interface, thereby simplifying the complexity of file system and enhancing system performance. | 08-05-2010 |
| 20100199027 | SYSTEM AND METHOD OF MANAGING INDEXATION OF FLASH MEMORY - The invention is a system of managing indexation of memory. Said system has a microprocessor, and a flash memory. Said flash memory has an indexed area comprising indexed items, and an index that is structured in a plurality of index areas comprising a plurality of entries. Said flash memory comprises an index summary comprising a plurality of elements. Each index summary element is linked to an index area of said index. Each index summary element is built from all entries belonging to said linked index area and is built using k hash functions, with 1≦k. | 08-05-2010 |
| 20100199028 | Non-volatile storage device with forgery-proof permanent storage option - The invention is related to non-volatile storage devices. | 08-05-2010 |
| 20100199029 | Storage device, computer system, and data writing method - A storage device that includes a flash memory device providing a storage medium, a cache memory for use with the flash memory device, and a control circuit. In the storage device, based on a write command and provided address information, the control circuit selects either the flash memory device or the cache memory as a writing destination of input data. | 08-05-2010 |
| 20100199030 | METHOD OF MANAGING FLASH MEMORY ALLOCATION IN AN ELECTRONI TOKEN - The invention is a method of managing flash memory-allocation in an electronic token. Said token has a memory comprising a list area and a managed area. Said managed area comprises allocated spaces and at least one free memory chunk. Said list area comprises at least one valid entry referencing a free memory chunk. Said valid entry comprises a state field. Said method comprises the step of selecting a free memory chunk further to an allocation request where said free memory chunk is referenced by an old entry, and the step of identifying a new allocated space in the selected free memory chunk. The state field of said valid entry is preset with a virgin state. Said method comprises the step of invalidating the old entry referencing the selected free memory chunk. | 08-05-2010 |
| 20100199031 | SYSTEM AND METHOD FOR CONTROLLING ACCESS TO A MEMORY DEVICE OF AN ELECTRONIC DEVICE - The invention relates to a system and method for controlling implementation of a command to a NAND memory device. The method comprises: monitoring an input/output (I/O) bus connected to the NAND memory device for an assertion of a write command for the NAND memory device. Upon detection of the write command, the method evaluates a destination address associated with the write command. If the destination address is not a restricted address for the NAND memory device, then the method allows the write command to modify the contents; and if the destination address is a restricted address for the NAND memory device, then the method prevents assertion of the write command on the contents. | 08-05-2010 |
| 20100199032 | ENHANCED DATA COMMUNICATION BY A NON-VOLATILE MEMORY CARD - A method of transmitting a stream of data bits from a memory card to a host device includes determining, at the memory card, a first number of data lines between the memory card and the host device, from one to a plurality of data lines. If the first number of data lines is determined to be a plurality of data lines, the method includes switching, at the memory card, the data stream between one of the first number of data lines and another of the first number of data lines after each occurrence of a second number of one or more bits of the data stream having passed toward the host device. The method also includes, if the first number of data lines is determined to be one data line, transmitting, from the memory card, the stream of data bits over the one data line to the host device. | 08-05-2010 |
| 20100205349 | SEGMENTED-MEMORY FLASH BACKED DRAM MODULE - A memory device for use with a primary power source, includes volatile memory including a plurality of memory segments defined by at least one starting addresses and a corresponding at least one ending address; an interface for connecting to a backup power source; a non-volatile memory; and a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory based on the at least one starting address and the at least one ending address. In some aspects, there is only one starting address and one ending address and only data that is stored in the volatile memory at addresses between the one starting address and one ending address is moved to the non-volatile memory. | 08-12-2010 |
| 20100205350 | SYSTEM AND METHOD OF HOST REQUEST MAPPING - Systems and methods for reading data are disclosed. In a particular embodiment, a data storage device includes a host interface that is adapted to couple the data storage device to a host. The host includes memory that is addressable by a host memory address space. The data storage device also includes a device address space that is independent from the host memory address space. The device address space includes a first address region and a second address region, where the second address region is distinct from the first address region. The data storage device also includes a non-volatile memory array and a controller coupled to the non-volatile memory array and further coupled to a mapped device. The controller is adapted to, in response to a first request from the host for access to the first address region of the device address space, perform a memory access operation at the non-volatile memory array. The controller is also adapted to, in response to a second request from the host for access to the second address region of the device address space, map the second request to the mapped device. | 08-12-2010 |
| 20100205351 | DATABASE JOIN OPTIMIZED FOR FLASH STORAGE - Computer-implemented systems and associated operating methods implement a fast join for databases which is adapted for usage with flash storage. A system comprises a processor that performs a join of two tables stored in a storage in pages processed in a column orientation wherein column values for all rows on a page are co-located in mini-pages within the page. The processor reduces input/output operations of the join by accessing only join columns and mini-pages containing join results. | 08-12-2010 |
| 20100205352 | MULTILEVEL CELL NAND FLASH MEMORY STORAGE SYSTEM, AND CONTROLLER AND ACCESS METHOD THEREOF - A multi level cell (MLC) NAND flash memory storage system is provided. A controller of the MLC NAND flash memory storage system declares it a signal level cell (SLC) NAND flash memory chip to a host system connected thereto and provides a plurality of SLC logical blocks to the host system. When the controller receives a write command and a user data from the host system, the controller writes the user data into a page of a MLC physical block and records the page of the SLC logical block corresponding to the page of the MLC physical block. When the controller receives an erase command from the host system, the controller writes a predetermined data into the page of the MLC physical block mapped to the SLC logical block to be erased, wherein the predetermined data has the same pattern as a pattern of the erased page. | 08-12-2010 |
| 20100205353 | MEMORY SYSTEM - A memory system according to an embodiment of the present invention comprises: a log overflow control unit that, when a third condition in which a second log accumulated in a log storage area exceeds a set value is satisfied, stops a recording operation of the second log in the log storage area by a log recording unit and causes a log recording unit to perform an update operation of a second management table in a master table and a recording operation of a first log in the log storage area, and that, when a first condition is satisfied next time, prohibits a commit operation by a log reflecting unit and causes a snapshot storing unit to perform a snapshot storing operation. | 08-12-2010 |
| 20100205354 | STORAGE DEVICE USING FLASH MEMORY - Provided is a system whose effective endurable number of rewrite times can be drastically improved in a storage device using a flash memory whose rewrite life is restricted. The logical address (LBA) of a sector in which data which is not used as a file system is accumulated is detected. Mapping information on a physical address (PBA) corresponding to the logical address is released. A block in which the mapping information on every logical address and physical address is released out of blocks of the flash memory is deleted and used as an alternative block for wear leveling. | 08-12-2010 |
| 20100205355 | MULTIPLEXING SECURE DIGITAL MEMORY - A method of storing data within a plurality of memory devices is disclosed. Each memory device of the plurality of memory devices comprises flash memory, and supports a first data transfer rate, A. Data is provided from a data interface to a multiplexer using a second data transfer rate, B, which is faster than the data transfer rate, A. Using the multiplexer, the data is divided into N data portions. Each one of the N data portions is provided to a different memory device of the plurality of memory devices using a third data transfer rate B/N, wherein B/N≦A. The N data portions are stored in parallel, each within a respective different memory device of the plurality of memory devices. | 08-12-2010 |
| 20100205356 | MEMORY CONTROLLER, MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY - In the control of the number of program-erase cycles, physical blocks (PBs) are divided into plural groups on a basis of the number of program-erase cycles and a search for a free PB is performed in the groups when assigning a logical block (LB) to the free PB. In the search, a free PB among a group covering a small number of program-erase cycles precedes that among a group covering a large number of program-erase cycles. Further, when searching out a free PB in the search, data stored in a PB (source PB) included in a group covering a smaller number of program-erase cycles than that covered by a group including the free PB searched out are transferred to the free PB if there is the source PB. The source PB is a PB to which a LB is assigned earliest among a group including it. | 08-12-2010 |
| 20100205357 | MEMORY CONTROLLER, MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY - In the control of the number of program-erase cycles, when assigning a logical block (LB) to a physical block (PB), the number of program-erase cycles of a first PB and that of a second PB are compared, which first PB is a free PB of which the number of program-erase cycles is the smallest among that of free PBs, which second PB is a PB earliest assigned a LB among PBs each assigned a LB. As a result, in a case where the number of program-erase cycles of the first PB is larger by a predetermined value or more than that of the second PB, data stored in the second PB are transferred to a free PB of which the number of program-erase cycles is the largest among free PBs, and then the LB is assigned to the second PB. | 08-12-2010 |
| 20100205358 | METHOD TO REWRITE FLASH MEMORY WITH EXCLUSIVELY ACTIVATED TWO BLOCKS AND OPTICAL TRANSCEIVER IMPLEMENTING CONTROLLER PERFORMING THE SAME - An effective algorithm for the CPU with a flash memory is disclosed to shorten a dead time to erase the flash memory and to write new data therein. The flash memory of the invention provides front and back blocks for the user data area. When the front block is filled, the back block is erased just after the front block is fully filled in advance to receive a new data next to be written. | 08-12-2010 |
| 20100205359 | Storage System Using Flash Memory Modules Logically Grouped for Wear-Leveling and Raid - A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group. | 08-12-2010 |
| 20100205360 | Removable Mother/Daughter Peripheral Card - A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features. | 08-12-2010 |
| 20100205361 | SEMICONDUCTOR MEMORY CARD ACCESS APPARATUS, A COMPUTER-READABLE RECORDING MEDIUM, AN INITIALIZATION METHOD, AND A SEMICONDUCTOR MEMORY CARD - A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. | 08-12-2010 |
| 20100205362 | Cache Control in a Non-Volatile Memory Device - A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that manages data transfer between the cache memory portion and the main memory portion according to at least one caching command received from a host. The management of data transfer, by the controller, includes transferring new data from the host to the cache memory portion, copying the data from the cache memory portion to the main memory portion and controlling (enabling/disabling) the scheduling of cache cleaning operations. | 08-12-2010 |
| 20100211721 | MEMORY NETWORK METHODS, APPARATUS, AND SYSTEMS - Apparatus and systems may include a first node group include a first network node coupled to a memory, the first network node including a first port, a second port, a processor port, and a hop port. Network node group may include a second network node coupled to a memory, the second network node including a first port, a second port, a processor port, and a hop port, the hop port of the second network node coupled to the hop port of the first network node and configured to communicate between the first network node and the second network node. Network node group may include a processor coupled to the processor port of the first network node and coupled to the processor port of the second network node, the processor configured to access the first memory through the first network node and the second memory through the second network node. Other apparatus, systems, and methods are disclosed. | 08-19-2010 |
| 20100211722 | METHOD FOR TRANSMITTING SPECIAL COMMANDS TO FLASH STORAGE DEVICE - The invention provides a data storage system. In one embodiment, the data storage system comprises a host and a flash storage device. The host sends a series of first access commands for accessing a plurality of special files to the flash storage device. The flash storage device having the stored plurality of special files and a command-symbol mapping table, sequentially generates a plurality of first digits respectively corresponding to the special files accessed by the first access commands to obtain a first data stream, converts the first data stream to a plurality of first special commands according to the command-symbol mapping table, and performs operations according to the first special commands. Each of the special files corresponds to a digit, the command-symbol mapping table records a corresponding relationship between a plurality of symbols and a plurality of special commands, and each of the symbols comprises a plurality of digits. | 08-19-2010 |
| 20100211723 | Memory controller, memory system with memory controller, and method of controlling flash memory - Access to flash memories is controlled so that efficiency of data writing and effective utilization of storage area go together. In the access control, priority order, for physical blocks each storing effective data, is managed so that a position of a physical block in the assignment order becomes higher according as assignment of a logical block to the physical block is performed more recently. When assigning a logical block to a free physical block, a determination is made whether a position of a previous physical block is higher than a predetermined position in the priority order. The previous physical block is a physical block, then, corresponding to the same logical block as the free physical block. When the determination is negative, effective data stored in the previous physical block is transferred to the free physical block. | 08-19-2010 |
| 20100211725 | INFORMATION PROCESSING SYSTEM - An information processing system comprises a main memory operative to store data, and a control circuit operative to access the main memory for data. The main memory includes a nonvolatile semiconductor memory device containing electrically erasable programmable nonvolatile memory cells each using a variable resistor, and a DRAM arranged as a cache memory between the control circuit and the nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device has a refresh mode of rewriting stored data. The control circuit activates the nonvolatile semiconductor memory device in said refresh mode based on the number of accesses to the nonvolatile semiconductor memory device. | 08-19-2010 |
| 20100211726 | METHOD FOR MANIPULATING STATE MACHINE STORAGE IN A SMALL MEMORY SPACE - A method includes configuring a flash memory device including a first memory sector having a primary memory sector correspondence, a second memory sector having an alternate memory sector correspondence, and a third memory sector having a free memory sector correspondence, copying a portion of the primary memory sector to the free memory sector, erasing the primary memory sector, and changing a correspondence of each of the first memory sector, the second memory sector, and the third memory sector. | 08-19-2010 |
| 20100217917 | SYSTEM AND METHOD OF FINALIZING SEMICONDUCTOR MEMORY - Systems and methods of finalizing a semiconductor memory are disclosed. A method includes receiving an instruction to finalize data at a data storage device that includes a controller coupled to a semiconductor memory. The data storage device also includes a status indicator to indicate a finalize status of the semiconductor memory. In response to receiving the instruction to finalize the data at the data storage device, the status indicator is set to a finalize value. Write to the semiconductor memory operations are prevented by the controller in response to the status indicator having the finalize value. | 08-26-2010 |
| 20100217918 | DATA STORAGE DEVICE AND METHOD FOR ACCESSING FLASH MEMORY - The invention provides a method for accessing a flash memory. In one embodiment, the flash memory comprises a plurality of memory units, each of the memory units has a physical address, and an address link table records a mapping relationship between a plurality of logical addresses and a plurality of physical addresses. First, first data to be written to a first logical address is received from a host. Whether the first data is predetermined data is the determined. Whether the first logical address is mapped to a null physical address is then determined according to the address link table. When the first data is the predetermined data and the first logical address is not mapped to the null physical address according to the address link table, the address link table is modified to map the first logical address to the null physical address. | 08-26-2010 |
| 20100217919 | MEMORY CONTROLLER, SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state. | 08-26-2010 |
| 20100217920 | Memory system and address allocating method of flash translation layer thereof - The memory system includes a flash memory and a memory controller. The flash memory has at least two addresses with different program times. The memory controller is configured to control the flash memory. The memory controller is configured to assign an address corresponding to a shorter program time from among the at least two addresses for a write operation executed at interruption of a power supply to the flash memory. The assigned address is used to store data of the memory controller in the flash memory. | 08-26-2010 |
| 20100217921 | Memory system and data processing method thereof - A method of processing data of a nonvolatile memory includes performing a randomization operation on a data unit including page data to be programmed into the nonvolatile memory and page metadata corresponding to the page data and generating a random seed; and programming the randomized data unit, and the random seed into the nonvolatile memory, the randomized data unit including the randomized page data and the randomized page metadata. The random seed is programmed within the page metadata and a position at which the random seed is programmed is based on a characteristic of the page data. | 08-26-2010 |
| 20100217922 | ACCESS MODULE, STORAGE MODULE, MUSICAL SOUND GENERATING SYSTEM AND DATA WRITING MODULE - An access module is connected to a storage module which stores multiplexed musical sound data in a non-compressed form. Based on a read request status of each sounding channel and access status of the nonvolatile storage module as a read target, a read instructing part transfers a read instruction to the storage module and reads musical sound data in parallel from the storage modules. In this musical sound generating system, since a plurality of pieces of musical sound data can be read from a plurality of nonvolatile storage modules in parallel, a sounding delay time can be made smaller than an acceptable time. For this reason, a prevailing mass NAND flash memory can be used as a memory for the musical sound data, thereby realizing a high sound quality and compact musical sound generating system. | 08-26-2010 |
| 20100217923 | STORAGE DEVICE WITH FLASH MEMORY - According to one embodiment, a write detector detects a predetermined state where a flash memory contains an area to which write data subject to a write request from a host is to be written and from which data has been erased. A data reception controller allows a data buffer to receive the requested write data in accordance with the detection of the predetermined state. | 08-26-2010 |
| 20100217924 | HYBRID MEMORY DEVICE WITH SINGLE INTERFACE - Described is a technology by which a memory controller is a component of a hybrid memory device having different types of memory therein (e.g., SDRAM and flash memory), in which the controller operates such that the memory device has only a single memory interface with respect to voltage and access protocols defined for one type of memory. For example, the controller allows a memory device with a standard SDRAM interface to provide access to both SDRAM and non-volatile memory with the non-volatile memory overlaid in one or more designated blocks of the volatile memory address space (or vice-versa). A command protocol maps memory pages to the volatile memory interface address space, for example, permitting a single pin compatible multi-chip package to replace an existing volatile memory device in any computing device that wants to provide non-volatile storage, while only requiring software changes to the device to access the flash. | 08-26-2010 |
| 20100217925 | BLOCK MANAGEMENT FOR MASS STORAGE - An embodiment of the present invention includes a nonvolatile memory system comprising nonvolatile memory for storing sector information, the nonvolatile memory being organized into blocks with each block including a plurality of sectors, each sector identified by a logical block address and for storing sector information. A controller is coupled to the nonvolatile memory for writing sector information to the latter and for updating the sector information, wherein upon updating sector information, the controller writes to the next free or available sector(s) of a block such that upon multiple re-writes or updating of sector information, a plurality of blocks are substantially filled with sector information and upon such time, the controller rearranges the updated sector information in sequential order based on their respective logical block addresses thereby increasing system performance and improving manufacturing costs of the controller. | 08-26-2010 |
| 20100217926 | Direct Data File Storage Implementation Techniques in Flash Memories - Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. The file based interface between the host and memory systems allows the memory system controller to utilize the data storage blocks within the memory with increased efficiency. | 08-26-2010 |
| 20100217927 | STORAGE DEVICE AND USER DEVICE INCLUDING THE SAME - A storage device includes a host interface, a buffer memory, a storage medium, and a controller. The host interface is configured to receive storage data and an invalidation command, where the invalidation command is indicative of invalid data among the storage data received by the host interface. The buffer memory is configured to temporarily store the storage data received by the host interface. The controller is configured to execute a transcribe operation in which the storage data temporarily stored in the buffer memory is selectively stored in the storage medium. Further, the controller is responsive to receipt of the invalidation command to execute a logging process when a memory capacity of the invalid data indicated by the invalidation command is equal to or greater than a reference capacity, and to execute an invalidation process when the memory capacity of the invalid data is less than the reference capacity. The logging process includes logging a location of the invalid data, and the invalidation process includes invalidating the invalid data. | 08-26-2010 |
| 20100223420 | Memory system and data management method of flash translation layer thereof - A data management method includes determining the size of input data, storing the input data in a log block if the size of the input data is determined to be a write unit, and storing the input data in a partial block if the size of the input data is determined to be smaller than the write unit. The log block is a temporary block storing data of same addresses and the partial block is a temporary block storing data regardless of their addresses. The memory system includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory. The memory controller is configured to temporarily store input data smaller than a write unit in a selected memory block even when the input data have different addresses. | 09-02-2010 |
| 20100223421 | User device including flash memory storing index and index accessing method thereof - A user device includes a flash memory configured to store an index including a plurality of index nodes and a controller configured to control the flash memory. The controller is configured to detect a pointer ID corresponding to a selected key of a first index node, translate the detected pointer ID to an index address by using a pointer table, and access a second index node corresponding to the selected key by using the index address. | 09-02-2010 |
| 20100223422 | Advanced Dynamic Disk Memory Module - Memory modules address the growing gap between main memory performance and disk drive performance in computational apparatus such as personal computers. Memory modules disclosed herein fill the need for substantially higher storage capacity in end-user add-in memory modules. Such memory modules accelerate the availability of applications, and data for those applications. An exemplary application of such memory modules is as a high capacity consumer memory product that can be used in Hi-Definition video recorders. In various embodiments, memory modules include a volatile memory, a non-volatile memory, and a command interpreter that includes interfaces to the memories and to various busses. The first memory acts as an accelerating buffer for the second memory, and the second memory provides non-volatile backup for the first memory. In some embodiments data transfer from the first memory to the second memory may be interrupted to provide read access to the second memory. | 09-02-2010 |
| 20100223423 | Direct File Data Programming and Deletion in Flash Memories - Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. The file based interface between the host and memory systems allows the memory system controller to utilize the data storage blocks within the memory with increased efficiency. | 09-02-2010 |
| 20100223424 | MEMORY SYSTEM AND CONTROL METHOD THEREOF - A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest. | 09-02-2010 |
| 20100228905 | MEMORY CONTROLLER, MEMORY CARD, AND NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system includes a memory card ( | 09-09-2010 |
| 20100228906 | Managing Data in a Non-Volatile Memory System - Management of data in a non-volatile memory system is disclosed. A write command may be received that indicates a logical block address for writing data associated with the write command. The logical block address may be within a logical zone. The logical zone may be one of a plurality of logical zones within the non-volatile memory, wherein each of the plurality of logical zones comprises a different range of logical block addresses than the rest of the plurality of logical zones. The logical zone may further comprise a temporary storage block. The data associated with the write command may be written to the temporary storage block of the logical zone when a size of the data associated with the write command does not exceed a threshold. The data associated with the write command may be transferred from the temporary storage block to the logical block address in response to a trigger event. | 09-09-2010 |
| 20100228907 | METHOD OF EVENLY USING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method of evenly using a plurality of blocks of a Flash memory comprises: providing at least one threshold value, which is utilized for sieving out blocks suitable for use from the plurality of blocks according to erase counts of the plurality of blocks; and by comparing erase counts of at least a portion of the plurality of blocks with the threshold value, sieving out a specific block for use from the plurality of blocks according to a purpose of use. An associated memory device and a controller thereof are also provided, where the controller comprises: a ROM arranged to store a program code, wherein the controller is provided with the at least one threshold value through the program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory. The controller sieves out the specific block according to the purpose of use. | 09-09-2010 |
| 20100228908 | MULTI-PORT MEMORY DEVICES AND METHODS - An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion. | 09-09-2010 |
| 20100228909 | Caching Performance Optimization - A method for managing data storage is described. The method includes receiving data from an external host at a peripheral storage device, detecting a file system type of the external host, and adapting a caching policy for transmitting the data to a memory accessible by the storage device, wherein the caching policy is based on the detected file system type. The detection of the file system type can be based on the received data. The detection bases can include a size of the received data. In some implementations, the detection of the file system type can be based on accessing the memory for file system type indicators that are associated with a unique file system type. Adapting the caching policy can reduce a number of data transmissions to the memory. The detected file system type can be a file allocation table (FAT) system type. | 09-09-2010 |
| 20100235563 | METHOD FOR ENHANCING PERFORMANCE OF A FLASH MEMORY, AND ASSOCIATED PORTABLE MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing performance of a Flash memory includes: providing a random access memory (RAM); utilizing the RAM to temporarily store at least one virtual Flash block; and selectively moving data of the virtual Flash block to the Flash memory in order to write at least one new page in the Flash memory. An associated portable memory device and a controller thereof are also provided, where the controller includes: a read only memory (ROM) arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory. In addition, the controller that executes the program code by utilizing the microprocessor selectively moves the data of the virtual Flash block to the Flash memory in order to write at least one new page in the Flash memory. | 09-16-2010 |
| 20100235564 | SEMICONDUCTOR MEMORY DEVICE - First conversion from a logical address to a physical address is performed, and data is written in to a region in a first storage region specified by the first conversion. Second conversion from a logical address to a physical address which is different from the first conversion is performed, and data is written into a region in a second storage region specified by the second conversion. When the controller detects sequential writing having a predetermined length or more, it shifts to a first write mode that data is written into the first storage region. When the controller detects that a difference between a logical address at the end of a previous write operation and a logical address at the start of a subsequent write operation is not present in a predetermined range, it shifts to a second write mode that data is written into the second storage region. | 09-16-2010 |
| 20100235565 | APPARATUS AND METHOD TO PROTECT METADATA AGAINST UNEXPECTED POWER DOWN - A system includes first memory configured to store first metadata to associate logical addresses with physical addresses. Second memory is configured to include the physical addresses, to store first data based on the physical addresses, and to store portions of the first metadata when a status of a predetermined group of the physical addresses is changed. A recovery module is configured to update the first metadata based on the portions of the first metadata stored in the second memory. | 09-16-2010 |
| 20100235566 | FLASH MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME - Described herein is a flash memory apparatus and method controlling the same. The flash memory apparatus includes a processor and one or more flash memory units. The processor controls one or more memory operations performed in the one or more flash memory units. The processor stops controlling a memory operation in a flash memory unit when the memory operation is performed, and continues performing the memory operation in the flash memory unit when the flash memory unit generates an interrupt signal. | 09-16-2010 |
| 20100235567 | AIRCRAFT INCLUDING DATA DESTRUCTION MEANS - The aircraft includes:
| 09-16-2010 |
| 20100235568 | STORAGE DEVICE USING NON-VOLATILE MEMORY - According to one embodiment, a storage device includes a plurality of writable non-volatile memory devices, a buffer memory, a memory controller, and a spare non-volatile memory device. The buffer memory temporarily stores write data from a host. The memory controller writes the write data in the buffer memory to the non-volatile memory devices in a distributed manner. The memory controller writes write data in the buffer memory not having been written to the non-volatile memory devices to the spare non-volatile memory device when detecting a power down, and writes the write data having been written to the spare non-volatile memory device to the buffer memory when the power is restored. | 09-16-2010 |
| 20100235569 | Storage Optimization System - A method and apparatus optimizes storage on solid-state memory devices. The system aggregates object storage write requests. The system determines whether objects associated with the object storage requests that have been aggregated fit in a block of the solid-state memory device within a defined tolerance. Upon the aggregation of object storage write requests that fit in a block of the solid-state memory device, the system writes the objects associated with the aggregated object storage write requests to the solid-state memory device | 09-16-2010 |
| 20100235570 | COMMAND CONTROLLER, PREFETCH BUFFER AND METHODS FOR ACCESSING A SERIAL FLASH IN AN EMBEDDED SYSTEM - The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. An embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash. | 09-16-2010 |
| 20100241786 | Apparatus and method for optimized NAND flash memory management for devices with limited resources - An apparatus and method for managing memory in low-end electronic devices is provided. The apparatus includes a memory management unit. The memory management unit configured to allocate a portion of random access memory and a portion of flash memory as swap areas. The memory management unit performs swapping operations by swapping pages of content between the random access memory swap area and one or more blocks of the flash memory swap area. Thereafter, a page of content can be loaded from the flash memory swap area. The memory management unit also allocates a portion of flash memory as a garbage collection area. The memory management unit transfers dirty pages from the flash swap area to the garbage collection unit to free up flash memory swap area blocks. | 09-23-2010 |
| 20100241787 | SENSOR PROTECTION USING A NON-VOLATILE MEMORY CELL - A method and apparatus for protecting an electrical device using a non-volatile memory cell, such as an STRAM or RRAM memory cell. In some embodiments, a memory element is connected in parallel with a sensor element, where the memory element is configured to be repetitively reprogrammable between a high resistance state and a low resistance state. The memory element is programmed to the low resistance state when the sensor element is in a non-operational state and reprogrammed to the high resistance state when the sensor element is in an operational state. | 09-23-2010 |
| 20100241788 | FLASH MEMORY WRITING MTHEOD AND STROAGE SYSTEM AND CONTROLLER USING THE SAME - A flash memory writing method for writing data into a flash memory storage system is provided. In the present method, a big data usage number and a small data usage number are counted for each logical unit in the flash memory storage system, so as to respectively represent the numbers of writing a big data and a small data into each the logical unit. When a host system writes new data into a logical unit in the flash memory storage system, the new data is written through different writing processes according to the big data usage number and the small data usage number of the logical unit. Thereby, the data writing efficiency is improved and the lifespan of the flash memory storage system is prolonged. | 09-23-2010 |
| 20100241789 | DATA STORAGE METHOD FOR FLASH MEMORY AND DATA STORAGE SYSTEM USING THE SAME - A data storage method for a flash memory storage device is provided. The method includes disposing a pattern identification unit in the flash memory storage device and disposing a pattern analysis unit in a host connected to the flash memory storage device. The method further includes analyzing a usage pattern of each flash memory storage address in the flash memory storage device by using the pattern analysis unit, receiving information from the pattern analysis unit through the pattern identification unit to identify the usage pattern of each flash memory storage address, and storing data into each flash memory storage address through a corresponding process according to the usage pattern of the flash memory storage address. Thereby, data can be stored according to the usage pattern of each flash memory storage address, and accordingly the speed of storing data into the flash memory storage device can be effectively increased. | 09-23-2010 |
| 20100241790 | METHOD OF STORING DATA INTO FLASH MEMORY IN A DBMS-INDEPENDENT MANNER USING THE PAGE-DIFFERENTIAL - The present invention proposes an effective and efficient method of storing data called page-differential logging for flash-based storage systems. The primary characteristics of the invention are: (1) it writes only the page-differential that is defined as the difference between an original page in flash memory and an up-to-date page in memory; (2) it computes and writes the page-differential only when an updated page needs to be reflected into flash memory. When an updated page needs to be reflected into flash memory, the present invention stores the page into a base page and a differential page in flash memory. When a page is recreated from flash memory, it reads the base page and the differential page, and then, creates the page by merging the base page with its page-differential in the differential page. This invention significantly improves I/O performance of flash-based storage systems compared with existing page-based and log-based methods. | 09-23-2010 |
| 20100241791 | CONTROLLER WHICH CONTROLS OPERATION OF NONVOLATILE SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY DEVICE INCLUDING NONVOLATILE SEMICONDUCTOR MEMORY AND CONTROLLER THEREFORE - A controller includes an instruction table memory, a program counter, a first decoder, and a first executing unit. The instruction table memory stores an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory. A read address in the instruction table memory is set to the program counter. The first decoder decodes the instruction code read from the instruction table memory to output a first decode signal. The first executing unit executes access to the nonvolatile semiconductor memory on the basis of the first decode signal output from the first decoder. | 09-23-2010 |
| 20100241792 | STORAGE DEVICE AND METHOD OF MANAGING A BUFFER MEMORY OF THE STORAGE DEVICE - A storage device including a processor to transmit N pages of data from one or more pages in a buffer memory where N is a natural number. The storage device also includes a flash memory to program in parallel the N pages of data to N flash chips. The N pages may be transmitted via one or more channels. | 09-23-2010 |
| 20100241793 | STORAGE SYSTEM AND METHOD FOR CONTROLLING STORAGE SYSTEM - The present invention efficiently uses the storage capacity in a storage system that has flash memory as a storage medium. | 09-23-2010 |
| 20100241794 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one aspect of the present invention includes: a memory cell array provided to perform programming in page units; and a control circuit provided to control the programming. The control circuit includes: means that performs a first detection for memory cells in a part provided as a unit smaller than a page, concurrently with programming to memory cells to be written in a page; and means that subjects the memory cells in the page to a second detection that takes into consideration a failure relief due to a redundant region, when the number of memory cells of unwritten state in the part as detected by the first detection becomes equal to or less than a first constant, and that ends the program operation when the number of memory cells of unwritten state in the page becomes equal to or less than a second constant. | 09-23-2010 |
| 20100241795 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 09-23-2010 |
| 20100241796 | MEMORY SYSTEM PROTECTED FROM ERRORS DUE TO READ DISTURBANCE AND READING METHOD THEREOF - A method of reading a memory system including a flash memory includes: reading data from a page in a first block of the flash memory, incrementing a counter each time data is read from the page to store a corresponding number of read-out cycles of the flash memory, and copying data from the first block of the flash memory to a second block of the flash memory when the counter exceeds a reference number of read-out cycles. The data from the first block includes data from the page. | 09-23-2010 |
| 20100241797 | STORAGE DEVICE AND STORING METHOD - To enable a capacity of an entire storage device to be kept by adding a flash drive or a flash module in the flash drive for a flash memory that has a failure, even if the storage device using the flash memory has a failure in its part such as a part of flash memory chip has a failure, for example, the flash memory chip has run out of its lifetime. In a storage device equipped with two or more memory device units with a plurality of semiconductor memory devices, each of which has a functional capacity unit smaller than a capacity of an entire semiconductor memory device and has a writing lifetime for each functional capacity unit, only a functional capacity unit whose writing lifetime is run out to be determined as unable to be written is substituted by a functional capacity unit in a memory device of the other memory device unit to keep a predetermined capacity of the entire device. | 09-23-2010 |
| 20100241798 | ROBUST INDEX STORAGE FOR NON-VOLATILE MEMORY - A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data structures/tables in the hierarchy, one or more of which can be updated in-place multiple times without having to overwrite data. This hierarchal address translation data structure and multiple update of data entries in the individual tables/data structures allow the hierarchal address translation data structure to be efficiently stored in a non-volatile memory array without markedly inducing write fatigue or adversely affecting the lifetime of the part. The hierarchal address translation of embodiments of the present invention also allow for an address translation layer that does not have to be resident in system RAM for operation. | 09-23-2010 |
| 20100250826 | MEMORY SYSTEMS WITH A PLURALITY OF STRUCTURES AND METHODS FOR OPERATING THE SAME - Memory systems, such as solid state drives, and methods of operating such memory systems are disclosed, such as those adapted to provide parallel processing of data using redundant array techniques. Individual flash devices or channels containing multiple flash devices are operated as individual drives in an array of redundant drives. Ranges of physical addresses corresponding to logical addresses are provided to a host for performing read and write operations on different channels, such as to improve read variability. | 09-30-2010 |
| 20100250827 | Apparatus for Enhancing Flash Memory Access - An apparatus for interfacing between a CPU and Flash memory units, enabling optimized sequential access to the Flash memory units. The apparatus interfaces between the address, control and data buses of the CPU and the address, control and data lines of the Flash memory units. The apparatus anticipates the subsequent memory accesses, and interleaves them between the Flash memory units. An optimization of the read access is therefore provided, thereby improving Flash memory throughput and reducing the latency. Specifically, the apparatus enables improved Flash access in embedded CPUs incorporated in a System-On-Chip (SOC) device. | 09-30-2010 |
| 20100250828 | CONTROL SIGNAL OUTPUT PIN TO INDICATE MEMORY INTERFACE CONTROL FLOW - Embodiments include but are not limited to apparatuses and systems including a memory array including a plurality of non-volatile memory cells, and a control signal output pin operatively coupled to the memory array. The control signal output pin may be configured to provide a control signal indicative of the memory interface control flow including, for example, an availability of the memory array for reading or writing. Other embodiments may be described and claimed. | 09-30-2010 |
| 20100250829 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR SENDING LOGICAL BLOCK ADDRESS DE-ALLOCATION STATUS INFORMATION - A system, method, and computer program product are provided for sending de-allocation status information. In use, a de-allocation status of at least a portion of memory associated with a logical block address is determined. Additionally, de-allocation status information is generated, based on the determination. Furthermore, the de-allocation status information is sent to a device. | 09-30-2010 |
| 20100250830 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR HARDENING DATA STORED ON A SOLID STATE DISK - A system, method, and computer program product are provided for hardening data stored on a solid state disk. In operation, it is determined whether a solid state disk is to be powered off. Furthermore, data stored on the solid state disk is hardened if it is determined that the solid state disk is to be powered off. | 09-30-2010 |
| 20100250831 | DATA STORAGE SYSTEM MANAGER AND METHOD FOR MANAGING A DATA STORAGE SYSTEM - A data storage system manager includes one or more servers, at least one data collector deployed on at least one of the servers, at least one policy engine deployed on at least one of the servers, and at least one configuration manager deployed on at least one the servers. The at least one data collector is configured to collect resource utilization information including data storage wear rate of data storage system data storage modules. The at least one policy engine is configured to evaluate the collected information and to initiate changes to a configuration of the data storage system based on data storage wear rate and work load distribution policies. The at least one configuration manager is configured to implement the changes initiated by the at least one policy engine to control the data storage wear rate and a skew of the work load distribution within the data storage system. | 09-30-2010 |
| 20100250832 | STORAGE SERVICE DEVICE WITH DUAL CONTROLLER AND BACKUP METHOD THEREOF - A storage service device with a dual controller and a backup method thereof are applicable to provide the same view service to an event-login log and a configuration file of a server. The storage service device includes a first control module, a second control module, a battery unit, a basic input/output system (BIOS), and a backup procedure. Once a power failure occurs to the server, the following backup procedure is performed a hardware interrupt signal is sent to the battery unit, so as to provide an operation power to a first memory module and a second memory module; an index page of the first memory module is synchronized with that of the second memory module; and the updated index pages are recorded into a first flash memory and a second flash memory respectively. | 09-30-2010 |
| 20100250833 | TECHNIQUES TO PERFORM POWER FAIL-SAFE CACHING WITHOUT ATOMIC METADATA - A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required. | 09-30-2010 |
| 20100250834 | METHOD AND SYSTEM TO PERFORM CACHING BASED ON FILE-LEVEL HEURISTICS - A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved. | 09-30-2010 |
| 20100250835 | METHOD FOR PROTECTING SENSITIVE DATA ON A STORAGE DEVICE HAVING WEAR LEVELING - Disclosed is a method for protecting sensitive data in a storage device having wear leveling. In the method, a write command, with an associated sensitive write signal indicating that sensitive data is associated with the write command, is received. The sensitive data is further associated with at least one address pointing to a storage location within an initial physical storage block. The write command is executed by writing to at least one storage location within an available physical storage block, pointing the at least one address to the at least one storage location within the available physical storage block, and erasing the initial physical storage block to complete execution of the write command. | 09-30-2010 |
| 20100250836 | Use of Host System Resources by Memory Controller - A method for data storage includes, in a system that includes a host having a host memory and a memory controller that is separate from the host and stores data for the host in a non-volatile memory including multiple analog memory cells, storing in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory. A command that causes the memory controller to access a given group of the analog memory cells is received from the host. In response to the command, a respective information item relating to the given group of the analog memory cells is retrieved from the host memory by the memory controller, and the given group of the analog memory cells is accessed using the retrieved information item. | 09-30-2010 |
| 20100250837 | Method for Addressing Page-Oriented Non-Volatile Memories - A method for addressing memory pages of a non-volatile memory in a memory system with a memory controller and a further volatile memory. The non-volatile memory is organized in erasable memory blocks with a multiplicity of memory pages, and each memory page, containing a number of sectors, can be written individually. The volatile memory holds an address translation table specifying an assignment of logical memory page addresses to physical memory page addresses. By way of the memory controller, a reconstruction table is stored as a copy of the address translation table in one or more memory blocks in the non-volatile memory, a log book table with data records containing changed assignments of logical memory page addresses to physical memory page addresses, is carried in the volatile memory and, if the log book table exceeds a predetermined size, a changed reconstruction table is stored in the non-volatile memory. | 09-30-2010 |
| 20100250838 | PORTABLE DATA CARRIER COMPRISING A WEB SERVER - In a method for providing data for a data processing device ( | 09-30-2010 |
| 20100250839 | METHOD FOR CONTROLLING MEMORY CARD AND METHOD FOR CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY - A method for controlling a memory card which includes a nonvolatile semiconductor memory whose memory area includes a plurality of write areas is disclosed. A first area which is a part of the plurality of write areas is set in accordance with management executed by a first file system. The first file system sequentially writes data along a direction in which addresses of the plurality of write areas increase. A second area which is a part of the plurality of write areas is set in accordance with management executed by a second file system. The second file system writes data in an order which does not depend on the addresses. | 09-30-2010 |
| 20100250840 | VERSION BASED NON-VOLATILE MEMORY TRANSLATION LAYER - A non-volatile memory and erase block/data block/sector/cluster update and address translation scheme utilizing a version number is detailed that enhances data updating and helps reduce program disturb of the memory cells of the non-volatile memory device. The various embodiments utilize a version number associated with each erase block, data block, sector, and/or cluster. This allows for determination of currently valid data block, sector and/or cluster associated with the logical ID of the data grouping by locating the most recent version associated with the logical ID. With this approach, old data need not be invalidated by programming a valid/invalid flag, avoiding the risk of program disturb in the surrounding data rows. | 09-30-2010 |
| 20100262752 | STORAGE VIRTUAL CONTAINERS - A controller of a Solid State Device (SSD) defines a mapping from memory devices, such as flash packages, that make up the SSD to one or more storage virtual containers. The storage virtual containers are exposed to an operating system by the controller through an interface. The operating system may then make operation requests to the one or more storage virtual containers, and the controller may use the mapping to fulfill the operation requests from the corresponding flash packages. The storage virtual containers are mapped to the flash packages to take advantage of the parallelism of the flash packages in the SSD so that the controller may fulfill operation requests received from the operating system in parallel. | 10-14-2010 |
| 20100262753 | METHOD AND APPARATUS FOR CONNECTING MULTIPLE MEMORY DEVICES TO A CONTROLLER - A control system includes a controller having shared pins and unique pins for receiving and outputting signals from and to first and second memory devices. The first memory device includes signal lines which are electrically connected to shared pins, and the second memory device includes signal lines which are electrically connected to the shared pins together with the signal lines from the first memory device. The controller selectively inputs signals from and output signals to the first memory device and second memory device through the select shared pins. | 10-14-2010 |
| 20100262754 | CPU DATA BUS PLD/FPGA INTERFACE USING DUAL PORT RAM STRUCTURE BUILT IN PLD - A programmable logic device and a system and method using the programmable logic device are disclosed. The programmable logic device may include first and second ports in data communication with a memory block including a pair of address areas. The system may include the programmable logic device in data communication with a central processing unit and a controller. The method may include generating a command from the central processing unit based on data read from one of the address areas and written to the second address area wherein the address areas are associated with a common memory address. | 10-14-2010 |
| 20100262755 | MEMORY SYSTEMS FOR COMPUTING DEVICES AND SYSTEMS - Memory systems and devices are provided. One memory system includes a controller configured to be coupled to a plurality of computing devices, a plurality of Multi-Level Cell (MLC) devices coupled to the controller, and a Single-Level Cell (SLC) device coupled to the controller and the plurality of MLC devices. The MLC devices are configured to split the storage of data across the plurality of MLC devices and the SLC device is configured to function as a parity device for the data. A memory device includes a controller, a plurality of MLC FLASH devices, and a SLC FLASH device. The MLC FLASH devices are configured to split the storage of data across the plurality of MLC FLASH devices and the SLC FLASH device is configured to function as a parity device for the data. Also provided are computing devices including the above memory device. | 10-14-2010 |
| 20100262756 | METHOD FOR WRITING TO AND ERASING A NON-VOLATILE MEMORY - A method for writing to and erasing a non-volatile memory is described. The method includes determining the size of a command window for use in n write operations for the non-volatile memory, each write operation having the same time period. A long latency erase command is sliced by a factor of n to provide a plurality of erase slices, each erase slice having the same time period. The method further includes executing n commands to the non-volatile memory, each command composed of the combination of one of the n write operations and one of the erase slices. The total of the time period of one erase slice added to the time period of one write operation is less than or equal to the size of the command window. | 10-14-2010 |
| 20100262757 | DATA STORAGE DEVICE - A data storage device may include a first memory board having multiple memory chips and a controller board that is arranged and configured to operably connect to the first memory board. The controller board may include an interface to a host and a controller that is arranged and configured to control command processing for multiple different types of memory chips, automatically recognize a type of the memory chips on the first memory board, receive commands from the host using the interface, and execute the commands using the memory chips. | 10-14-2010 |
| 20100262758 | DATA STORAGE DEVICE - A data storage device may include a first memory board including multiple memory chips and a controller board that is arranged and configured to operably connect to the first memory board. The controller board may include an interface to a host and a controller that includes a power module and that is arranged and configured to control command processing for multiple memory chips having different voltages, automatically recognize a voltage of the memory chips on the first memory board, configure the power module to operate at the recognized voltage of the memory chips, receive commands from the host using the interface and execute the commands using the memory chips. | 10-14-2010 |
| 20100262759 | DATA STORAGE DEVICE - A data storage device may include a first memory board and a second memory board, where the first memory board and the second memory board each comprise multiple memory chips. The data storage device may include a controller board that is arranged and configured to operably connect to the first memory board and the second memory board, where the controller board includes a high speed interface and a controller that is arranged and configured to receive commands from a host using the high speed interface and to execute the commands, where the first memory board and the second memory board are each separately removable from the controller board. | 10-14-2010 |
| 20100262760 | COMMAND PROCESSOR FOR A DATA STORAGE DEVICE - An apparatus for queuing and ordering commands for a data storage device may include a slot tracker module that is arranged and configured to track available slots for commands from a host, a command transfer module that is operably coupled to the slot tracker module and that is arranged and configured to retrieve commands from the host based on a number of the available slots, a pending command module that is operably coupled to the command transfer module and that is arranged and configured to queue and order the commands from the host for processing using an ordered list that is based on an age of the commands and a task dispatch module that is operably coupled to the pending command module and that is arranged and configured to dispatch the commands for processing using the ordered list from the pending command module and an availability of storage locations. | 10-14-2010 |
| 20100262761 | PARTITIONING A FLASH MEMORY DATA STORAGE DEVICE - A method of partitioning a data storage device that has a plurality of memory chips includes determining a number memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips, defining a second partition of the data storage device via the host where the second partition includes a second subset of the plurality of memory chips, such that the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset. | 10-14-2010 |
| 20100262762 | RAID CONFIGURATION IN A FLASH MEMORY DATA STORAGE DEVICE - A method of storing data in a flash memory data storage device that includes a plurality of memory chips is disclosed. The method includes determining a number of memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and defining a second partition of the data storage device via a host coupled to the data storage device, where the second partition includes a second subset of the plurality of memory chips. First data is written to the first partition while reading data from the second partition, and first data is written to the second partition while reading data from the first partition. | 10-14-2010 |
| 20100262763 | DATA ACCESS METHOD EMPLOYED IN MULTI-CHANNEL FLASH MEMORY SYSTEM AND DATA ACCESS APPARATUS THEREOF - A data access method used in a multi-channel flash memory system includes: respectively writing a plurality of data into a plurality of buffer areas of a buffer unit through direct memory accessing; and sequentially reading the plurality of data from the plurality of buffer areas, and respectively and synchronously storing the plurality of read data into the plurality of flash memory units, wherein each of the plurality of data is a data block protected by an error correction code (ECC). | 10-14-2010 |
| 20100262764 | METHOD FOR ACCESSING STORAGE APPARATUS AND RELATED CONTROL CIRCUIT - A storage apparatus includes a first storage unit and at least a second storage unit. A method for accessing the storage apparatus generates a plurality of bad block lists regarding the plurality of the storage units, respectively, and according to at least one bad block indicated by a bad block list of the first storage unit, configures at least a good block in each second storage unit corresponding to the at least one bad block of the first storage unit as a replacement block of each second storage unit. Accordingly, the method generates a mapping result of each second storage unit according to a bad block list of the second storage unit and each replacement block, and accesses the storage apparatus according to the bad block list of the first storage unit and each mapping result. | 10-14-2010 |
| 20100262765 | STORAGE APPARATUS, COMPUTER SYSTEM HAVING THE SAME, AND METHODS THEREOF - A storage apparatus includes a memory unit and a controller to set up a memory space of the memory unit as a user data space and a spare space according to a signal representing at least one of the user data space and spare space. An electronic apparatus controls the storage apparatus, and a method controls at least one of the storage apparatus and the electronic apparatus to control a memory space of the storage apparatus. | 10-14-2010 |
| 20100262766 | GARBAGE COLLECTION FOR FAILURE PREDICTION AND REPARTITIONING - A method of formatting a data storage device that includes a plurality of flash memory chips includes monitoring a failure rate of memory blocks of one or more flash memory chips of a storage device that has a first usable size for user space applications, estimating a future usable size of the data storage device based on the monitored failure rate, and defining, via a host coupled to the data storage device, a second usable size of the data storage device for user space applications based on the monitored failure rate. | 10-14-2010 |
| 20100262767 | DATA STORAGE DEVICE - A data storage device may include a command bus, a status bus, multiple memory devices that are operably coupled to the command bus and to the status bus, and a controller including multiple channel controllers, where the channel controllers are operably coupled to the command bus and to the status bus and each of the channel controllers is arranged and configured to control one or more of the memory devices. The data storage device may include multiple programmable logic devices that are operably coupled to the status bus, where each of the programmable logic devices is configured to retrieve a ready/busy signal from each of the memory devices under control of one of the channel controllers using the status bus, serialize the ready/busy signals and communicate the serialized ready/busy signals to the channel controllers. | 10-14-2010 |
| 20100262768 | CONFIGURABLE FLASH MEMORY CONTROLLER AND METHOD OF USE - A FLASH memory controller is disclosed. The controller comprises a microcontroller. The microcontroller including firmware for providing different mappings for different types of FLASH memory chips. The controller also includes FLASH control logic for communicating with the microcontroller and adapted to communicate via a FLASH data bus to at least one FLASH memory chip. The FLASH control logic including mapping logic for configuring the FLASH data bus based upon the type of FLASH memory chip coupled thereto. A method and system in accordance with the present invention provides the following advantages: Configurable data bus on the FLASH memory controller through software to simplify routing complexity. Configurable chip select and control bus for flexibility of FLASH memory placement. Elimination of external resistor network for layout simplicity. A scalable architecture for higher data bus bandwidth support. Auto-detection of FLASH memory type and capacity configuration. | 10-14-2010 |
| 20100268864 | Logical-to-Physical Address Translation for a Removable Data Storage Device - A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone. | 10-21-2010 |
| 20100268865 | Static Wear Leveling - Methods for extending the service life of a data storage device and devices operable to perform those methods are presented. A master lookup table block may comprise lookup table blocks and store an erase count indicator for each lookup table block. Each lookup table block may be associated with a logical zone of a memory and comprise entries. Each entry may be associated with a logical block and comprise an erase count for a physical block corresponding to that logical block. A physical block erasure may be performed on a first physical block in the memory. The physical block erasure may be tracked by incrementally increasing a first erase count. An actual erase count may be determined for the first physical block. The entry for a logical block corresponding to the first physical block may be exchanged with another entry within a different lookup table block when the actual erase count for the first physical block exceeds a threshold. The different lookup table block may have a lower erase count indicator relative to that of the lookup table block comprising the entry for the logical block corresponding to the first physical block. | 10-21-2010 |
| 20100268866 | SYSTEMS AND METHODS FOR OPERATING A DISK DRIVE - System and methods for storing data to a storage device are provided. In embodiments, the storage device may include a disk drive with a solid-state memory for storing certain frequently updated information. In some embodiments, the solid-state memory may be used to store journaling information. | 10-21-2010 |
| 20100268867 | METHOD AND APPARATUS FOR UPDATING FIRMWARE AS A BACKGROUND TASK - A method comprising storing data in a first memory that includes a first portion that has read-only access during a normal mode of operation; and during a update mode of operation: copying at least one data structure from the first memory to a second memory where it is available for use during the update mode; and updating data in the first portion of the first memory. | 10-21-2010 |
| 20100268868 | FLASH STORAGE DEVICE AND OPERATING METHOD THEREOF - The invention also provides a flash storage device. In one embodiment, the flash storage device is coupled to a host, and comprises a random access memory and a controller. The random access memory stores a plurality of link tables therein, wherein each of the link tables corresponds to one of a plurality of management units of at least one flash memory, and the link tables store corresponding relationships between logical addresses and physical addresses of the corresponding management units. The controller receives an access logical address from the host, determines an access physical address corresponding to the access logical address according to the link tables stored in the random access memory, and accesses data from the flash memory according to the access physical address. | 10-21-2010 |
| 20100268869 | MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE AND CONTROLLER - A memory system comprises a nonvolatile memory device and a controller. The controller comprises a working memory and is configured to control the nonvolatile memory device. The nonvolatile memory device is configured to store drive data required to access the nonvolatile memory device. When an initialization operation of the memory system is performed, the controller activates an operation standby signal after loading a portion of the drive data stored in the nonvolatile memory device into the working memory. | 10-21-2010 |
| 20100268870 | DATA STORAGE DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME - A data storage device includes a flash memory including a plurality of data blocks and a flash translation layer that divides the plurality of data blocks into a data block of a first group and a data block of a second group, and that records the data signal to a data block of the first group or a data block of the second group which is extended from a data block of the first group. | 10-21-2010 |
| 20100268871 | NON-VOLATILE MEMORY CONTROLLER PROCESSING NEW REQUEST BEFORE COMPLETING CURRENT OPERATION, SYSTEM INCLUDING SAME, AND METHOD - A non-volatile memory controller, system and method capable of processing a next request as an interrupt before completing a current operation are disclosed. The non-volatile memory system includes a first memory storing meta data loaded from a flash memory; a second memory storing the meta data copied from the first memory; and a flash memory controller copying the meta data from the first memory to the second memory, changing the meta data in the second memory, and then re-copying the changed meta data from the second memory to the first memory during a first-type operation that requires changes in the meta data. | 10-21-2010 |
| 20100268872 | DATA STORAGE SYSTEM COMPRISING MEMORY CONTROLLER AND NONVOLATILE MEMORY - A data storage system comprising a storage device comprising at least one nonvolatile memory, and a controller connected to the storage device through a channel. The memory controller sends part or all of a command, address and data for a next operation to the nonvolatile memory while the nonvolatile memory device is in a busy state. The memory controller then performs a background operation while the nonvolatile memory device remains in the busy state. | 10-21-2010 |
| 20100268873 | FLASH MEMORY CONTROLLER UTILIZING MULTIPLE VOLTAGES AND A METHOD OF USE - A Flash memory controller is disclosed. The Flash memory controller comprises a host interface, a Flash memory interface, controller logic coupled between the host interface, the controller logic handling a plurality of voltages. The controller also includes a mechanism for allowing a multiple voltage host to interface with a high voltage or a multiple voltage Flash memory. A multiple voltage Flash memory controller in accordance with the present invention provides the following advantages over conventional Flash memory controllers: (1) a voltage host is allowed to interface with multiple Flash memory components that operate at different voltages in any combination; (2) power consumption efficiency is improved by integrating the programmable voltage regulator, and voltage comparator mechanism with the Flash memory controller; (3) External jumper selection is eliminated for power source configuration; and (4) Flash memory controller power source interface pin-outs are simplified. | 10-21-2010 |
| 20100274949 | DATA ACCESS METHOD FOR FLASH MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data access method for accessing a flash memory storage system, a storage system and a controller using the same are provided. A flash memory has a plurality of physical blocks, which are grouped into a system area, a data area, and a spare area. One or more variable tables are established to record transient information of each set of mother-child blocks of the data area and the spare area. The number of the variable table could be adjusted adaptively according to time required for writing the variable table into the system area, such that an overall data access efficiency of the flash memory storage system is enhanced. | 10-28-2010 |
| 20100274950 | MEMORY SYSTEM - A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit. | 10-28-2010 |
| 20100274951 | ELECTRONIC STORAGE DEVICE WITH IMPROVED STORAGE METHOD - An electronic storage device includes a first memory segment having at least one source block to store information, a second memory segment having at least one backup block corresponding to the source block to make a backup of the information in a LSB memory page of the source block and a control unit connecting with said first memory segment and second memory segment. The control unit reads/writes the first memory segment and second memory segment through two different signal channels respectively. The information can be simultaneously written into the first and second memory segment to get a backup of the information so that the information can be stored safely. The control unit recycles the backup block of the second memory segment not only after the source block of the first memory segment entirely finishes writing the information but also after the source block is erased up in order to release the storage space of the backup block. | 10-28-2010 |
| 20100274952 | CONTROLLER, DATA STORAGE DEVICE AND DATA STORAGE SYSTEM HAVING THE CONTROLLER, AND DATA PROCESSING METHOD - A controller, a data storage device and a data storage system including the controller, and a data processing method are provided. The controller may process a plurality of instructions in parallel by including a plurality of address translation central processing units (CPUs) in a multi-channel parallel array structure, thereby improving the performance of a semiconductor memory system. | 10-28-2010 |
| 20100274953 | DATA STORAGE DEVICE AND INFORMATION PROCESSING SYSTEM INCORPORATING DATA STORAGE DEVICE - A data storage device comprises a plurality of memory devices and a memory controller. The memory controller exchanges data with the memory devices via a plurality of channels. The memory controller decodes an external command to generate a driving power mode and accesses the memory devices according to the driving power mode. | 10-28-2010 |
| 20100274954 | PROGRAM UPDATE SYSTEM AND ELECTRONIC DEVICE WITH PROGRAM UPDATE FUNCTION - A manufacturing cost of an integrated circuit chip used in a program update system or in an electronic device with program update function is reduced. A first integrated circuit chip has a USB interface circuit, a compression decoder, a CPU and a mask ROM. The first integrated circuit chip is a single chip consolidating a microcomputer with a USB host function and the compression decoder. A second integrated circuit chip has a CPU and an FROM, and serves as a system microcomputer to control the whole system of a car audio. A control program stored in the mask ROM is updated using the FROM incorporated in the second integrated circuit chip. | 10-28-2010 |
| 20100274955 | Flash Memory Storage System and Method - A flash memory storage system includes a memory array containing a plurality of memory cells and a controller for controlling the flash memory array. The controller dedicates a first group of memory cells to operate with a first number of bits per cell and a second, separate group of memory cells to operate with a second number of bits per cell. A mechanism is provided to apply wear leveling techniques separately to the two groups of cells to evenly wear out the memory cells. | 10-28-2010 |
| 20100274956 | SYSTEMS AND APPARATUS FOR MAIN MEMORY - A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules. | 10-28-2010 |
| 20100274957 | SYSTEM AND APPARATUS WITH A MEMORY CONTROLLER CONFIGURED TO CONTROL ACCESS TO RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY - An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits. | 10-28-2010 |
| 20100274958 | METHODS OF ASSEMBLY OF A COMPUTER SYSTEM WITH RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY - An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits. | 10-28-2010 |
| 20100281202 | WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES - Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses. | 11-04-2010 |
| 20100281203 | Nonvolatile Memory Device and Method for Operating the Same - A nonvolatile memory device includes a selecting unit configured to select one of a read data or a program signal indicating a program period, an output unit configured to output an output signal of the selecting unit to the outside of a chip, and an output pin connected to the output unit. | 11-04-2010 |
| 20100281204 | MEMORY SYSTEM - A memory system includes a WC | 11-04-2010 |
| 20100281205 | Micro Control Module For Universal Connection And Universal Connection Method Thereof - A micro control module for universal connection and a universal connection method thereof are provided. The micro control module includes a supporting interface module, a micro control unit, and a memory unit. The micro control unit is configured to read interface-setting data saved in the supporting interface module and save the interface-setting data into the memory unit. When a wireless transmission module is electrically connected to the micro control module, the micro control unit generates an identification result, selects the appropriate interface-setting data from the memory unit, and reads the corresponding initialization data from the supporting interface module, so as to initialize the wireless transmission module. | 11-04-2010 |
| 20100281206 | METHOD OF CUSTOMIZING A MEMORY LIFESPAN MANAGEMENT POLICY IN AN ELECTRONIC TOKEN - The invention is a method of customizing a memory lifespan management policy of an electronic token. The electronic token is intended to be connected to a device able to establish a wireless channel. The electronic token has a microprocessor, a communication interface, a first memory intended to comprise said memory lifespan management policy, first means for exchanging data with a distant machine by means of a wireless channel established by said connected device, second means for applying said memory lifespan management policy in said electronic token, and third means for updating said memory lifespan management policy. Said method comprises the steps of—sending data from the distant machine to the electronic token by means of a wireless channel,—updating said memory lifespan management policy as a function of data received from said distant machine. | 11-04-2010 |
| 20100281207 | FLASH-BASED DATA ARCHIVE STORAGE SYSTEM - A flash-based data archive storage system having a large capacity storage array constructed from a plurality of dense flash devices is provided. The flash devices are illustratively multi-level cell (MLC) flash devices that are tightly packaged to provide a low-power, high-performance data archive system having substantially more capacity per cubic inch than more dense tape or disk drives. The flash-based data archive system may be adapted to employ conventional data de-duplication and compression methods to compactly store data. Furthermore, the flash-based archive system has a smaller footprint and consumes less power than the tape and/or disk archive system. | 11-04-2010 |
| 20100281208 | System and Method for Data Storage - A data storage architecture is composed of an array of a flash memory solid state disk and a hard disk drive or any nonvolatile random access storage that are intelligently coupled by an intelligent processing unit such as a multi-core graphic processing unit. The solid state disk stores seldom-changed and mostly read reference data blocks while the hard disk drive stores compressed deltas between currently accessed I/O blocks and their corresponding reference blocks in the solid state disk so that random writes are not performed on the solid state disk during online I/O operations. The solid state disk and hard disk drive are controlled by the intelligent processing unit, which carries out high speed computations including similarity detection and delta compression/decompression. The architecture exploits the fast read performance of solid state disks and the high speed computation of graphic processing units to replace mechanical operations on hard disk drives while avoiding slow and wearing solid state drive writes. | 11-04-2010 |
| 20100281209 | Press-Push Flash Drive Apparatus With Metal Tubular Casing And Snap-Coupled Plastic Sleeve - A press-push type computer peripheral “flash drive” device includes an elongated (e.g., metal) tubular casing containing a PCBA having a plug connector. A plastic housing assembly includes front and rear cap portions mounted over the open ends of the tubular casing, and a fixed plastic sleeve portion disposed in the tubular casing. The PCBA is secured to a plastic sliding rack structure that is disposed in the tubular casing and includes an actuating button protruding through a slot formed in a wall of the tubular casing. When the actuating button is manually pushed and slid along the slot, a portion of the sliding rack structure slides against the plastic sleeve portion in deploying and retracting the USB connector out of the device. | 11-04-2010 |
| 20100287328 | WEAR LEVELING TECHNIQUE FOR STORAGE DEVICES - A method for managing wear levels in a storage device having a plurality of data blocks, the method comprising moving data to data blocks having higher erasure counts based on a constraint on static wear levelness that tightens over at least a portion of the lives of the plurality of data blocks. | 11-11-2010 |
| 20100287329 | Partial Page Operations for Non-Volatile Memory Systems - A read command initiates reads of pages or portions of pages of non-volatile memory using a memory address that specifies a row, column and length. A host controller can use the read command with a read operation or status request. In some implementations, the memory address further specifies a die or plane and a block. | 11-11-2010 |
| 20100287330 | METHOD FOR WRITING DATA INTO FLASH MEMORY - Method for writing data into flash memory is disclosed. The method includes storing the frequently updated data and the not-aligned data collectively into some of the physical memory blocks of the flash memory. In other words, the method collectively writes those data into the same physical memory blocks of the flash memory as far as possible. By doing this, the invalid physical memory pages in the physical memory blocks can be generated collectively. As a result, the storage releasing efficiency of garbage collection can be greatly improved. | 11-11-2010 |
| 20100287331 | ELECTRONIC DEVICE AND METHOD FOR RECORDING POWER-ON TIME THEREOF - An electronic device and a method for recording power-on time include a flash memory to store a plurality of bits used to record power-on time. The electronic device sets the plurality of bits stored in the flash memory to a first value, sets a changing interval, and copies the plurality of bits from the flash memory to a random access memory (RAM). The electronic device further searches for a first bit of the first value from the plurality of bits in the RAM, and records an index of the first bit of the first value in a variable. The electronic device further changes the bit corresponding to the variable to a second value and increases the variable by 1 when the changing interval arrives. The electronic device further writes the bit changed to the second value from the RAM to the flash memory. | 11-11-2010 |
| 20100287332 | DATA STORING SYSTEM, DATA STORING METHOD, EXECUTING DEVICE, CONTROL METHOD THEREOF, CONTROL DEVICE, AND CONTROL METHOD THEREOF - A data storing system including: a non-volatile memory configured to have a plurality of memory blocks each capable of independently operating and allow random access to each of addresses; a controller configured to control writing of data to the non-volatile memory; and an executing unit configured to execute a predetermined application, wherein the executing unit decides the number of interleaves indicating the number of memory blocks operated in parallel among the plurality of memory blocks, and the executing unit notifies the controller of the decided number of interleaves. | 11-11-2010 |
| 20100287333 | DATA STORAGE DEVICE AND RELATED METHOD OF OPERATION - A data storage device comprises a plurality of memory devices, a buffer memory, and a controller. The plurality of memory devices are connected to a plurality of channels and a plurality of ways. The buffer memory temporarily stores data to be written in the memory devices. The controller stores the data in the buffer memory based on channel and way information of the memory devices. | 11-11-2010 |
| 20100287334 | ADDRESSING SCHEME TO ALLOW FLEXIBLE MAPPING OF FUNCTIONS IN A PROGRAMMABLE LOGIC ARRAY - A programmable processing device comprises a plurality of universal digital blocks (UDBs) in a UDB linear array. Each register in each UDB is associated with a plurality of memory addresses, where each memory address is from each of the different memory address spaces associated with different access mode widths of different digital peripheral functions. A digital peripheral function of an access mode width is mapped to one or more contiguous UDBs starting with a first UDB in the UDB linear array. Based on the access mode width, one of the associated memory addresses is chosen for the first UDB. | 11-11-2010 |
| 20100287335 | Read Enable Signal Adjusting Flash Memory Device and Read Control Method of Flash Memory Device - Disclosed is a flash memory device for adjusting a read signal timing and read control method of the flash memory device. The flash memory device includes a plurality of flash memory units, a common input/output bus connected with each of the plurality of flash memory units, and a controller to propagate the read control signal to a flash memory unit selected from among the plurality of flash memories and to receive data read from the selected flash memory unit via the common input/output bus, the controller being connected with the common input/output bus, wherein the controller adjusts a propagation timing of the read control signal unit based on a propagation delay corresponding to the selected flash memory unit, and thereby controlling a timing optimized for each flash memory unit. | 11-11-2010 |
| 20100293317 | PCM MEMORIES FOR STORAGE BUS INTERFACES - A memory controller for a phase change memory (PCM) that can be used on a storage bus interface is described. In one example, the memory controller includes an external bus interface coupled to an external bus to communicate read and write instructions with an external device, a memory array interface coupled to a memory array to perform reads and writes on a memory array, and an overwrite module to write a desired value to a desired address of the memory array. | 11-18-2010 |
| 20100293318 | METHOD FOR MEMORY MANAGEMENT - The invention relates to a method for memory management, in which memory usage data relating to the use of the memory is recorded. The memory usage data is determined in response to a number of memory write and/or read accesses. | 11-18-2010 |
| 20100293319 | Solid state drive device - The solid state drive device includes a memory device including a plurality of flash memories and a memory controller connected with a host and configured to control the memory device. The memory controller includes first and second cores, a host interface configured to interface with the host, and a flash memory controller configured to control the plurality of flash memories. The first core is configured to control transmission and reception of data to and from the host. The second core is configured to control transmission and reception of data to and from the memory device. | 11-18-2010 |
| 20100293320 | METHOD AND APPARATUS FOR BYTE-ACCESS IN BLOCK-BASED FLASH MEMORY - Techniques are described herein for managing data in a block-based flash memory device which avoid the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. In addition, the block-based flash memory can emulate both programming and erasing on a byte-by-byte basis, like that provided by an EEPROM. | 11-18-2010 |
| 20100293321 | SYSTEMS AND METHOD FOR FLASH MEMORY MANAGEMENT - A system and method for merging sectors of a flash memory module, the method includes: receiving multiple sectors, each received sector is associated with a current erase block out of multiple (L) erase blocks; accumulating the received sectors in a sector buffer, the sector buffer is stored in a non-volatile memory module; maintaining a merged sector map indicative of a sectors of the sector buffer that have been merged and sectors of the sector buffer waiting to be merged; finding a first sector waiting to be merged according to the merged sector map; merging the first sector and other sectors that belong to a same erase block as the first sector; and updating the merged sector map to indicate that that the first second and the other sectors that belonged to the same erase block were merged. | 11-18-2010 |
| 20100293322 | SEMICONDUCTOR RECORDING APPARATUS AND SEMICONDUCTOR RECORDING SYSTEM - A semiconductor recording apparatus includes a logical-to-physical conversion table | 11-18-2010 |
| 20100293323 | Semiconductor and Flash Memory Systems - A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied. | 11-18-2010 |
| 20100293324 | DIRECT LOGICAL BLOCK ADDRESSING FLASH MEMORY MASS STORAGE ARCHITECTURE - A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address. | 11-18-2010 |
| 20100299474 | INFORMATION PROCESSING APPARATUS, MEDIA DRIVE AND MEDIA DATA CACHING MANAGEMENT METHOD IN INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes a first caching processing module which starts a caching moving image data stored in a storage medium in a memory device when the storage medium is loaded in a media drive, and a second caching processing module which erases all of moving image data items cached in the memory device when the storage medium is ejected from the media drive. | 11-25-2010 |
| 20100299475 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITE-IN METHOD THEREOF - A non-volatile semiconductor memory device, comprising: a non-volatile memory array, storing multi-values by setting a plurality of different threshold voltages for each memory cell, and a control circuit, controlling a write-in operation to the memory cell array. When data have been written into the memory cell, the control circuit selects an adjacent word line, uses an erasing level to perform write-in which is weaker than the data write-in, and verifies soft programming of the amount of one page, such that a narrow-banded erasing level distribution is realized in an adjacent memory cell. | 11-25-2010 |
| 20100299476 | MASS MEMORY DEVICE AND STORAGE SYSTEM - A mass memory device is disclosed as including a memory module, a management module for physical management of the memory module, and a control module for controlling the management module. The management module is connected for communication with the control module by an MII-family bus. | 11-25-2010 |
| 20100306447 | DATA UPDATING AND RECOVERING METHODS FOR A NON-VOLATILE MEMORY ARRAY - Methods for updating and recovering user data of a non-volatile memory array such as a flash memory are disclosed. An indication for indicating a mapping relationship for a logical address is established when original user data of the logical addresses is updated into new user data. The indication records new pointers, which record the mapping relationships between logical addresses and physical addresses storing the new user data of the logical addresses. Alternatively, the indication records memory positions of the non-volatile memory array which are defined as designated memory positions and a sequence for using these designated memory positions. | 12-02-2010 |
| 20100306448 | CACHE AUTO-FLUSH IN A SOLID STATE MEMORY DEVICE - A device, system and method in which data in a write cache, that must at some point be written to non-volatile memory, is written to non-volatile memory after expiration of a threshold time period during which no new host commands are received. If either the last dirty entry is written back or a host command is received during the write-back process, the time threshold time period and auto-flush process is restarted. | 12-02-2010 |
| 20100306449 | Transportable Cache Module for a Host-Based Raid Controller - In accordance with the present disclosure, a system and method for an information handling system having transportable cache module is disclosed herein. The information handling system has a memory controller coupled to a central processing unit and a plurality of memory modules. The transportable cache module has a protected memory module, a nonvolatile memory module, a module controller, and an independent power source. The module controller is operative to copy a protected memory region from the protected memory module to a nonvolatile memory region on the nonvolatile memory module. The independent power source is operative to supply power to the protected memory module, the nonvolatile memory module, and the module controller. | 12-02-2010 |
| 20100306450 | SECURE DELIVERY OF DIGITAL MEDIA VIA FLASH DEVICE - A flash device for secure delivery of media content is provided. The flash device can include a controller module and a memory module. The controller module can include at least one local central processing unit, at least one register having factory initialized data written therein, and at least one memory module interface. The factory initialized data can include: a vendor identification (“VID”) string, a product identification (“PID”) string, and a manufacturer identification string. The memory module can include at least one read-only partition having digital data disposed therein, where at least a portion of the digital data comprises at least one machine executable instruction set. | 12-02-2010 |
| 20100306451 | ARCHITECTURE FOR NAND FLASH CONSTRAINT ENFORCEMENT - Described embodiments provide for constraint checking for constraints imposed on NAND flash devices. An exemplary implementation of a computing environment comprises at least one NAND data storage device. In the illustrative implementation, the data processing and storage management paradigm allows for the storage of data according using a selected constraint enforcement algorithm. A NAND data storage constraint checking module can be operable to enforce one or more selected device constraints with one or more co-operating components to the NAND data store. | 12-02-2010 |
| 20100306452 | MULTI-MAPPED FLASH RAID - Disclosed is a storage system. The storage system includes a redundant array of inexpensive disks (RAID) controller. The RAID controller includes a flash memory controller coupled to a flash memory. The flash memory controller may perform background management tasks. These include logging and error reporting, address translation, cache table management, bad block management, defect management, wear leveling, and garbage collection. The array controller also allows the flash memory to be divided into multiple mappings. | 12-02-2010 |
| 20100306453 | METHOD FOR OPERATING A PORTION OF AN EXECUTABLE PROGRAM IN AN EXECUTABLE NON-VOLATILE MEMORY - A method for operating at least a portion of an executable program in an executable non-volatile memory is described. The method includes determining, by a user input, at least a portion of an executable program for pinning in the executable non-volatile memory. The portion of the executable program is pinned to the executable non-volatile memory. The portion of the executable program is then executed from the executable non-volatile memory. | 12-02-2010 |
| 20100306454 | ELECTRONIC DEVICES AND OPERATION METHODS OF A FILE SYSTEM - An operation method of file system includes retrieving the first header of the first file, adding the auxiliary data to the first header to generate the second header, writing the dummy data into the second header to adjust the data length of the second header, thereby serving as the third header, and modifying the link relation of clusters recorded in the file allocation table such that the third header and the second data segment are linked together, thereby generating the second file. | 12-02-2010 |
| 20100306455 | METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a plurality of blocks of a Flash memory includes: sieving out at least one first block having invalid pages from the plurality of blocks; and moving data of a portion of valid pages of the first block to a second block, where data of all valid pages of the first block is not moved to the second block at a time. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks. The controller that executes the program code by utilizing the microprocessor sieves out the first block from the plurality of blocks, and moves the data of the portion of valid pages of the first block to the second block. | 12-02-2010 |
| 20100306456 | METHOD FOR EVEN UTILIZATION OF A PLURALITY OF FLASH MEMORY CHIPS - A method for addressing a memory having a plurality of flash memory chips organized in erasable blocks, which in turn contain writable sectors, and where an erase counter is associated with each memory block. The overwriting of the sectors occurs by way of alternative memory blocks searched in the same chip for low erase counter values, as long as a threshold value of the erase counter is not exceeded. The copying operations are conducted efficiently using a copy command internal to the memory chip. As soon as the threshold value is exceeded, alternative memory blocks are searched in other memory chips as well. | 12-02-2010 |
| 20100312947 | Apparatus and method to share host system ram with mass storage memory ram - A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM. | 12-09-2010 |
| 20100312948 | MEMORY SYSTEM - A memory system includes a DRAM | 12-09-2010 |
| 20100312951 | METHOD, DEVICE AND DATA STRUCTURE FOR DATA STORAGE ON MEMORY DEVICES - A method is provided for storing data on memory devices comprising a plurality of erasable units, wherein the size of said erasable units is an integer multiple of a first integer value, comprising providing a data structure comprising a plurality of data units each including a data unit header, wherein the size of said data units is equal to said first integer value, a plurality of data items and corresponding data item headers within each data unit, associating at least one data unit to each erasable unit, storing said data in said data items and storing data item status information in the corresponding data item headers, and storing data unit status information in said data unit headers. | 12-09-2010 |
| 20100312952 | Multiprocessor System Having an Input/Output (I/O) Bridge Circuit for Transferring Data Between Volatile and Non-Volatile Memory - A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request. | 12-09-2010 |
| 20100312953 | METHOD AND APPARATUS FOR REDUCING WRITE CYCLES IN NAND-BASED FLASH MEMORY DEVICES - A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode but instead used to shuffle data within the at least one block using a dynamic page address scheme, whereby data are dynamically moved from one page to an empty page in the same block using dynamic page mapping. | 12-09-2010 |
| 20100312954 | Multi-Chip Semiconductor Devices Having Non-Volatile Memory Devices Therein - A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied. | 12-09-2010 |
| 20100318718 | MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE - A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device. | 12-16-2010 |
| 20100318719 | METHODS, MEMORY CONTROLLERS AND DEVICES FOR WEAR LEVELING A MEMORY - The present disclosure includes methods, memory controllers and devices for wear leveling a memory. One method embodiment includes selecting, in at least a substantially random manner, a number of memory locations as at least a portion of a sample subset, the sample subset including fewer than all memory locations of the memory. A memory location having a particular wear level characteristic is identified from among the sample subset of memory locations, and data is written to the memory location identified from among the sample subset. | 12-16-2010 |
| 20100318720 | Multi-Bank Non-Volatile Memory System with Satellite File System - A multi-bank non-volatile memory system is presented. A first of the banks has a main copy of the file system and each of the other banks has a satellite copy of the file system. The back end firmware of the controller executes a thread for each of the banks. After the boot process, during normal memory operations, each of the threads can operate using its own copy of the file system without interrupting the other threads in order to access the file system. | 12-16-2010 |
| 20100318721 | PROGRAM FAILURE HANDLING IN NONVOLATILE MEMORY - In a nonvolatile memory system, data received from a host by a memory controller is transferred to an on-chip cache, and new data from the host displaces the previous data before it is written to the nonvolatile memory array. A safe copy is maintained in on-chip cache so that if a program failure occurs, the data can be recovered and written to an alternative location in the nonvolatile memory array. | 12-16-2010 |
| 20100318722 | DATA INTERLEAVING METHOD FOR STORAGE DEVICE AND RELATED STORAGE DEVICE - The present invention provides a data interleaving method for a storage device and a related storage device. The storage device comprises a plurality of non-volatile memory units, a buffer, and a processing unit. The method comprises: transmitting a plurality of first data required to be written to the plurality of non-volatile memory units to the buffer one by one; and respectively performing a plurality of interleaving operations to transmit the plurality of first data received by the buffer in sequence to the plurality of non-volatile memory units, respectively. The data interleaving method and the related storage device of the present invention only has to use one buffer, and thus the data interleaving method and the related storage device of the present invention can reduce requirement of buffer memory. | 12-16-2010 |
| 20100318723 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND NONVOLATILE MEMORY SYSTEM - A nonvolatile memory device includes a plurality of memory controllers. Each of the memory controllers has an aggregation processing part and an aggregation synchronization part. Based on a signal from the aggregation synchronization part, the aggregation processing part aggregates valid data of a temporary physical block into another physical block. When one of the memory controllers requires an aggregation process, the aggregation synchronization part sends a synchronization signal to the other memory controller, so that the aggregation process is simultaneously carried out by the other memory controller. Thus, in the nonvolatile memory device having a plurality of memory controllers, it is possible to reduce the time required for the aggregation process and carry out a high-speed writing process. | 12-16-2010 |
| 20100318724 | FLASH MEMORY CONTROL CIRCUIT, FLASH MEMORY STORAGE SYSTEM, AND DATA TRANSFER METHOD - A flash memory control circuit including a microprocessor unit, a first interface unit, a second interface unit, a buffer memory, a memory management unit, and a data read/write unit is provided. The memory management unit manages a plurality of flash memory units, wherein each of the flash memory units has a plurality of flash memories, each of the flash memories has a plurality of memory cell arrays, and each of the memory cell arrays at least has an upper page and a lower page. The memory management unit groups the memory cell arrays of the corresponding flash memories into a plurality of data transfer unit sets (DTUSs). The data read/write unit interleavingly transfers data to the flash memory units in units of the DTUSs. Thereby, the flash memory control circuit can transfer the data stably and the usage of the buffer memory can be reduced. | 12-16-2010 |
| 20100318725 | Multi-Processor System Having Function of Preventing Data Loss During Power-Off in Memory Link Architecture - Exemplary embodiments relate to a multi-processor system including: a first processor for writing a power-off check command to a first mail box, reading a power-off wait message or a power-off allowance message written to a second mail box, and waiting or turning off the multi-processor system, in a power-off operation mode; a second processor for indicating whether data is completely stored during a current processing operation in response to the power-off check command in the first mail box and writing the power-off wait message or the power-off allowance message to the second mail box according to the indication result; and a multi-port semiconductor memory device having an internal register that includes the first and second mail boxes and dedicated and shared memory areas for data processing. The first and second mail boxes serve as latch storage units, and the dedicated and shared memory areas are accessed by the first and second processors. | 12-16-2010 |
| 20100318726 | MEMORY SYSTEM AND MEMORY SYSTEM MANAGING METHOD - Correspondences between logical blocks and physical blocks of first and second memories are controlled such that an identical logical block is subject to correspondence with a physical block of the first memory and to a physical block of the second memory, and data is stored in the physical blocks subject to correspondence with the identical logical block such that pages that contain data do not overlap between the physical blocks so that operation performed on the first memory and operation performed on the second memory can be performed in parallel, thereby achieving speedup and an increase in efficiency in data writing to non-volatile memory, to which overwriting is inapplicable and to which writing involves block-to-block data move. | 12-16-2010 |
| 20100318727 | MEMORY SYSTEM AND RELATED METHOD OF LOADING CODE - A memory system comprises a processor, a main memory comprising a volatile random access memory (RAM) that stores data to be accessed by the processor and a nonvolatile memory that provides a swap space for the RAM, and a disk that provides data transfer to the RAM with a greater latency than the nonvolatile memory. | 12-16-2010 |
| 20100318728 | SOLID STATE DRIVE DEVICE - A solid state drive (SSD) device is provided. The SSD device includes: a first memory device storing data; a memory controller, connected to a host, and controlling the memory device; and a security device encoding and storing the data using a key and decoding the stored data using the key, wherein the security device stores the key and is detachable from the memory controller. | 12-16-2010 |
| 20100318729 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A NAND type flash memory having a program verifying function is provided, which can search for stored data at high speed. The flash memory reads search data that corresponds to stored data stored in a block in a front page of the block in a reverse-order search mode, compares the search data with the non-search data from a controller, and returns a block address and a page address of the search data that matches with the non-search data to the controller. At this time, the flash memory checks the match between the search data and the non-search data by comparing “0” data using the program verifying function provided in the flash memory itself. | 12-16-2010 |
| 20100318730 | Dual Channel Memory Architecture Having Reduced Interface Pin Requirements Using a Double Data Rate Scheme for the Address/Control Signals - Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals. | 12-16-2010 |
| 20100325339 | STORAGE SYSTEM AND METHOD FOR CONTROLLING THE SAME - Optimum load distribution processing is selected and executed based on settings made by a user in consideration of load changes caused by load distribution in a plurality of asymmetric cores. | 12-23-2010 |
| 20100325340 | Memory Wear Control - The disclosure is related to systems and methods of controlling wear of a memory. In a particular embodiment, a system is disclosed that comprises a memory and a performance governor circuit coupled to the memory. The performance governor circuit is adapted to control a wear of the memory as a function of time. | 12-23-2010 |
| 20100325341 | Memory Device and Memory Interface - Memory devices and memory interfaces are disclosed. In an implementation a memory controller of a memory device is configured to receive a first part of an address for memory access, and to perform a memory access based on said first part and a part of a previously received address. | 12-23-2010 |
| 20100325342 | MEMORY CONTROLLER AND NONVOLATILE STORAGE DEVICE USING SAME - In a controller (memory controller) ( | 12-23-2010 |
| 20100325343 | MEMORY SYSTEM - This disclosure concerns a memory system including: chips (MC | 12-23-2010 |
| 20100325344 | DATA WRITING METHOD FOR FLASH MEMORY AND CONTROL CIRCUIT AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data into a flash memory chip is provided, wherein the flash memory chip includes a plurality of physical units. The data writing method includes providing a flash memory control circuit and configuring a plurality of logical units, wherein each logical unit is mapped to at least one physical unit. The data writing method also includes configuring a plurality of logical addresses and mapping the logical addresses to the logical units, wherein at least one logical unit is mapped to at least two non-continuous logical addresses. The data writing method further includes writing the data from a host system into the corresponding physical units according to the logical units mapped to the logical addresses through the flash memory control circuit. Thereby, the data to be moved while writing data into the physical units is reduced, and accordingly the data writing speed is effectively increased. | 12-23-2010 |
| 20100325345 | METHOD FOR MANAGING STORAGE SYSTEM USING FLASH MEMORY, AND COMPUTER - To facilitate the management of a storage system that uses a flash memory as a storage area. A controller of the storage system provided with a flash memory chip manages a surplus capacity value of the flash memory chip, and transmits a value based on the surplus capacity value to a management server, on the basis of at least one of a definition of a parity group, a definition of an internal LU, and a definition of a logical unit. The management server displays a state of the storage system by using the received value based on the surplus capacity value. | 12-23-2010 |
| 20100325346 | PARALLEL FLASH MEMORY CONTROLLER, CHIP AND CONTROL METHOD THEREOF - A parallel flash memory controller, a chip, and a control method thereof are disclosed. First, an on-chip control bus sends flash memory control instructions in parallel to instruction parsing units ( | 12-23-2010 |
| 20100325347 | APPARATUS FOR CONTROLLING NAND FLASH MEMORY - Provided is an apparatus for controlling NAND flash memory. The apparatus for controlling NAND flash memory includes: a register unit in which a start address of a macro-command to be executed, selected from macro-commands included in a command script in which at least one macro-command in which a plurality of micro-commands for controlling a unit operation of NAND flash memory are arranged in an array shape, is described, is recorded; a command fetch unit, if a start address of the macro-command to be executed is recorded in the register unit, accessing first memory connected based on the start address of the macro-command to be executed and sequentially reading the plurality of micro-commands from the start address of the macro-command to be executed; a command interpretation unit interpreting the read micro-commands and outputting the result of interpretation including types of the micro-commands and command parameters; and a command execution unit generating interface signals for controlling an operation of NAND flash memory according to each of the micro-commands based on the result of interpretation. Time required for data transmission and NAND flash control can be reduced, and a high performance can be obtained. | 12-23-2010 |
| 20100325348 | DEVICE OF FLASH MODULES ARRAY - This invention provides a device of Flash Modules Array or Flash Array (FA) for short, with a higher capacity, higher speed and lower power consumption. A device of flash array comprises: a one or more physical I/O interfaces, for performing data transmission with the outside or upstream; one or more ports for flash modules consisting of multiple flash memory modules, a flash array controller, set between the physical I/O interface and the flash modules, further including: a block mapping unit, for performing the address mapping between the logical address which is transmitted between the physical I/O interface and the outside and the physical address which is transmitted between the physical I/O interface and the flash array. The invention is applied in the field of flexible solid state storage device. | 12-23-2010 |
| 20100325349 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device, includes a plurality of flash memories and a controller for the flash memories. The flash memory includes a data cache operable to hold data for at least one record page in writing, the flash memory includes a plurality of erasure blocks each having a plurality of record pages, the record page is classified into a first record page and a second record page of which write time is longer than a write time of the first record page, and the controller for the flash memories is configured to: divide the plurality of flash memories into at least two groups; perform write control by interleaving data in the groups for each record page; determine whether a page to be written data is of the first record page or the second record page; and when it is determined that the page to be written data is the first record page, after a lapse of a first predetermined time from start of writing data of one of the groups, the controller starts writing data of another one of the groups, and when it is determined that the page to be written data is the second record page, after a lapse of a second predetermined time being longer than the first predetermined time from start of writing data of one of the groups, the controller starts writing data of another one of the groups. | 12-23-2010 |
| 20100325350 | SEMICONDUCTOR DEVICE - In executing an EEPROM emulation by a flash memory incorporated in a semiconductor device, there is a problem that the data holding period of the flash memory is shorter than the EEPROM. The flash memory manages data by block unit. Therefore, it is required to securely perform a block change before the specification of the data holding period of the flash memory passes. For satisfying this problem, for an EEPROM substitution area in a flash memory, a data level check voltage is set between an internal verification voltage and a read-out voltage. When data level becomes below the data level check voltage, the block change is performed. | 12-23-2010 |
| 20100325351 | MEMORY SYSTEM HAVING PERSISTENT GARBAGE COLLECTION - Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations. | 12-23-2010 |
| 20100325352 | HIERARCHICALLY STRUCTURED MASS STORAGE DEVICE AND METHOD - A hierarchically-structured computer mass storage system and method. The mass storage system includes a mass storage memory drive, control logic on the mass storage memory drive that includes a controller and one or more devices for executing a hierarchical storage management technique, a volatile memory cache configured to be accessed by the control logic, and first and second non-volatile storage arrays on the mass storage memory drive and comprising, respectively, first and second non-volatile memory devices. The first and second non-volatile memory devices have properties including access times and write endurance, and at least one of the access time and the write endurance of the first non-volatile memory devices is faster or higher, respectively, than the second non-volatile memory devices. Desired data storage localities on the storage arrays are determined through access patterns and selectively utilizing the properties of the memory devices to match the data storage requirements. | 12-23-2010 |
| 20100325353 | FLASH MEMORY SYSTEM CONTROL SCHEME - A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size. | 12-23-2010 |
| 20100325354 | MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION - A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events. | 12-23-2010 |
| 20100332725 | PINNING CONTENT IN NONVOLATILE MEMORY - Systems and methods relating to pinning selected data to sectors in non-volatile memory. A graphical user interface allows a user to specify certain data (e.g., directories or files) to be pinned. A list of pinned sectors can be stored so that a driver or controller that operates on a sector basis and not a file or directory basis can identify data to be pinned. | 12-30-2010 |
| 20100332726 | STRUCTURE AND METHOD FOR MANAGING WRITING OPERATION ON MLC FLASH MEMORY - A method for managing a writing operation for a multi-level cell (MLC) nonvolatile memory by a host is provided. The MLC nonvolatile memory has a plurality of MLC blocks, each MLC cell of each MLC block can store multiple logical data bits. The method includes forming a turbo writing unit from the spare block pool; writing a data sent by the host to the turbo writing unit; and changing the role of the turbo writing unit into a turbo data unit. The turbo writing unit is formed with at least one of the MLC blocks, each MLC cell of the at least one of the MLC blocks stores a portion of the logical data bits the MLC cell is capable of storing. | 12-30-2010 |
| 20100332727 | EXTENDED MAIN MEMORY HIERARCHY HAVING FLASH MEMORY FOR PAGE FAULT HANDLING - A computer system with flash memory in the main memory hierarchy is disclosed. In an embodiment, the computer system includes at least one processor, a memory management unit coupled to the at least one processor, and a random access memory (RAM) coupled to the memory management unit. The computer system may also include a flash memory coupled to the memory management unit, wherein the computer system is configured to store at least a subset of a plurality of pages in the flash memory during operation. Responsive to a page fault, the memory management unit may determine, without invoking an I/O driver, if a requested page associated with the page fault is stored in the flash memory and further configured to, if the page is stored in the flash memory, transfer the page into RAM. | 12-30-2010 |
| 20100332728 | SYSTEM AND METHOD OF SELECTING A FILE PATH OF A REMOVABLE STORAGE DEVICE - Systems and methods of identifying a file path of a removable storage device are disclosed. A method includes, at a host device that is coupled to the removable storage device, selecting a file path that is associated with the removable storage device by accessing a size associated with a root directory accessible to the host device, where the root directory corresponds to the removable storage device. The file path is selected based upon the size associated with the root directory. The selected file path is verified by initiating a memory access operation using the selected file path. | 12-30-2010 |
| 20100332729 | MEMORY OPERATIONS USING LOCATION-BASED PARAMETERS - Systems and methods of performing memory operations using location-based parameters are disclosed. A method includes identifying a first set of parameter values associated with a first physical block of a memory array. The first set of parameter values is identified based on a first physical location of the first physical block. A memory access operation is initiated with respect to the first physical block in accordance with the first set of parameter values. | 12-30-2010 |
| 20100332730 | METHOD AND SYSTEM FOR MANAGING A NAND FLASH MEMORY - A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure to a non-volatile memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory in one embodiment of the invention. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure in one embodiment of the invention. | 12-30-2010 |
| 20100332731 | FLASH MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME AND DATA STORAGE SYSTEM - A flash memory apparatus is provided. In one embodiment, the flash memory apparatus with a plurality of operation states is coupled to a host and includes a controller having an engine and a register array. A state machine logic circuit of the engine is provided for transition of the operation states and the register array provides state transition information. When a command is received from the host, the engine obtains the state transition information from the register array according to a first operation state and determines whether the valid command is one of a plurality of valid commands corresponding to the first operation state. The state machine logic circuit determines transition to the operation states according to the state transition information. The transition of the first operation state to the second operation state is performed in response to the valid command. | 12-30-2010 |
| 20100332732 | MEMORY SYSTEMS AND MAPPING METHODS THEREOF - Memory systems and mapping methods thereof are provided. In one embodiment of a memory system, an interface device is coupled between a flash memory and a host and stores a flash translation layer. The flash translation layer utilizes a data block mapping table and a page mapping table to manage data blocks and log blocks of the flash memory by a page mapping scheme and utilizes a random write page mapping table independent from the block mapping table and the page mapping table to manage the random write blocks by a random write mapping scheme. When a first predetermined condition is satisfied, the flash translation layer converts one of the data blocks (and one of the log block corresponding to the converted data block if any) into random write block(s) and utilizes the random write mapping schemes to manage the random write block(s). When a second predetermined condition is satisfied, the flash translation layer merges and converts random write block(s) into a data block and utilizes the page mapping scheme to manage the converted random write block(s). | 12-30-2010 |
| 20100332733 | MATERIAL SERVER AND METHOD OF STORING MATERIAL - According to one embodiment, a material server that includes a NAND flash memory which stores material that includes one or all of moving image data, audio data, and ANC data. A material ID detector detects a material ID in inputted material when such material is inputted into the material server. A block allocation unit in the material server allocates a block for storing the material each material ID. A plurality of buffers in the material server buffer the material each inputted material ID. A buffering data monitor in the material server monitors buffering data size in the buffers. A memory accessing unit in the material server writes buffered material to the NAND memory when a buffering data monitor detects that the buffering data size amounts to one page size. | 12-30-2010 |
| 20100332734 | FLASH MEMORY DEVICES AND METHODS FOR CONTROLLING A FLASH MEMORY DEVICE - A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array. | 12-30-2010 |
| 20100332735 | FLASH MEMORY DEVICE AND METHOD FOR PROGRAMMING FLASH MEMORY DEVICE - A flash memory device resilient to bit errors and a programming method suitable for the flash memory are provided. The flash memory device stores data in a parallel manner in a superpage which is generated by grouping a plurality of physical pages into a logical page. The flash memory device spreads input data using a predetermined spreading code to generate spread data. The spread data is stored on a superpage-by-superpage basis. | 12-30-2010 |
| 20100332736 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device comprises storing first data of a first memory block in a page buffer unit, and then programming the first data into a redundant memory block coupled to the page buffer unit, storing second data of a second memory block in the page buffer unit, and then programming the second data into the first memory block, storing third data of a third memory block in the page buffer unit, and then programming the third data into the second memory block, storing the second data of the first memory block in the page buffer unit, and then programming the stored second data into the third memory block, and storing the first data stored in the redundant memory block in the page buffer unit, and then programming the stored first data into the first memory block. | 12-30-2010 |
| 20100332737 | FLASH MEMORY PREPROCESSING SYSTEM AND METHOD - A flash memory preprocessing system comprises at least one flash memory device, a memory controller controlling program and read operations of the at least one flash memory device, and a flash preprocessor receiving program data from an external source, generating preprocessed data by converting the received program data, and outputting the preprocessed data to the memory controller. The memory controller controls the at least one flash memory device to perform a program operation on the at least one flash memory device according to the preprocessed data. | 12-30-2010 |
| 20100332738 | STORAGE DEVICE AND DATA PROCESSING METHOD - A storage device for connecting to a host system includes a flash memory and a controller coupled to the flash memory. The flash memory includes a plurality of memory blocks. The controller writes test data to the flash memory, and compares the test data read from the flash memory with the original test data to generate a bit error message corresponding to the flash memory. Then, the controller chooses and labels a quick read block from the plurality of memory blocks according to the bit error message, and finally writes a specific file to the quick read block. | 12-30-2010 |
| 20100332739 | Storage device, storage controlling device, and storage controlling method - A storage device includes a programmable device into which predetermined control data is written, a control data storing unit that stores therein write control data and read control data, the write control data being control data for realizing a function to save data stored in a cache memory into a nonvolatile memory when an abnormal shut-down occurs and the read control data being control data for realizing a function to restore the data saved in the nonvolatile memory into the cache memory when an electric power source is turned on after the abnormal shut-down, a writing unit that, when an electric power source is turned on after occurrence of the abnormal shut-down of the storage device, writes the read control data into the programmable device, and a restoring instructing unit that instructs the programmable device to restore the data saved in the nonvolatile memory into the cache memory. | 12-30-2010 |
| 20100332740 | ZONED INITIALIZATION OF A SOLID STATE DRIVE - Zoned initialization of a solid state drive is provided. A solid state memory device includes a controller for controlling storage and retrieval of data to and from the device. A set of solid state memory components electrically coupled to the controller. The set is electrically divided into a first zone and a second zone, wherein the first zone is at least partially initialized independent from the second zone. An interface is coupled between the controller and the set of solid state memory components to facilitate transfer of data between the set of solid state memory components and the controller. | 12-30-2010 |
| 20100332741 | Interleaving Policies for Flash Memory - Articles and associated methods and systems relate to selecting read interleaving policies independently of selecting write interleaving policies. In various implementations, the selection may be static or dynamic during operation. In implementations that dynamically select read interleaving policies and write interleaving policies, the selection may be based on various operating conditions, such as temperature, power source, battery voltage, and operating mode. Examples of operating modes may include (1) reading or writing to flash memory when connected to an external power source, (2) reading from flash memory when powered by portable power source (e.g., battery), and (3) writing to flash memory when powered by a portable power source. | 12-30-2010 |
| 20100332742 | DEVICE AND METHOD FOR MONITORING AND USING INTERNAL SIGNALS IN A PROGRAMMABLE SYSTEM - The invention relates to a device for monitoring and using internal signals in a programmable system ( | 12-30-2010 |
| 20110004720 | METHOD AND APPARATUS FOR PERFORMING FULL RANGE RANDOM WRITING ON A NON-VOLATILE MEMORY - A method for performing random writing on a NV memory includes: writing page mapping information regarding a portion of a full range of addresses of the NV memory and providing at least one page mapping table corresponding to a predetermined size; and accessing the NV memory according to the page mapping information. An apparatus for performing full range random writing on an NV memory includes: a controller arranged to perform the full range random writing; and a program code, at least a portion of which is embedded within the controller or received from outside the controller. The controller executing the program code writes page mapping information regarding at least a portion of a full range of addresses of the NV memory and provides at least one page mapping table corresponding to a predetermined size. The controller executing the program code accesses the NV memory according to the page mapping information. | 01-06-2011 |
| 20110004721 | LOADING SECURE CODE INTO A MEMORY - A method and system of controlling access to a programmable memory including: allowing code to be written to the programmable memory in a first access mode; preventing execution of the code stored in the programmable memory in the first access mode; verifying the integrity of the code stored in the programmable memory; if the integrity of the code stored in the programmable memory is verified, setting a second access mode, wherein in the second access mode, further code is prevented from being written to the programmable memory, and execution of the code stored in the programmable memory is allowed. | 01-06-2011 |
| 20110004722 | DATA TRANSFER MANAGEMENT - Methods, controllers, and systems for managing data transfer, such as those in solid state drives (SSDs), are described. In some embodiments, the data transfer between a host and a memory is monitored and then assessed to provide an assessment result. A number of storage units of the memory allocated to service another data transfer is adjusted based on the assessment result. Additional methods and systems are also described. | 01-06-2011 |
| 20110004723 | DATA WRITING METHOD FOR FLASH MEMORY AND CONTROL CIRCUIT AND STORAGE SYSTEM USING THE SAME - A data writing method for a flash memory and a control circuit and a storage system using the same are provided. The data writing method includes determining whether the size of data to be stored by a host system is smaller than a predetermined value according to a write command received from the host system, when the size of the data is smaller than the predetermined value, the data is written into a corresponding buffer physical block or a corresponding spare buffer physical block. The data writing method further includes combining valid data belonging to the same logical block during the executions of several write commands. Accordingly, the response time during the execution of each write command is shortened, and the problem of timeout is avoided. | 01-06-2011 |
| 20110004724 | METHOD AND SYSTEM FOR MANIPULATING DATA - A method of manipulating data includes receiving a data manipulation command for corresponding data, which corresponds to a first logical block address, to a second logical block address. The method further includes mapping the second logical block address to a physical block address, which is mapped to the first logical block address, in response to the data manipulation command. A system for manipulating data includes a host and a flash translation layer. The host transmits a data manipulation command for corresponding data, which corresponds to a first logical block address, to a second logical block address. The flash translation layer maps the second logical block address to a physical block address, which is mapped to the first logical block address, in response to the data manipulation command. | 01-06-2011 |
| 20110004725 | DATA STORAGE DEVICE AND METHOD - According to one embodiment, a data storage device, includes: a recording medium, statuses of storage areas of the recording medium being managed by groups; a managing table storage module storing a managing table in which bit information pieces are associated to indexes representing the groups, the bit information pieces indicating the statuses of the storage areas initially set to an erased status; a transfer controller storing, upon receiving a write command, data in the storage areas; and a controller updates the bit information pieces of one of the groups to which the storage areas belongs to a stored status. Upon receiving an erase command, the transfer controller overwrites the storage areas by predetermined data. The main controller is configured to update the bit information pieces to the erased status. | 01-06-2011 |
| 20110004726 | PIECEWISE ERASURE OF FLASH MEMORY - Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-erase commands within the memory device may be insufficient to erase the information stored in the storage cell. Moreover, the first circuit includes an interface that receives the multiple piecewise-erase commands from the control logic and that transmits the multiple piecewise-erase commands to the memory device. | 01-06-2011 |
| 20110010484 | OPTIMIZED PAGE PROGRAMMING ORDER FOR NON-VOLATILE MEMORY - During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages. | 01-13-2011 |
| 20110010485 | Flash Memory Control Device - A flash memory control device includes a controller and an expansion device. The expansion device is electrically connected to the controller and one and more flash memory devices for temporarily storing data, integrating data and presenting processing status, wherein the controller orders the expansion device to transform data to the one and more flash memory devices or receive data from the one and more flash memory devices according to processing status. | 01-13-2011 |
| 20110010486 | REALTIME LINE OF RESPONSE POSITION CONFIDENCE MEASUREMENT - A PET event position calculation method using a combination angular and radial event map wherein identification of the radial distance of the event from the centroid of the scintillation crystal with which the event is associated as well as angular information is performed. The radial distance can be converted to a statistical confidence interval, which information can be used in downstream processing. More sophisticated reconstruction algorithms can use the confidence interval information selectively, to generate higher fidelity images with higher confidence information, and to improve statistics in dynamic imaging with lower confidence information. | 01-13-2011 |
| 20110010487 | Health Reporting From Non-Volatile Block Storage Device to Processing Device - Methods and devices are provided for adapting an I/O pattern, with respect to a processing device using a non-volatile block storage device based on feedback from the non-volatile block storage device. The feedback may include information indicating a status of the non-volatile block storage device. In response to receiving the feedback, a storage subsystem, included in an operating system executing on processing device, may change a behavior with respect to the non-volatile block storage device in order to avoid, or reduce, a negative impact to the non-volatile block storage device or to enhance an aspect of the non-volatile block storage device. The feedback may include performance information and/or operating environmental information of the non-volatile block storage device. When the non-volatile block storage device is not capable of providing the feedback, the processing device may request information about the non-volatile block storage device from a database service. | 01-13-2011 |
| 20110010488 | SOLID STATE DRIVE DATA STORAGE SYSTEM AND METHOD - The present disclosure relates to a data storage system and method that includes at least two solid state devices that can be classified in at least two different efficiency levels, wherein data progression is used to allocate data to the most cost-appropriate device according to the nature of the data. | 01-13-2011 |
| 20110010489 | LOGICAL BLOCK MANAGEMENT METHOD FOR A FLASH MEMORY AND CONTROL CIRCUIT STORAGE SYSTEM USING THE SAME - A logical block management method for managing a plurality of logical blocks of a flash memory device is provided. The logical block management method includes providing a flash memory controller, grouping the logical blocks into a plurality of logical zones, wherein each logical block maps to one of the logical zones. The logical block management method also includes counting a use count value for each logical block, and dynamically adjusting mapping relations between the logical blocks and the logical zones according to the use count values. Accordingly, the logical block management method can effectively utilizing the logical zones to determine usage patterns of the logical blocks and use different mechanisms to write data, so as to increase the performance of the flash memory storage device. | 01-13-2011 |
| 20110010490 | SOLID STATE DRIVE AND RELATED METHOD OF OPERATION - A solid state drive (SSD) comprises an input/output interface and a memory controller. The input/output interface stores a plurality of input/output commands. The memory controller comprises first and second input/output contexts and an input/output scheduler. The first and second input/output contexts process input/output commands from the input/output interface in an alternating sequence. The input/output scheduler schedules operations of the first and second input/output contexts. In particular, the input/output scheduler suspends execution of a first input/output command by the first input/output context upon determining that an execution time of the first input/output command exceeds an interval before a deadline time. After suspending execution of the first input/output command, the input/output scheduler transmits a second input/output command to the second input/output context. | 01-13-2011 |
| 20110010491 | DATA STORAGE DEVICE - A data storage device comprising: at least two flash devices for storing data; a circuit board, wherein each of the flash devices are integrated on the circuit board; a controller integrated on the circuit board for reading and writing to each flash devices, wherein the controller interfaces each flash devices; at least one NOR Flash device in communication with the controller through a host bus; at least one host bus memory device in communication with the controller and at least one NOR Flash device through the host bus; at least one interface in communication with the controller and adapted to physically and electrically couple to a system, receive and store data therefrom and retrieve and transmit data to the system. | 01-13-2011 |
| 20110010492 | Data Protection for Non-Volatile Semiconductor Memory Using Block Protection Flags - Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch. | 01-13-2011 |
| 20110010493 | NONVOLATILE STORAGE GATE, OPERATION METHOD FOR THE SAME, AND NONVOLATILE STORAGE GATE EMBEDDED LOGIC CIRCUIT, AND OPERATION METHOD FOR THE SAME - Provided is a nonvolatile storage gate embedded logic circuit embedding a nonvolatile storage gate which can hold data after power supply cutoff and can cut off a power supply at the same time shifting into a standby state. The nonvolatile storage gate embedded logic circuit includes a logic calculation unit having a logic gate, and a nonvolatile storage gate having a nonvolatile storage element, a data interface control unit disposed so as to be adjoining to the nonvolatile storage element, and receiving a nonvolatile storage control signal for data read-out from the nonvolatile storage element and data write-in to the nonvolatile storage element, and a volatile storage element disposed so as to be adjoining to the nonvolatile storage element, receiving a data input signal and a clock signal, and outputting a data output signal. | 01-13-2011 |
| 20110016260 | MANAGING BACKUP DEVICE METADATA IN A HIGH AVAILABILITY DISK SUBSYSTEM - A system includes a data storage device, a controller coupled with the data storage device, a backup device coupled with the controller for backing up a modified portion of data and volatile memory metadata stored by the controller, and a backup power source for powering the controller. The controller includes a pre-specified region of volatile memory for storing backup device metadata for managing a modified portion of data, the metadata comprising one or more intents corresponding to modified data written back to the data storage device. The controller is configured to invalidate the one or more intents. During a restore operation, the controller is configured to store the backup device metadata in the pre-specified region of volatile memory when a charge on the backup power source is at least a minimum threshold charge and to store the updated backup device metadata in the backup device during an interruption of power. | 01-20-2011 |
| 20110016261 | PARALLEL PROCESSING ARCHITECTURE OF FLASH MEMORY AND METHOD THEREOF - A parallel processing architecture of flash memory and method thereof are described. A processing unit classifies a plurality of commands to generate a first command group and a second command group respectively. The processing unit executes the first command group and the second command group. A first control unit performs the first command group to access the data stored in the first memory unit, and a second control unit simultaneously performs the second command group to access the data stored in the second memory unit for processing the data stored in the first and the second memory units in parallel. | 01-20-2011 |
| 20110016262 | STORAGE AND METHOD FOR PERFORMING DATA BACKUP USING THE STORAGE - A method for performing data backup using a storage device starts a backup battery when an electronic device is powered off, reads data from a memory of the electronic device by a system on chip (SoC) of the storage device, and writes the data into a field programmable gate array (FPGA) of the storage device. The method further encodes the data by the FPGA, and stores the encoded data into a flash memory of the storage device. | 01-20-2011 |
| 20110016263 | METHOD FOR PERFORMING DATA PATTERN MANAGEMENT REGARDING DATA ACCESSED BY A CONTROLLER OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing data pattern management regarding data accessed by a controller of a Flash memory includes: when the controller receives a write command, generating a first random function, where the write command is utilized for instructing the controller to write the data into the Flash memory; and adjusting a plurality of bits of the data bit by bit to generate a pseudo-random bit sequence, and writing the pseudo-random bit sequence into the Flash memory to represent the data, whereby data pattern distribution of the data is adjusted. An associated memory device and the controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control the access to the Flash memory and manage a plurality of blocks; and a randomizer arranged to generate a random function. The controller can perform data pattern management. | 01-20-2011 |
| 20110016264 | METHOD AND APPARATUS FOR CACHE CONTROL IN A DATA STORAGE DEVICE - According to one embodiment, a data storage device is provided, which has a cache controller that performs cache control, by using a buffer memory divided into segments, which are managed. The cache controller performs sequential hit judge on each segment, in accordance with the requested access range designated by a read or write command coming from a host system. The cache controller updates the hit upper-limit LBA set for each segment if the result of the hit judge is a mishit. | 01-20-2011 |
| 20110016265 | STORAGE DEVICE AND DATA PROCESS METHOD - A storage device includes a flash memory, a temporary storage unit, and a control unit. The flash memory includes a number of memory blocks, each of which has a number of pages. The temporary storage unit receives and stores a number of written commands transferred from a host system. Each written command is corresponding to user information. The control unit is coupled with the temporary storage unit and the flash memory, and adjusts executing sequence of the written commands according to a volume of the user information and unused pages in the memory block. | 01-20-2011 |
| 20110016266 | SEMICONDUCTOR DEVICE - On a single semiconductor package PK | 01-20-2011 |
| 20110016267 | Low-Power USB Flash Card Reader Using Bulk-Pipe Streaming with UAS Command Re-Ordering and Channel Separation - A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams. | 01-20-2011 |
| 20110022776 | DATA RELIABILITY IN STORAGE ARCHITECTURES - Among other subject matter, storage architectures are provided that store data reliably in connection with a system. The storage architecture ( | 01-27-2011 |
| 20110022777 | SYSTEM AND METHOD FOR DIRECT MEMORY ACCESS IN A FLASH STORAGE - A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol. | 01-27-2011 |
| 20110022778 | Garbage Collection for Solid State Disks - Described embodiments provide a method of recovering storage space on a solid state disk (SSD). An index and valid page count are determined for each block of a segment of an SSD. If the valid page count of at least one block in the segment is zero, a quick clean is performed. A quick clean deallocates blocks having zero valid pages and places them in a queue for erasure. Otherwise, a deep clean is performed. A deep clean determines a compaction ratio, N-M, wherein N is a number of partially valid blocks and M is a number of free blocks required to compact the valid data from the N partially valid blocks into M entirely valid blocks. At least one data structure of the SSD is modified to refer to the M entirely valid blocks, and the N partially valid blocks are placed in the queue for erasure. | 01-27-2011 |
| 20110022779 | Skip Operations for Solid State Disks - Described embodiments provide skip operations for transferring data to or from a plurality of non-contiguous sectors of a solid-state memory. A host layer module sends data to, and receives commands from, a communication link. Received commands are one of read requests or write requests, with commands including i) a starting sector address, ii) a skip mask indicating the span of all sector addresses in the request and the sectors to be transferred, iii) a total number of sectors to be transferred; and, for write requests, iv) the data to be written to the sectors. A buffer stores data for transfer to or from the solid-state memory. A buffer layer module i) manages the buffer, ii) segments the span of the request into a plurality of chunks, and iii) determines, based on the skip mask, a number of chunks to be transferred to or from the solid-state memory. | 01-27-2011 |
| 20110022780 | RESTORE INDEX PAGE - Techniques for restoring index pages stored in non-volatile memory are disclosed where the index pages map logical sectors into physical pages. Additional data structures in volatile and non-volatile memory can be used by the techniques for restoring index pages. In some implementations, a lookup table associated with data blocks in non-volatile memory can be used to provide information regarding the mapping of logical sectors into physical pages. In some implementations, a lookup table associated with data blocks and a range of logical sectors and/or index pages can be used. | 01-27-2011 |
| 20110022781 | CONTROLLER FOR OPTIMIZING THROUGHPUT OF READ OPERATIONS - A controller, techniques, systems, and devices for optimizing throughput of read operations in flash memory are disclosed. Various optimizations of throughput for read operations can be performed using a controller. In some implementations, read operations for a multi-die flash memory device or system can be optimized to perform a read request with a highest priority (e.g., an earliest received read request) as soon as the read request is ready. In some implementations, the controller can enable optimized reading from multiple flash memory dies by monitoring a read/busy state for each die and switching between dies when a higher priority read operation is ready to begin. | 01-27-2011 |
| 20110022782 | FLASH STORAGE WITH ARRAY OF ATTACHED DEVICES - A flash storage system includes a flash storage controller coupled to storage modules of a flash storage array via universal serial buses. Each storage module includes at least one flash memory device. The flash storage controller receives a programming command of a communication protocol and generates universal serial bus commands based on the programming command. The flash storage controller issues the universal serial bus commands to storage modules in the flash storage array via the universal serial buses. The storage modules process the universal serial bus commands to access data in the flash storage devices of the storage modules. | 01-27-2011 |
| 20110022783 | FLASH STORAGE WITH INCREASED THROUGHPUT - A flash storage system includes a flash storage controller coupled to storage modules of a flash storage array via universal serial buses. Each storage module includes at least one flash memory device. The flash storage controller receives a programming command of a communication protocol and generates universal serial bus commands based on the programming command. The flash storage controller issues the universal serial bus commands to storage modules in the flash storage array via the universal serial buses. The storage modules process the universal serial bus commands to access data in the flash storage devices of the storage modules. | 01-27-2011 |
| 20110022784 | MEMORY SYSTEM - A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel. | 01-27-2011 |
| 20110022785 | METHOD FOR PROGRAMMING A MEMORY-PROGRAMMABLE CONTROLLER WITH RESISTANT STORAGE OF DATA IN MEMORY - The invention relates to a method for programming and/or diagnosis of a memory-programmable controller, having at least one memory-programmable function component. For programming, a predetermined programming system is used. In the context of this programming system variables are predetermined, and information exchange sequences are used for the programming. Results of the programming are output during at least one programming mode via an output device, and input information is at least in part stored permanently in memory. | 01-27-2011 |
| 20110022786 | FLASH MEMORY STORAGE APPARATUS, FLASH MEMORY CONTROLLER, AND SWITCHING METHOD THEREOF - A flash memory storage apparatus including a multi level cell (MLC) NAND flash memory, a flash memory controller, and a host transmission bus is provided. The MLC NAND flash memory includes a plurality of blocks for storing data, wherein each of the blocks has an upper page and a lower page, and the writing speed of the lower page is faster than that of the upper page. The flash memory controller is electrically connected to the MLC NAND flash memory and is used for executing storage mode switching steps. The host transmission bus is electrically connected to the flash memory controller and is used for communicating with a host. The flash memory storage apparatus provided by the present invention can provide multiple storage modes in order to store different data. | 01-27-2011 |
| 20110022787 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME - A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area. | 01-27-2011 |
| 20110022788 | INTEGRATING DATA FROM SYMMETRIC AND ASYMMETRIC MEMORY - Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component. | 01-27-2011 |
| 20110022789 | MEMORY DEVICE, HOST DEVICE, MEMORY SYSTEM, MEMORY DEVICE CONTROL METHOD, HOST DEVICE CONTROL METHOD AND MEMORY SYSTEM CONTROL METHOD - A memory card | 01-27-2011 |
| 20110029715 | WRITE-ERASE ENDURANCE LIFETIME OF MEMORY STORAGE DEVICES - A memory management system and method for managing memory blocks of a memory device of a computer. The system includes a free block data structure including free memory blocks for writing, and sorting the free memory blocks in a predetermined order based on block write-erase endurance cycle count and receiving new user-write requests to update existing data and relocation write requests to relocate existing data separately, a user-write block pool for receiving youngest blocks holding user-write data (i.e., any page being updated frequently) from the free block data structure, a relocation block pool for receiving oldest blocks holding relocation data (i.e., any page being updated infrequently) from the free block data structure, and a garbage collection pool structure for selecting at least one of user-write blocks and relocation blocks for garbage collection, wherein the selected block is moved back to the free block data structure upon being relocated and erased. | 02-03-2011 |
| 20110029716 | SYSTEM AND METHOD OF RECOVERING DATA IN A FLASH STORAGE SYSTEM - A flash storage system includes a system controller that generates redundant data based on data stored in flash storage devices of the flash storage system. The system controller stores the redundant data in one or more of the flash storage devices. Additionally, the system controller identifies data that has become unavailable in one or more of the flash storage device, recovers the unavailable data based on the redundant data, and stores the recovered data into one or more other flash storage devices of the flash storage system. | 02-03-2011 |
| 20110029717 | FLASH STORAGE DEVICE WITH FLEXIBLE DATA FORMAT - A flash storage device includes a flash storage for storing data and a controller for receiving a command containing data and selecting a sector size for the data. The controller allocates the data among data sectors having the sector size and writes the data sectors to the flash storage. In some embodiments, the controller generates system data and stores the system data in the data sectors or a system sector, or both. | 02-03-2011 |
| 20110029718 | METHOD AND SYSTEM TO IMPROVE THE PERFORMANCE OF A MULTI-LEVEL CELL (MLC) NAND FLASH MEMORY - A method and system to improve the performance of a multi-level cell (MLC) NAND flash memory. In one embodiment of the invention, the metadata associated with the data stored in a MLC NAND flash memory is stored only in one or more lower pages of the MLC NAND flash memory. The MLC NAND flash memory has lower and upper pages, where the lower pages have a faster programming time or rate than the upper pages in one embodiment of the invention. By storing the metadata only in the pages of the MLC NAND flash memory that have low latencies of programming, the quality of service (QoS) of the MLC NAND flash memory can be improved. | 02-03-2011 |
| 20110029719 | DATA WRITING METHOD FOR FLASH MEMORY AND CONTROL CIRCUIT AND STORAGE SYSTEM USING THE SAME - A data writing method for moving data in a plurality of flash memory modules during a write command of a host system is executed is provided, wherein each of the flash memory modules has a plurality of physical blocks. The present data writing method includes transferring first data received from the host system to one of the flash memory modules and writing the first data into the physical blocks of the flash memory module according to the write command. The present data writing method also includes moving at least one second data in the physical blocks of another one of the flash memory modules during the first data is written. Thereby, when the host system is about to write data into the other flash memory module, the time for executing the write command is effectively reduced. | 02-03-2011 |
| 20110029720 | Flash Storage Device and Operation Method Thereof - The invention provides a flash storage device. In one embodiment, the flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each of the plurality of blocks comprises a plurality of pages for storing data, and each of the plurality of pages has a physical address. The controller divides a plurality of logical addresses into a plurality of logical address ranges, records a plurality of partial link tables respectively storing a mapping relationship between logical addresses of a corresponding logical address range and corresponding physical addresses, stores the partial link tables in the flash memory, combines the partial link tables to obtain a link table, and converts logical addresses sent by a host to physical addresses according to the link table. | 02-03-2011 |
| 20110029721 | Cascaded combination structure of flash disks to create security function - Disclosed is a cascaded combination structure of flash disks to create security function, comprising of a plurality of data disks and a key disk. Each of the data disks includes a public zone and a private zone matched with the key disk. When the key disk is series-connected with the data disks, the private zone can be displayed and load/save by a public program in the key disk. Accordingly, there can be secured and hid the data in the private zone so that the data in the private zone is unable to be embezzled by other illegal users. | 02-03-2011 |
| 20110029722 | ELECTRONIC CONTROL APPARATUS INCLUDING ELECTRICALLY REWRITABLE NON-VOLATILE MEMORY - The electronic control apparatus includes an electrically rewritable non-volatile memory, a writing voltage there of being larger in absolute value than a reading voltage thereof, and a control section configured to access the non-volatile memory to perform data writing or data reading. The non-volatile memory includes a first terminal to receive the writing voltage generated by a voltage generating means disposed outside the electronic control apparatus, the first terminal being electrically isolated from the external voltage generating means. | 02-03-2011 |
| 20110029723 | Non-Volatile Memory Based Computer Systems - Non-volatile memory based computer systems and methods are described. According to one aspect of the invention, at least one non-volatile memory module is coupled to a computer system as main storage. The non-volatile memory module is controlled by a northbridge controller configured to control the non-volatile memory as main memory. The page size of the at least one non-volatile memory module is configured to be the size of one of the cache lines associated with a microprocessor of the computer system. According to another aspect, at least one non-volatile memory module is coupled to a computer system as data read/write buffer of one or more hard disk drives. The non-volatile memory module is controlled by a southbridge controller configured to control the non-volatile memory as an input/out device. The page size of the at least one non-volatile memory module is configured in proportion to characteristics of the hard disk drives. | 02-03-2011 |
| 20110029724 | Partial Block Data Programming And Reading Operations In A Non-Volatile Memory - Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units. | 02-03-2011 |
| 20110029725 | Switching Drivers Between Processors - Systems, methods, and computer software for operating a device can be used to operate the device in multiple modes. The device can be operated in a first operating mode adapted for processing data, in which a first processor executes a driver for a nonvolatile memory and a second processor performs processing of data stored in files on the nonvolatile memory. An instruction can be received to switch the device to a second operating mode adapted for reading and/or writing files from or to the nonvolatile memory. The driver for the nonvolatile memory can be switched from the first processor to the second processor in response to the instruction, and the driver for the nonvolatile memory can be executed on the second processor after performing the switch. A communications driver can be executed on the first processor in response to the instruction to switch the device to the second operating mode. | 02-03-2011 |
| 20110029726 | DATA UPDATING METHOD, MEMORY SYSTEM AND MEMORY DEVICE - A data updating method, a memory system and a memory device in which the memory device is connectable to a host device and has a memory section and a memory controller, the memory section consists of a first memory section which can be divided into partitions having multiple different attributes, and a work space which is managed by the memory controller, and the method of updating data which is stored in the memory device uses one of the writing methods which has been selected from among multiple different writing methods of writing data into the partition, depending on the attribute of the partition, to perform an updating process, and can securely update the data. | 02-03-2011 |
| 20110035534 | Dual-scope directory for a non-volatile memory storage system - A device, system, and method are disclosed. In one embodiment the device includes a non-volatile memory (NVM) storage array to store a plurality of storage elements. The device also includes a dual-scope directory structure having a background space and a foreground space. The structure is capable of storing several entries that each correspond to a location in the NVM storage array storing a storage element. The background space includes entries for storage elements written into the array without any partial overwrites of a previously stored storage element in the background space. The foreground space includes entries for storage elements written into the array with at least one partial overwrite of one or more previously stored storage elements in the background space. | 02-10-2011 |
| 20110035535 | Tracking a lifetime of write operations to a non-volatile memory storage - A method, device, and system are disclosed. In one embodiment method begins by incrementing a count of a total number of write operations to a non-volatile memory storage for each write operation to the non-volatile memory storage. The method then receives a request for the total count of lifetime write operations from a requestor. Finally, the method sends the total count of lifetime write operations to the requestor. | 02-10-2011 |
| 20110035536 | NON-VOLATILE MEMORY DEVICE GENERATING WEAR-LEVELING INFORMATION AND METHOD OF OPERATING THE SAME - A non-volatile memory device which includes a non-volatile memory core including a memory cell array and a controller configured to generate wear-leveling information from internal operation information of the memory cell array after a write operation, independent of a request from an external device. The wear-leveling information is selectively provided to the external device. | 02-10-2011 |
| 20110035537 | MULTIPROCESSOR SYSTEM HAVING MULTI-COMMAND SET OPERATION AND PRIORITY COMMAND OPERATION - A multiprocessor system comprises a multi-port semiconductor memory device, a first processor, and a memory link architecture. The multi-port semiconductor memory device comprises a mailbox area and a shared memory area accessible through a plurality of ports. The first processor is configured to write a multi-command set comprising multiple commands for multiple read/write operations to a command area of the shared memory, and to write a message to the mailbox area to indicate the writing of the multi-command set. The memory link architecture comprises a second processor connected to the multi-port semiconductor memory device, and a nonvolatile semiconductor memory device connected to the second processor. The second processor is configured to read the multi-command set from the mailbox area and to sequentially perform the multiple read/write operations according to the multi-command set. | 02-10-2011 |
| 20110035538 | NONVOLATILE MEMORY SYSTEM USING DATA INTERLEAVING SCHEME - A memory system comprises a plurality of nonvolatile memory devices configured for interleaved access. Programming times are measured and recorded for various memory cell regions of the nonvolatile memory devices, and interleaving units are formed by memory cell regions having different programming times. | 02-10-2011 |
| 20110035539 | STORAGE DEVICE, AND MEMORY CONTROLLER - The memory controller of a storage device includes a scramble pattern generator, a scramble processor, a logical and physical address conversion table, a memory interface, and a controller, in which the physical page is managed by dividing to a data section and a management section. For the data section, the controller controls the scramble pattern generator to generate a scramble pattern on the basis of a logical address specific to the data section, and controls the scramble processor to scramble the data of the data section corresponding to the logical address by using the scramble pattern, and for the management section, the controller controls the scramble pattern generator to generate a scramble pattern on the basis of a physical address as the write destination of the management section, and scrambling the management data by the scramble processor by using the scramble pattern, so that data is written and reading to and from the semiconductor memory. | 02-10-2011 |
| 20110035540 | FLASH BLADE SYSTEM ARCHITECTURE AND METHOD - A flash blade and associated methods enable improved areal density of information storage, reduced power consumption, decreased cost, increased IOPS, and/or elimination of unnecessary legacy components. In various embodiments, a flash blade comprises a host blade controller, a switched fabric, and one or more storage elements configured as flash DIMMs. Storage space provided by the flash DIMMs may be presented to a user in a configurable manner. Flash DIMMs, rather than magnetic disk drives or solid state drives, are the field-replaceable unit, enabling improved customization and cost savings. | 02-10-2011 |
| 20110035541 | STORAGE DEVICE AND DEDUPLICATION METHOD - This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area. | 02-10-2011 |
| 20110035542 | ASIC including vertically stacked embedded non-flash re-writable non-volatile memory - A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked upon one another. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 02-10-2011 |
| 20110035543 | MEMORY DRIVE THAT CAN BE OPERATED LIKE OPTICAL DISK DRIVE AND METHOD FOR VIRTUALIZING MEMORY DRIVE AS OPTICAL DISK DRIVE - The present invention relates to a memory drive that can be virtualized as an optical disk drive and a virtualizing method thereof. One embodiment of the present invention discloses a method for virtualizing a memory drive as an optical disk drive, the memory drive comprising a storage memory and a storage memory controller, which reads or writes data from and to the storage memory. Therefore, according to one embodiment of the present invention, a solid-state which comprises a flash memory and a flash memory controller can be used like an optical disk. | 02-10-2011 |
| 20110040924 | Controller and Method for Detecting a Transmission Error Over a NAND Interface Using Error Detection Code - The embodiments described herein provide a controller and method for detecting a transmission error over a NAND interface using error detection code. In one embodiment, a controller receives a write command, data, and an error detection code associated with the data from a host through a first NAND interface of the controller using a NAND interface protocol. The controller uses the error detection code to detect if a transmission error occurred. In another embodiment, a controller generates an error detection code based on data read from a flash memory device and provides the data and error detection code to a host through a first NAND interface of the controller, so the host can detect if a transmission error occurred. | 02-17-2011 |
| 20110040925 | Method and Apparatus for Addressing Actual or Predicted Failures in a FLASH-Based Storage System - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of adapting to the failure of one or more FLASH memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different FLASH memory device. The controller also detects failure of a FLASH memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed FLASH memory device. | 02-17-2011 |
| 20110040926 | FLASH-based Memory System With Variable Length Page Stripes Including Data Protection Information - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using different size page stripes. The controller is configured to store data in FLASH memory devices in the form of page stripes, each page stripe comprising a plurality of pages of information, each page of information being stored in a different FLASH memory chip. The controller stores the data in a manner such that the pages making up each page stripe includes a plurality of data pages and at least one data protection page. In one implementation, the page stripes stored by the controller include a first page stripe having N data pages and one data protection page, and a second page stripe having M data pages and one data protection page, where N is an integer greater than three and M is an integer less than N. | 02-17-2011 |
| 20110040927 | Method and Apparatus for Performing Enhanced Read and Write Operations in a FLASH Memory System - Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string. | 02-17-2011 |
| 20110040928 | METHOD FOR IDENTIFYING A PAGE OF A BLOCK OF FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE - A memory device includes a flash memory and a controller. The flash memory includes a plurality of blocks, and each block includes a plurality of pages. The controller is utilized for reading a plurality of bits from an identification region of a page, and determining whether the page is blank or not according to the plurality of bits. | 02-17-2011 |
| 20110040929 | METHOD AND APPARATUS FOR MODIFYING DATA SEQUENCES STORED IN MEMORY DEVICE - A method of modifying data sequences in a memory system comprises receiving program data having a first data sequence, and determining whether the received first data sequence matches one of “m” predefined sequences stored in the memory system. The method further comprises replacing the received first data sequence with a replacement sequence upon determining that the received first data sequence matches one of the “m” predefined sequences, and outputting the replacement sequence from the memory system. The replacement sequence typically comprises pattern bits indicating a pattern of the first data sequence and location bits indicating a start location of the first data sequence. | 02-17-2011 |
| 20110040930 | Method for Accessing Flash Memory Device and Memory System Including the Same - Provided are a method for accessing a flash memory device and a memory system including the same. In the method, first and second storage regions of a memory block of the flash memory device are set to free blocks, and each of the first and second storage regions are set to a data block independently. | 02-17-2011 |
| 20110040931 | MEMORY CONTROL METHOD AND DEVICE, MEMORY ACCESS CONTROL METHOD, COMPUTER PROGRAM, AND RECORDING MEDIUM - To dramatically increase the number of times data can be written into a flash memory. | 02-17-2011 |
| 20110040932 | Efficient Reduction of Read Disturb Errors in NAND FLASH Memory - Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block. | 02-17-2011 |
| 20110047316 | SOLID STATE MEMORY DEVICE POWER OPTIMIZATION - Memory device power optimization includes operating a memory device, wherein the memory device includes a plurality of data channels and each of the plurality of data channels includes a plurality of data storage units. A controller receives a command to enable a power saving feature and determines a frequency of accessing of data stored in the data storage units, sorts the data into the data channels according to the frequency of the accessing of the data and powers down the data channels that are storing data with a frequency of accessing the data that is below a pre-determined threshold value. | 02-24-2011 |
| 20110047317 | SYSTEM AND METHOD OF CACHING INFORMATION - A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache. | 02-24-2011 |
| 20110047318 | Reducing capacitive load in a large memory array - In various embodiments, field-effect transistors (FETs) or other high-resistance electronic switches may be used to take a large group of parallel-connected memory devices and separate them into smaller groups of parallel-connected devices, so that the signal lines in each group may be electrically isolated from the signals lines in the other groups. In this way, when one memory device is selected for an operation, only the other memory devices in that group will contribute to the capacitive load on the signal lines to the memory controller, while the capacitive load from the memory devices in the other groups will be electrically isolated by having their associated FETs turned off. The resultant reduced capacitive load may permit higher operating speeds and higher data rates for read or write operations with the memory devices. | 02-24-2011 |
| 20110047319 | Memory devices and systems including write leveling operations and methods of performing write leveling operations in memory devices and systems - A memory device controller having a write leveling mode of operation comprises: a clock generator that generates a periodic clock signal for transmission to a memory device; a data strobe generator that generates a data strobe signal for transmission to the memory device; and a control unit that generates command signals for transmission to the memory device, the controller, during operation in the write leveling mode, generating a command signal and a write leveling control signal for transmission to the memory device. | 02-24-2011 |
| 20110047320 | SYSTEM AND METHOD FOR PERFORMING PROGRAM OPERATION ON NONVOLATILE MEMORY DEVICE - A data processing system performs a data processing method by receiving and interpreting a command packet corresponding to a program operation, identifying a size of data to be programmed in the program operation, and programming the data using a buffered or un-buffered program operation based on the size of the data. | 02-24-2011 |
| 20110047321 | STORAGE PERFORMANCE MANAGEMENT METHOD - The computer system having a storage subsystem for storing data in a logical storage extent created in a physical storage device constituted of a physical storage medium, a host computer for reading/writing data from/to the logical storage extent via a network, and a management computer for managing the storage subsystem. The management computer records components of the storage subsystem, a connection relation between the components included in a network path, a correlation between the logical storage extent and the components, and a load of each component, specifies components included in a leading path from an interface through which the storage subsystem is connected with the network to the physical storage medium, measures loads of the specified components to improve performance. | 02-24-2011 |
| 20110047322 | METHODS, SYSTEMS AND DEVICES FOR INCREASING DATA RETENTION ON SOLID-STATE MASS STORAGE DEVICES - Methods, systems and devices for increasing the reliability of solid state drives containing one or more NAND flash memory arrays. The methods, systems and devices take into account usage patterns that can be employed to initiate proactive scrubbing on demand, wherein the demand is automatically generated by a risk index that can be based on one or more of various factors that typically contribute to loss of data retention in NAND flash memory devices. | 02-24-2011 |
| 20110047323 | MEMORY SYSTEM, MULTI-BIT FLASH MEMORY DEVICE, AND ASSOCIATED METHODS - A memory system includes a multi-bit flash memory device and a flash controller configured to control the multi-bit flash memory device. The flash controller is configured to output a series of commands, pointers, and addresses to the multi-bit flash memory device for read/program operations. | 02-24-2011 |
| 20110047324 | Memory device with vertically embedded non-Flash non-volatile memory for emulation of nand flash memory - A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example. | 02-24-2011 |
| 20110047325 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND SIGNAL PROCESSING SYSTEM - A nonvolatile semiconductor memory device includes: memory cells regularly arranged in a matrix pattern, and having as a charge storage medium a nonconductive nitride film capable of configuring two physical bits in each memory cell; and bit lines connecting in common a source or drain of one of two memory cells adjoining in a row direction with a source or drain of the other memory cell. One of two bits in each memory cell having the nonconductive nitride film is accessed by a first address group allocated to a first function, and the other bit is accessed by a second address group allocated to a second function. | 02-24-2011 |
| 20110055453 | INTERRUPTIBLE NAND FLASH MEMORY - A NAND flash memory logical unit. The NAND flash memory logical unit includes a control circuit that responds to commands and permits program and/or erase commands to be interruptible by read commands. The control circuit includes a set of internal registers for performing the current command, and a set of external registers for receiving commands. The control circuit also includes a set of supplemental registers that allow the NAND flash memory logical unit to have redundancy to properly hold state of an interrupted program or erase command. When the interrupted program or erase command is to resume, the NAND flash memory logical unit thus can quickly resume the paused program or erase operation. This provides significant improvement to read response times in the context of a NAND flash memory logical unit. | 03-03-2011 |
| 20110055454 | SYSTEMS AND METHODS FOR DETERMINING THE STATUS OF MEMORY LOCATIONS IN A NON-VOLATILE MEMORY - Systems and methods are provided for storing data in a portion of a non-volatile memory (“NVM”) such that the status of the NVM portion can be determined with high probability on a subsequent read. An NVM interface, which may receive write commands to store user data in the NVM, can store a fixed predetermined sequence (“FPS”) with the user data. The FPS may ensure that a successful read operation on a NVM portion is not misinterpreted as a failed read operation or as an erased NVM portion. For example, if the NVM returns an all-zero vector when a read request fails, the FPS can include at least one “1” or one “0”, as appropriate, to differentiate between successful and unsuccessful read operations. In some embodiments, the FPS may also be used to differentiate between disturbed data, which passes an error correction check, and correct data. | 03-03-2011 |
| 20110055455 | INCREMENTAL GARBAGE COLLECTION FOR NON-VOLATILE MEMORIES - Systems and methods are provided for performing incremental garbage collection for non-volatile memories (“NVMs”), such as flash memory. In some embodiments, an electronic device including the NVM may perform incremental garbage collection to free up and erase a programmed block of the NVM. The programmed block may include valid data and invalid data, and the electronic device may be configured to copy the valid data from the programmed block to an erased block in portions. In between programming each portion of the valid data to the erased block, the electronic device can program host data to the erased block. This way, the electronic device can stagger the garbage collection operations and prevent a user from having to experience one long garbage collection operation. | 03-03-2011 |
| 20110055456 | METHOD FOR GIVING READ COMMANDS AND READING DATA, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A method for giving a read command to a flash memory chip to read data to be accessed by a host system is provided. The method includes receiving a host read command; determining whether the received host read command follows a last host read command; if yes, giving a cache read command to read data from the flash memory chip; and if no, giving a general read command and the cache read command to read data from the flash memory chip. Accordingly, the method can effectively reduce time needed for executing the host read commands by using the cache read command to combine the host read commands which access continuous physical addresses and pre-read data stored in a next physical address. | 03-03-2011 |
| 20110055457 | METHOD FOR GIVING PROGRAM COMMANDS TO FLASH MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A method for giving program commands to a flash memory chip is provided, the method is suitable for writing data from a host system into the flash memory chip. In the present method, a plurality of host write commands and data corresponding to the host write commands are received from the host system by using a native command queuing (NCQ) protocol, and cache program commands are gived to the flash memory chip to write the data into the flash memory chip. Accordingly, the time for executing the host write commands is effectively shortened by writing the data through the cache program commands and the NCQ protocol. | 03-03-2011 |
| 20110055458 | Page based management of flash storage - Methods and circuits for page based management of an array of Flash RAM nonvolatile memory devices provide paged base reading and writing and block erasure of a flash storage system. The memory management system includes a management processor, a page buffer, and a logical-to-physical translation table. The management processor is in communication with an array of nonvolatile memory devices within the flash storage system to provide control signals for the programming of selected pages, erasing selected blocks, and reading selected pages of the array of nonvolatile memory devices. | 03-03-2011 |
| 20110055459 | METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a plurality of blocks of a Flash memory includes: dynamically determining a link type regarding a logical block address according to at least one criterion, where the link type is selected from a plurality of predetermined link types; and regarding the logical block address, recording/updating the link type and linking information corresponding to the link type. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks. | 03-03-2011 |
| 20110055460 | METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a plurality of blocks of a Flash memory includes: recording/updating linking information regarding a logical block address, wherein the linking information includes a plurality of physical block addresses linking to the logical block address, and each physical block address represents a block of the plurality of blocks; and when a block represented by a physical block address of the plurality of physical block addresses has no any valid page, selectively erasing the block and removing the physical block address from the linking information. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks. | 03-03-2011 |
| 20110055461 | SYSTEMS AND METHODS FOR PRE-EQUALIZATION AND CODE DESIGN FOR A FLASH MEMORY - A system, computer readable program, and method for programming flash memory, the method includes: providing multiple pairs of most significant bit (MSB) page uncoded bit error rates (UBERs) and least significant bit (LSB) page UBERs; selecting a selected MSB page code rate and a selected LSB page code rate so that a selected MSB page UBER associated with the selected MSB page code rate and a selected LSB page UBER associated with the selected LSB page code rate support a highest average UBER out of the multiple pairs of MSB page UBERs and LSB page UBERs, wherein the selected MSB page code rate and the selected LSB page code rate are obtainable under a desired code rate constraint; and determining an encoding and programming scheme that may be based on the selected MSB page UBER, the selected MSB code rate, the selected LSB page UBER and the selected LSB code rate. | 03-03-2011 |
| 20110055462 | MEMORY SYSTEM, CONTROLLER, AND DATA TRANSFER METHOD - According to one embodiment, a memory system includes a nonvolatile first memory, a nonvolatile second memory, a data-copy processing unit and a data invalidation processing unit. The first memory has a storage capacity for n (n≧2) pages per word line. The nonvolatile second memory temporarily stores user data write-requested from a host apparatus. The data-copy processing unit executes data copy processing including reading out, in page units, the user data stored in the second memory and sequentially writing the read-out user data in page units in the first memory. The data invalidation processing unit selects, after the execution of the data copy processing, based on whether the memory cell group per word line stores user data for n pages, user data requiring backup out of the user data subjected to the data copy processing and leaves the selected user data in the second memory as backup data. | 03-03-2011 |
| 20110055463 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THE SAME - It is an object to prevent miswriting by radio in a relatively easy way in a semiconductor device which is capable of data communication (reception/transmission) through wireless communication, in particular, in an RFID tag provided with an OTP memory or a write-once memory. Alternatively, it is an object to prevent data from being tampered. Further alternatively, it is an object to inhibit access to a memory in a relatively easy way and to inhibit reading of data in a semiconductor device which is capable of data communication (reception/transmission) through wireless communication. In a semiconductor device including a control circuit and an OTP memory, a memory includes at least a sector for preventing additional writing and an information sector. When data for preventing additional writing is written to the sector for preventing additional writing and information is written to the information sector which is electrically connected to the sector for preventing additional writing, additional writing to the information sector to which the information is written is impossible. | 03-03-2011 |
| 20110055464 | Device driver including a flash memory file system and method thereof and a flash memory device and method thereof - A device driver including a flash memory file system and method thereof and a flash memory device and method thereof are provided. The example device driver may include a flash memory file system configured to receive data scheduled to be written into the flash memory device, the flash memory file system selecting one of a first data storage area and a second data storage area within the flash memory device to write the received data to based upon an expected frequency of updating for the received data, the first data storage area configured to store data which is expected to be updated more often than the second data storage area. The example flash memory device may include a first data storage area configured to store first data, the first data having a first expected frequency for updating and a second data storage area configured to store second data, the second data having a second expected frequency of updating, the first expected frequency being higher than the second expected frequency. | 03-03-2011 |
| 20110055465 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell, wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell. | 03-03-2011 |
| 20110055466 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 03-03-2011 |
| 20110055467 | DATA AREA MANAGING METHOD IN INFORMATION RECORDING MEDIUM AND INFORMATION PROCESSOR EMPLOYING DATA AREA MANAGING METHOD - Area management information is cached in a cache memory by controlling the access size when an information processor accesses the area management information in an information recording medium. When the processing content of the information processor is to retrieve a free area from the area management information, a physical management block size determined from the physical characteristics of the information recording medium is used. When the processing content is to acquire a link destination from the area management information, minimum access unit of the information recording medium is used. Consequently, overhead can be lessened when the area management information is accessed. | 03-03-2011 |
| 20110055468 | Flash Memory Data Correction and Scrub Techniques - In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase. | 03-03-2011 |
| 20110060861 | Systems and Methods for Variable Level Use of a Multi-Level Flash Memory - Various embodiments of the present invention provide systems, methods and circuits for use of a memory system. As one example, an electronics system is disclosed that includes a memory bank, a memory access controller circuit, and an encoding circuit. The memory bank includes a plurality of multi-bit memory cells that each is operable to hold at least two bits. The memory access controller circuit is operable to determine a use frequency of a data set maintained in the memory bank. The encoding circuit is operable to encode the data set to yield an encoded output for writing to the memory bank. The encoding level for the data set is selected based at least in part on the use frequency of the data set. | 03-10-2011 |
| 20110060862 | Systems and Methods for Switchable Memory Configuration - Various embodiments of the disclosure provide systems, methods and circuits for implementation and use of a memory system. As one example, a memory system is disclosed that includes a plurality of memory devices and a configuration circuit. The configuration circuit includes at least one input, a plurality of outputs, and a programmable control circuit. The plurality of outputs are communicably coupled to the plurality of memory devices, and the programmable control circuit is operable to selectably couple the input to at least one of the plurality of outputs. | 03-10-2011 |
| 20110060863 | CONTROLLER - A controller stores therein a sector address set indicating logical storage positions within a nonvolatile-memory storage area; page addresses indicating, in units of pages, physical storage positions within the nonvolatile-memory storage area; and pieces of management information each indicating whether one or more special sectors each being either a bad sector or a trimmed sector trimmed by a TRIM command are present in the corresponding page, while associating them with each other. When an access to a specified sector address is requested, the device refers to the piece of management information and judges whether any special sector is present in the page identified by the page address corresponding to the sector address. The device generates predetermined response data if the page contains one or more special sectors and accesses the nonvolatile-memory storage position corresponding to the sector address if the page contains no special sector. | 03-10-2011 |
| 20110060864 | CONTROLLER AND DATA STORAGE DEVICE - A volatile management memory stores management information for managing a use state of a storage medium. A management information storing unit divides the management information into plural division pieces and individually stores them in the storage medium. A main controller receives a command from a host device while the division pieces are being stored, performs data processing for the storage medium in response to the command between each division piece is stored, updates the management information divided into the division pieces according to the data processing content, and creates a log representing an update content of the management information. A log storing unit stores the log in the storage medium. A restoring unit reads the division pieces stored in the storage medium to the management memory as the management information, updates the management information according to the log stored in the storage medium, and restores the updated management information. | 03-10-2011 |
| 20110060865 | Systems and Methods for Flash Memory Utilization - Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a non-volatile memory, a flash memory, and a read/write controller circuit. The read/write controller circuit is coupled to both the flash memory and the non-volatile memory, and is operable to receive a data set directed to the flash memory and to direct the data set to the random access memory. | 03-10-2011 |
| 20110060866 | MEMORY SYSTEM - According to one embodiment, a memory system includes a first memory chip includes a first temporary memory and a first block, a second memory chip includes a second temporary memory and a second block, and a memory controller that controls writing of logical pages to the first and second memory chips. The memory controller forms a second unit having the same page number as the first unit by the first temporary memory and the lowermost physical page in the first block, forms a third unit having the same page number as the first unit by the second temporary memory and the lowermost physical page in the second block, and writes the logical pages by an interleave operation in order of the second unit, the third unit, the first unit in the first block, and the first unit in the second block. | 03-10-2011 |
| 20110060867 | DATA STORAGE DEVICE AND COMPUTER SYSTEM INCORPORATING SAME - A data storage device is configured to operate as an internal device of a first host system or an external device of a second host system, depending on whether it is connected to the second host system. A connection detector detects connections between the data storage device and the second host system and facilitates communication between the data storage device and the second host system upon detecting such connections. | 03-10-2011 |
| 20110060868 | MULTI-BANK FLASH MEMORY ARCHITECTURE WITH ASSIGNABLE RESOURCES - This disclosure has described embodiments of a nonvolatile memory that includes at least two concurrently accessible memory banks ( | 03-10-2011 |
| 20110060869 | LARGE CAPACITY SOLID-STATE STORAGE DEVICES AND METHODS THEREFOR - Non-volatile storage devices and methods capable of achieving large capacity SSDs containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and optionally a memory controller. The bank switching circuitry is functionally interposed between the banks of memory devices and either the connector or the memory controller. The bank switching circuitry operates to switch accesses by a system logic or the memory controller among the at least two banks. | 03-10-2011 |
| 20110060870 | NONVOLATILE MEMORY SYSTEMS WITH EMBEDDED FAST READ AND WRITE MEMORIES - A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system. | 03-10-2011 |
| 20110060871 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories. | 03-10-2011 |
| 20110060872 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories. | 03-10-2011 |
| 20110060873 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories. | 03-10-2011 |
| 20110060874 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories. | 03-10-2011 |
| 20110060875 | FRACTIONAL PROGRAM COMMANDS FOR MEMORY DEVICES - A memory system ( | 03-10-2011 |
| 20110066787 | METHOD AND SYSTEM FOR SECURELY PROGRAMMING OTP MEMORY - A semiconductor chip may be operable to receive and copy an OTP programming vector presented by the semiconductor chip programming device into its memory after it boots up from the boot read-only memory (ROM). The OTP programming vector which is a computer program may comprise an encrypted data to be programmed into the one-time programmable (OTP) memory in the semiconductor chip and may be signed with an electronic signature. The semiconductor chip may be operable to authenticate the OTP programming vector in the memory. The authenticated OTP programming vector in the memory may be executed to decrypt the data and program the data in a random data format into the OTP memory and then report the status via one or more general purpose input/output (GPIO) pins on the semiconductor chip. | 03-17-2011 |
| 20110066788 | CONTAINER MARKER SCHEME FOR REDUCING WRITE AMPLIFICATION IN SOLID STATE DEVICES - A solid state storage device and method are provided. Multiple blocks are configured as storage memory for a solid state storage device, and each block includes multiple pages. A controller is configured to operate the solid state storage device. A free block of the multiple blocks is assigned a marker level by the controller. For a particular page of the multiple pages, each particular page of data is written to a block of the multiple blocks with a marker level corresponding to a level of dynamicity calculated by the controller for that particular page. | 03-17-2011 |
| 20110066789 | FILE SYSTEM DERIVED METADATA FOR MANAGEMENT OF NON-VOLATILE MEMORY - A file system programs metadata on a non-volatile memory device. The metadata can include data associating files with ranges of logical block addresses. During a garbage collection process, the data can be used to determine portions of physical blocks of the non-volatile memory device that are associated with files that have been deleted. Using the programmed metadata during garbage collection results in erasure of larger portions of blocks and improved wear leveling. | 03-17-2011 |
| 20110066790 | MAIN MEMORY WITH NON-VOLATILE MEMORY AND DRAM - One embodiment is main memory that includes a combination of non-volatile memory (NVM) and dynamic random access memory (DRAM). An operating system migrates data between the NVM and the DRAM. | 03-17-2011 |
| 20110066791 | CACHING DATA BETWEEN A DATABASE SERVER AND A STORAGE SYSTEM - Techniques are provided for using an intermediate cache between the shared cache of a database server and the non-volatile storage of a storage system. The intermediate cache may be local to the machine upon which the database server is executing, or may be implemented within the storage system. In one embodiment, the database system includes both a DB server-side intermediate cache, and a storage-side intermediate cache. The caching policies used to populate the intermediate cache are intelligent, taking into account factors that may include which database object an item belongs to, the item type of the item, a characteristic of the item; or the database operation in which the item is involved. | 03-17-2011 |
| 20110066792 | Segmentation Of Flash Memory For Partial Volatile Storage - This disclosure provides a method and system that segment flash memory to have differently managed regions. More particularly, flash memory is segmented into a “non-volatile” region, where program counts are restricted to preserve baseline retention assumptions, and a “volatile” region, where program counts are unrestricted. Contrary to conventional wisdom, wear leveling is not performed on all flash memory, as the volatile region is regarded as degraded, and as the non-volatile region has program counts restricted to promote long-term retention. More than two regions may also be created; each of these may be associated with intermediate program counts and volatility expectations, and wear leveling may be applied to each of these on an independent basis if desired. Refresh procedures may optionally be applied to the region of flash memory which is treated as volatile memory. | 03-17-2011 |
| 20110066793 | Implementing RAID In Solid State Memory - The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving data to be stored, dividing data into logical data blocks, assigning the blocks to a logical block grouping comprising at least one physical data storage block from two or more of multiple solid state physical memory devices, storing the blocks in physical data storage blocks, determining a code that corresponds to the persisted data, and storing the code that corresponds to the data stored in the logical block grouping. Blocks of damaged stored data may be recovered by identifying the logical data block and logical block grouping corresponding to the damaged physical data storage block, reading the data and the code stored in the identified grouping, and comparing the code to the read data other than the data stored in the damaged block. | 03-17-2011 |
| 20110066794 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device comprises a board, a first semiconductor storage device placed on the board, and a second semiconductor storage device placed on the board. Each of the first and second semiconductor storage devices has a first pad for inputting a chip enable signal, a second pad for inputting a write enable signal, a third pad for inputting an output enable signal, a fourth pad for inputting an address signal, and a fifth pad for inputting data. The first semiconductor storage device has a sixth pad which is electrically connected to the first pad of the second semiconductor device, and the second semiconductor storage device has a seventh pad which is electrically connected to the first pad of the first semiconductor device. | 03-17-2011 |
| 20110072189 | METADATA REDUNDANCY SCHEMES FOR NON-VOLATILE MEMORIES - Systems and methods are provided for storing data to or reading data from a non-volatile memory (“NVM”), such as flash memory, using a metadata redundancy scheme. In some embodiments, an electronic device, which includes an NVM, may also include a memory interface for controlling access to the NVM. The memory interface may receive requests to write user data to the NVM. The user data from each request may be associated with metadata, such as a logical address, flags, or other data. In response to a write request, the NVM interface may store the user data and its associated metadata in a first memory location (e.g., page), and may store a redundant copy of the metadata in a second memory location. This way, even if the first memory location becomes inaccessible, the memory interface can still recover the metadata from the backup copy stored in the second memory location. | 03-24-2011 |
| 20110072190 | MEMORY DEVICE AND METHOD - A device is disclosed having a memory module that comprises a first memory block, a second memory block, a programmable storage location, and a memory controller. The first memory block of non-volatile memory comprises a plurality of word locations and an address decoder coupled to a first access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the first access port. The second memory block comprising a plurality of word locations and an address decoder coupled to a second access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the second access port. The memory controller comprising an input coupled to the programmable storage location, and to access, in response to the programmable configuration information having a first value, a first portion of the first memory block and a first portion of the second memory block as interleaved memory, a second portion of the first memory block as non-interleaved memory, and a second portion of the second memory block as non-interleaved memory. | 03-24-2011 |
| 20110072191 | Uniform Coding System for a Flash Memory - A uniform coding system for a flash memory is disclosed. A statistic decision unit determines a coding word according to a plurality of inputs. An inverse unit controllably inverts input data to be encoded. The input data are then encoded into encoded data according to a statistic determined by the statistic decision unit. | 03-24-2011 |
| 20110072192 | SOLID STATE MEMORY WEAR CONCENTRATION - A memory system includes a volatile memory and a non-volatile memory. The volatile memory is configured as a random access memory or cache for the nonvolatile memory. Wear concentration logic targets one or more selected devices of the nonvolatile memory for accelerated wear. | 03-24-2011 |
| 20110072193 | DATA READ METHOD, AND FLASH MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data read method for reading data to be accessed by a host system from a plurality of flash memory modules is provided. The data read method includes receiving command queuing information related to a plurality of host read commands from the host system, each of the host read commands is corresponding to one of a plurality of data input/output buses coupled to the flash memory modules. The data read method also includes re-arranging the host read commands and generating a command giving sequence according to the data input/output buses corresponding to the host read commands. The data read method further includes sequentially receiving and processing the host read commands from the host system according to the command giving sequence and pre-reading data corresponding to a second host read command. Thereby, the time for executing the host read commands can be effectively shortened. | 03-24-2011 |
| 20110072194 | Logical-to-Physical Address Translation for Solid State Disks - Described embodiments provide logical-to-physical address translation for data stored on a storage device having sectors organized into blocks and superblocks. A flash translation layer maps a physical address in the storage device to a logical sector address. The logical sector address corresponds to mapping data that includes i) a page index, ii) a block index, and iii) a superblock number. The mapping data is stored in at least one summary page corresponding to the superblock containing the physical address. A block index and a page index of a next empty page in the superblock are stored in a page global directory corresponding to the superblock. A block index and a page index of the at least one summary page and the at least one active block table for each superblock are stored in at least one active block table of the storage device. | 03-24-2011 |
| 20110072195 | METHOD FOR MANAGING A MEMORY DEVICE HAVING MULTIPLE CHANNELS AND MULTIPLE WAYS, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a memory device having multiple channels and multiple ways includes: with regard to a logical page, finding a Flash memory chip for being written from a plurality of Flash memory chips according to a predetermined order of the Flash memory chips, and during finding the Flash memory chip, omitting any Flash memory chip that is busy or not suitable for writing; and writing data belonging to the logical page and a serial number for indicating a writing order into a corresponding physical page within a block of the Flash memory chip that is found. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory chips. | 03-24-2011 |
| 20110072196 | Cache Synchronization for Solid State Disks - Described embodiments provide a media controller that synchronizes data cached in a buffer and corresponding data stored in one or more sectors of a storage device. A buffer layer module of the media controller caches data transferred between the buffer and the storage device. One or more contiguous sectors are associated with one or more chunks. The buffer layer module updates a status corresponding to each chunk of the cached data and scans the status corresponding to a first chunk of cached data. If, based on the status, the first chunk of cached data is more recent than the corresponding data stored on the storage device, a media layer module synchronizes the data on the storage device with the cached data. The status corresponding to the group of one or more sectors is updated. The media layer module scans a next chunk of cached data, if present. | 03-24-2011 |
| 20110072197 | Buffering of Data Transfers for Direct Access Block Devices - Described embodiments provide a method of transferring, by a media controller, data associated with a host data transfer between a host device and a storage media. A buffer layer module of the media controller segments the host data transfer into one or more data transfer segments. Each data transfer segment corresponds to at least a portion of the data. The buffer layer module allocates a number of physical buffers to a virtual circular buffer for buffering the one or more data transfer segments. The buffer layer module transfers, by the virtual circular buffer, each of the data transfer segments between the host device and the storage media through the allocated physical buffers. | 03-24-2011 |
| 20110072198 | ACCESSING LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION DATA FOR SOLID STATE DISKS - Described embodiments provide a media controller for a storage device having sectors, the sectors organized into blocks and superblocks. The media controller stores, on the storage device, logical-to-physical address translation data in N summary pages, where N corresponds to the number of superblocks of the storage device. A buffer layer module of the media controller initializes a summary page cache in a buffer. The summary page cache has space for M summary page entries, where M is less than or equal to N. For operations that access a summary page, the media controller searches the summary page cache for the summary page. If the summary page is stored in the summary page cache, the buffer layer module retrieves the summary page from the summary page cache. Otherwise, the buffer layer module retrieves the summary page from the storage device and stores the retrieved summary page to the summary page cache. | 03-24-2011 |
| 20110072199 | STARTUP RECONSTRUCTION OF LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION DATA FOR SOLID STATE DISKS - Described embodiments provide reconstruction of logical-to-physical address mapping data for one or more sectors of a storage device at startup of a media controller. The sectors of the storage device are organized into blocks and superblocks and the address mapping data is stored in a volatile memory. At a startup condition of the media controller, a buffer layer module of the media controller allocates space in the volatile memory for one or more logical-to-physical address mapping data structures. A media layer module of the media controller determines a block type of each block of the storage device and places each block of the storage device into corresponding groups based on the determined block type of each block. The one or more blocks of each group are processed, and one or more address mapping data structures for the storage device are constructed in the allocated space in the volatile memory. | 03-24-2011 |
| 20110072200 | Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface - A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command. | 03-24-2011 |
| 20110072201 | Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface - A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command. | 03-24-2011 |
| 20110072202 | METHOD FOR WEAR LEVELING IN A NONVOLATILE MEMORY - A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased. | 03-24-2011 |
| 20110072203 | METHOD AND DEVICES FOR INSTALLING AND RETRIEVING LINKED MIFARE APPLICATIONS - A method for installing linked MIFARE applications (TK | 03-24-2011 |
| 20110072204 | MEMORY SERVER - A memory server providing remote memory for servers independent from the memory server. The memory server includes memory modules and a page table. A memory controller for the memory server allocates memory in the memory modules for each of the servers and manages remote memory accesses for the servers. The page table includes entries identifying the memory module and locations in the memory module storing data for the servers. | 03-24-2011 |
| 20110078362 | OPERATING AN EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY - An emulated electrically erasable memory system includes a random access memory (RAM) and a non-volatile memory (NVM). A write access to the RAM is received which provides first write data and a first address, where the first write data is stored in the RAM at the first address, and a currently filling sector of the NVM is updated to store both the first write data and the first address as a first record. In response to the write access, based on whether there are any remaining active records in an oldest filled sector of the NVM, a portion of an erase process or a transfer of up to a predetermined number of active records from the oldest filled sector to the currently filling sector is performed. The predetermined number of active records is less than a maximum number of total records that may be stored within the oldest filled sector. | 03-31-2011 |
| 20110078363 | BLOCK MANAGEMENT METHOD FOR A FLASH MEMORY AND FLASH MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME - A block management method for managing a plurality of physical blocks of a flash memory chip is provided. The block management method includes configuring a plurality of logical addresses; mapping the logical addresses to a plurality of logical blocks; and mapping the logical blocks to the physical blocks. Additionally, the block management method also includes obtaining deleting records related to a plurality of deleted logical addresses from a host system, wherein data stored in the deleted logical addresses is recognized as invalid by the host system. And, the block management method further includes obtaining a deleted logical block, marking each of the logical addresses mapped to the deleted logical block as a bad logical address, and linking the physical block mapped to the deleted logical block to a spare area. Accordingly, the block management method can effectively prolong the lifespan of a flash memory chip. | 03-31-2011 |
| 20110078364 | SOLID STATE STORAGE SYSTEM FOR CONTROLLING RESERVED AREA FLEXIBLY AND METHOD FOR CONTROLLING THE SAME - A solid state storage system includes a flash memory area and a memory controller. The flash memory area includes memory blocks and replacement blocks configured to replace bad blocks occurring within the memory blocks. The memory controller is configured to perform a logical-to-physical address mapping on logical blocks including the replacement blocks, and select the replacement blocks using logical addresses of the logical blocks corresponding to the bad blocks. | 03-31-2011 |
| 20110078365 | DATA ACCESS METHOD OF A MEMORY DEVICE - The invention provides a data access method of a memory device. In one embodiment, the memory device comprises a plurality of memories. First, a plurality of commands sequentially received from a host is stored in a command queue. A target command is then retrieved from the command queue. A target memory accessed by the target command is then determined. Whether the target memory is in a busy state is then determined. When the target memory is not in a busy state, access operations requested by the target command are then performed. When the target memory is in a busy state, a substitute command is selected from a plurality of subsequent commands stored in the command queue and access operations requested by the substitute command are performed, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command. | 03-31-2011 |
| 20110078366 | Semiconductor device with non-volatile memory and random access memory - A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data. | 03-31-2011 |
| 20110082963 | POWER INTERRUPT MANAGEMENT - The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (LA) table using the transaction log. | 04-07-2011 |
| 20110082964 | PARTITIONING PROCESS TO IMPROVE MEMORY CELL RETENTION - Subject matter disclosed herein relates to improving memory cell retention for non-volatile flash memory. | 04-07-2011 |
| 20110082965 | PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE - A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages. | 04-07-2011 |
| 20110082966 | Authentication and Securing of Write-Once, Read-Many (WORM) Memory Devices - These embodiments relate to authentication and securing of write-once, read-many (WORM) memory devices. In one embodiment, a memory device comprises a controller operable in first and second modes of operation after stored security information is validated, wherein in the first mode of operation, the memory device operates in a read-only mode, and wherein in the second mode of operation, the memory device operates in a write-once, read-many (WORM) mode. In another embodiment, the controller is operative to perform security methods. | 04-07-2011 |
| 20110082967 | Data Caching In Non-Volatile Memory - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, can perform data caching. In some implementations, a method and system include receiving information that includes a logical address, allocating a physical page in a non-volatile memory structure, mapping the logical address to a physical address of the physical page, and writing, based on the physical address, data to the non-volatile memory structure to cache information associated with the logical address. The logical address can include an identifier of a data storage device and a logical page number. | 04-07-2011 |
| 20110082968 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 04-07-2011 |
| 20110082969 | Associative data storage devices for authentication of collectable objects - In one embodiment of the present invention, an associative data storage device for authentication of collectable objects is described. A non-volatile electronic data storage device is used in combination with at least one collectable object. The non-volatile electronic data storage device is detached from the collectable object and electronically configured to store at least one immutable digital image of at least one unique appearance characteristic of the collectable object. The data storage device is provided with tamper resistant visual markings that are associative with visual markings of the collectable object so as to provide association of the data storage device with the collectable object. The non-volatile electronic data storage device is compatible with a standard computer system for a user to view one or more digital images of the unique appearance characteristics of the collectable object for authentication and identification of the collectable object. In preferred embodiments, the non-volatile data storage device is a solid-state Flash Memory type data storage device. | 04-07-2011 |
| 20110087823 | APPARATUS AND METHOD FOR PRODUCING IDS FOR INTERCONNECTED DEVICES OF MIXED TYPE - A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR-, AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input are fed to one device of the serial interconnection configuration. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. | 04-14-2011 |
| 20110087824 | FLASH MEMORY ACCESSING APPARATUS AND METHOD THEREOF - A flash memory accessing apparatus is disclosed. The flash memory accessing apparatus includes a controller, a first channel memory set and a second channel memory set. The first channel memory set includes a first flash memory and at least one first memory expanding socket. The second channel memory set includes a second flash memory and at least one second memory expanding socket. The controller determines the accessing method to be implemented on the first memory and second flash memory according to whether there is any flash memory inserted into the first memory expanding socket and the second memory expanding socket. | 04-14-2011 |
| 20110087825 | Electronic Device with Removable USB Flash Drive and USB Flash Drive with Added Functionality - A USB flash drive for removable connection to another device such as a cell phone, camera, computer, gaming system and photo printer, for example. In one embodiment, a cell phone having a USB port is provided wherein the USB flash drive configured to connect into a slot in the cell phone housing. A user may then quickly transfer data downloaded to the USB flash drive when connected to the cell phone, and another device such as a photo printer, for example. One or more optional additional functionality is incorporated into the USB flash drive such as, for example, a camera, internet card and MP3 player. | 04-14-2011 |
| 20110087826 | FLASH MEMORY ACCESSING APPARATUS AND ACCESSING METHOD THEREOF - A flash memory accessing apparatus is disclosed. The flash memory accessing apparatus includes a memory controller, a first open NAND flash interface (ONFI) and an expanding flash memory module. The first ONFI is used for connecting a main flash memory module. The memory controller obtains a detecting result by, detecting whether the main flash memory module and the expanding flash memory module are single side or double side. The memory controller further configures an accessing method of the main flash memory module and the expanding flash memory module according to the detecting result. | 04-14-2011 |
| 20110087827 | DATA WRITING METHOD FOR A FLASH MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a flash memory chip is provided. The method includes configuring a plurality of logical page addresses, grouping the logical page addresses into a plurality of logical blocks, and recording the data dispersion degree of each of the logical blocks. The method also includes receiving write-in data from the host system, identifying a logical block that a logical page address to be written by the host system belongs to, and writing the write-in data into the flash memory chip according to the data dispersion degree of the logical block, wherein the data dispersion degree of each of the logical blocks is not larger than a logical block data dispersion degree threshold value. Accordingly, the method can effectively reduce the time for executing a host write command. | 04-14-2011 |
| 20110087828 | METHOD FOR ENHANCING PERFORMANCE OF ACCESSING A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing performance of accessing a Flash memory, which includes a plurality of blocks and is positioned in a memory device, includes: during writing data into the Flash memory, establishing/updating at least one linking table in a random access memory (RAM) of the memory device, wherein regarding the Flash memory, the linking table indicates linking relationships between logical addresses and physical addresses, or indicates linking relationships between physical addresses and logical addresses; and writing the linking table into the Flash memory only when it is detected that a flush cache command is sent from a host device. An associated memory device and a controller thereof are also provided, where the controller includes: a read only memory (ROM) arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory. | 04-14-2011 |
| 20110087829 | DATA STORAGE DEVICE AND DATA ACCESS METHOD - The invention provides a data storage device. In one embodiment, the data storage device comprises a storage medium, a random access memory, and a controller. The storage medium stores a plurality of link tables. The random access memory comprises a plurality of storage units respectively corresponding to a plurality of logical address ranges. The controller receives a target logical address from the host, determines a target link table corresponding to a logical address set comprising the target logical address, determines a target storage unit corresponding to a logical address range comprising the target logical address, determines whether the target storage unit has stored the target link table, and when the target storage unit has stored the target link table, determines a target physical address mapped to the target logical address according to a mapping relationship stored in the target link table, and accesses data stored in the storage medium according to the target physical address. | 04-14-2011 |
| 20110087830 | SYSTEM, METHOD AND APPARATUS FOR EMBEDDED FIRMWARE CODE UPDATE - A wireless module is provided for wirelessly updating code to any appropriate peripheral device and may allow for wireless communication with the desired peripheral device to update an operating software code. The wireless module has the similar size, shape, and form factor as the current Memory Stick™. In one embodiment, the method of updating code to the wireless module and/or the desired peripheral devices includes providing a fail-safe code to the peripheral device, updating the peripheral device with a new code utilizing the wireless module, and executing a primary code for operation of the peripheral device. Further, the wireless module may be provided to any number of peripheral devices compatible with the Memory Stick™ removable data storage media. The wireless module is removably connected to the desired peripheral device and provides the peripheral device with a fail-safe system, method and apparatus for updating the embedded operational software code without recalling and servicing the peripheral device. | 04-14-2011 |
| 20110087831 | MEMORY SYSTEM AND METHOD OF WRITING INTO NONVOLATILE SEMICONDUCTOR MEMORY - A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block. | 04-14-2011 |
| 20110087832 | WEAR LEVELING IN STORAGE DEVICES BASED ON FLASH MEMORIES AND RELATED CIRCUIT, SYSTEM, AND METHOD - A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased. | 04-14-2011 |
| 20110093646 | PROCESSOR-BUS ATTACHED FLASH MAIN-MEMORY MODULE - A method for processing a read request identifying an address. The method includes receiving, at a module including a flash memory and a memory buffer, the read request from a requesting processor, mapping, using a coherence directory controller within the module, the address to a cache line in a cache memory associated with a remote processor, and sending a coherency message from the module to the remote processor to change a state of the cache line in the cache memory. The method further includes receiving, at the module, the cache line from the remote processor, sending, using processor bus and in response to the read request, the cache line to the requesting processor, identifying a requested page stored within the flash memory based on the address, storing a copy of the requested page in the memory buffer, and writing the cache line to the copy of the requested page. | 04-21-2011 |
| 20110093647 | System And Method For Controlling Flash Memory - A system and method for controlling flash memory is provided, so that the flash memory controller can, without using the RB signal, use control interface to read the state register of at least a flash memory with received data for operation to detect whether the flash memory has already finishing operation on the received data, and when the operation on received data is to read, the controller can execute the state data switch so that the IO of flash memory can output correct flash memory data for read, or when the operation on received data is to write, the controller can execute another data operation to save time and accelerate the data operation speed of the flash memory. | 04-21-2011 |
| 20110093648 | ACHIEVING A HIGH THROUGHPUT IN A STORAGE CACHE APPLICATION USING A FLASH SOLID STATE DISK - According to one embodiment, a method for using flash memory in a storage cache comprises receiving data to be cached in flash memory of a storage cache, at least some of the received data being received from at least one of a host system and a storage medium, selecting a block of the flash memory for receiving the data, buffering the received data until sufficient data has been received to fill the block, and overwriting existing data in the selected block with the buffered data. According to another embodiment, a method comprises receiving data, at least some of the data being from a host system and/or a storage medium, and sequentially overwriting sequential blocks of the flash memory with the received data. Other devices and methods for working with flash memory in a storage cache according to various embodiments are included and described herein. | 04-21-2011 |
| 20110093649 | METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a plurality of blocks of a Flash memory includes: providing at least one logical-to-physical block linking table within the Flash memory, wherein regarding a plurality of logical block addresses, the logical-to-physical block linking table initially stores at least one initial value falling outside a range of respective physical block addresses of the Flash memory to prevent the logical block addresses from being initially linked to the physical block addresses; and when it is required to write data belonging to a logical block address into the Flash memory, writing a physical block address of the physical block addresses into an updated version of the logical-to-physical block linking table in order to link the logical block address to the physical block address. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM; and a microprocessor. | 04-21-2011 |
| 20110093650 | NONVOLATILE MEMORY SYSTEM AND RELATED METHOD OF PRESERVING STORED DATA DURING POWER INTERRUPTION - A nonvolatile memory system comprises a temporary power supply that supplies power in the event of an unexpected power interruption. The temporary power supply provides power while metadata stored in one or more buffers is compressed and transferred to a nonvolatile memory device. | 04-21-2011 |
| 20110093651 | DATA STORAGE APPARATUS AND CONTROLLING METHOD OF THE DATA STORAGE APPARATUS - According to one embodiment, a data storage apparatus includes a first nonvolatile storage, a second nonvolatile storage and a controller. The controller is configured to control data writing and data reading for the first and second nonvolatile storage. The controller includes an allocation control module. The allocation control module is configured to allocate part of a storage area of the first nonvolatile storage to a logical address space and to allocate part or all of a storage area of the second nonvolatile storage to the logical address space in order to use the part of the storage area of the first nonvolatile storage allocated to the logical address space as storage area of substantial data, and to use part or whole of a remaining part of the storage area of the first nonvolatile storage not allocated to the logical address space as nonvolatile cache for the second nonvolatile storage. | 04-21-2011 |
| 20110093652 | MULTI-BIT-PER-CELL FLASH MEMORY DEVICE WITH NON-BIJECTIVE MAPPING - To store input data in a plurality of memory cells, a mapping function of bit sequences to physical parameter states of the cells is provided. The cells are programmed, in accordance with the mapping function, to store the input data, in a way that would store uniformly distributed data with a programming state distribution other than any native state distribution of the mapping function. To store input data in a single memory cell, a mapping function of bit sequences to states of a physical parameter of the cell, such that if uniformly distributed data were stored in a plurality of such memory cells then the states of the physical parameter of the cells would be distributed non-uniformly, is provided. The memory cell is programmed to store the input data in accordance with the mapping function. | 04-21-2011 |
| 20110093653 | MEMORY ADDRESS MANAGEMENT SYSTEMS IN A LARGE CAPACITY MULTI-LEVEL CELL (MLC) BASED FLASH MEMORY DEVICE - Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM. | 04-21-2011 |
| 20110099320 | Solid State Drive with Adjustable Drive Life and Capacity - A method for adjusting a drive life and a capacity of a solid state drive (SSD), the SSD comprising a plurality of memory devices includes determining a desired drive life for the SSD; determining a utilization for the SSD; and allocating a portion of the plurality of memory devices as available memory and a portion of the plurality of memory devices as spare memory based on the desired drive life and the utilization. An SSD with an adjustable drive life and capacity includes a plurality of memory devices; and a memory allocation module configured to: determine a desired drive life for the SSD; determine a utilization for the SSD; and allocate a portion of the plurality of memory devices as available memory and a portion of the plurality of memory devices as spare memory based on the desired drive life and the utilization. | 04-28-2011 |
| 20110099321 | ENABLING SPANNING FOR A STORAGE DEVICE - A storage device, e.g., an SSD, is configured to enable spanning for a logical block between pages of the device. In one example, a device includes a data storage module to receive data to be stored, wherein the data comprises a plurality of logical blocks, and wherein a size of the plurality of logical blocks exceeds a size of a first page of the device, and a spanning determination module to determine whether to partition one of the plurality of logical blocks into a first partition and a second partition, wherein the data storage module is configured to partition the one of the plurality of logical blocks into the first partition and the second partition and to store the first partition in the first page and the second partition in a second, different page when the spanning determination module determines to partition the one of the plurality of logical blocks. | 04-28-2011 |
| 20110099322 | DATA STORAGE DEVICE WITH INTEGRATED DNA STORAGE MEDIA - An integral digital memory storage device having a standard form factor to be received by and communicating with a computing device and having memory capability for storage of digital data. An integral multiwell DNA sample tray is carried in a body of the memory storage device for protection and exposed by manipulation of the case for receiving DNA samples. | 04-28-2011 |
| 20110099323 | NON-VOLATILE SEMICONDUCTOR MEMORY SEGREGATING SEQUENTIAL, RANDOM, AND SYSTEM DATA TO REDUCE GARBAGE COLLECTION FOR PAGE BASED MAPPING - A non-volatile semiconductor memory is disclosed comprising a memory device having a memory array including a plurality of memory segments. A plurality of sequential access write commands and random access write commands are received from a host, wherein each write command identifies at least one logical block address (LBA). The LBAs for the sequential access write commands are mapped to a plurality of the memory segments to generate sequential mapping data, and the sequential mapping data is mapped to a first one of the zones. The LBAs for the random access write commands are mapped to a plurality of the memory segments to generate random mapping data, and the random mapping data is mapped to a second one of the zones. | 04-28-2011 |
| 20110099324 | FLASH MEMORY STORAGE SYSTEM AND FLASH MEMORY CONTROLLER AND DATA PROCESSING METHOD THEREOF - A flash memory storage system including a flash memory chip, a connector, and a flash memory controller is provided. The flash memory controller configures a plurality of logical addresses and maps the logical addresses to a part of the physical addresses in the flash memory chip, and a host system uses a file system to access the logical addresses. Besides, the flash memory controller identifies a deleted logical address among the logical addresses and marks data in the physical address mapped to the deleted logical address as invalid data. Thereby, the flash memory storage system can identify data deleted by the host system in the physical addresses, so that the time for sorting data can be effectively reduced. | 04-28-2011 |
| 20110099325 | USER DEVICE AND MAPPING DATA MANAGEMENT METHOD THEREOF - In the mapping data management method, data that is being used by a host is stored in response to a power-off command from a user. The host generates a power-off notification signal to a storage device. The storage device stores mapping data of a volatile memory in a nonvolatile memory in response to the power-off notification signal. | 04-28-2011 |
| 20110099326 | FLASH MEMORY SYSTEM AND DEFRAGMENTATION METHOD - Provided is a flash memory system supporting flash defragmentation. The flash memory system includes a host and a flash storage device. In response to a flash defragmentation command by the host, the flash storage device performs flash defragmentation by grouping fragments stored in fragmented blocks of a flash memory on a flash memory management unit basis. The flash memory management unit may be a memory block or page. The flash storage device performs the flash defragmentation regardless of the arrangement order of fragmented files stored in the flash memory. | 04-28-2011 |
| 20110107009 | NON-VOLATILE MEMORY CONTROLLER DEVICE AND METHOD THEREFOR - A method of storing information at a non-volatile memory includes storing a status bit prior to storing data at the memory. A second status bit is stored after storing of the data. Because the storage of data is interleaved with the storage of the status bits, a brownout or other corrupting event during storage of the data will likely result in a failure to store the second status bit. Therefore, the first and second status bits can be compared to determine if the data was properly stored at the non-volatile memory. | 05-05-2011 |
| 20110107010 | ONE-TIME PROGRAMMABLE MEMORY DEVICE AND METHODS THEREOF - A portion of a programmable memory device is configured as a one-time programmable (OTP) memory, where in response to a write access to the memory device, a memory controller determines whether the write access is associated with a memory location designated as an OTP memory location. If so, the memory controller performs a read of the memory location, and allows the write access only if each memory cell of the memory location is in an un-programmed state. Thus, only a single write access to an OTP memory location is permitted, and subsequent write attempts are disallowed. Further, to enhance detection of programmed cells, the read of the OTP memory location is performed with a lower read voltage than a read voltage associated with a write access to a non-OTP memory location, thereby improving detection of programmed memory cells in the OTP memory location. | 05-05-2011 |
| 20110107011 | DATA DEFRAGMENTATION OF SOLID-STATE MEMORY - A method and apparatus for improving the performance of a computer system having a solid-state (flash) memory device as the main system memory. After weeks or months of frequent use, solid-state memories can become badly fragmented, and although every memory cell has basically the same access time to retrieve or to write data from or into that cell, vendors have found that self-defragging utilities within the memory device often improves overall performance. Yet if such defragging utilities are automatically run when other applications are running simultaneously, the drain on system performance can be very detrimental. To avoid the occurrence of unwanted self-defragging of these solid-state memory devices, we inhibit under some circumstances such functionality until it is deemed safe to do so. | 05-05-2011 |
| 20110107012 | NON-VOLATILE SEMICONDUCTOR MEMORY COMPRISING POWER FAIL CIRCUITRY FOR FLUSHING WRITE DATA IN RESPONSE TO A POWER FAIL SIGNAL - A non-volatile semiconductor memory is disclosed comprising a first memory device having a memory array including a plurality of memory segments, and a data register for storing write data prior to being written to one of the memory segments. A memory controller comprises a microprocessor for executing access commands received from a host. Interface circuitry generates control signals that enable the microprocessor to communicate with the first memory device. Power fail circuitry transmits a flush command to the first memory device through the interface circuitry in response to a power fail signal, wherein the first memory device responds to the flush command by transferring the write data stored in the data register to the memory segment. | 05-05-2011 |
| 20110107013 | High Throughput Flash Memory System - There is disclosed a memory system and method. The memory system may include a plurality of memory planes including two or more data memory areas, and a memory controller adapted to controlling reading, writing, and erasing of the plurality of memory planes. When any one of the data memory areas is occupied with one of a write operation and an erase operation, the controller may reconstruct data stored in the one occupied data memory area by reading parity information and data stored in the plurality of memory areas other than the one occupied data memory area. | 05-05-2011 |
| 20110107014 | MEMORY DEVICE PAGE BUFFER CONFIGURATION AND METHODS - Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time. | 05-05-2011 |
| 20110107015 | DATA WRITING METHOD FOR A FLASH MEMORY, AND FLASH MEMORY CONTROLLER AND FLASH MEMORY STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a flash memory chip having a plurality of physical blocks is provided. The method includes configuring a plurality of logical access addresses and recording address centers and address radiuses for the physical blocks. The method also includes receiving data to be written in logical access addresses, determining opened physical blocks among the physical blocks, and writing the data into the flash memory chip based on the logical access addresses, and the address centers and the address radiuses of the opened physical blocks. Accordingly, the method can effectively reduce the degree of data dispersion of each of the physical blocks, reduce the time for organizing valid data, and increase the speed for writing data. | 05-05-2011 |
| 20110107016 | SOLID STATE STORAGE SYSTEMS AND METHODS FOR FLEXIBLY CONTROLLING WEAR LEVELING - Solid-state storage systems and methods are provided for controlling a wear leveling process for uniform use of the memory cells that replaces worn memory blocks with less frequently used memory blocks. The wear leveling process is performed by changing the physical locations of the storage cells within each memory zone or plane. Reference values of target memory block erase counts and worn memory block erase counts are used for searching target memory blocks to be used as replacements. | 05-05-2011 |
| 20110107017 | Storage Apparatus and Data Access Method Thereof - A storage apparatus includes a first data section, a second data section, and a common data section. The first data section stores first data, the second data section stores second data, and the common data section stores common data. The storage apparatus stores a single copy of the common data. The common data and the first data correspond to a first memory bank. The common data and the second data correspond to a second memory bank. | 05-05-2011 |
| 20110107018 | PLURAL-PARTITIONED TYPE NONVOLATILE STORAGE DEVICE AND SYSTEM - A plural-partitioned type nonvolatile storage device which solves the problem that a memory card composed of a flash memory and a controller, when a storage area is divided into a plurality of partitions, cannot be correctly used with a conventional host apparatus incapable of recognizing plural partitions. The memory card includes, as its storage areas, a device characteristic data storage area, a division table storage area, and a device storage area, where the device storage area is partitioned into plural partitions. The memory card can have different, modes for adapting different accesses from the external host, and allows the external host to access partitions corresponding to the mode. Division information as to a dividing method for the plural partitions, and access information as to the host-accessible partitions corresponding to each individual mode are stored in the division table storage area. Plural types of device characteristic data corresponding to mode, respectively, are stored in the device characteristic data storage area. | 05-05-2011 |
| 20110113183 | Method for Managing a Non-Violate Memory and Computer Readable Medium Thereof - A method for managing a non-violate memory is provided. The non-violate memory has a number of blocks, and each block has a number of sub-blocks. The method includes a number of steps. First, a last physical address is obtained. The last physical address corresponds to a sub-block which is close to another sub-block where data is newly stored. Next, it is determined, for each sub-block of at least one block, the validity of data being stored. The at least one block is at least one neighboring block of a block containing the corresponding sub-block of the last physical address. Then, a mapping table is produced according to the step of determining the validity of data. | 05-12-2011 |
| 20110113184 | DATA BACKUP METHOD FOR A FLASH MEMORY AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data backup method for backing up data temporarily stored in a cache memory of a flash memory storage device is provided, where the flash memory storage device has a plurality of physical units. The data backup method includes logically grouping a portion of the physical units into a data area and a cache area. The data backup method also includes determining whether a trigger signal is received; and when the trigger signal is received, copying the data temporarily stored in the cache memory into the cache area. Accordingly, the data backup method can quickly write the data temporarily stored in the cache memory into the physical units, thereby preventing a time out problem which may occur in the flash memory storage device. | 05-12-2011 |
| 20110113185 | MEMORY APPARATUS AND MEMORY CONTROLLER FOR ACCESSING NON-VOLATILE MEMORY - A memory apparatus includes a non-volatile memory and a memory controller, where the memory controller is coupled to the non-volatile memory and is utilized for accessing the non-volatile memory, and the memory controller and the non-volatile memory are positioned in two independent chips, respectively. When external data is intended to be written into the non-volatile memory, the memory controller compresses the external data and stores compressed external data into the non-volatile memory. | 05-12-2011 |
| 20110113186 | REDUCING ERASE CYCLES IN AN ELECTRONIC STORAGE DEVICE THAT USES AT LEAST ONE ERASE-LIMITED MEMORY DEVICE - A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed. | 05-12-2011 |
| 20110113187 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SAME - According to one embodiment, a semiconductor device includes a NAND flash memory, an SRAM, and a controller. The NAND flash memory includes a plurality of blocks with a plurality of memory cells and a decoder which selects the blocks. The NAND flash memory is capable of erasing data in a plurality of the blocks simultaneously during a multi-block erase operation. The decoder stores bad-block information at least during a read operation and a write operation and stores information on a plurality of erase target blocks during the multi-block erase operation. The SRAM stores the information on the erase target blocks. The controller reads information on the erase target blocks from the SRAM to set the information into the decoder in a multi-block erase operation. | 05-12-2011 |
| 20110113188 | MEMORY CARD AND HOST DEVICE THEREOF - A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal. | 05-12-2011 |
| 20110119428 | Method of duplicating data to multiple random accessible storage devices - A method of duplicating data to multiple random accessible storage devices has steps of reading one segment of source data having multiple segments, continuously detecting newly-connected random accessible storage devices, duplicating same segments to all connected random accessible storage devices, stopping duplicating the source data to any random accessible storage device that has stored all segments of the source data and repeating the steps from the beginning. When duplicating the source data to all connected random accessible storage devices, same segments of the source data are written to all connected random accessible storage devices. Therefore, a single writing task is proceeded in each writing session. The source data can be written to all random accessible storage devices at high speed. Consequently, efficiency of asynchronously duplicating data to multiple random accessible storage devices is increased. | 05-19-2011 |
| 20110119429 | NONVOLATILE MEMORY CONTROLLER AND METHOD FOR WRITING DATA TO NONVOLATILE MEMORY - The invention provides a nonvolatile memory controller. In one embodiment, the nonvolatile memory controller receives new data for writing a nonvolatile memory from a host, and comprises a signature calculating circuit, a signature buffer, a signature comparison circuit, a data comparison circuit, and a nonvolatile memory interface circuit. The signature calculating circuit calculates a first signature according to the new data. The signature buffer outputs a second signature corresponding to old data stored in the nonvolatile memory, wherein the old data has the same logical address as that of the new data. The signature comparison circuit determines whether the first signature is identical to the second signature. The nonvolatile memory interface circuit writes the new data to the nonvolatile memory when the first signature is determined to be different from the second signature by the signature comparison circuit. | 05-19-2011 |
| 20110119430 | METHODS FOR MEASURING USABLE LIFESPAN AND REPLACING AN IN-SYSTEM PROGRAMMING CODE OF A MEMORY DEVICE, AND DATA STORAGE SYSEM USING THE SAME - A data storage system comprises a host and a flash memory device having a non-non-volatile memory. A controller of the flash memory device calculates an average erase count of the flash memory to obtaining a remaining period of time indicating usable lifespan of the flash memory device. The host obtains an index by comparing the average erase count with a first threshold and determines a performance capability status for the flash memory device. The performance capability status is set to a first status when the average erase count exceeds the first threshold. The host generates an indication based on the performance capability status and performs a limp function responsive to the first status. The limp function loads a predetermined in-system programming code for replacing an original one to configure a minimum number of at least some spare blocks of the flash memory reserved and used for data update operations. | 05-19-2011 |
| 20110119431 | MEMORY SYSTEM WITH READ-DISTURB SUPPRESSED AND CONTROL METHOD FOR THE SAME - According to one embodiment, a memory system includes a memory and a controller. The memory includes NAND strings. Each of the NAND strings includes memory cells. The memory cells capable of holding data. The memory writing and reading data in units of a page corresponding to a set of the memory cells and erasing data in units of a block corresponding to a set of the NAND strings. The controller controls the memory. The controller includes a holding unit and a control unit. The holding unit holds a table in which information on a check page is recorded, for each zone corresponding to a set of the blocks. The control unit references the table to calculate a read error and instructs the memory to write the data in the block including the check page to another block in the memory, if the occurrence rate exceeds a preset threshold. | 05-19-2011 |
| 20110119432 | NONVOLATILE MEMORY DEVICES HAVING IMPROVED READ PERFORMANCE RESULTING FROM DATA RANDOMIZATION DURING WRITE OPERATIONS - Memory devices include an array of non-volatile memory cells and a memory control circuit. The memory control circuit, which is electrically coupled to the array of non-volatile memory cells, includes a pseudo-random data coder/decoder circuit. This pseudo-random data coder/decoder circuit is configured to convert a first block of input data to be written into the memory device into a second block of data. This second block of data is encoded as a two-dimensional pseudo-random distribution of data values, which are more uniformly distributed relative to data values in the first block of input data. The memory control circuit is further configured to write the second block of data into the array of non-volatile memory cells during a plurality of page write operations. | 05-19-2011 |
| 20110119433 | METHOD AND APPARATUS FOR EMULATING BYTE WISE PROGRAMMABLE FUNCTIONALITY INTO SECTOR WISE ERASABLE MEMORY - A method and system for emulating a byte-wise programmable memory in a sector-wise erasable memory, where emulating a byte-wise programmable memory in a sector-wise erasable memory is based on dividing the sector-wise erasable memory in a plurality of sectors, dividing each of the sectors into several memory locations suitable to store containers, with each container having a header and a payload portion, and storing a data value relating to an application in the payload portion of one of the containers and header information identifying the application in the header in an available container. The containers can be block containers, and the data portion can have two or more payload values. The storing action can be performed in such a way that the two or more payload values in the payload portion together uniquely represent the data value. | 05-19-2011 |
| 20110119434 | System And Method For Safely Updating Thin Client Operating System Over A Network - A method for updating a thin client image includes the steps of writing a service operating system (OS) from a network device to limited capacity memory of a thin client device, writing a large part of a new image from the network to the memory of the thin client in a series of portions, without writing over the service OS, and writing a final small part of the new image over the service OS. | 05-19-2011 |
| 20110119435 | FLASH MEMORY STORAGE SYSTEM - A flash memory storage system has a plurality of flash memory devices comprising a plurality of flash memories, and a controller having an I/O processing control unit for accessing a flash memory device specified by a designated access destination in an I/O request received from an external device from among the plurality of flash memory devices. A parity group can be configured of flash memory devices having identical internal configuration. | 05-19-2011 |
| 20110119436 | FLASH MEMORY SYSTEM AND DATA WRITING METHOD THEREOF - Provided are a flash memory system and a data reading method thereof, the method including serially reading groups of data and parity codes corresponding to each of the respective groups from a page buffer; calculating the parity for each serially read group; checking for errors in each serially read group by comparing each calculated parity with a corresponding serially read parity code, respectively; and providing an output signal indicative of any comparative parity errors detected, wherein the reading of each group of data is followed by the reading of the parity code for the group, and the checking for errors in each group of data is done during the serial reading operation. | 05-19-2011 |
| 20110125953 | FLASH MEMORY ORGANIZATION FOR REDUCED FAILURE RATE - A memory system includes logic to distribute bits of a data word from a first memory across multiple pages of a flash memory. | 05-26-2011 |
| 20110125954 | DATA STORAGE METHOD FOR FLASH MEMORY, AND FLASH MEMORY CONTROLLER AND FLASH MEMORY STORAGE SYSTEM USING THE SAME - A data storage method for storing data into a flash memory chip is provided. The flash memory chip has a plurality of physical addresses, and these physical addresses include a plurality of fast physical addresses and a plurality of slow physical addresses. In the data storage method, the usage rate of the physical addresses is monitored. When the usage rate is not larger than a usage rate threshold value, only the fast physical addresses are used for storing the data into the flash memory chip. When the usage rate is larger than the usage rate threshold value, the fast physical addresses and the slow physical addresses are used for storing the data into the flash memory chip. Thereby, the speed of storing data into the flash memory chip is effectively increased. | 05-26-2011 |
| 20110125955 | FLASH STORAGE DEVICE, DATA STORAGE SYSTEM, AND DATA WRITING METHOD - The invention provides a flash storage device. In one embodiment, the flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of storage units for data storage, wherein the total capacity of each of the storage units is equal to a storage unit capacity. When the flash storage device receives a read capacity command from a host, the controller determines the size of a logical block to be a specific multiple of the storage unit capacity, and sends information about the logical block size to the host in response to the read capacity command, wherein the specific multiple is a natural number. After the host receives the information from the flash storage device, the host retrieves the logical block size from the information, and sends only write data with an amount equal to a multiple of the logical block size to the flash storage device. | 05-26-2011 |
| 20110125956 | TECHNIQUES FOR MULTI-MEMORY DEVICE LIFETIME MANAGEMENT - Techniques are provided for identifying at least one aspect associated with a lifetime of each of a plurality of memory devices. Further, data is moved between the plurality of memory devices, based on the at least one aspect. | 05-26-2011 |
| 20110125957 | System for accessing non-volatile memory - Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data. | 05-26-2011 |
| 20110125958 | SEMICONDUCTOR MEMORY CARD ACCESS APPARATUS, A COMPUTER-READABLE RECORDING MEDIUM, AN INITIALIZATION METHOD, AND A SEMICONDUCTOR MEMORY CARD - A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster. | 05-26-2011 |
| 20110125959 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase operation to a portion of a NAND flash memory chip. In the event it is determined to change the value of the voltage threshold, the value of the voltage threshold is changed and the changed value of the voltage threshold and an identifier associated with the portion of the NAND flash memory chip is stored. | 05-26-2011 |
| 20110131364 | REPROGRAMMING A NON-VOLATILE SOLID STATE MEMORY SYSTEM - A non-volatile memory system ( | 06-02-2011 |
| 20110131365 | Data Storage System and Method - A data storage system and method are disclosed. The data storage system includes a first and a second memory and a memory control unit. The first memory is non-volatile, and the second memory is designed to store dynamic information of the first memory. The memory control unit includes a snapshot module, a recording module and a power-off recovery module, and is operative to handle the data loss of the second memory when an unexpected power-off occurs. When the power of the system is recovered, an initial address stored in the first memory by the snapshot module and link information and updating information recorded in the first memory by the recording module are obtained by the power-off recovery module to recovery the second memory. | 06-02-2011 |
| 20110131366 | MEMORY MANAGEMENT UNIT AND MEMORY MANAGEMENT METHOD - According to one embodiment, a memory management unit which controls a first memory as a nonvolatile memory and a second memory as a volatile memory, the memory management unit includes, judging whether data in the first memory desired to be accessed is stored in the second memory, setting an error flag to issue error data when the data is not stored in the second memory, and reading, into a free space of the second memory, the data to be accessed in the first memory. | 06-02-2011 |
| 20110131367 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE, AND WEAR LEVELING METHOD FOR NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a memory core and a controller for controlling the wear level of a memory block in the nonvolatile memory device. The controller determines the wear level of a memory block by obtaining data of an actual wear level from a charge measurement cell of a selected region of the memory cell, and stores the wear level of the selected region in an erase count table. | 06-02-2011 |
| 20110131368 | METHOD AND APPARATUS FOR MANAGING ERASE COUNT OF MEMORY DEVICE - A non-volatile memory device having a hidden cell located separate from data storage cells, and a method of effectively managing an erase count of the non-volatile memory device. The method includes preparing the non-volatile memory device that includes a hidden cell located separate from data storage cells and is not accessible to users of the data storage cells, and increasing an erase count stored in an erase count storing region of the hidden cell corresponding to at least one erased data storage cell when the at least one data storage cell is erased. | 06-02-2011 |
| 20110131369 | LOGIC DEVICE - A logic device for communicating with a memory package with a first protocol, communicating with a memory controller with a second protocol, and for performing a protocol conversion between the first and the second protocol. | 06-02-2011 |
| 20110138103 | INTRA-BLOCK MEMORY WEAR LEVELING - A method for intra-block wear leveling within solid-state memory subjected to wear, having a plurality of memory cells includes the step of writing to at least certain ones of the plurality of memory cells, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level. For example, if a behavior of at least some of the plurality of memory cells is not characterized, then the method may comprise characterizing a behavior of at least some of the plurality of memory cells and writing to at least certain ones of the plurality of memory cells, based on the characterized behavior, and in a non-uniform manner. | 06-09-2011 |
| 20110138104 | MULTI-WRITE CODING OF NON-VOLATILE MEMORIES - Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code such that the first codeword encodes the write data and is consistent with a target set of distributions of electrical charge levels in the memory page; and writing the first codeword to the memory page. If the memory page is in the previously written state: selecting a coset from a linear code such that the coset encodes the write data and includes one or more words that are consistent with previously written content of the memory page; selecting a subsequent codeword from the one or more words in the coset; and writing the subsequent codeword to the memory page. | 06-09-2011 |
| 20110138105 | NON-VOLATILE MEMORIES WITH ENHANCED WRITE PERFORMANCE AND ENDURANCE - Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate. | 06-09-2011 |
| 20110138106 | EXTENDING SSD LIFETIME USING HYBRID STORAGE - A hybrid storage device uses a write cache such as a hard disk drive, for example, to cache data to a solid state drive (SSD). Data is logged sequentially to the write cache and later migrated to the SSD. The SSD is a primary storage that stores data permanently. The write cache is a persistent durable cache that may store data of disk write operations temporarily in a log structured fashion. A migration policy may be used to determine how long to cache the data in the write cache before migrating the data to the SDD. The migration policy may be implemented using one or more migration triggers that cause the contents of the write cache to be flushed to the SSD. Migration triggers may include a timeout trigger, a read threshold trigger, and a migration size trigger, for example. | 06-09-2011 |
| 20110138107 | USB NON-VOLATILE MEMORY SYSTEM FOR AN ELECTRONIC ENGINE CONTROLLER - An electronic engine controller has a processor, a data controller, and a non-volatile memory. During an engine operation, power is supplied to the processor, data controller, and non-volatile memory from an engine power source. Sensor data is received at the processor which supplies the sensor data to the data controller. The data controller stores the sensor data in the non-volatile memory. During data retrieval, power is supplied to the data controller and the non-volatile memory from a USB communications channel. The data controller retrieves the saved sensor data from the non-volatile memory and provides it to the USB communications channel. | 06-09-2011 |
| 20110138108 | METHOD OF ACTIVE FLASH MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method of active Flash management is provided. The method is applied to a controller of a memory device, where the controller is utilized for accessing a Flash memory in the memory device, and the Flash memory includes a plurality of blocks. The method includes: extracting high level information of a file system of the Flash memory from contents stored in the Flash memory; and according to the high level information, managing operations that the controller performs on the Flash memory, in order to optimize at least one portion of the operations. An associated memory device and the controller thereof are further provided. | 06-09-2011 |
| 20110138109 | METHOD FOR WEAR-LEVELING AND APPARATUS THEREOF - A method for Wear-Leveling includes: utilizing a comparison circuit to compare an average erase count with an erase count of a first data block; and utilizing a first free block as a replacement for storing data content of the first data block so as to make the first data block become a free block when the erase count of the first data block is smaller than the average erase count. | 06-09-2011 |
| 20110138110 | METHOD AND CONTROL UNIT FOR PERFORMING STORAGE MANAGEMENT UPON STORAGE APPARATUS AND RELATED STORAGE APPARATUS - A storage apparatus has a first storage unit and a second storage unit. A method for performing storage management upon the storage apparatus includes: storing an input data into the first storage unit; and, while the input data is being stored into the first storage unit, checking whether the input data is continuous, wherein a portion of the input data which is not stored into the first storage unit yet will be stored into the first storage unit if the input data is found to be continuous, and the portion of the input data which is not stored into the first storage unit yet will be stored into the second storage unit if the input data is found to not be continuous. | 06-09-2011 |
| 20110138111 | FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING SAME - A flash memory device comprises a memory cell array comprising memory cells arranged in rows and columns. A first page of data is programmed in selected memory cells of the memory cell array, and a second page of data is subsequently programmed in the selected memory cells. The first page of data is programmed using a program voltage having a first start value, and the second page of data is programmed using a program voltage having a second start value determined by a programming characteristic of the selected memory cells. | 06-09-2011 |
| 20110138112 | Virtualization of Storage Devices - Systems and techniques relating to storage technologies are described. A described technique includes operating drives such as a solid state drive (SSD) and a disk drive, where the SSD and the disk drive are virtualized as a single logical drive having a logical address space, where the logical drive maps logical block addresses to the SSD and to the disk drive. The technique includes determining, based on a file to be written to the logical drive, a target logical address that corresponds to one of the SSD and the disk drive, and writing the file to the logical drive at the target logical address to effect storage on one of the SSD and the disk drive. | 06-09-2011 |
| 20110138113 | RAID STORAGE SYSTEMS HAVING ARRAYS OF SOLID-STATE DRIVES AND METHODS OF OPERATION - RAID storage systems and methods adapted to enable the use of NAND flash-based solid-state drives. The RAID storage system includes an array of solid-state drives and a controller operating to combine the solid-state drives into a logical unit. The controller utilizes data striping to form data stripe sets comprising data (stripe) blocks that are written to individual drives of the array, utilizes distributed parity to write parity data of the data stripe sets to individual drives of the array, and writes the data blocks and the parity data to different individual drives of the array. The RAID storage system detects the number of data blocks of at least one of the data stripe sets and then, depending on the number of data blocks detected, may invert bit values of the parity data or add a dummy data value of “1” to the parity value. | 06-09-2011 |
| 20110138114 | Methods and Apparatus For Interfacing Between a Flash Memory Controller and a Flash Memory Array - Methods and apparatus are provided for interfacing between a flash memory controller and a flash memory array. The interface comprises a communication channel between the flash memory controller and the flash memory array, wherein the communication channel carries data for a target cell in the flash memory array on a first edge of a clock signal and wherein the communication channel carries additional information for the target cell on a second edge of the clock signal. For an exemplary write access, the additional information comprises, for example, information about one or more aggressor cells associated with the target cell. For an exemplary read access, the additional information comprises, for example, soft information for the data for the target cell transmitted on the first edge. | 06-09-2011 |
| 20110138115 | SOLID STATE MEMORY (SSM), COMPUTER SYSTEM INCLUDING AN SSM, AND METHOD OF OPERATING AN SSM - In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer. | 06-09-2011 |
| 20110138116 | Direct-attached/network-attached Storage Device - A multi-port data storage device that can be used simultaneously by both a direct-attached device and a network-attached device, comprising a hard disk drive (HDD), a DAS port, an NAS port, and a controller for controlling access to the HDD by the DAS port and the NAS port. | 06-09-2011 |
| 20110138117 | MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, ACCESSING DEVICE, NONVOLATILE STORAGE SYSTEM, AND METHOD AND PROGRAM FOR WRITING DATA - A digital still camera performs temporary high-speed writing when capturing a large number of images in a short time. Lengthy processing for erased block allocation or copying performed inside a nonvolatile storage device may disable the captured images to be written completely (may cause some frames to drop). A nonvolatile storage system includes an access device ( | 06-09-2011 |
| 20110145472 | METHOD FOR ADDRESS SPACE LAYOUT RANDOMIZATION IN EXECUTE-IN-PLACE CODE - A method for dynamically (i.e., upon boot) rewriting, in a failure resistant manner, of part of, or the entirety of, the flash memory for a device allows for a changing of location for logical blocks of execute-in-place code. Conveniently, the rewriting results in a randomization, of varying degree, of the address space layout upon each boot up cycle. | 06-16-2011 |
| 20110145473 | Flash Memory Cache for Data Storage Device - A storage device made up of multiple storage media is configured such that one such media serves as a cache for data stored on another of such media. The device includes a controller configured to manage the cache by consolidating information concerning obsolete data stored in the cache with information concerning data no longer desired to be stored in the cache, and erase segments of the cache containing one or more of the blocks of obsolete data and the blocks of data that are no longer desired to be stored in the cache to produce reclaimed segments of the cache. | 06-16-2011 |
| 20110145474 | Efficient Use Of Flash Memory In Flash Drives - A data storage device having non-volatile solid state memory permits efficient access by permitting multiple pending commands from a host device. A controller in the data storage device stores information about each command from the host device, and determines which stored command, if any, is presently able to be performed based on the portion of the non-volatile memory and the type of access of the command. The data storage device provides reduced access delays, improves read/write throughput, and avoids the cost of additional memory in the data storage device, by allowing accesses to idle portions of memory to proceed, and by signaling the host device when the data storage device is able to accept data to be written to portions of the non-volatile memory already active due to a previous command. | 06-16-2011 |
| 20110145475 | REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS - Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full. | 06-16-2011 |
| 20110145476 | Persistent Content in Nonvolatile Memory - Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations. Persistent storage may be maintained by systems with or without memory management units. | 06-16-2011 |
| 20110145477 | FLASH TRANSLATION LAYER USING PHASE CHANGE MEMORY - A FLASH translation layer (FTL) includes a translation table that is maintained in non-FLASH memory. The translation table maps logical addresses to physical addresses and may be maintained in phase change memory (PCM). A bad block table (BBT) may also be maintained in non-FLASH memory. | 06-16-2011 |
| 20110145478 | METHOD TO IMPROVE A SOLID STATE DISK PERFORMANCE BY USING A PROGRAMMABLE BUS ARBITER - A method to improve a solid state disk performance by using a programmable bus arbiter is generally presented. In this regard, in one embodiment, a method is introduced comprising delaying a request from a solid state drive for access to an interface for a time to allow a host to access the interface to transmit a command to the solid state drive. Other embodiments are described and claimed. | 06-16-2011 |
| 20110145479 | EFFICIENT USE OF HYBRID MEDIA IN CACHE ARCHITECTURES - A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system. | 06-16-2011 |
| 20110145480 | FLASH MEMORY STORAGE SYSTEM FOR SIMULATING REWRITABLE DISC DEVICE, FLASH MEMORY CONTROLLER, COMPUTER SYSTEM, AND METHOD THEREOF - A flash memory storage system including a flash memory chip, a connector, and a controller is provided. The flash memory chip has a plurality of physical blocks. The connector is configured to couple to a host system. The controller is coupled to the flash memory chip and the connector. The controller configures a plurality of logical blocks and maps the logical blocks to a portion of the physical blocks. In addition, the controller identifies rewritable disc commands from the host system and writes data from the host system into the physical blocks mapped to the logical blocks according to the rewritable disc commands. Thereby, a rewritable disc device is simulated by using the flash memory storage system. | 06-16-2011 |
| 20110145481 | FLASH MEMORY MANAGEMENT METHOD AND FLASH MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME - A flash memory management method for managing a plurality of physical units of a flash memory chip is provided. The flash memory management method includes grouping a portion of the physical units into a data area and a spare area; configuring a plurality of logical units and setting mapping relationships between the logical units and the physical units of the data area. The flash memory management method further includes receiving data and writing the data into the physical unit mapped to a second logical unit among the logical units, and the data belongs to a first logical unit among logical units. Accordingly, the flash memory management method can effectively reduce the number of times for organizing valid data, thereby reducing the time for executing a host write-in command. | 06-16-2011 |
| 20110145482 | BLOCK MANAGEMENT METHOD FOR FLASH MEMORY, AND FLASH MEMORY CONTROLLER AND FLASH MEMORY STORAGE DEVICE USING THE SAME - A block management method for managing blocks of a flash memory storage device is provided. The flash memory storage device includes a flash memory controller. The block management method includes the following steps. At least a part of the blocks is grouped into a first partition and a second partition. Whether an authentication code exists is determined. When the authentication code exists, the blocks belonging to the first partition are provided for a host system to access, so the host system displays the first partition and hides the second partition. An authentication information is received from the host system. Whether the authentication information and the authentication code are identical is authenticated. When the authentication information and the authentication code are identical, the blocks belonging to the second partition are provided for the host system to access, so the host system displays the second partition and hides the first partition. | 06-16-2011 |
| 20110145483 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROCESSING DATA FOR ERASE OPERATION OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory blocks, and erase flag storage block storing erase flag information to indicate erase states of the plurality of memory blocks. The erase flag information can be used to monitor completion of erase operations of the memory blocks and to update erase count information of the memory blocks. | 06-16-2011 |
| 20110145484 | Exhaustive Parameter Search Algorithm for Interface with Nand Flash Memory - The Exhaustive Parameter Search (EPS) algorithm of this invention enables communicating devices to access to a large variety of NAND Flash memories. The EPS algorithm exploits the fact that the parameters needed for successful initial communication with NAND Flash memory (block Size and page Size) have only few possible values. The EPS algorithm tries all possible values to find a magic number stored in the NAND Flash memory. The correct parameters for the particular NAND Flash memory are read after detection of the magic number. This ensures that accurate parameters are used after successful detection of the magic number detection. The OEM must write the known parameters of the NAND Flash memory in a predetermined location following the magic number. | 06-16-2011 |
| 20110145485 | METHOD FOR MANAGING ADDRESS MAPPING TABLE AND A MEMORY DEVICE USING THE METHOD - An address mapping table includes arrays each being allocated to a logical address and in which a physical address mapping the logical address is stored. In the case where the physical address mapped to the logical address is changed, a value of a difference between a pre-changed physical address and a physical address to be changed is stored in the address mapping table. When the logical address is mapped to the physical address, the mapped physical address is calculated by adding up the logical address and values stored in the arrays allocated to the logical address. The address mapping table is managed to decrease the number of erase counts of a memory device in which the address mapping table is stored. | 06-16-2011 |
| 20110145486 | MEMORY MANAGEMENT DEVICE AND METHOD - According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data. | 06-16-2011 |
| 20110145487 | Methods and Apparatus for Soft Demapping and Intercell Interference Mitigation in Flash Memories - Methods and apparatus are provided for soft demapping and intercell interference mitigation in flash memories. In one variation, a target cell in a flash memory device capable of storing at least two data levels, s, per cell is read by obtaining a measured read value, r, for at least one target cell in the flash memory; obtaining a value, h, representing data stored for at least one aggressor cell in the flash memory; selecting one or more probability density functions based on a pattern of values stored in at least a portion of the flash memory, wherein the probability density functions comprises pattern-dependent disturbance of one or more aggressor cells on the at least one target cell in the flash memory; evaluating at least one selected probability density function based on the measured read value, r; and computing one or more log likelihood ratios based on a result of the evaluating step. | 06-16-2011 |
| 20110145488 | FLASH MEMORY MODULE, STORAGE APPARATUS USING FLASH MEMORY MODULE AS RECORDING MEDIUM AND ADDRESS TRANSLATION TABLE VERIFICATION METHOD FOR FLASH MEMORY MODULE - A purpose of the invention is to immediately return the operation in a flash memory module from low power consumption mode to regular mode. A flash memory controller having memory that stores an address translation table for translating between a logical page address and a physical page address in the flash memory chip controls regular mode and low power consumption mode of operating at lower power consumption than in regular mode by halting operation, or decreasing power supply voltage or lowering operating frequency. A flash memory module having the flash memory controller verifies data in the address translation table while low power consumption mode is set. | 06-16-2011 |
| 20110145489 | HYBRID STORAGE DEVICE - A hybrid storage device comprises both solid-state disk (SDD) and at least one hard disk drive (HDD). The hybrid storage device has at least two operational modes: concatenation and safe. According to one aspect, the total capacity of hybrid storage device is the sum of SSD and at least one HDD in a concatenation or big mode, while the total capacity is the capacity of the HDD in a safe mode. | 06-16-2011 |
| 20110145490 | DEVICE AND METHOD OF CONTROLLING FLASH MEMORY - Disclosed is a flash memory controlling method and controlling device. The flash memory controlling method including calculating a cost for each of available block recycling schemes based on a multi-block erase function when the multi-block erase function is supported, the multi-block erase function being a function that simultaneously erases data stored in a plurality of blocks of a flash memory and selecting at least one scheme from among the available block recycling schemes based on the calculated cost, and managing at least one block using the at least one method selected from among the available block recycling schemes. | 06-16-2011 |
| 20110153910 | Flash Memory-Interface - Flash-type memory access and control is facilitated (e.g., as random-access memory). According to an example embodiment, an interface communicates with and controls a flash memory circuit over a peripheral interface bus. The interface uses a FIFO buffer coupled to receive data from and store data for the flash memory circuit and to provide access to the stored data. An interface controller communicates with the flash memory circuit via the peripheral interface bus to initialize the flash memory circuit and to access data thereto, in response to requests from a processor. In some applications, the flash memory circuit is initialized by sending commands to it. The interface may be placed into a read-only mode in which data in the flash memory is accessed as part of main (computer) processor memory, using the FIFO to buffer data from the flash. | 06-23-2011 |
| 20110153911 | METHOD AND SYSTEM FOR ACHIEVING DIE PARALLELISM THROUGH BLOCK INTERLEAVING - A method and system for achieving die parallelism through block interleaving includes non-volatile memory having a multiple non-volatile memory dies, where each die has a cache storage area and a main storage area. A controller is configured to receive data and write sequentially addressed data to the cache storage area of a first die. The controller, after writing sequentially addressed data to the cache storage area of the first die equal to a block of the main storage area of the first die, writes additional data to a cache storage area of a next die until sequentially addressed data is written into the cache area of the next die equal to a block of the main storage area. The cache storage area may be copied to the main storage area on the first die while the cache storage area is written to on the next die. | 06-23-2011 |
| 20110153912 | Maintaining Updates of Multi-Level Non-Volatile Memory in Binary Non-Volatile Memory - A method of operating a memory system is presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first portion, where data is stored in a binary format, and a second portion, where data is stored in a multi-state format. The controller manages the transfer of data to and from the memory system and the storage of data on the non-volatile memory circuit. The method includes receiving a first set of data and storing this first set of data in a first location in the second portion of the non-volatile memory circuit. The memory system subsequently receives updated data for a first subset of the first data set. The updated data is stored in a second location in the first portion of the non-volatile memory circuit, where the controller maintains a logical correspondence between the second location and the first subset of the first set of data. | 06-23-2011 |
| 20110153913 | Non-Volatile Memory with Multi-Gear Control Using On-Chip Folding of Data - A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host. | 06-23-2011 |
| 20110153914 | REPURPOSING NAND READY/BUSY PIN AS COMPLETION INTERRUPT - A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed. | 06-23-2011 |
| 20110153915 | READ PREAMBLE FOR DATA CAPTURE OPTIMIZATION - Systems and/or methods are provided that facilitate data capture optimization for devices accessing memories via a bus. In an aspect, a memory can output a read preamble prior to pushing data onto a bus. The read preamble can be a known sequence of one or more bits. A host device accessing the memory via the bus can analyze the read preamble and, particularly, timing characteristics of the read preamble. The timing characteristics can be utilized to identify an optimal capture point within a window of data validity. | 06-23-2011 |
| 20110153916 | HYBRID MEMORY ARCHITECTURES - Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system. | 06-23-2011 |
| 20110153917 | STORAGE APPARATUS AND ITS CONTROL METHOD - Proposed are a storage apparatus and its control method capable of performing power saving operations while covering the shortcomings of a flash memory such as the life being short and much time being required for rewriting data. This storage apparatus manages the storage areas provided by each of multiple nonvolatile memories as a pool, provides a virtual volume to a host computer, dynamically allocates the storage area from a virtual pool to the virtual volume according to a data write request from the host computer for writing data into the virtual volume, and places the data in the allocated storage area. In addition, the storage apparatus centralizes the placement destination of data from the host computer to a storage area provided by certain nonvolatile memories and stop the power supply to the nonvolatile memories that are unused, monitors the data rewrite count and/or access frequency to storage areas provided by the nonvolatile memories that are active, migrates data to another storage area if the data rewrite count increases, and distributes the data placement destination if the access frequency becomes excessive. | 06-23-2011 |
| 20110153918 | DATA WRITING METHOD AND DATA STORAGE DEVICE - The invention provides a data writing method for a flash memory. First, a write command, a write address, and write data are received from a host. When a total number of block pairs in the flash memory is equal to a threshold value, and execution of the write command increases the total number of block pairs, the write data is written to a data buffer block of the flash memory, and the write address is stored in an address storage table. A target block pair comprising a target mother block and a target child block is then selected from the block pairs for integration. The target mother block and the target child block are integrated into an integrated block during receiving intervals of a plurality of subsequent write commands. Finally, the write command is executed according to the write data stored in the data buffer block and the write address stored in the address storage table. | 06-23-2011 |
| 20110153919 | DEVICE, SYSTEM, AND METHOD FOR REDUCING PROGRAM/READ DISTURB IN FLASH ARRAYS - A method, device and computer readable medium for programming a nonvolatile memory block. The method may include programming information, by a memory controller, to the nonvolatile memory block by performing a sequence of programming phases of descending bit significances. The device may include a nonvolatile memory block; and a memory controller that may be configured to determine a bit significance level of the nonvolatile memory block; program the nonvolatile memory block by performing at least one programming phase; and program the nonvolatile memory block to an erase value that may be higher than the pre-erase value; wherein the erase value and the pre-erase value may be selected based on the bit significance level of the nonvolatile memory block. The method may include packing three single level cell (SLC) nonvolatile memory blocks to one three-bit per cell nonvolatile memory block in order of the three SLC bit significances. | 06-23-2011 |
| 20110153920 | ELECTRONIC APPARATUS OF RECORDING DATA USING NON-VOLATILE MEMORY - An electronic apparatus for recording data using a non-volatile memory is provided. The electronic apparatus includes a non-volatile memory and a controller. The non-volatile memory stores a plurality of sets of playing information of the electronic apparatus. The controller is coupled to the non-volatile memory for receiving an input data and transforming a data structure of the input data into a bitmapping data structure. The controller includes a bitmapping module that is capable of transforming the input data into data having at least one bit but less than one byte in a bitmapping manner. | 06-23-2011 |
| 20110153921 | System Embedding Plural Controller Sharing Nonvolatile Memory - An embedded memory card system includes a first CPU, a second CPU, a nonvolatile memory storing data, and a device busy state machine selecting one of the first CPU and the second CPU to access the nonvolatile memory. The nonvolatile memory is accessed by the one of the first CPU and the second CPU selected by the device busy state machine. | 06-23-2011 |
| 20110153922 | NON-VOLATILE MEMORY DEVICE HAVING ASSIGNABLE NETWORK IDENTIFICATION - Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller. | 06-23-2011 |
| 20110161551 | VIRTUAL AND HIDDEN SERVICE PARTITION AND DYNAMIC ENHANCED THIRD PARTY DATA STORE - A system reserves and manages a hidden service partition through components of the hardware platform of a computing device. The hidden partition is not accessible by way of a host operating system on the computing device. A hardware platform controller provisions a portion of nonvolatile storage through configuration settings of the hardware platform controller. When the host system requests settings related to storage in the system, the request is routed through the interfaces of the hardware platform, and the hardware platform controller reports in accordance with the configuration settings, hiding the service partition. The hidden partition is dynamically modifiable through secure remote access to the hardware platform controller, not through the host system such as operating system or BIOS. | 06-30-2011 |
| 20110161552 | Command Tracking for Direct Access Block Storage Devices - Described embodiments provide tracking and processing of commands received by a storage device. For each received command, the storage device determines one or more requested logical block addresses (LBAs), including a starting LBA and a length of one or more LBAs of the received command. The storage device determines whether command reordering is restricted. If command reordering is not restricted, the storage device processes the received commands. Otherwise, if command reordering is restricted, the storage device conflict checks each received command. If no conflict is detected, the storage device tracks and processes the received command. Otherwise, if a conflict is detected, the storage device queues the received command. | 06-30-2011 |
| 20110161553 | MEMORY DEVICE WEAR-LEVELING TECHNIQUES - The wear-leveling techniques include discovering a persistent state of one or more memory devices, or building and caching persistent state parameters for each logical unit of a given memory device if a persistent state is not discovered for a given memory device. The techniques may also include processing memory access commands utilizing the cached persistent state parameters. When processing memory access commands, the logical block address and length parameter of a logical address of a command may be translated to a plurality of physical addresses for accessing one or more memory devices, each physical address includes a device address, a logical unit address, a block address, and a page address, wherein the block address includes one or more interleaved address bits. | 06-30-2011 |
| 20110161554 | Method and Controller for Performing a Sequence of Commands - The embodiments described herein provide a method and controller for performing a sequence of commands. In one embodiment, a controller receives a command from a host to perform a memory operation in a flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands. The controller analyzes the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands. If the at least one bit indicates that the command is a stand-alone command, the controller performs the command. If the at least one bit indicates that the command is part of a sequence of commands, the controller performs the command as part of the sequence of commands. | 06-30-2011 |
| 20110161555 | DYNAMIC DATA FLOW MANAGEMENT IN A MULTIPLE CACHE ARCHITECTURE - The disclosure is related to systems and methods of dynamic dataflow in a multiple cache architecture. In an embodiment, a system having a data storage device with a multiple cache architecture may detect at least one attribute affecting a data storage workload or data storage performance. The system may select at least one of a plurality of data flow schemes based on the at least one attribute, which may be done to optimize the data storage workload for various conditions. In another embodiment, a data storage controller may automatically and dynamically select one of multiple data flow schemes within a data storage device having a multiple cache architecture. The data storage controller may monitor attributes to determine which data flow scheme to select for various workloads of the data storage device. | 06-30-2011 |
| 20110161556 | SYSTEMS AND METHODS FOR STORING DATA IN A MULTI-LEVEL CELL SOLID STATE STORAGE DEVICE - This disclosure is related to systems and methods for storing data in multi-level cell solid state storage devices, such as Flash memory devices. In one example, a multi-level cell memory array has programmable pages, a first page having a first programming time, and a second page having a second programming time that is different than the first programming time. In one embodiment, the first programming time is faster than the second programming time. Further, a controller coupled to the multi-level cell memory array may be configured to select the first page to store the data when a priority level of a write operation indicates a first priority level and select the second page to store the data when the priority level indicates a second priority level. | 06-30-2011 |
| 20110161557 | DISTRIBUTED MEDIA CACHE FOR DATA STORAGE SYSTEMS - This disclosure is related to distributed media cache for data storage systems, such as disc drives, flash devices, or hybrid devices. In one example, a data storage device comprises a data storage medium and a controller adapted to selectively divide a media cache into a plurality of physically separate media cache portions on the data storage medium based on a physical attribute of the data storage medium and to store data received from a host system into the media cache portions. | 06-30-2011 |
| 20110161558 | RECORD SORTING - A method, computer program product, and computing system for record sorting is described. The method may comprise splitting an incoming record into a separate key block and payload block. The method may further comprise storing the key block in a first memory. The method may also comprise assigning the payload block an address in a second memory at the beginning of a sort. Moreover, the method may store, with the key block in the first memory, the address of the payload block in the second memory. Additionally, the method may store the payload block at the address in the second memory. | 06-30-2011 |
| 20110161559 | PHYSICAL COMPRESSION OF DATA WITH FLAT OR SYSTEMATIC PATTERN - Systems and methods are disclosed to improve the performance of a memory system by freeing up physical memory areas that correspond to logical block address ranges that have repeated data patterns. A controller detects data patterns in incoming data. When a data pattern is detected, the data is not written to non-volatile storage area. Rather, the logical block address range of the data is marked in a data structure as having pattern data. The pattern may also be recorded in the data structure as a pattern descriptor. Because the data having the data pattern is not written to the non-volatile storage area, the freed up corresponding physical memory area may be utilized by the memory system for other purposes, thereby improving the overall performance and endurance of the memory system. | 06-30-2011 |
| 20110161560 | ERASE COMMAND CACHING TO IMPROVE ERASE PERFORMANCE ON FLASH MEMORY - Systems and methods are disclosed to reduce the number of partial logical groups that are erased by writing erase patterns to memory in a non-volatile memory system. When a non-aligned erase command is received, the logical addresses of data associated with the erase command may be marked as erased. If the logical group corresponds to the size of a physical metablock, the controller may also issue a physical erase command for complete logical groups within the erase command. For those parts of the erase command that encompass only partial logical groups, the ranges of the logical block addresses marked for erasure are stored. As subsequent erase commands are received the address ranges of the erase commands are added to the previously stored address ranges. When a set of erase commands spans an entire logical group, the logical group is marked for physical erasure in its entirety. | 06-30-2011 |
| 20110161561 | VIRTUALIZATION OF CHIP ENABLES - Virtual chip enable techniques perform memory access operations on virtual chip enables rather than physical chip enables. Each virtual chip enable is a construct that includes attributes that correspond to a unique physical or logical memory device. | 06-30-2011 |
| 20110161562 | REGION-BASED MANAGEMENT METHOD OF NON-VOLATILE MEMORY - A region-based management method of a non-volatile memory is provided. In the region-based management method, the storage space of all chips in the non-volatile memory is divided into physical regions, physical block sets, and physical page sets, and a logical space is divided into virtual regions, virtual blocks, and virtual pages. In the non-volatile memory, each physical block set is the smallest unit of space allocation and garbage collection, and each physical page set is the smallest unit of data access. The region-based management method includes a three-level address translation architecture for converting logical block addresses into physical block addresses. | 06-30-2011 |
| 20110161563 | BLOCK MANAGEMENT METHOD OF A NON-VOLATILE MEMORY - A block management method applicable to a non-volatile memory storage system is provided. The non-volatile memory storage system includes a plurality of chips. Each chip includes a plurality of physical blocks. The physical blocks form a plurality of physical block sets. Each logical block in a logical space corresponds to at most two physical block sets. In the block management method, when a logical block corresponds to two physical block sets filled with data and more data is to be written, a free physical block set is allocated for storing the data. Then, one of the two physical block sets corresponding to the logical block is selected according to a predetermined criterion. The valid data in the selected physical block set is copied into the free physical block set. Next, the selected physical block set is erased and collected to the pool of free physical block sets. | 06-30-2011 |
| 20110161564 | BLOCK MANAGEMENT AND DATA WRITING METHOD, AND FLASH MEMORY STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for managing a plurality of physical blocks is provided. The method includes grouping the physical blocks into a plurality of physical units, grouping a portion of the physical units into a data area and a spare area, configuring a plurality of logical units, and grouping the logical units into a plurality of logical unit groups and configuring another portion of the physical units as a plurality of global random physical units corresponding to the logical unit groups, wherein each of the global random physical units corresponds to one of the logical unit groups. The method further includes getting the physical units from the spare area as global random substitute physical units of the global random physical units. Accordingly, the method can store data in the global random physical units or the global random substitute physical units, thereby reducing the time for executing a host write command. | 06-30-2011 |
| 20110161565 | FLASH MEMORY STORAGE SYSTEM AND CONTROLLER AND DATA WRITING METHOD THEREOF - A flash memory storage system having a flash memory controller and a flash memory chip is provided. The flash memory controller configures a second physical unit of the flash memory chip as a midway cache physical unit corresponding to a first physical unit and temporarily stores first data corresponding to a first host write command and second data corresponding to a second host write command in the midway cache physical unit, wherein the first and second data corresponding to slow physical addresses of the first physical unit. Then, the flash memory controller synchronously copies the first and second data from the midway cache physical unit into the first physical unit, thereby shortening time for writing data into the flash memory chip. | 06-30-2011 |
| 20110161566 | WRITE TIMEOUT CONTROL METHODS FOR FLASH MEMORY AND MEMORY DEVICES USING THE SAME - A write timeout control method for a flash memory having a plurality of spare blocks and data blocks including a plurality of mother blocks is disclosed. The method includes the steps of: receiving a write command and a starting logical block address; determining an update mode according to a target mother block linked to the starting logical block address; determining whether a pre-clean operation is performed on a first mother block; if so, performing a post-clean operation on the first mother block during a first time period; re-configuring the first mother block as a spare block; performing a programming process to write data o |
