| Entries |
| Document | Title | Date |
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| 20080320203 | Memory Management in a Computing Device - A computing device incorporating memory such as mobile SDRAM, which is capable of conserving energy by being operated in a low-power self-refresh mode, is enabled to identify those regions of memory which are allocated but inactive. These regions are collected into specific banks of memory so as to create banks of memory containing only inactive data and which can then be placed in self-refresh. This reduces the power consumed by the computing device, and improves the energy efficiency of the device. | 12-25-2008 |
| 20090043943 | METHOD AND APPARATUS OF MULTIPLE ABBREVIATIONS OF INTERLEAVED ADDRESSING OF PAGED MEMORIES AND INTELLIGENT MEMORY BANKS THEREFOR - An interleaved addressing technique for addressing a plurality of memory banks ( | 02-12-2009 |
| 20090049227 | AVOIDING FAILURE OF AN INITIAL PROGRAM LOAD IN A LOGICAL PARTITION OF A DATA STORAGE SYSTEM - An initial program load (IPL) of a logical partition (LPAR) is managed by establishing a logical path to the LPAR from a storage controller. When a notice is received by the storage controller from the LPAR that the IPL has commenced, the LPAR address is stored in a data structure. After the storage controller initiates a pack change state interrupt, the stored address is compared with the addresses in a list of all LPARS to which the interrupt is directed. If the list of addresses includes the stored address, the stored address is removed from the list. Thus, the pack change state interrupt is transmitted only to the addresses in the list, leaving the LPAR to complete the IPL without interruption. After the storage controller receives a notice from the LPAR that the IPL has completed, the address of the LPAR is removed from the data structure. | 02-19-2009 |
| 20090049228 | AVOIDING FAILURE OF AN INITIAL PROGRAM LOAD IN A LOGICAL PARTITION OF A DATA STORAGE SYSTEM - An initial program load (IPL) of a logical partition (LPAR) is managed by establishing a logical path to the LPAR from a storage controller. When a notice is received by the storage controller from the LPAR that the IPL has commenced, the LPAR address is stored in a data structure. After the storage controller initiates a pack change state interrupt, the stored address is compared with the addresses in a list of all LPARS to which the interrupt is directed. If the list of addresses includes the stored address, the stored address is removed from the list. Thus, the pack change state interrupt is transmitted only to the addresses in the list, leaving the LPAR to complete the IPL without interruption. After the storage controller receives a notice from the LPAR that the IPL has completed, the address of the LPAR is removed from the data structure. | 02-19-2009 |
| 20090055570 | DETECTION OF SPECULATIVE PRECHARGE - A DRAM controller may be configured to re-order read/write requests to maximize the number of page hits and minimize the number of page conflicts and page misses. A three-level prediction algorithm may be performed to obtain auto-precharge prediction for each read/write request, without having to track every individual page. Instead, the DRAM controller may track the history of page activity for each bank of DRAM, and make a prediction to first order based history that is not bank based. The memory requests may be stored in a queue, a specified number at a time, and used to determine whether a page should be closed or left open following access to that page. If no future requests in the queue are to the given bank containing the page, recent bank history for that bank may be used to obtain a prediction whether the page should be closed or left open. If the page is not closed as a result of the determination and/or prediction, it may be left open and closed after it has remained idle a specified length of time following the last access to the page. | 02-26-2009 |
| 20090083473 | FUNCTION-PROVIDING SYSTEM - From among identical modules stored on a module storage 112 and a module storage 212, an authenticated printing management module 130 selects the module with higher level information. For example, an ID authentication module 132 is stored in both the module storage 112 of an MFP 10 and the module storage 212 of a network interface card 11. The authenticated printing management module 130 selects the ID authentication module of the network interface card 11, in accordance with level information that represents an ID authentication module selection hierarchy. By so doing, where modules necessary for executing authenticated printing are included on both the MFP 10 and the network interface card 11, modules present on either the MFP 10 or the network interface card 11 are able to be selected appropriately for use. | 03-26-2009 |
| 20090100212 | METHOD, APPARTUS, COMPUTER PROGRAM PRODUCT, AND DATA STRUCTURE FOR PROVIDING AND UTILIZING HIGH PERFORMANCE BLOCK STORAGE METADATA - An enhanced mechanism for the allocation, organization and utilization of high performance block storage metadata provides a stream of data (e.g., in a server system, storage system, DASD, etc.) that includes a sequence of fixed-size blocks which together define a page. Each of the fixed-size blocks includes a data block and a footer. A high performance block storage metadata unit associated with the page is created from a confluence of the footers. Each footer in the confluence of footers has space available for application metadata, which are provided as one or more information units. At least one of the footers includes a Checksum field containing a checksum that covers at least the confluence of footers. This approach is advantageous in that it provides data integrity protection, protects against stale data, and significantly increases the amount of metadata space available for application use. | 04-16-2009 |
| 20090106479 | MANAGING MEMORY SYSTEMS CONTAINING COMPONENTS WITH ASYMMETRIC CHARACTERISTICS - A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components. | 04-23-2009 |
| 20090119442 | Managing Write-to-Read Turnarounds in an Early Read After Write Memory System - Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank. | 05-07-2009 |
| 20090132751 | Ethernet Controller - A controller, in particular an Ethernet controller has a control unit operable to receive commands and data through an I/O interface; a plurality of registers arranged in a register block which is divided into a plurality of register banks, wherein at least one register controls a function of the controller; a register address unit having logic for accessing one of the plurality of registers by a plurality of addressing schemes, wherein the addressing schemes at least has a direct address provided by received data, a combined address provided by a partial address from a received command and a bank address stored in a bank register, and an address selected form a plurality of predetermined addresses through a received command. | 05-21-2009 |
| 20090144481 | Enhanced Microprocessor or Microcontroller - A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch. | 06-04-2009 |
| 20090157940 | Techniques For Storing Data In Multiple Different Data Storage Media - A data storage system comprises a first data storage medium and a second data storage medium. The first and the second data storage media are different types of data storage media. The data storage system assigns a first range of logical block addresses to physical addresses in the first data storage medium. The data storage system is configured to dynamically reassign the first range of logical block addresses to physical addresses in the second data storage medium. Alternatively, the data storage system can assign a first range of logical block addresses to physical addresses in the first data storage medium and to physical addresses in the second data storage medium. The data storage system stores data associated with the first range of logical block addresses in both of the first and the second data storage media. One of the data storage media can be NAND Flash memory. | 06-18-2009 |
| 20090172244 | HIERARCHICAL SECONDARY RAID STRIPE MAPPING - Methods and apparatus of the present invention include new data and parity mapping for a two-level or hierarchical secondary RAID architecture. The hierarchical secondary RAID architecture achieves a reduced mean time to data loss compared with a single-level RAID architecture. The new data and parity mapping technique provides load-balancing between the disks in the hierarchical secondary RAID architecture and facilitates sequential access. | 07-02-2009 |
| 20090187696 | METHOD FOR DATA STORAGE MEANS AND A SYSTEM WITH DATA STORAGE MEANS - A system and a method for data storage means includes a set of data storage sub-assemblies and connectable to storage control means adapted to retrieve, for a plurality of simultaneous user applications, data stored in the data storage means. The method divides a data composition into a plurality of payload data subsets, and stores the payload data subsets in the data storage sub-assemblies. The storage control means is adapted to retrieve, for a user application, the payload data subsets in a predetermined retrieving sequence, wherein a sequence of a number of payload data subsets, which number corresponds to the number of data storage sub-assemblies in the set of data storage sub-assemblies, and which payload data subsets follow sequentially one immediately upon the other in the retrieving sequence, are stored in separate ones of the data storage sub-assemblies in the set of data storage sub-assemblies. | 07-23-2009 |
| 20090198866 | CODE MEMORY CAPABLE OF CODE PROVISION FOR A PLURALITY OF PHYSICAL CHANNELS - The invention provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a selecting multiplexer, a core memory module, and a code buffer. The selecting multiplexer repeatedly latches on to a plurality of addresses generated by the physical channels according to a sequence of the physical channels to generate a code memory address signal. The core memory module stores code data, and retrieves the code data according to the code memory address signal to generate a code memory data signal. The code buffer respectively retrieves a plurality of code segments requested by the physical channels from the code memory data signal according to the sequence of the physical channels, and stores the code segments. | 08-06-2009 |
| 20090276559 | Arrangements for Operating In-Line Memory Module Configurations - In one embodiment, a method is disclosed for timing responses to a plurality of memory requests. The method can include sending a plurality of memory requests to a plurality of in-line memory modules. The requests can be sent over a channel from a plurality of channels, where each channel can have a plurality of lanes. The method can receive responses to the plurality of memory requests over the channel and monitor the response to detect a timing relationship between at least two lanes from the plurality of lanes. In addition, the method can adjust a timing of a register loading and unloading sequence in response to the monitoring of multiple lanes and channels. Other embodiments are also disclosed. | 11-05-2009 |
| 20090282183 | ELECTRONIC TAG SYSTEM HAVING BANK STATUS AND CONTROLLING METHOD THEREOF - An electronic tag system, an electronic tag, and a controlling method thereof according to the present invention include an electronic tag that includes a memory having a divided band and a bank status that stores a status of data stored in the divided bank, a controlling circuit that reads and writes the data from and to the bank and changes the status and a controlling device that allows the controlling circuit connected through the electronic tag and an electronic tag reader/writer to transmit and receive the read and written data from and to the bank and issue an instruction to change the status. | 11-12-2009 |
| 20090300261 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory unit having a first and a second port and including plural banks; a bank address conversion circuit operative to convert a first bank address fed from external into a second bank address different from the first bank address and operative to supply the first bank address to one of the first and second ports and supply the second bank address to the other of the first and second ports; and a write data conversion circuit operative to convert input data fed from external into write data different from the input data and operative to supply the input data to one of the first and second ports and supply the converted write data to the other of the first and second ports. | 12-03-2009 |
| 20090300262 | METHODS AND DEVICES FOR TREATING AND/OR PROCESSING DATA - At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.). | 12-03-2009 |
| 20090319718 | MEMORY CONTROLLER ADDRESS MAPPING SCHEME - A data processing system is provided with a memory controller ( | 12-24-2009 |
| 20090319719 | System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices - A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control information from the integrated circuit buffer device to the first memory device. | 12-24-2009 |
| 20090327571 | COMMAND PROCESSING APPARATUS, METHOD AND INTEGRATED CIRCUIT APPARATUS - A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank | 12-31-2009 |
| 20090327572 | EXCHANGING INFORMATION BETWEEN COMPONENTS COUPLED WITH AN A I2C BUS VIA SEPARATE BANKS - A method and apparatus for exchanging information between components coupled with an a I | 12-31-2009 |
| 20090327573 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, including a memory banks and associated local data buses, and a bus connection circuit connected to the local data buses associated with two or more of the memory banks to perform a selective data transfer between a global data bus and those local data buses. | 12-31-2009 |
| 20100005218 | ENHANCED CASCADE INTERCONNECTED MEMORY SYSTEM - A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device, and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. The memory channel includes unidirectional downstream link segments coupled to the memory controller and operable for transferring configurable data frames. The memory channel further includes unidirectional upstream link segments coupled to the memory controller and operable for transferring data frames. | 01-07-2010 |
| 20100005219 | 276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES - A memory module including a plurality of memory channel connectors for communicating with a memory controller via a plurality of high-speed channels. The memory module also includes a plurality of memory devices arranged in one or more ranks, and a plurality of independently operable hub devices. Each hub device includes an interface for receiving signals from and driving signals to the memory controller on one of the high-speed channels via one or more of the memory channel connectors. Each hub device also includes a plurality of independently operable ports to communicate with all or a subset of the ranks of memory devices. | 01-07-2010 |
| 20100005220 | 276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES - A memory module that includes a first group of memory devices arranged in one or more ranks and a second group of memory devices arranged in one or more ranks. The memory module also includes a first and second port, wherein the first port is operable simultaneously with and independently of the second port. The memory module further includes a first memory device bus in communication with the first port and the first group of memory devices, and a second memory device bus in communication with the second port and the second group of memory devices. The memory module further includes a hub device configured to re-drive information in a cascade interconnect system. The hub device includes logic for reading data from and writing data to the ranks of memory devices via the first and second ports and the first and second memory device buses. | 01-07-2010 |
| 20100005221 | Address generation for multiple access of memory - A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical memory addresses to the memory bank in a backward twofold access order, and a half butterfly network (at least half, and barrel shifters in 8-tuple embodiments) is disposed between the memory bank and the forward unit and the backward unit. A set of control signals is generated which are applied to the half or more butterfly network (and to the barrel shifters where present) so as to access the memory bank with an n-tuple parallelism in a linear order in a first instance, and a quadratic polynomial order in a second instance, where n=2, 4, 8, 16, 32, . . . . This access is for any n-tuple of the logical addresses, and is without memory access conflict. In this manner memory access may be controlled data decoding. | 01-07-2010 |
| 20100023671 | Enhanced Microprocessor or Microcontroller - A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block. | 01-28-2010 |
| 20100030942 | ENCODED CHIP SELECT FOR SUPPORTING MORE MEMORY RANKS - Method and systems are disclosed for increasing the number of ranks supported in a memory system. In one embodiment, a plurality of predefined subsets of memory chips on a memory module is selected. A chip select signal uniquely identifying the selected subset of memory chips is generated. The chip select signal is encoded as a multi-bit word having a bit width that is less than the number of predefined subsets of memory chips. Each bit of the encoded chip select signal is transmitted along a separate chip select line. The transmitted chip select signal is decoded to determine the identity of the selected subset of memory chips. The selected subset of memory chips identified by the decoded chip select signal are read or written. | 02-04-2010 |
| 20100036997 | MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE - The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations. | 02-11-2010 |
| 20100042771 | INFORMATION PROCESSING APPARATUS AND ORDER GUARANTEE METHOD - A scheme is provided that guarantees the completion of cache invalidation processing in an information processing apparatus that performs directory-based coherence control. Each processor includes a cache and a Fence control unit that transmits an identifier to be returned to its own processor toward each bank through a network at timing when guarantee of completion of consistency processing of data stored in shared memory and the cache is requested and confirms that the identifier is returned from each bank. Each bank includes a memory main body, a directory that issues an invalidation request for invalidating the data stored in the cache according to an area where the data is written to the memory main body, and an invalidation request queue that queues the invalidation request and the identifier and transmits one of the invalidation request and the identifier through the network in a sequence of queuing. | 02-18-2010 |
| 20100049898 | MEMORY MANAGEMENT SYSTEM AND METHOD THEREOF - The invention discloses a memory management system and a memory management method are disclosed. The memory management system includes a first memory, at least one secondary memory, and a memory management device. The first memory includes a normal access memory bank and at least one switching access memory bank. The secondary memory includes at least one secondary access memory bank corresponding to the switching access memory bank. The memory management device reads/writes the normal access memory bank or the secondary access memory bank. | 02-25-2010 |
| 20100064091 | INFORMATION PROCESSING APPARATUS AND METHOD - An information processing apparatus includes bank overflow flag confirming means for confirming whether a bank overflow flag is set, the bank overflow flag notifying the occurrence of a bank-full state where, in a storage area including plural banks formed therein to store data, not-yet-read data is stored in all the banks, read pointer control means for, upon confirming that the bank overflow flag is set, moving a location designated by a read pointer cyclically designating each of the banks as a bank, from which the data is to be read, to a bank positioned next to a bank at a location designated by a write pointer cyclically designating each of the banks as a bank, into which the data is to be written, and reading means for reading the data from the bank designated by the read pointer after the location designated by the read pointer has been updated. | 03-11-2010 |
| 20100070676 | Memory Data Bus Placement and Control - In one embodiment, a memory device comprises a plurality of memory banks. At least two of the memory banks share the same bus. Logic is coupled to the memory banks via the different buses. The logic controls access to the memory banks. A bi-directional tri-state buffer is interposed between adjacent memory banks along the same bus so that each bus is segmented into a plurality of sections, each bus section being coupled to one or more different ones of the memory banks. | 03-18-2010 |
| 20100082876 | System and method of use of fast updatable counters using dynamic random access memories - A system and method for enabling one or more memories to maintain, update, and provide counter values. In a first version a dynamic random access memory, or DRAM, is bi-directionally communicatively coupled with a processor. The DRAM is divided into a plurality of banks. In the first version a set of subcounters is established, wherein each subcounter element is separately and singly located within a different DRAM bank. The value of a counter can be derived by reading and processing, e.g., adding, all of the values of each of an assigned set of subcounter subvalues maintained within the plurality of banks. Conversely, a counter value may be updated by updating a single assigned subcounter of a single bank. The first method allows a hosting computer to select a subcounter having a shortest access time, where the subcounter is an element of a set of subcounters assigned to maintain a given counter value. | 04-01-2010 |
| 20100082877 | MEMORY ACCESS CONTROL APPARATUS - A memory access control apparatus includes an arbiter and a sub-arbiter receiving and arbitrating access requests from a plurality of memory masters; a memory controller; and a memory having a plurality of banks. When a bank of the memory used by an access request allowed by the arbiter and currently being executed and a bank of the memory to be accessed by an access request by the sub-arbiter are different and the type of access request allowed by the arbiter and currently being executed and the type of memory access to be performed by the sub-arbiter are identical, then it is decided that access efficiency will not decline, memory access by the arbiter is suspended and memory access by the sub-arbiter is allowed to squeeze in (FIG. | 04-01-2010 |
| 20100100661 | PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES - An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols. | 04-22-2010 |
| 20100138587 | SHUNTED INTERLEAVE FOR ACCESSING PLURAL MEMORY BANKS, PARTICULARLY THOSE HAVING PARTIALLY ACCESSED CELLS CONTAINING DATA FOR CACHE LINES - A bank select device has a plurality of addressable locations and a plurality of storage locations correlated to each other so that each storage location is correlated to plural addressable locations and each addressable location is correlated to one storage location. Each storage location contains a respective bank select. The addressable locations and storage locations are grouped into interleave patterns such that, for each pattern, there are Q storage locations and 2 | 06-03-2010 |
| 20100161874 | MULTIPLE SLOT MEMORY SYSTEM - A memory system having a memory controller plus one or more registered memory modules, each registered memory module having a bank of memory chips and an associated register. A pre-register address/command bus connects the memory controller with the associated register. Each registered memory module has a post-register command/address bus that connects the memory chips in parallel with the associated register. The post-register command/address bus terminates with termination resistors that are connected to a voltage level that is approximately half of the supply voltage level. The memory controller provides chip select signals to the associated register of the registered memory modules. The associated registers, however, switch command/address signals to the memory chips independent of the chip select signals. | 06-24-2010 |
| 20100191894 | Digital Data Architecture Employing Redundant Links in a Daisy Chain of Component Modules - A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output link connects to a module after it, and inputs arranged similarly, so that any single module can be by-passed in the event of malfunction. Multiple chains may be cross-linked and/or serviced by hubs or chains of hubs. Preferably, the redundant links are used in a non-degraded operating mode to provide higher bandwidth and/or reduced latency of communication. The exemplary embodiment is a memory subsystem in which the modules are buffered memory chips. | 07-29-2010 |
| 20100205345 | MICROCONTROLLER WITH LINEAR MEMORY ACCESS IN A BANKED MEMORY - A microcontroller has a data memory divided into a plurality of memory banks, an address multiplexer for providing an address to the data memory, an instruction register providing a first partial address to a first input of the address multiplexer, a bank select register which is not mapped to the data memory for providing a second partial address to a the first input of the address multiplexer, and a plurality of special function registers mapped to the data memory, wherein the plurality of special function registers comprises an indirect access register coupled with a second input of the address multiplexer, and wherein the data memory comprises more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped. | 08-12-2010 |
| 20100205346 | MICROCONTROLLER WITH SPECIAL BANKING INSTRUCTIONS - An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register. | 08-12-2010 |
| 20100217915 | HIGH AVAILABILITY MEMORY SYSTEM - A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank includes a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments. The memory system also includes a memory controller in communication with the multiple memory channels. The memory controller distributes an access request across the memory channels to access a full rank. The full rank includes at least two of the partial ranks on separate memory channels. Partial ranks on a common memory module can be concurrently accessed. The memory modules can use at least one checksum memory device as a dedicated checksum memory device or a shared checksum memory device between at least two of the concurrently accessible partial ranks. | 08-26-2010 |
| 20100241782 | MEMORY ACCESS CONTROLLER, SYSTEMS, AND METHODS FOR OPTIMIZING MEMORY ACCESS TIMES - A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access configuration for each of a plurality of memory banks in a given memory system. The memory access configuration provided for each memory bank can either be to leave open or close at least one memory page in each memory bank. In this manner, a memory access configuration can be provided for each memory bank on an individualized basis to optimize memory access times based on the type of data activity in each memory bank. In embodiments described herein, the memory controller can also be configured to allow for dynamic configuration of one or more memory banks. Dynamic configuration involves changing or overriding the memory access configuration for a particular memory bank to optimize memory access times. | 09-23-2010 |
| 20100241783 | MEMORY NODE FOR USE WITHIN A DATA STORAGE SYSTEM HAVING A PLURALITY OF INTERCONNECTED MEMORY NODES - A memory node for use within a data storage system having a plurality of interconnected memory nodes is provided. The memory node comprises three data input interfaces, three data output interfaces, a memory module for storing data, and a controller coupled to the three data output interfaces, the three data input interfaces, and the memory module. The controller is configured to receive data via one of the three input interfaces, the data having a predetermined destination, read a first portion of the data to determine if the memory node is the predetermined destination, store a second portion of the data on the memory module, if the memory node is the predetermined destination, and transmit the received data via at least one of the three data output interfaces, if the memory node is not the predetermined destination. | 09-23-2010 |
| 20100241784 | System and method for storing data in a virtualized high speed memory system - A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. | 09-23-2010 |
| 20100262751 | Memory Control Unit Mapping Physical Address to DRAM Address for a Non-Power-of-Two Number of Memory Ranks Using Lower Order Physical Address Bits - A processor for low rank addressing of processor memory with non-power-of-two ranks. The processor includes cores that receive access requests to the processor memory (e.g., one or more DIMMs). The processor includes a memory controller connected to the core(s) that generates an address to the processor memory. The generating of the address includes identifying select rank bits in the physical address, determining whether the select rank bits map to a rank that is absent, and, when the physical address maps to an absent rank, modifying the physical address to include a modified set of select rank bits that are mapped to one of the ranks present in the processor memory. The modifying of the physical address may include swapping the lower rank bits with a higher order set of bits in the physical address. The memory controller proceeds with PA to DA conversions with the modified physical address. | 10-14-2010 |
| 20100325337 | METHOD AND SYSTEM FOR VISUALIZING A STORAGE AREA NETWORK - A method and system for visualizing a SAN is disclosed. In one embodiment, a method for visualizing a SAN includes scanning SAN components in the SAN to determine respective types of the SAN components and connectivity information between the SAN components. The method also includes generating a hierarchically-laid-out SAN graph by determining respective positions of the SAN components in the SAN based on the types of the SAN components and the connectivity information. The method further applying a force-directed model to the hierarchically-laid-out SAN graph to generate a SAN topology layout, wherein attractive and repulsive forces between the SAN components are tuned based on the types of the SAN components and the connectivity information. In addition, the method includes displaying the SAN topology layout on the display area of a display device in a management station coupled to the SAN. | 12-23-2010 |
| 20100325338 | DATA TRANSMISSION CONTROL DEVICE AND DATA TRANSMISSION CONTROL METHOD - First and second modules output a predetermined volume of data at a certain rate around the same time. A setting is made so that transfer addresses from the second module are shifted relative to transfer addresses from the first module such that a bank to which the first module issues a data transfer request is in a position separate from a bank to which the second module issues a data transfer request. | 12-23-2010 |
| 20100332718 | SYSTEM AND METHOD FOR PROVIDING CONFIGURABLE LATENCY AND/OR DENSITY IN MEMORY DEVICES - Memory devices, memory controllers, methods, and systems are provided, such as methods for masking the row cycle latency time of a memory array. In one embodiment, a memory device that is configurable to operate in full or reduced density modes is provided. In a reduced density mode, certain banks within the memory array function as duplicate memory banks associated with an addressable memory bank. Write operations performed in the reduced density mode may write a data segment to an addressed memory bank as well as its associated duplicate banks. When repeated read requests are issued for the data segment, the read requests may be interleaved between the addressed bank and its duplicate banks, thereby masking the row cycle time of each physical bank. That is, the interval between each read out of the data segment from the memory array will appear to be less than the row cycle time. | 12-30-2010 |
| 20100332719 | Memory Write Signaling and Methods Thereof - In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources. | 12-30-2010 |
| 20110029712 | MEMORY DEVICE AND METHOD WITH ON-BOARD CACHE SYSTEM FOR FACILITATING INTERFACE WITH MULTIPLE PROCESSORS, AND COMPUTER SYSTEM USING SAME - A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The cache system operates in a manner that can be transparent to a memory controller to which the memory device is connected. Alternatively, the memory controller can control the operation of the cache system. | 02-03-2011 |
| 20110040923 | DATA PACKET ACCESS CONTROL APPARATUS AND METHOD THEREOF - A data packet access control apparatus and a data packet access control method are disclosed. RAM resources in a data packet processing chip are used to implement a Bypass FIFO. The Bypass FIFO is used as a first-level cache for small amount of data, and an external RAM of the data packet processing chip is used as a second-level cache for large amount of data. In this way, some data packets are read and written within the chip and not all data packets have to be read and written through the external RAM. A data packet reading/writing operation may be performed to the external RAM by a BANK interleave mode. | 02-17-2011 |
| 20110078359 | Systems and Methods for Addressing Physical Memory - One embodiment of the present invention sets forth a technique for computing dynamic random access memory (DRAM) addresses from linear physical addresses for memory subsystems implementing integral power of two virtual page sizes, and an arbitrary number of available partitions. Each DRAM address comprises a row address, column address, bank address, and partition address. The linear physical address is used to generate to the DRAM address in units of a DRAM bank size. Address scrambling may be implemented to overcome transient access contention to specific DRAM pages by multiple client modules. | 03-31-2011 |
| 20110078360 | DATA HANDLING SYSTEM COMPRISING MEMORY BANKS AND DATA REARRANGEMENT - It is an object of the invention to provide a memory architecture that can handle data interleaving efficiently. This and other objects are achieved by the system according to the invention. The data handling system, is configured for receiving at an input a plurality of commands. The system comprises: a plurality of memory banks; a distributor connected to the input and having a plurality of distributor outputs. Each specific one of the plurality of memory banks ( | 03-31-2011 |
| 20110087821 | APPARATUS TO ACCESS MULTI-BANK MEMORY - A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made. | 04-14-2011 |
| 20110107005 | SEMICONDUCTOR DEVICE - A renewal of an internal address generated by an internal address generator that is used for a refresh operation of information in a memory unit including a plurality of memory cells is preformed during a refresh operation before an activated word line connected to the memory cell corresponding to the internal address is inactivated in the refresh operation. | 05-05-2011 |
| 20110107006 | Multiprocessor system and method thereof - A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port. | 05-05-2011 |
| 20110138100 | METHOD AND SYSTEM FOR CONCURRENT BACKGROUND AND FOREGROUND OPERATIONS IN A NON-VOLATILE MEMORY ARRAY - A method and system for permitting host write operations in one part of a flash memory concurrently with another operation in a second part of the flash memory is disclosed. The method includes receiving data at a front end of a memory system, selecting at least one of a plurality of subarrays in the memory system for executing a host write operation, and selecting at least one other subarray in which to execute a second operation. The write operation and second operation are then executed substantially concurrently. The memory system includes a plurality of subarrays, each associated with a separate subarray controller, and a front end controller adapted to select and initiate concurrent operations in the subarrays. | 06-09-2011 |
| 20110138101 | MAINTAINING DATA COHERENCE BY USING DATA DOMAINS - A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain. | 06-09-2011 |
| 20110153908 | ADAPTIVE ADDRESS MAPPING WITH DYNAMIC RUNTIME MEMORY MAPPING SELECTION - A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel. | 06-23-2011 |
| 20110167192 | System and method for storing data in a virtualized high speed memory system - A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. | 07-07-2011 |
| 20110167193 | SHARING PHYSICAL MEMORY LOCATIONS IN MEMORY DEVICES - A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit. | 07-07-2011 |
| 20110173369 | MEMORY MANAGEMENT USING PACKET SEGMENTING AND FORWARDING - Systems, devices and methods according to these exemplary embodiments provide for memory management techniques and systems for storing data. Data is segmented for storage in memory. According to one exemplary embodiment, each fragment is routed via a different memory bank and forwarded until they reach a destination memory bank wherein the fragments are reassembled for storage. According to another exemplary embodiment, data is segmented and stored serially in memory banks. | 07-14-2011 |
| 20110179213 | MEMORY MODULE AND MEMORY MODULE SYSTEM - A memory module and a memory module system are provided. The memory module system includes a plurality of memory modules each module comprising a plurality of memory blocks and a plurality of corresponding routers each storing a channel identification (ID) and a module ID corresponding to one or more memory blocks; and a controller configured to access the memory modules. During initialization, the controller reads and stores the channel ID and the module ID from each of the routers. The controller outputs a channel ID and a module ID that correspond to one or more memory blocks to be accessed. | 07-21-2011 |
| 20110202704 | MEMORY CONTROLLER, METHOD OF CONTROLLING MEMORY ACCESS, AND COMPUTING APPARATUS INCORPORATING MEMORY CONTROLLER - A computing apparatus for accessing a multiple bank memory is provided. The computing apparatus includes a processor, a memory and a memory controller which is configured to store data in a data buffer by accessing the memory in an aligned word unit and output, in response to a request for an unaligned memory access by the processor, requested data by extracting the request data from the data buffer. | 08-18-2011 |
| 20110258362 | REDUNDANT DATA STORAGE FOR UNIFORM READ LATENCY - A memory apparatus ( | 10-20-2011 |
| 20110276740 | CONTROLLER FOR SOLID STATE DISK WHICH CONTROLS ACCESS TO MEMORY BANK - A controller for a solid state disk is provided. The controller includes a storage module to store an index of at least one idle bank among a plurality of memory banks, and a control module to control an access to the at least one idle bank using the stored index. Here, the access to the at least one idle bank may be controlled based on a state of a channel corresponding to each of the at least one idle bank. | 11-10-2011 |
| 20110283042 | Transaction splitting apparatus and method - A transaction splitting apparatus and method are provided in which neighboring sub-transactions accessing a predetermined bank in each memory may access different banks. The transaction splitting apparatus includes a first processing unit to split a transaction into at least one sub-transaction, the transaction accessing a first bank among a plurality of banks comprised in a memory, and a second processing unit to translate an address of the at least one sub-transaction, to interleave the at least one sub-transaction using the plurality of banks. | 11-17-2011 |
| 20110283043 | LARGE CAPACITY SOLID-STATE STORAGE DEVICES AND METHODS THEREFOR - Non-volatile storage devices and methods capable of achieving large capacity solid state drives containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and a memory controller. The bank switching circuitry is integrated onto the memory controller and functionally interposed between the banks of memory devices and the front end of the memory controller. The bank switching circuitry operates to switch accesses by the memory controller among the at least two banks. | 11-17-2011 |
| 20110289258 | MEMORY INTERFACE WITH REDUCED READ-WRITE TURNAROUND DELAY - Embodiments of a memory system that communicates bidirectional data between a memory controller and a memory IC via bidirectional links using half-duplex communication are described. Each of the bidirectional links conveys write data or read data, but not both. States of routing circuits in the memory controller and the memory IC are selected for a current command being processed so that data can be selectively routed from a queue in the memory controller to a corresponding bank set in the memory IC via one of the bidirectional links, or to another queue in the memory controller from a corresponding bank set in the memory IC via another of the bidirectional links. This communication technique reduces or eliminates the turnaround delay that occurs when the memory controller transitions from receiving the read data to providing the write data, thereby eliminating gaps in the data streams on the bidirectional links. | 11-24-2011 |
| 20110296078 | MEMORY POOL INTERFACE METHODS AND APPARATUSES - Techniques are provided which may be implemented in various methods and/or apparatuses that to provide a memory pool interface capability to interface with a plurality of shared processes/engines and/or a virtual buffer interface associated there with. | 12-01-2011 |
| 20110307643 | Memory Management Process and Apparatus for the Same - Memory management process for optimizing the access to a central memory located within a processing system comprising a set of specific units communicating with each other through said memory, said process involving the steps of: a) arranging in a local memory at least a first and a second bank of storage (A, B) for the purpose of temporary object exchanged between a first data object producer ( | 12-15-2011 |
| 20110320680 | Method and Apparatus for Efficient Memory Bank Utilization in Multi-Threaded Packet Processors - A method and apparatus for efficient memory bank utilization in multi-threaded packet processors is presented. A plurality of memory access requests, are received and are buffered by a plurality of memory First In First Out (FIFO) buffers, each of the memory FIFO buffers in communication with a memory controller. The memory access requests are distributed evenly across said memory banks by way of the memory controller. This reduces and/or eliminates memory latency which can occur when sequential memory operations are performed on the same memory bank. | 12-29-2011 |
| 20120005400 | Dual In Line Memory Module with Multiple Memory Interfaces - A memory module such as a DIMM includes two separate memories with corresponding data, address and control interfaces. Each separate memory core includes plural memory banks for corresponding portions of the data interface. The separate interfaces include separate byte strobes and control signals. The two memories may be separately powered or share power connection. The two memories may be disposed on a single semiconductor integrated circuit or separate semiconductor integrated circuit. The two memories may be connected to two external memory interfaces of a single data processor or to separate data processors. | 01-05-2012 |
| 20120131257 | Multi-Context Configurable Memory Controller - The exemplary embodiments provide a multi-context configurable memory controller comprising: an input-output data port array comprising a plurality of input queues and a plurality of output queues; at least one configuration and control register to store, for each context of a plurality of contexts, a plurality of configuration bits; a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts, the plurality of data operations comprising memory address generation, memory write operations, and memory read operations, the configurable circuit element comprising a plurality of configurable address generators; and an element controller, the element controller comprising a port arbitration circuit to arbitrate among a plurality of contexts having a ready-to-run status, and the element controller to allow concurrent execution of multiple data operations for multiple contexts having the ready-to-run status. | 05-24-2012 |
| 20120131258 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME - A semiconductor memory apparatus includes, inter alia, a master chip and a plurality of slave chips. Each of the slave chips includes a plurality of banks. A first reception signal, a first timing signal, a bank address signal, and a slice selection signal to the slave chips may be provided by a master chip. The slave chips include a slice determining unit configured to compare the slice selection signal and a slice code and generate a slice enable signal, and a bank selecting unit configured to receive the bank address signal in response to the first reception signal and the slice enable signal and generate a bank enable signal in response to the bank address signal and the first timing signal. | 05-24-2012 |
| 20120159038 | Re-Mapping Memory Transactions - Systems and methods for re-mapping memory transactions are described. In an embodiment, a method includes receiving a memory request from a hardware subsystem to a memory, replacing a first identifier with a modified identifier in the memory request, and transmitting the memory request to the memory through a processor complex. The method further includes receiving a response from the memory, determining that the response corresponds to the memory request, replacing the modified identifier with the first identifier in the response, and transmitting the response to the hardware subsystem. In some embodiments, a system may be implemented as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles. | 06-21-2012 |
| 20120179854 | Systems, Methods, and Devices for Configuring a Device - Disclosed are methods and devices, among which is a method for configuring an electronic device. In one embodiment, an electronic device may include one or more memory locations having stored values representative of the capabilities of the device. According to an example configuration method, a configuring system may access the device capabilities from the one or more memory locations and configure the device based on the accessed device capabilities. | 07-12-2012 |
| 20120215960 | DEVICE FOR INCREASING CHIP TESTING EFFICIENCY AND METHOD THEREOF - A device for increasing chip testing efficiency includes a pattern generator, a reading unit, a logic operation circuit, and a judgment unit. The pattern generator is used for writing a logic voltage to each bank of a memory chip. The reading unit is used for reading logic voltages stored in all memory cells of each bank. The logic operation circuit is used for executing a first logic operation on the logic voltages stored in all memory cells of each bank to generate a plurality of first logic operation results corresponding to each bank, and executing a second logic operation on the plurality of first logic operation results to generate a second logic operation result corresponding to the memory chip. The judgment unit determines whether the memory chip passes the test according to the second logic operation result. | 08-23-2012 |
| 20120246379 | TECHNIQUES FOR DIFFERENT MEMORY DEPTHS ON DIFFERENT PARTITIONS - Embodiments of the present technology are directed toward techniques for enabling different memory partitions to have different memory depths. | 09-27-2012 |
| 20120246380 | NEIGHBORHOOD OPERATIONS FOR PARALLEL PROCESSING - A memory device includes a plurality of storage units in which to store data of a bank, wherein the data has a logical order prior to storage and a physical order different than the logical order within the plurality of storage units and a within-device reordering unit to reorder the data of a bank into the logical order prior to performing on-chip processing. In another embodiment, the memory device includes an external device interface connectable to an external device communicating with the memory device, an internal processing element to process data stored on the device and multiple banks of storage. Each bank includes a plurality of storage units and each storage unit has two ports, an external port connectable to the external device interface and an internal port connected to the internal processing element. | 09-27-2012 |
| 20120278524 | RECONFIGURABLE MEMORY MODULE AND METHOD - A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes. | 11-01-2012 |
| 20120324143 | METHODS AND APPARATUS FOR DATA ACCESS BY A REPROGRAMMABLE CIRCUIT MODULE - In some embodiments, an apparatus includes a set of memory modules, a reprogrammable circuit module and a set of data channels. Each memory module is associated with an address translation table configured to store a set of address pairs each including a physical memory address and a logical memory address. The reprogrammable circuit module is configured to retrieve a first physical memory address associated with a first logical memory address and a second physical memory address associated with a second logical memory address. Each data channel couples the reprogrammable circuit module to at least one memory module. The reprogrammable circuit module is configured to send a first and a second query to the first and the second memory module, via a first data channel based on the first physical memory address or a second data channel based on the second physical memory address, respectively. | 12-20-2012 |
| 20130013843 | EFFICIENT STORAGE OF MEMORY VERSION DATA - Systems and methods for efficient memory corruption detection in a processor. A processor detects a first data structure is to be allocated in a physical memory. The physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Either the processor or an operating system (OS) determines a first version number corresponding to the first data structure. During initialization of the first data structure, the first version number may be stored in a first location in the spare bank. The processor receives from the OS a pointer holding the first version number. When the processor executes memory access operations targeting the first data structure, the processor compares the first version number with a third version number stored in a location in the physical memory indicated by the memory access address. The processor may set a trap in response to determining a mismatch. | 01-10-2013 |
| 20130111101 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF | 05-02-2013 |
| 20130117493 | Reliable Memory Mapping In A Computing System - Methods, apparatus, and products for reliable memory mapping in a computing system, the computing system including a plurality of memory modules, including: determining, by a channel mapping module, a reliability rating for each of a plurality of memory controller address ranges; mapping, by the channel mapping module, critical system-level memory addresses to the most reliable memory controller address ranges; and directing, by the channel mapping module, memory accesses addressed to a critical system-level memory address to the most reliable memory controller address ranges. | 05-09-2013 |
| 20130138862 | Transferring Encoded Data Slices in a Distributed Storage Network - A method begins by a distributed storage (DS) processing module identifying encoded data slices of stored encoded data slices to transfer, wherein the stored encoded data slices are assigned addresses within a local distributed storage network (DSN) address range, wherein a global DSN address space is divided into a plurality of address sectors, and wherein the local DSN address range is a portion of an address sector. The method continues with the DS processing module determining whether another local DSN address range in the address sector exists and when the other local DSN address range in the address sector exists, determining whether to transfer identified encoded data slices into the other local DSN address range. When the at least some of the identified encoded data slices are to be transferred, the method continues with the DS processing module initiating a data transfer protocol to transfer the identified encoded data slices. | 05-30-2013 |
| 20130173841 | CONVENIENT, FLEXIBLE, AND EFFICIENT MANAGEMENT OF MEMORY SPACE AND BANDWIDTH - A device may receive a request to read data from or write data to a memory that includes a number of memory banks. The request may include an address. The device may perform a mapping operation on the address to map the address from a first address space to a second address space, identify one of the memory banks based on the address in the second address space, and send the request to the identified memory bank. | 07-04-2013 |
| 20130254454 | MEMORY SYSTEM AND BANK INTERLEAVING METHOD - According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence. | 09-26-2013 |
| 20130262737 | STORAGE CONTROL APPARATUS , STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM AND PROCESSING METHOD - Disclosed herein is a storage control apparatus including: a command processing section configured to receive a command requesting accesses to a plurality of access units by specifying an address in a memory space including a plurality of banks; and an address generating section configured to generate an address of an access unit serving as an object of the accesses in a bank selected from the banks as a bank determined in advance for the specified address. | 10-03-2013 |
| 20130268715 | DYNAMIC BANK MODE ADDRESSING FOR MEMORY ACCESS - One embodiment sets forth a technique for dynamically mapping addresses to banks of a multi-bank memory based on a bank mode. Application programs may be configured to perform read and write a memory accessing different numbers of bits per bank, e.g., 32-bits per bank, 64-bits per bank, or 128-bits per bank. On each clock cycle an access request may be received from one of the application programs and per processing thread addresses of the access request are dynamically mapped based on the bank mode to produce a set of bank addresses. The bank addresses are then used to access the multi-bank memory. Allowing different bank mappings enables each application program to avoid bank conflicts when the memory is accesses compared with using a single bank mapping for all accesses. | 10-10-2013 |
| 20140115227 | SELECTIVE COUPLING OF AN ADDRESS LINE TO AN ELEMENT BANK OF A VECTOR REGISTER FILE - A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port. | 04-24-2014 |
| 20140156907 | SMART MEMORY - Systems and methods to process packets of information using an on-chip processing system include a memory bank, an interconnect module, a controller, and one or more processing engines. The packets of information include a packet header and a packet payload. The packet header includes one or more operator codes. The transfer of individual packets is guided to a processing engine through the interconnect module and through the controller by operator codes included in the packets. | 06-05-2014 |
| 20140195715 | SCALABLE MEMORY SYSTEM - A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance. | 07-10-2014 |
| 20140215119 | STORAGE CONTROL DEVICE, ELECTRONIC APPARATUS, STORAGE MEDIUM, AND STORAGE CONTROL METHOD - A storage control device includes a first storage unit, a write control unit, and a read control unit. The first storage unit includes a plurality of storage areas corresponding to a plurality of addresses. The write control unit performs a write process to sequentially designate one of the plurality of addresses and write data to the storage area corresponding to the designated address, in a predetermined first order. The read control unit performs a read process to sequentially designate one of the plurality of addresses and read data stored in the storage area corresponding to the designated address, in a second order opposite to the first order, starting with the address corresponding to the storage area in which data has been stored immediately near a predetermined start timing after the beginning of execution of the write process, the read process being started at the predetermined start timing. | 07-31-2014 |
| 20150095546 | SYSTEM AND METHOD FOR BANK LOGICAL DATA REMAPPING - A method and system are disclosed for remapping logical addresses between memory banks of discrete or embedded multi-bank storage device. The method may include a controller of a storage device tracking a total erase count for a storage device, determining if an erase count imbalance greater than a threshold exists between banks, and then remapping logical address ranges from the highest erase count bank to the lowest erase count bank to even out wear between the banks. The system may include a controller that may maintain a bank routing table, an erase counting mechanism and execute instructions for triggering a remapping process to remap an amount of logical addresses such that an address range is reduced for a hotter bank and increased for a colder bank. | 04-02-2015 |
| 20150095547 | MAPPING MEMORY CONTROLLER CONNECTORS TO MEMORY CONNECTORS - Provided are a device, system, and method for mapping memory controller connectors to memory connectors. A memory is programmed to transmit for each of a plurality of the memory data connectors, a pattern on the memory data connectors that has a first value for a selected memory data connector of the memory data connectors and a different value from the first value for the memory data connectors other than the selected memory data connector. For each of the memory data connectors, a read command is issued to read the pattern on the memory data connectors. a device data connector receiving the first value in the read pattern is mapped to the selected memory data connector transmitting the first value. | 04-02-2015 |
| 20150293707 | Partition Extension Method and Apparatus - In a distributed storage system, a method for extending a number N of data node devices comprises a server receives an instruction of adding X new data nodes into the distributed storage system. Then, the server obtains a number M of the all partitions included in a hash ring and determines that M/(N+X) is lower than a preset threshold. The hash ring is organized according to a distributed hash table (DHT), and includes a plurality of partitions. Each partition is mapping to a data node. Based upon the determination, the server generates new partitions by multiplying partitions mapping to each data node, based upon the determination. After storing mapping relationship between the new partitions and the X new data nodes, the server adds the X new data nodes into the distributed storage system. | 10-15-2015 |
| 20150347037 | VERIFICATION OF MANAGEMENT OF REAL STORAGE VIA MULTI-THREADED THRASHERS IN MULTIPLE ADDRESS SPACES - A method, system, and computer program product to verify management of real storage via multi-threaded thrashers in multiple address spaces are described. The method includes dynamically scaling a number of units of work and a number of address spaces based on a number of available processors and dynamically scaling an amount and page size of storage pages representing virtual storage accessed by each of the number of units of work based on a total available memory. The method also includes obtaining, at each of the units of work, different types of storage frame sizes and attributes, accessing the storage pages corresponding with the respective different types of storage frame sizes and attributes and performing a respective function, and verifying, for each of the units of work performing the respective function, a location of the storage pages and content of the storage pages based on the respective function. | 12-03-2015 |
| 20150364168 | SIDECAR SRAM FOR HIGH GRANULARITY IN FLOOR PLAN ASPECT RATIO - A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M−A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle. | 12-17-2015 |
| 20150370487 | STORAGE DEVICE AND ADDRESS-CORRESPONDING METHOD, DATA-ACCESSING METHOD, AND IDENTIFYING AND ACCESSING METHOD THEREOF - A storage device is connected with a host. The storage device includes a control module, a first storage module and a second storage module. The first storage module having a first storage region and a second storage region is connected with the control module. The second storage module is connected with the control module. To-be-accessed data are stored and read in the first storage region or the second storage region of the first storage module by the control module. The to-be-accessed data stored and read in the first storage region are correspondingly stored and read in the second storage module by the control module, so that the second storage region is exclusively used for temporary storage of data, the storage modules are effectively utilized, and the lifetime decrease of the storage device is avoided. | 12-24-2015 |
| 20150378884 | STORAGE SYSTEM CONTROLLING ADDRESSING OF SOLID STORAGE DISKS (SSD) - In accordance with various embodiments of the invention, the storage processor | 12-31-2015 |
| 20160041761 | INDEPENDENTLY CONTROLLING SEPARATE MEMORY DEVICES WITHIN A RANK - Multiple memory devices within a rank may be accessed individually by assigning respective device identifiers to memory devices within a rank and/or including an indicator on respective portions of a data path that are coupled to different devices within a rank. A device identifier assignment command is implemented during memory system initialization to assign the device identifiers. Device identifiers are sent to corresponding memory devices in the rank via the data path when the device identifier assignment command is asserted. Device identifier fields are added to certain commands in a command path protocol. Individual memory devices within a rank are addressable by including their respective device identifier in the device identifier field of a memory command on the command path. Individual memory devices within a rank may also be accessed by configuring the devices to execute commands only when an indicator is received on their respective portion of the data path. | 02-11-2016 |
| 20160070644 | OFFSET RANGE OPERATION STRIPING TO IMPROVE CONCURRENCY OF EXECUTION AND REDUCE CONTENTION AMONG RESOURCES - An offset range striping technique increases concurrency of operation execution directed to metadata managed by a volume layer of a storage input/output (I/O) stack, while reducing contention among resources of one or more nodes of a cluster. A logical unit (LUN) may be apportioned into multiple volumes, each of which may be partitioned into multiple regions, wherein each region is represented by a dense tree. The technique increases concurrency of operation execution (e.g., modifications to the metadata at the offset ranges), while reducing contention among the resources (e.g., CPUs and NVLogs) by distributing the offset range operations among the regions and mapping the regions to services and NVLogs. Such increased concurrency and reduction of contention may be achieved by implementation of the technique to (i) apportion each region into disjoint chunks (i.e., stripes) of contiguous offset ranges; (ii) organize a plurality of regions into one or more zones and populate a first zone before allocating a second zone; and (iii) stagger the mapping of services to starting regions of the volumes. | 03-10-2016 |
