| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710268000 | Source or destination identifier | 15 |
| 20090049221 | SYSTEM AND METHOD OF OBTAINING ERROR DATA WITHIN AN INFORMATION HANDLING SYSTEM - A system and method of obtaining error data within an information handling system is disclosed. According to one aspect, an interrupt handling system can include a first system management interrupt handler operable to initiate access to a first interrupt event message. The interrupt handling system can also include a first resource operable to generate the first interrupt event message. In one form, the first interrupt event message can identify a first interrupt event occurrence detectable by the first system management interrupt handler. The interrupt handling system can further include a memory including a first allocated memory location configured to store the first interrupt event message using the first system management interrupt handler. In one form, the first system management interrupt handler can be responsive to a second system management interrupt handler request to read the first interrupt event message. | 02-19-2009 |
| 20090083467 | Method and System for Handling Interrupts Within Computer System During Hardware Resource Migration - A method and system for handling interrupts within a computer system during hardware resource migration are disclosed. In at least some embodiments, the method includes (a) programming an address conversion component so that incoming interrupt signals are directed to a control component rather than to a source processing resource, and (b) accumulating the incoming interrupt signals at the control component. Additionally the method also includes, subsequent to the migration of the partition from the source processing resource to a destination processing resource, (c) sending the accumulated incoming interrupt signals to the destination processing resource, and (d) reprogramming the address conversion component so that further incoming interrupt signals are directed to the destination processing resource. | 03-26-2009 |
| 20090106469 | SIGNALING AN INTERRUPT REQUEST THROUGH DAISY CHAINED DEVICES - A system and a method for asynchronously signaling interrupts from a plurality of devices in a computing system, while optimizing the latencies in handling the interrupts. In a particular embodiment, an interrupt is signaled via a plurality of daisy chained devices by handing over the interrupt request from one device to another while retaining information regarding any interrupts handed over (also referred to as passed). In this way, the interrupt source can be readily identified (using a binary search, for example) thereby reducing interrupt latency and memory resources required to retain interrupt history. | 04-23-2009 |
| 20090172232 | METHOD AND SYSTEM FOR HANDLING A MANAGEMENT INTERRUPT EVENT - A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes sequestering one or more processor cores for handling the management interrupt. Generated management interrupts are directed to the sequestered processor core and not to other processor cores allocated to a main partition. The sequestered processor core(s) handles the management interrupt without disrupting the current operation of the remaining processor cores. | 07-02-2009 |
| 20110047310 | Method and System for Generating and Delivering Inter-Processor Interrupts in a Multi-Core Processor and in Ceterain Shared Memory Multi-Processor Systems - Certain embodiments of the present invention arc directed to providing efficient and easily-applied mechanisms for inter-core and inter-processor communications and inter-core and inter-processor signaling within multi-core microprocessors and certain multi-processor systems. In one embodiment of the present invention, local advanced programmable interrupt controllers within, or associated with, cores of a multi-core microprocessor and/or processors of a multi-processor system are enhanced so that the local advanced programmable interrupt controllers can be configured to automatically generate inter-core and inter-processor interrupts when WRITE operations are directed to particular regions of shared memory. | 02-24-2011 |
| 20110153893 | Source Core Interrupt Steering - An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein. | 06-23-2011 |
| 20120124265 | METHOD FOR EXECUTING SYSTEM MANAGEMENT INTERRUPT - A method for executing a system management interrupt (SMI) is provided. When a power on self test (POST) is executed, a first identifier is generated and stored into a system management mode block of a memory. During a process for starting an operating system (OS), the first identifier is read from the system management mode block as a second identifier, and the second identifier is stored into an OS block of the memory. When the OS wants to use a system management interrupt, the first identifier and the second identifier are respectively read from the system management mode block and the OS block. Afterwards, it is determined whether the first identifier and the second identifier are the same. If the first identifier and the second identifier are the same, the SMI is executed. | 05-17-2012 |
| 20130080673 | VALIDATING MESSAGE-SIGNALED INTERRUPTS - The disclosed embodiments provide a system that validates message-signaled interrupts. During operation, the system receives a message-signaled interrupt from a requesting device. This message-signaled interrupt includes an interrupt vector that identifies an interrupt, and is accompanied by an identification tag that identifies the source of the interrupt. The system uses the interrupt vector to access a stored tag from a tracking mechanism that associates source devices with their assigned interrupt vector(s). The system then compares the identification tag and the stored tag to validate the message-signaled interrupt. | 03-28-2013 |
| 20130080674 | Source Core Interrupt Steering - An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein. | 03-28-2013 |
| 20140082244 | Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes - Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt. | 03-20-2014 |
| 20140143469 | TRANSMITTING AN INTERRUPT PACKET - A method and system for transmitting an aggregated interrupt packet are described herein. The method includes sending metadata from a client device to a host device. The method also includes detecting at least two sets of data from the client device. Additionally, the method includes detecting an identifier for the client device. Furthermore, the method includes generating an aggregated interrupt packet in the client device that comprises the identifier and the at least two sets of data for the client device. The method also includes sending the aggregated interrupt packet from the client device to the host device. | 05-22-2014 |
| 20140237151 | DETERMINING A VIRTUAL INTERRUPT SOURCE NUMBER FROM A PHYSICAL INTERRUPT SOURCE NUMBER - In an embodiment, a request is received from a virtual machine that specifies a virtual ISN and a hardware resource. A physical ISN is selected that is assigned to the hardware resource. The physical ISN is assigned to the virtual ISN as an assigned pair. The request and the physical ISN are sent to the hardware resource. A physical interrupt is received from the hardware resource that specifies the physical ISN. In response to the receipt of the physical interrupt that specifies the physical ISN, the virtual machine and the virtual ISN that is assigned to the first physical ISN are determined from the physical interrupt and the assigned pair from among a plurality of virtual machines. In response to determining the virtual machine and first virtual ISN that is assigned to the physical ISN, a virtual interrupt that comprises that virtual ISN is sent to the virtual machine. | 08-21-2014 |
| 20150067219 | DYNAMIC DESIGNATION OF THE BOOTSTRAP PROCESSOR IN A MULTI-CORE MICROPROCESSOR - A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor. | 03-05-2015 |
| 20160011997 | Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes | 01-14-2016 |
| 20160055109 | BUS RELAYING DEVICE - A relaying device, when having received an interrupt notification | 02-25-2016 |
