| Entries |
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| 20080288696 | DEVICE WITH A PROCESSOR AND A PERIPHERAL UNIT AND METHOD FOR GENERATING AN ACKNOWLEDGMENT SIGNAL - A device is provided that includes a processor, a peripheral unit, and a first logic, and to a method for generating an acknowledgment signal. The processor is clocked by a processor clock signal, which runs asynchronously to the peripheral clock signal, by which the peripheral unit is clocked. The peripheral unit sends an interrupt request synchronously to the peripheral clock signal to the processor, which thereupon is woken up from its idle state, to process the interrupt request in its working state. After the processing or during the processing of the interrupt request, the processor generates an acknowledgment signal synchronous to the processor clock signal. The first logic generates an acknowledgment signal, which is synchronous to the peripheral clock signal and by which the peripheral unit is informed about the processed interrupt request, from the acknowledgment signal synchronous to the processor clock signal. | 11-20-2008 |
| 20090049219 | INFORMATION PROCESSING APPARATUS AND EXCEPTION CONTROL CIRCUIT - To provide an information processing apparatus capable of performing switching between an exception handler and normal processing, the information processing apparatus comprising: An information processing apparatus comprising: a processor; a data processing unit operable to perform particular processing upon receiving a processing request from the processor; an interrupt controller operable to issue an interrupt request to the processor; and an exception control unit operable to control the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line, the data processing unit includes a notification unit operable to notify, via the dedicated line, the exception control unit of status information showing a current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor. | 02-19-2009 |
| 20090049220 | INTERRUPT-RELATED CIRCUITS, SYSTEMS, AND PROCESSES - An electronic interrupt circuit includes an interrupt-related input line ( | 02-19-2009 |
| 20090070511 | PROCESSOR SELECTION FOR AN INTERRUPT IDENTIFYING A PROCESSOR CLUSTER - In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described. | 03-12-2009 |
| 20090172231 | Data processing device and bus access control method therein - A data processing device includes a computing circuit that accesses a peripheral device connected to through a internal bus, an internal bus connection circuit that is provided between the computing circuit and the internal bus, and switches an enable and a disable state of an access from the computing circuit to the internal bus, an exception notification controller that outputs an exception occurrence notification signal to the computing circuit based on an error occurred in the peripheral device, and a bus disablement controller that instructs the internal bus connection circuit to disable an access from the computing circuit to the internal bus in accordance with the notification of the exception occurrence notification signal, and instructs the internal bus connection circuit to cancel the disablement of the access in accordance with a start of an exception processing based on the exception occurrence notification signal. | 07-02-2009 |
| 20090177829 | INTERRUPT REDIRECTION WITH COALESCING - An interrupt redirection and coalescing system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payloads communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The efficiency of processing may be improved by combining multiple interrupt notifications into a single interrupt message to a processor. For some interrupts on a multi-processor computer, such as those signaling completion of an input/output (I/O) operation assigned to a device, the efficiency of processing the interrupt may vary from processor to processor. Processing efficiency and overall computer system operation may be improved by appropriately coalescing interrupt messages within and/or across a plurality of queues, where interrupts are queued on the basis of which processor they target. | 07-09-2009 |
| 20090177830 | Handling interrupts in data processing - A method of processing data comprising: processing a function using a processor operable to perform a plurality of functions, the processor having interrupts enabled; receiving an interrupt at the processor; suspending processing of the function; accessing at least one control parameter, the at least one control parameter indicating whether processing of the function should be resumed from the point where it was interrupted or whether the function should be repeated following the interrupt; following completion of the interrupt continuing processing of the function either at a start of the function or at a point at which it was interrupted dependent upon the control parameter. A function being an application, a thread, a system software routine, or multiple processing steps defined by software. | 07-09-2009 |
| 20090198850 | PROCESSOR, ELECTRONIC APPARATUS, INTERRUPTION CONTROL METHOD AND INTERRUPTION CONTROL PROGRAM - A processor 1 provided with a plurality of cores, an interrupt operation dedicated core 20 which is used only for an interrupt operation; a normal core 11 to 1 | 08-06-2009 |
| 20090216930 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD THEREOF - An information processing apparatus connected with an IO device, having a processing unit, a channel device transferring data between the information processing apparatus and the IO device having a activation controller activating the channel device, a storage device having a predetermined area storing a result operation executed by the channel device, an interrupt controller controlling an interrupt required by the channel device to the processing unit, a channel device controller controlling the channel device and a driver writing a request for a first interrupt in the area of the storage device through the channel device and requiring the first interrupt to the processing unit by using the interrupt controller, wherein the processing unit executes driver commands for reading information stored in the area and requesting the first interrupt when the processing unit detects the request for the first interrupt. | 08-27-2009 |
| 20090240861 | Method and system for controlling an operation time of a computer - A method and system for controlling computer operation time is provided for counting how long the time for using the computer lasts. The steps of the time counting method are as following. First step is counting an operation time period for using the computer at the computer powered on; second step is determining the operation time period equal to a predetermined operating-time limit; third step is controlling the computer into an interrupted operating state when the operation time period is equal to the predetermined operating-time limit, wherein an interrupted time period for the computer stayed in the interrupted operating state is counted; fourth step is determining the interrupted time period equal to a predetermined suspension time; and fifth step is controlling the computer back to a normal operating state when the interrupted time period is equal to the predetermined suspension time, wherein the operation time period is re-counted. | 09-24-2009 |
| 20090327554 | SYNCHRONIZING PROCESSORS WHEN ENTERING SYSTEM MANAGEMENT MODE - A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, and determine whether to exit the entry synchronization loop after the timeout value has been reached. | 12-31-2009 |
| 20090327555 | Processor Interrupt Determination - Processor interrupt determination procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable by a computer to determine, based on a performance goal, which of a plurality of processors is to be targeted by a device that is to perform an input/output operation when an interrupt message is discovered that is from the device and that targets the determined processor. The interrupt message is communicated to the device to indicate availability of the determined processor for use by the device. When an interrupt message is discovered that is from the device and that targets an alternative processor near the determined processor when compared with other processors in the plurality of processors, the interrupt message that targets the alternative processor is communicated to the device to indicate availability of the alternative processor for use by the device. | 12-31-2009 |
| 20090327556 | Processor Interrupt Selection - Processor selection procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable to cause a processor executing the instructions to select, based on a performance goal, which of a plurality of processors is to further handle a device interrupt and when the selected processor is available, notify the selected processor to further handle the device interrupt. | 12-31-2009 |
| 20100023666 | Interrupt control for virtual processing apparatus - A data processing system supporting one or more virtual processing apparatuses is provided with external interrupt interface hardware | 01-28-2010 |
| 20100095040 | MULTI-CORE PROCESSOR, CONTROL METHOD THEREOF, AND INFORMATION PROCESSING APPARATUS - A multi-core processor which includes a plurality of processor dies. The multi-core processor has a first processor core which processes a first task and a second processor core which processes a second task. The first processor core and the second processor core are formed on each of the plurality of processor dies. When the first processor core makes a request for the second task processing in processing the first task, information on the second task is stored in a memory area used by the first processor core and interrupt notification is made to each of the second processor cores provided respectively on the plurality of processor dies. Each of the second processor cores having received the interrupt notification accesses the memory area used by the first processor core provided on the same processor die as the processor die on which the second processor core is provided. | 04-15-2010 |
| 20100115169 | Processor and interrupt handling method - Disclosed are a processor and an interrupt handling method. The processor of the present exemplary embodiments may include a plurality of processing elements and may predict whether a periodic interrupt occurs during a parallel processing mode before entering a mode in which the plurality of processing elements share a single task to process the single task in parallel. The processor may delay entering the parallel processing mode based on the prediction. The processor may reduce overhead that stores a context of the plurality of processing elements when the interrupt occurs. | 05-06-2010 |
| 20100153605 | REDISPATCHING SUSPENDED TASKS AFTER COMPLETION OF I/O OPERATIONS ABSENT I/O INTERRUPTS - Input/output (I/O) interrupts are avoided at the completion of I/O operations. A task requests (implicitly or explicitly) an I/O operation, and processing of the task is suspended awaiting completion of the I/O operation. At the completion of the I/O operation, instead of an I/O interrupt, an indicator associated with the task is set. Then, when the task once again becomes the current task to be executed, the indicator is checked. If the indicator indicates the I/O operation is complete, execution of the task is resumed. | 06-17-2010 |
| 20100153606 | APPROACHES FOR MEETING SMI DURATION LIMITS BY TIME SLICING SMI HANDLERS - Approaches that allow the context of an SMI task to be saved between SMIs. Upon entering an SMI handler for a task, a new task context stack is created. Thereafter, the SMI handler uses the task context, leaving the original stack unchanged. When the time limit for a single SMI is almost reached, the CPU is directed back to the original stack, and the task context stack persists in memory and retains the context of the task in hand. The soft SMI exits with an indication to signify that a new SMI should be invoked to continue processing. The entity that caused the first soft SMI then invokes another, passing in an indication to signify that this is a continuation of the prior task. On entering the SMI handler, the handler notes the request for continuation, switches to the saved task context stack and continues processing where it left off. | 06-17-2010 |
| 20100174842 | Effectively Mixing Real-Time Software with a Non-Real-Time Operating System - This disclosure describes a processor system that allows non-real time code to execute normally, while permitting a real time interrupt in hardware or software to execute with minimal added latency. | 07-08-2010 |
| 20100191887 | Monitoring Interrupt Acceptances in Guests - In one embodiment, an interrupt acceptance control circuit is provided. The interrupt acceptance control circuit may monitor one or more guest interrupt controllers in a system in response to an IPI (or device interrupt) issued in a guest, to determine if each targeted vCPU in the guest has accepted the interrupt. If not, the interrupt acceptance control circuit may communicate the lack of acceptance to the VMM, in one embodiment. The VMM may attempt to schedule the vCPUs that have not accepted the interrupt, for example. | 07-29-2010 |
| 20100235558 | Multiprocessor System Having Multiple Watchdog Timers and Method of Operation - A multiprocessor system with multiple watchdog timers, the timers causing all the processors in the system to concurrently process a common interrupt signal asserted by any of the watchdog timers timing out. The processors, in response to the common interrupt signal, store data residing in their local memories into a memory common to all the processors. The stored data is then stored in a permanent storage device for later analysis. Thereafter, all of the processors are reset. | 09-16-2010 |
| 20100262743 | System management mode inter-processor interrupt redirection - A method, processor, and system are disclosed. In one embodiment method includes a first processor core among several processor cores entering into a system management mode. At least one of the other additional processor cores apart from the first processor core remain operational and do not enter the system management mode. Then, once in the system management mode, the first processor core responds to an inter-processor interrupt. | 10-14-2010 |
| 20100274940 | INTERRUPT COALESCING FOR OUTSTANDING INPUT/OUTPUT COMPLETIONS - In a computer system, a method of controlling coalescence of interrupts includes dynamically basing a current level of interrupt coalescing upon a determination of outstanding input/output (I/O) commands for which corresponding I/O completions have not been received. Deliveries of interrupts are executed on the basis of the current level and in an absence of enabling timing-triggered delivery of an interrupt. | 10-28-2010 |
| 20100318707 | EXTERNAL DEVICE ACCESS APPARATUS, CONTROL METHOD THEREOF, AND SYSTEM LSI - An external device access apparatus according to the present invention includes: an address control unit that accepts a prefetch request and a prefetch data readout request from a master and performs a prefetch operation and a prefetch data readout operation; a readout data storage unit that stores data read out through the prefetch operation; a storage operation status holding unit that holds a prefetch operation status indicating whether or not the prefetch operation has been completed; and an acceptance signal generation unit that outputs, to the master, an acceptance signal indicating that the prefetch data readout request has been accepted from the master. First information indicating a status of the prefetch operation is outputted to the master based on the prefetch operation status. | 12-16-2010 |
| 20110040914 | MECHANISM FOR RECORDING UNDELIVERABLE USER-LEVEL INTERRUPTS - A method includes recording a user-level interrupt as undeliverable in a mailbox at least partially based on an interrupt domain identifier and an interrupt recipient identifier included in a user-level interrupt message associated with the user-level interrupt. The recording is at least partially based on an indication that the user-level interrupt is undeliverable to a recipient application thread executing on a processor core of a plurality of processor cores in a multi-core system. | 02-17-2011 |
| 20110040915 | FLEXIBLE NOTIFICATION MECHANISM FOR USER-LEVEL INTERRUPTS - A method includes delivering a user-level interrupt message indicative of a user-level interrupt to one or more recipients according to a user-level interrupt delivery configuration selected from a plurality of user-level interrupt delivery configurations. The one or more recipients correspond to one or more application threads executing on one or more processor cores of a plurality of processor cores in a multi-core system. A method includes generating an indicator of a user-level interrupt being undeliverable to one or more intended recipients of a user-level interrupt message according to a failed delivery notification mode configuration. The user-level interrupt may be issued by an application thread executing on a first processor core of a plurality of processor cores in a multi-core system. | 02-17-2011 |
| 20110093638 | HARDWARE MULTI-THREADING CO-SCHEDULING FOR PARALLEL PROCESSING SYSTEMS - A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core. | 04-21-2011 |
| 20110106994 | METHOD AND APPARATUS FOR QUALIFYING COLLECTION OF PERFORMANCE MONITORING EVENTS BY TYPES OF INTERRUPT WHEN INTERRUPT OCCURS - A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit. | 05-05-2011 |
| 20110145460 | PROCESSING SYSTEM OPERABLE IN VARIOUS EXECUTION ENVIRONMENTS - A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs. The system also comprises a register coupled to at least one of the processor cores for identifying active execution environments. The system also comprises a global interrupt handler operable to selectively route interrupts to one or more of the interrupt inputs of said plural processor cores. The system also comprises a conversion circuit having plural interrupt-related output lines, and said conversion circuit fed with at least some of said respective wait for interrupt outputs and respective security outputs and fed by said register. | 06-16-2011 |
| 20110145461 | METHOD AND DEVICE FOR BALANCING INTERRUPT LOAD OF MULTICORE PROCESSOR - A method and a device for balancing an interrupt load of a multicore processor are provided, the multicore processor includes multiple cores and an interrupt controller for controlling interrupt handling of the cores, characterized in that the method includes: pre-configuring a default processing core and a scheduling core group corresponding to an interrupt device, wherein the default processing core is one core in the scheduling core group; configuring the interrupt controller to route the interrupt device to the corresponding default processing core; and controlling the interrupt controller to route the interrupt device to one or multiple cores in the scheduling core group to which the default processing core belongs, when the number of interrupts of the interrupt device exceeds an interrupt threshold or a processing amount of the default processing core exceeds an interrupt load. | 06-16-2011 |
| 20110173363 | PROCESSOR SYSTEM WITH AN APPLICATION AND A MAINTENANCE FUNCTION - A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output. The processor system also comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application. | 07-14-2011 |
| 20110197003 | Interrupt Virtualization - In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt. | 08-11-2011 |
| 20110197004 | Processor Configured to Virtualize Guest Local Interrupt Controller - In an embodiment, a guest interrupt control unit in a hardware processor may be configured to detect that an interrupt has been recorded in a memory location corresponding to a virtual processor, wherein the interrupt is targeted at the virtual processor. In response to the virtual processor being active on the hardware processor, the guest interrupt control unit is configured to provide the interrupt to the guest that includes the virtual processor. In an embodiment, a processor is configured to execute instructions from a guest, wherein the processor is configured to detect an instruction that accesses interrupt controller state data associated with a virtual processor in the guest, and wherein the processor is configured to access a memory location that stores interrupt controller state data corresponding to the virtual processor in response to the instruction. | 08-11-2011 |
| 20110202699 | PREFERRED INTERRUPT BINDING - A method and system for binding interrupts to central processing units (CPUs). An interrupt controller receives an interrupt that is generated by a device coupled to the computer system. The interrupt controller identifies a preferred CPU associated with the device based on a predetermined binding. If the preferred CPU is currently available, the interrupt is sent to the preferred CPU. If the preferred CPU is not currently available, the interrupt is sent to another CPU in the computer system that is currently available. | 08-18-2011 |
| 20110208888 | SYSTEMS ON CHIPS HAVING INTERRUPT PROXY FUNCTIONS AND INTERRUPT PROCESSING METHODS THEREOF - Provided is a system on chip (SoC) capable of rapidly processing interrupts generated in various modules without causing an error. The SoC includes a processor configured to process a task, a plurality of modules on the SoC and operationally coupled to the processor through a system bus, and an interrupt proxy processing unit operationally coupled to the processor and the plurality of modules and configured to solely process an interrupt-related task from a first module of the plurality of modules | 08-25-2011 |
| 20110219157 | DATA PROCESSING DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND ABNORMALITY DETECTION METHOD - A data processing device for detecting the abnormal operation of a CPU is provided. The data processing device comprises a CPU, an interrupt counter, and a counter-abnormal-value detection circuit. The interrupt counter increments a count value based on an interrupt start signal which is outputted in response to an interrupt signal indicative of an interrupt request to the CPU and which indicates that the interrupt request has been accepted, and decrements the count value based on an end-of-interrupt signal which indicates that processing corresponding to the interrupt has completed. The counter-abnormal-value detection circuit detects abnormalities by comparing the count value with a predetermined value. | 09-08-2011 |
| 20120089761 | APPARATUS AND METHOD FOR PROCESSING AN INTERRUPT - Provided are an apparatus and method for processing an interrupt. The apparatus includes a plurality of processing cores that are each configured to process an interrupt. The apparatus also includes an interrupt distributing unit configured to receive the interrupt, determine whether or not execution mode of each processing core is IRQ mode for exception processing or interrupt processing, and provide the received interrupt to a processing core that is not in IRQ mode. | 04-12-2012 |
| 20120173782 | METHOD AND SYSTEM FOR MANAGING SLEEP STATES OF INTERRUPT CONTROLLERS IN A PORTABLE COMPUTING DEVICE - A method and system for managing sleep states of one or more interrupt controllers of processors contained within a portable computing device are described. The method includes a processor defining wake-up interrupt settings in a storage device contained within the portable computing device. This storage device may comprise message random access memory (“RAM”). After wake-up settings have been established in message RAM, a processor may generate an alert that the wake-up settings in the message RAM have been defined. Next, a controller reviews the wake-up interrupt settings in the message RAM for a plurality of interrupt controllers that correspond with a plurality of processors contained within the portable computing device. The controller merges the wake-up settings in the message RAM and then sends the merged wake-up settings to an always-on power manager (“APM”). The APM is responsible for issuing signals to place interrupt controllers of processors into a sleep state. | 07-05-2012 |
| 20120198113 | Time measurement of power button signal activation - Embodiments herein relate to measuring a continuous time period a power button signal is in an active state. In an embodiment, a controller is to measure the continuous time period the power button signal is in an active state, where the power button signal enters the active state when a power button is physically activated by a user to initiate a power down of a system. Further, the controller is to generate and send an interrupt to the system if the continuous time period is greater than a controller time, the interrupt having higher priority than an operating system of the system. | 08-02-2012 |
| 20120226844 | DUAL PROCESSOR SYSTEM AND METHOD FOR USING THE SAME - A dual processor system comprises a first processor, a second processor, and a dual-ported random access memory (DPRAM). When the first processor stores data to be processed by the second processor to the DPRAM and writes interrupt data to the DPRAM, the DPRAM generates a first information status. The second processor reads the interrupt data once when detecting the first information status, processes the to be processed data when successfully reading the interrupt data once, and reads the interrupt data twice when completing processing the to be processed data. The DPRAM generates a second information status when the second processor successfully reads the interrupt data twice, and the first processor identifies that the second processor has processed the to be processed data when detecting the second information status. | 09-06-2012 |
| 20120246370 | METHOD AND APPARATUS FOR MANAGING OPERATING SYSTEMS IN EMBEDDED SYSTEM - A method for managing operating systems in an embedded system to solve the problem of performance loss and high product complexity caused by the running of multiple operating systems on a single CPU is provided. The embedded system includes at least two operating systems. The method includes: receiving an interrupt instruction; saving a state of a currently running operating system; and switching the currently running operating system to a target operating system corresponding to the interrupt instruction. | 09-27-2012 |
| 20130007325 | SECURE HANDLING OF INTERRUPTED EVENTS - Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claimed. | 01-03-2013 |
| 20130007326 | HOST CONTROLLER APPARATUS, INFORMATION PROCESSING APPARATUS, AND EVENT INFORMATION OUTPUT METHOD - The present invention aims to provide a host controller apparatus, an information processing apparatus, and an event information output method that are capable of outputting event information to a system memory while achieving power saving. A host controller apparatus according to the present invention includes: an event controller that outputs occurred event information to a system memory; and an interruption controller that outputs an interrupt signal to a CPU executing an event recorded in the system memory, the interrupt signal requesting execution of the event output from the event controller to the system memory. The event controller outputs the occurred event information to the system memory in synchronization with a timing at which the interruption controller outputs the interrupt signal to the CPU. | 01-03-2013 |
| 20130019042 | MECHANISM TO SAVE SYSTEM POWER USING PACKET FILTERING BY NETWORK INTERFACEAANM Ertugay; Osman N.AACI BellevueAAST WAAACO USAAGP Ertugay; Osman N. Bellevue WA USAANM Thaler; David G.AACI RedmondAAST WAAACO USAAGP Thaler; David G. Redmond WA USAANM Hari; MahenderAACI RedmondAAST WAAACO USAAGP Hari; Mahender Redmond WA USAANM Ritz; Andrew J.AACI SammamishAAST WAAACO USAAGP Ritz; Andrew J. Sammamish WA USAANM Dabagh; AlirezaAACI KirklandAAST WAAACO USAAGP Dabagh; Alireza Kirkland WA US - A network interface that connects a computing device to a network may be configured to process incoming packets and determine an action to take with respect to each packet, thus decreasing processing demands on a processor of the computing device. The action may be indicating the packet to an operating system of the computing device immediately, storing the packet in a queue of one or more queues or discarding the packet. When the processor is interrupted, multiple packets aggregated on the network interface may be indicated to the operating system all at once to increase the device's power efficiency. Hardware of the network interface may be programmed to process the packets using filter criteria specified by the operating system based on information gathered by the operating system, such as firewall rules. | 01-17-2013 |
| 20130046911 | STORAGE CONTROL APPARATUS - An aspect of the invention is a storage control apparatus, comprising a plurality of processors, a memory, an I/O device coupled to a storage device, a virtualization module that allocates a first processor to a first guest and a second processor to a second guest from among the plurality of processors, and an interrupt control module that receives an interrupt from the I/O device and transmits the interrupt to any one of the plurality of processors, wherein the virtualization module comprises, a state detection module that detects at least one of a state of the first guest and a state of the first processor, and an interrupt delivery destination control module that switches the interrupt with respect to the first processor to the second processor when at least one of the state of the first guest and the state of the first processor becomes a predetermined state. | 02-21-2013 |
| 20130067133 | HANDLING INTERRUPTS IN DATA PROCESSING - A method and apparatus for processing data in which a function is processed using a processor operable to perform a plurality of functions is disclosed. When an interrupt is received during processing of the function at a point during the processing at which a portion of the function has been processed then a control parameter is accessed. In response to the control parameter having a value indicting that the function has idempotence processing of the function is stopped without processing the function further, and information on progress of the function is discarded such that following completion of the interrupt the portion of the function that has already been processed is processed again. In response to the control parameter having a value indicating that the function does not have idempotence, processing of the function is suspended without discarding information on progress of the function that has already been processed such that following completion of the interrupt the processing is resumed from a point that it reached when it was suspended. | 03-14-2013 |
| 20130097351 | System and Method for High-Performance, Low-Power Data Center Interconnect Fabric - A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch. | 04-18-2013 |
| 20130103871 | Method of Handling Network Traffic Through Optimization of Receive Side Scaling - An information handling system includes a plurality of processors that each includes a cache memory, and a receive side scaling (RSS) indirection table with a plurality of pointers that each points to one of the processors. A network data packet received by the information handling system determines a pointer to a first processor. In response to determining the pointer, information associated with the network data packet is transferred to the cache memory of the first processor, The information handling system also includes a process scheduler that moves a process associated with the network data packet from a second processor to the first processor, and an RSS module that directs the process scheduler to move the process and associates the first pointer with the processor in response to directing the process scheduler. | 04-25-2013 |
| 20130111092 | SYSTEM AND METHOD FOR ADJUSTING POWER USAGE TO REDUCE INTERRUPT LATENCY | 05-02-2013 |
| 20130111093 | COMPUTER-READABLE STORAGE MEDIUM, INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND INFORMATION PROCESSING METHOD | 05-02-2013 |
| 20130138850 | INTERRUPT CONTROL METHOD AND MULTICORE PROCESSOR SYSTEM - In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and notifies the other cores of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least cache memories of the other cores when the first data is written; and a second core different from the first core, maintaining the first data written as the interrupt flag, and notified of the execution request executes the interrupt processing, and writes over the area prescribing the interrupt flag written in the cache memory of the second core, with second data indicating no-detection of the interrupt signal. | 05-30-2013 |
| 20130159581 | METHOD AND APPARATUS FOR REMAPPING INTERRUPT TYPES - A method and apparatus are provided for controlling system management interrupts is disclosed. The method comprises: receiving an interrupt signal; determining a type associated with the interrupt signal; using the determined type to access control information indicating an action to be applied to the determined type of interrupt; and blocking, passing or remapping the interrupt signal in response to the control information. The apparatus comprises a memory, an interrupt unit and a logic circuit. The memory is adapted to store control information regarding a plurality of types of interrupt signals. The interrupt unit is adapted to receive the interrupt signal, and use the interrupt type contained in the interrupt signal to access the control information stored in the memory. The logic circuit is adapted to block, pass or remap said interrupt signal in response to the control information. | 06-20-2013 |
| 20130166804 | INFORMATION PROCESSING APPARATUS AND RECORDING APPARATUS USING THE SAME - A memory control unit is connected to a first bus and a second bus and that controls writing and reading of data to a memory; a control unit controls the information processing apparatus; a first circuit device is connected to the first bus and outputs a data write request to the memory control unit and a notification signal; a second circuit device is connected to the first bus and outputs a data read request to the memory control unit in accordance with the notification signal and an interrupt signal to the control unit in response to the data read request; and a third circuit device is connected to the second bus and outputs a data read request stored in the memory to the memory control unit in accordance with an instruction from the control unit which has received an interrupt signal. | 06-27-2013 |
| 20130166805 | INTERRUPT CAUSE MANAGEMENT DEVICE AND INTERRUPT PROCESSING SYSTEM - A peripheral device sends an interrupt generation notification to a bus bridge. The bus bridge receives the interrupt generation notification, transfers the received interrupt generation notification to a CPU, reads an interrupt cause from the peripheral device that has sent the interrupt generation notification, and writes to a memory the interrupt cause that has been read. Upon receiving the interrupt generation notification, the CPU reads the interrupt cause from the memory which allows fast access, and begins interrupt processing corresponding to the interrupt cause. Interrupt processing time up to commencement of the interrupt processing can be reduced. | 06-27-2013 |
| 20130185469 | INTERRUPT SIGNAL ACCEPTING APPARATUS AND COMPUTER APPARATUS - An interrupt signal accepting apparatus manages two OSs, relates devices sharing the same interrupt number respectively with an OS caused to perform an interrupt processing and an interrupt priority unique to a device, and manages an interrupt number priority conversion table showing the relation between the interrupt number and the interrupt priority. Each device continuously outputs an interrupt request having the same interrupt number until the interrupt processing is completed. An interrupt controller converts the interrupt number into the interrupt priority in accordance with the interrupt number priority conversion table when there is an interrupt signal from the devices. An interrupt signal control section causes a running OS to perform the interrupt processing to change the interrupt priority in the interrupt number priority conversion table when the converted interrupt priority matches an interrupt priority related to the running OS, and stops the running OS and starts the other OS when the interrupt priorities do not match. | 07-18-2013 |
| 20130219096 | PROGRAMMABLE EVENT DRIVEN YIELD MECHANISM WHICH MAY ACTIVATE OTHER THREADS - Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors. | 08-22-2013 |
| 20130262727 | RACE FREE INTERRUPT - A computer device includes a processor, a circuit block capable of issuing an interrupt to the processor, and a cacheable memory configured to include a register that is mapped to the logic block for storing interrupt status information of the logic block. | 10-03-2013 |
| 20130275638 | Interrupt Virtualization - In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt. | 10-17-2013 |
| 20140013021 | PROCESSOR CORE AND MULTI-CORE PROCESSOR SYSTEM - In one embodiment of the present invention, processor | 01-09-2014 |
| 20140025857 | RESOURCE MANAGEMENT IN A MULTICORE ARCHITECTURE - A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters. | 01-23-2014 |
| 20140047151 | INTERRUPT PROCESSING UNIT FOR PREVENTING INTERRUPT LOSS - Techniques are disclosed relating to systems that allow sending and receiving of interrupts between processing elements. In various embodiments, a system includes an interrupt processing unit that in turn includes various indicators corresponding to processing elements. In some embodiments, the interrupt processing unit may be configured to receive an interrupt and determine whether a first processing element associated with the interrupt is available to receive interrupts. The system may initiate a corrective action if the first processing element is not available to receive interrupts. In some embodiments, the corrective action may include redirecting the interrupt to a second processing element. In some embodiments, the interrupt processing unit may include a dropped interrupt management register to store information corresponding to the second processing element. In some embodiments, the corrective action may include altering the power state of the first processing element such that it becomes available to receive interrupts. | 02-13-2014 |
| 20140052882 | Latency Sensitive Software Interrupt and Thread Scheduling - Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some embodiments gather information identifying latency-sensitive tasks. Task(s) can be (re)assigned to different processor core(s) for execution when it has been determined that an originally assigned processor core has exceeded a usage threshold. | 02-20-2014 |
| 20140082243 | ACHIEVING DETERMINISTIC EXECUTION OF TIME CRITICAL CODE SECTIONS IN MULTI-CORE SYSTEMS - Systems and methods may provide for detecting a time critical code section associated with a real time processor core and suspending execution on a suspendable processor core in response to the time critical code section. Additionally, execution on the suspendable core may be resumed when the real time processor core reaches the end of the time critical code section. In one example, execution is suspended by issuing an inter-processor interrupt (IPI) from the real time core to the suspendable core, wherein execution may be resumed when the real time core conducts a write to a memory location that is monitored by the suspendable core during suspension of execution. | 03-20-2014 |
| 20140136744 | RESET METHOD AND NETWORK DEVICE - The present invention relates to a reset method and a network device. The method includes: receiving, by an SPI Flash, a reset instruction sent by a processor; and performing reset processing corresponding to the reset instruction according to the reset instruction, where the reset instruction includes interrupting a current operation, recording interruption state information when the current operation is interrupted, and setting a current state to a state of responding to a read instruction of the processor; after finishing the reset operation, sending, by the processor, a read instruction to the SPI Flash, and receiving interruption state information sent by the SPI Flash according to the read instruction; and then determining, according to the interruption state information, whether the interrupted operation in the SPI Flash needs to be continued, and if yes, sending an instruction of continuing the interrupted operation to the SPI Flash. | 05-15-2014 |
| 20140136745 | METHOD AND APPARATUS FOR ALLOCATING INTERRUPTS IN A MULTI-CORE SYSTEM - An apparatus and a method for allocating interrupts in a multi-core system are provided. According to an embodiment, an interrupt control register unit records the interrupt processing capacity of each core of a multi-core system by receiving an interrupt, and checking the interrupt control register unit when receiving the interrupt and allocating the interrupt to a core which has been checked to be in an interrupt processing enabled state in the checking step. When the core is allocating the interrupt, the core transmits, to the interrupt control register unit, a signal representing the interrupt control register corresponding to the core which is changed to an interrupt processing disabled state, and can process the interrupt. | 05-15-2014 |
| 20140143468 | REAL-TIME SAMPLING DEVICE AND METHOD THEREOF - A real-time sampling device for being coupled to a processing unit includes a first register, a second register, a third register, a trigger output element and a timer for outputting an interrupt signal. The first register externally receives and processes a first input signal to produce processed data. The second register retrieves the processed data from the first register upon receiving the interrupt signal, and the processing unit, upon receiving the interrupt signal, retrieves the processed data from the second register and performs calculation thereon to produce a processed data calculation value and temporarily store the processed data calculation value in the third register. The trigger output element outputs the processed data calculation value in the third register in real time upon receiving the interrupt signal. The real-time sampling device an be applied to digital control systems in order to perform real-time sampling on controlled subjects. | 05-22-2014 |
| 20140149623 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD - A disclosed information processing apparatus includes: a first processing unit; and a second processing unit that is in either of an operational state and a suspended state. The first processing unit and the second processing unit are coupled by a first signal line through which a first signal that represents a state of the second processing unit passes and by a second signal line through which a second signal that causes an interrupt to the second processing unit passes. The second processing unit outputs the first signal according to a state of the second processing unit. The first processing unit determines, based on the first signal, whether the first processing unit causes the second processing unit to resume. When the first processing unit causes the second processing unit to resume, the first processing unit outputs the second signal, and the second processing unit resumes, upon receiving the second signal. | 05-29-2014 |
| 20140156896 | ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER IDENTIFIER (APIC ID) ASSIGNMENT FOR A MULTI-CORE PROCESSING UNIT - Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID. | 06-05-2014 |
| 20140173150 | SYSTEM ON CHIP, METHOD OF OPERATING THE SAME, AND APPARATUS INCLUDING THE SAME - A method of operating a system on chip (SoC) includes calculating a first residence time indicating an amount of time that at least one task resides in an execution queue in the SoC, wherein the at least one task is assigned to at least one core of a multi-core processor in the SoC, calculating a total unit residence time indicating an amount of time that all tasks other than the at least one task reside in the execution queue, calculating a second residence time for the at least one core by adding the first residence time of the at least one task and the total unit residence time, and adjusting at least one of an operating frequency and a voltage of the at least one core based on the second residence time. | 06-19-2014 |
| 20140173151 | Increasing Turbo Mode Residency Of A Processor - In one embodiment, the present invention includes a method for accessing a task stored in an entry of a task queue that identifies the task and a first core of a processor on which the task has been scheduled, reassigning the task to a coldest idle core of the processor, and sending the task to the coldest idle core and maintaining the processor in a turbo mode. Other embodiments are described and claimed. | 06-19-2014 |
| 20140189185 | INTERRUPT MONITORING SYSTEM AND COMPUTER SYSTEM - An interrupt monitoring apparatus includes a storage that stores a given threshold that corresponds to an external interrupt notification; a measuring circuit that measures time that elapses from a time when the external interrupt notification is received until a time when dispatch notification is received from a CPU; a comparing circuit that compares the given threshold and the time measured by the measuring circuit; and an output circuit that outputs to the CPU, a comparison result obtained by the comparing circuit. | 07-03-2014 |
| 20140223062 | NON-AUTHORIZED TRANSACTION PROCESSING IN A MULTIPROCESSING ENVIRONMENT - A protocol for executing the instructions of a non-authorized transaction on the same processor in a multiprocessor environment is provided. A first instruction of a non-authorized transaction including a sequence of instructions is executed. A determination of whether the unauthorized transaction is aborted after each executed instruction. In response to an abort, the non-authorized transaction is rolled back and restarted at the first instruction of the non-authorized transaction. In response to an absence of an abort, the next instruction is executed until all sequenced instructions of the non-authorized transaction are completed on a same processing device. | 08-07-2014 |
| 20140250251 | AUTOMATICALLY AND TRANSPARENTLY PRESERVING TESTING STATE ACROSS SESSIONS - Disclosed is a technique for an automated testing harness that transparently preserves testing state across system sessions. The testing harness can be configured to execute a script of testing instructions, one or more of which can trigger a change in a system session. Prior to performing the session change, the testing harness can save test state and suspend the test. Upon resuming the test, the test harness can overwrite the initial values with the saved state values. To enable the automated testing, the testing harness can include a launch daemon and one or more launch agents. Upon a session change, an active launch agent can notify a launch daemon of its active status. This can cause the launch daemon to resume the test and restore the test state to the saved values. | 09-04-2014 |
| 20140281089 | Servicing A Globally Broadcast Interrupt Signal In A Multi-Threaded Computer - Methods, apparatuses, and computer program products for servicing a globally broadcast interrupt signal in a multi-threaded computer comprising a plurality of processor threads. Embodiments include an interrupt controller indicating in a plurality of local interrupt status locations that a globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include a thread determining that a local interrupt status location corresponding to the thread indicates that the globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include the thread processing one or more entries in a global interrupt status bit queue based on whether global interrupt status bits associated with the globally broadcast interrupt signal are locked. Each entry in the global interrupt status bit queue corresponds to a queued global interrupt. | 09-18-2014 |
| 20140281090 | Servicing A Globally Broadcast Interrupt Signal In A Multi-Threaded Computer - Methods, apparatuses, and computer program products for servicing a globally broadcast interrupt signal in a multi-threaded computer comprising a plurality of processor threads. Embodiments include an interrupt controller indicating in a plurality of local interrupt status locations that a globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include a thread determining that a local interrupt status location corresponding to the thread indicates that the globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include the thread processing one or more entries in a global interrupt status bit queue based on whether global interrupt status bits associated with the globally broadcast interrupt signal are locked. Each entry in the global interrupt status bit queue corresponds to a queued global interrupt. | 09-18-2014 |
| 20140281091 | METHOD AND APPARATUS FOR IDENTIFYING CAUSE OF INTERRUPT - A method of identifying a cause of an interrupt related to an interrupt indication received from an interrupt indicating circuit in a processor, includes the steps of having the interrupt indicating circuit provided with a plurality of lowest-layer registers having a plurality of bits, each of the plurality of bits corresponding to the cause of the interrupt, and one or more upper-layer registers for aggregating the plurality of lowest-layer registers; forming a hierarchical structure with the one or more upper-layer registers and the plurality of lowest-layer register; and identifying the cause of the interrupt by having the processor read the upper-layer registers and the lowest-layer registers in order following the hierarchical structure. | 09-18-2014 |
| 20140337553 | METHOD AND SYSTEM FOR INTERRUPT SIGNALING IN AN INTER-INTEGRATED CIRCUIT (I2C) BUS SYSTEM - Embodiments of a method and system are disclosed. One embodiment of a method for signaling an interrupt in an I2C system that includes a master I2C device and at least one slave I2C device that are connected by an SDA line and an SCL line is disclosed. The method involves, at the slave I2C device, pulling the SDA line low to signal an interrupt and at the slave I2C device, releasing the SDA line in response to either the SCL line having been pulled low or the expiration of a predetermined time period, whichever occurs first. In an embodiment, the predetermined time period is 1 ms. | 11-13-2014 |
| 20140359187 | CONTROL APPARATUS AND CONTROL METHOD - PCI devices write an MSI message in a memory and polling routines, which are executed by CPU cores respectively, poll the memory. The polling routines poll a cause of interrupt during an interval between tasks, during an interval between threads, and during idle and cause a CPU core with the lowest load to perform interrupt processing. An IO task performs inter-task communication with another IO task by using a command queue. | 12-04-2014 |
| 20150046618 | Method of Handling Network Traffic Through Optimization of Receive Side Scaling4 - An information handling system includes a plurality of processors that each includes a cache memory, and a receive side scaling (RSS) indirection table with a plurality of pointers that each points to one of the processors. A network data packet received by the information handling system determines a pointer to a first processor. In response to determining the pointer, information associated with the network data packet is transferred to the cache memory of the first processor. The information handling system also includes a process scheduler that moves a process associated with the network data packet from a second processor to the first processor, and an RSS module that directs the process scheduler to move the process and associates the first pointer with the processor in response to directing the process scheduler. | 02-12-2015 |
| 20150046619 | HOST CONTROLLER APPARATUS, INFORMATION PROCESSING APPARATUS, AND EVENT INFORMATION OUTPUT METHOD - The present invention aims to provide a host controller apparatus, an information processing apparatus, and an event information output method that are capable of outputting event information to a system memory while achieving power saving. A host controller apparatus according to the present invention includes: an event controller that outputs occurred event information to a system memory; and an interruption controller that outputs an interrupt signal to a CPU executing an event recorded in the system memory, the interrupt signal requesting execution of the event output from the event controller to the system memory. The event controller outputs the occurred event information to the system memory in synchronization with a timing at which the interruption controller outputs the interrupt signal to the CPU. | 02-12-2015 |
| 20150046620 | PESSIMISTIC INTERRUPT AFFINITY FOR DEVICES - A computing apparatus identifies that a first processor of a host has forwarded information for a device to a second processor that controls the device. After identifying that the first processor has forwarded the information to the second processor and in response to determining that one or more update criteria have been satisfied, the computing apparatus causes future information for the device to be forwarded to the second processor. | 02-12-2015 |
| 20150067218 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD THEREOF, AND COMPUTER-READABLE STORAGE MEDIUM - A series of processing that includes a first control step for controlling an apparatus that executes predetermined processing and a second control step for controlling the apparatus based on a control result of the first control step is executed. An execution history of the first control step or the second control step is stored in a memory. The series of processing is interrupted in a case where a predetermined interruption factor occurs during execution of the series of processing. In a case where the interruption is executed, a start step for resuming the series of processing is set to the first control step or the second control step, based on the execution history stored in the memory. | 03-05-2015 |
| 20150113191 | RESOURCE SERIALIZATION IN A TRANSACTIONAL EXECUTION FACILITY - Embodiments include methods, systems and computer program products that include executing a begin transaction instruction to begin a transaction comprising a sequence of instructions, wherein the begin transaction instruction indicates that a resource will be accessed by the first processing device. Embodiments also include determining whether it is safe for the first processing device to access the resource. Based on a determination that it is safe for the first processing device to access the resource, embodiments include processing the sequence of instructions of the transaction. Based on a determination that the sequence of instructions of the transaction has been completed, embodiments include executing an end transaction instruction, wherein the end transaction instruction indicates that the first processing device has completed its access of the resource. Based on a determination that it is not safe for the first processing device to access the resource, embodiments include aborting the transaction. | 04-23-2015 |
| 20150113192 | Method and System for Processing Data Conflict - A method and a system for processing a data conflict are provided that relate to the field of signal interface technologies of an integrated circuit, where the method includes sending a power management bus (PMBus) command to a slave device by using a PMBus, so as to perform power management; when the PMBus command fails to be sent, determining whether the number of times that the PMBus command fails to be sent is greater than or equal to a preset value, where the preset value is configured in advance during system initialization; starting timing if the number of times that the PMBus command fails to be sent is less than the preset value; and resending the PMBus command when timing duration reaches resending time. The present invention is applicable to a scenario in which multiple master devices (Masters) send the PMBus command by using the PMBus. | 04-23-2015 |
| 20150113193 | Interrupt Distribution Scheme - In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor. | 04-23-2015 |
| 20150120978 | INPUT/OUTPUT MEMORY MAP UNIT AND NORTHBRIDGE - The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests. | 04-30-2015 |
| 20150134867 | DEVICE AND METHOD FOR INTERRUPT COALESCING - An external logic device for a network interface controller enables interrupt coalescing from a network interface controller. The network interface controller has a cause register for storing information about interrupt causes and drives an interrupt line. The external logic device is connectable to the cause register for reading the contents of the cause register, and to the interrupt line of the network interface controller and to an interrupt input of a processor for forwarding interrupts from the interrupt line of the network interface controller to the processor. The external logic device has a timer which is initializable when the interrupt line contains an interrupt, and is constructed to delay the forwarding of interrupts, depending on the current contents of the cause register, until a timeout of the timer is reached. | 05-14-2015 |
| 20150149676 | SYSTEM FOR FORMULATING TEMPORAL BASES FOR OPERATION OF PROCESSES FOR PROCESS COORDINATION - A novel approach to coordinate processes in a process environment includes establishing a coherent temporal and resource framework for operation of selected processes in order to formulate a basis for coordination. A key aspect of the present innovation includes the novel techniques for coordinating processes including transmission of electromagnetism and transmission of electromagnetic radiation in a process environment by effecting periodic interruptions, based upon the abovementioned coherent temporal and resource framework, while maintaining the required operational and safety procedures. | 05-28-2015 |
| 20150317265 | Information Processing Device - A novel information processing device that is highly convenient or reliable is provided. Alternatively, a novel information processing device is provided. The novel information processing device includes an input portion supplying a map and a memory portion storing a program. The program includes interrupt processing in which a data set is generated from the map, a step of extracting a pattern from the data set generated through the interrupt processing, and a step of supplying instructions associated with a reference table when the extracted pattern is included in the reference table. | 11-05-2015 |
| 20150331816 | COMPUTER APPARATUS AND CONTROL METHOD OF COMPUTER APPARATUS - At start-up of a computer apparatus, a CPU executes a first initialization procedure included in a RAS module to initialize resources to be used by the RAS module. After execution of the first initialization procedure, the CPU executes an initialization procedure included in an OS to initialize resources to be used by the OS. After execution of the initialization procedure, the CPU executes a second initialization procedure included in the RAS module to copy an interrupt determining part included in the OS to the RAS module, and to set the interrupt detection unit such that upon detecting an interrupt the interrupt detection unit calls an interrupt determining part copied to the RAS module, instead of the interrupt determining part in the OS. | 11-19-2015 |
| 20150339142 | Memory Monitor Emulation - According to one example, a method includes with a hypervisor, detecting that a guest has executed a memory monitor command for a virtual processor, making a copy of a memory address associated with the memory monitor command, the copy being placed in hypervisor memory, and with the hypervisor, in response to detecting that the guest system has executed a wait command, executing a loop until the copy is different than the data stored in the memory address. | 11-26-2015 |
| 20150339155 | Virtual Processor States - A method includes, with a hypervisor, detecting that a virtual processor of a virtual machine has accessed a designated address, the designated address being associated with a time value, causing the virtual processor to enter a halt state for a period of time, and causing the virtual processor to exit the halt state after a period of time has passed, the period of time being based on the time value. | 11-26-2015 |
| 20150347328 | Methods for Mitigating System Interrupts for an Electronic Device - An electronic device may include an applications processor that communicates with a peripheral input-output (I/O) device using a coprocessor. The applications processor may include a first interprocessor communications (IPC) module, whereas the coprocessor may include a second IPC module for interfacing with the first IPC module. The first IPC module may forward a group of transactions to a submission queue and may ring a submission doorbell interrupt to signal that work items are pending in the submission queue. In response, the second IPC module may dequeue the work items from the submission queue and process these items at the I/O device. The second IPC module may provide a group of completed transactions to a completion queue and may ring a completion doorbell interrupt to signal that items are pending in the completion queue. Thereafter, the completed items are forwarded to other parts of the applications processor for processing. | 12-03-2015 |
| 20150378791 | DETECTING DEADLOCKS INVOLVING INTER-PROCESSOR INTERRUPTS - Creating, maintaining and using a lock dependency graph in a way that includes the following steps: (i) acquiring a first restriction on processor access in a multi-processor computer system; (ii) modeling the first restriction as first locking primitive information; and (iii) storing data corresponding to the first locking primitive information in a lock dependency graph. The first restriction on processor access is one of the following two types: (i) disabling the interrupts on a given processor; and/or (ii) sending inter-processor interrupts with synchronous waiting from one processor to another (including itself). | 12-31-2015 |
| 20150378941 | INSTRUCTIONS AND LOGIC TO INTERRUPT AND RESUME PAGING IN A SECURE ENCLAVE PAGE CACHE - Instructions and logic interrupt and resume paging in secure enclaves. Embodiments include instructions, specify page addresses allocated to a secure enclave, the instructions are decoded for execution by a processor. The processor includes an enclave page cache to store secure data in a first cache line and in a last cache line for a page corresponding to the page address. A page state is read from the first or last cache line for the page when an entry in an enclave page cache mapping for the page indicates only a partial page is stored in the enclave page cache. The entry for a partial page may be set, and a new page state may be recorded in the first cache line when writing-back, or in the last cache line when loading the page when the instruction's execution is being interrupted. Thus the writing-back, or loading can be resumed. | 12-31-2015 |
| 20150378942 | TRANSACTIONAL EXECUTION ENABLED SUPERVISOR CALL INTERRUPTION WHILE IN TX MODE - A computer can manage an interruption while a processor is executing a transaction in a transactional-execution (TX) mode. Execution, in a program context, of the transaction is begun by a processor in TX mode. An interruption request is detected for an interruption, by the processor, in TX mode. The interruption is accepted by the processor to execute a TX compatible routine in a supervisor context for changing supervisor resources. The TX compatible routine is executed within the TX mode. The processor returns to the program context to complete the execution of the transaction. Based on the transaction aborting, the processor does not commit changes to the supervisor resources. | 12-31-2015 |
| 20160085699 | Enabling method and enabling device for debugging port of terminal, and terminal - An enabling method and enabling device for a debugging port of a terminal, and a terminal are described, which are configured to enable a debugging port of a terminal under the condition of failure of a touch screen. The method includes: an instruction of enabling a debugging port input by a user is acquired, wherein the instruction is generated by simultaneously executing first operation of pressing a key of a terminal and second operation of covering an infrared sensor of the terminal; an interrupt service subprogram of the infrared sensor is triggered according to the instruction; a state of the infrared sensor and a pressed state of the key of the terminal are judged according to the interrupt service subprogram, and judgement results are obtained; and when the judgement results are determined to be consistent with preset standards, a screen of the terminal is controlled to be unlocked, and the debugging port is enabled. By adopting the technical solutions of the embodiment of the disclosure, an Android Debug Bridge (ADB) debugging port of a mobile phone Universal Serial Bus (USB) may be reliably enabled under the condition of failure of the touch screen to import personal information in a mobile phone into a computer by mobile phone management software in the computer through a USB cable. | 03-24-2016 |
| 20160117190 | Virtual Processor Direct Interrupt Delivery Mechanism - A method comprising is described. The method includes receiving an interrupt targeting a virtual processor, determining a status of the virtual processor and directly delivering the interrupt to the virtual processor upon determining that the virtual processor is operating in a running state. | 04-28-2016 |
| 20160124771 | THROTTLING CIRCUITRY - Techniques are disclosed relating to processor power control and interrupts. In one embodiment, an apparatus includes a processor configured to assert an indicator that the processor is suspending execution of instructions until the processor receives an interrupt. In this embodiment, the apparatus includes power circuitry configured to alter the power provided to the processor based on the indicator. In this embodiment, the apparatus includes throttling circuitry configured to, in response to receiving a request from the power circuitry to alter the power provided to the processor, block the request until the end of a particular time interval subsequent to receipt of the request or de-assertion of the indicator. In some embodiments, the particular time interval corresponds to latency between the processor receiving an interrupt and de-asserting the indicator. | 05-05-2016 |
| 20160140062 | MESSAGE FILTERING IN A DATA PROCESSING SYSTEM - Each processor of a plurality of processors is configured to execute an interrupt message instruction. A message filtering unit includes storage circuitry configured to store captured identifier information from each processor. In response to a processor of the plurality of processors executing an interrupt message instruction, the processor is configured to provide a message type and a message payload to the message filtering unit. The message filtering unit is configured to use the captured identifier information to determine a recipient processor indicated by the message payload and, in response thereto, provides an interrupt request indicated by the message type to the recipient processor. | 05-19-2016 |
| 20160140063 | MESSAGE FILTERING IN A DATA PROCESSING SYSTEM - A data processing system includes a plurality of processors, each processor configured to execute instructions, including a message send instruction, and a message filtering unit. The message filtering system is configured to receive messages from one or more of the plurality of processors in response to execution of message send instructions, each message indicating a message type and a message payload. The message filtering unit is configured to determined, for each received message, a recipient processor indicated by the message payload. The message filtering system is further configured to, in response to receiving, within a predetermined interval of time, at least two messages having a same recipient processor and indicating a same message type, delivering a single interrupt request indicated by the same message type to the same recipient processor, wherein the single interrupt request is representative of the at least two messages. | 05-19-2016 |
| 20160154751 | MEMORY ACCESS BY DUAL PROCESSOR SYSTEMS | 06-02-2016 |
| 20160188496 | COMPUTER INSTRUCTIONS FOR LIMITING ACCESS VIOLATION REPORTING WHEN ACCESSING STRINGS AND SIMILAR DATA STRUCTURES - Embodiments are directed to a computer implemented method of accessing a data frame, wherein a first portion of the data frame is in a first memory block, and wherein a second portion of the data frame is in a second memory block. The method includes initiating, by a processor, an access of the data frame. The method further includes accessing, by the processor, the first portion of the data frame. The method further includes, based at least in part on a determination that the processor does not have access to the second memory block, accessing at least one default character as a replacement for accessing the second portion of the data frame. | 06-30-2016 |
| 20160188505 | DIRECT ACCESS TO A HARDWARE DEVICE FOR VIRTUAL MACHINES OF A VIRTUALIZED COMPUTER SYSTEM - In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device. | 06-30-2016 |
| 20160196222 | SYSTEMS AND METHODS FOR NETWORK I/O BASED INTERRUPT STEERING | 07-07-2016 |
