Class / Patent application number | Description | Number of patent applications / Date published |
710266000 | Programmable interrupt processing | 33 |
20080228980 | Microcontroller and Method for the Operation Thereof - A microcontroller (MC) has integrated functional modules (FM) encompassing a first functional module (FM | 09-18-2008 |
20080276028 | METHOD OF DETECTING AND RECOVERING A LOST SYSTEM MANAGEMENT INTERRUPT (SMI) IN A MULTIPROCESSOR (MP) ENVIRONMENT - Method, computer program product and system for handling multiple system management interrupt (SMI) events in a multiprocessor system. In response to receiving an SMI event, processors enter system management mode (SMM) and execute SMI handler code. An SMI handler that determines fewer than all of the processor are in the SMI handler for the event will schedule an further SMI event based upon the content of the detected SMI event, then issues a resume (RSM) instruction and exits the SMI handler. The method recovers lost SMI events caused by latency between multiple processors entering or exiting SMM. | 11-06-2008 |
20080288695 | DYNAMIC CREATION OF LOW-LEVEL INTERFACES - In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the host code. A patching mechanism evaluates the operating system version, processor, and code to be patched. If patchable, low-level interfaces are created dynamically; a dispatcher is written into an unused location in vector space, and instructions copied from each interrupt vector to be patched to a guest interrupt vector. For an interrupt, the new, patched instructions branch to the dispatcher, which then branches to the appropriate patched interrupt guest code. If the processor is operating as a virtual machine, the guest interrupt code handles the interrupt, otherwise the original copied instructions are replayed, followed by execution at the original host instruction in vector space that exists after the copied and patched instructions. | 11-20-2008 |
20090037631 | Input Output Access Controller - A device for high-assurance processing is disclosed. A processing circuit uses an access controller to assure that the processing circuit operates properly. The processing circuit runs software programs and is programmable. The access controller is programmable, but not programmable by the processing circuit. Peripherals or segments of the address space of the processing circuit is regulated. In a particular state, the peripherals that are available are regulated by the access controller. In some embodiments, the transition from state-to-state can also be regulated by the access controller. | 02-05-2009 |
20090070509 | Method of detecting and protecting falling portable computer hard disk through software monitoring driver - In a method of detecting and protecting a hard disk of a falling portable computer, a falling sensor detects a falling state of a portable computer and sends an interrupt signal to a keyboard controller of the computer, and a falling state signal is responded at a default signal port of the keyboard controller. A software monitoring driver executes polling via an I/O driver about the falling state signal at the default signal port of the keyboard controller, and determines based on the falling state signal whether to actuate a hard disk protection mechanism, in which the software monitoring driver interrupts hard disk data access on the computer via a hard disk driver, and causes a system BIOS of the computer to send a parking control signal to the hard disk. | 03-12-2009 |
20090070510 | PROCESSOR SELECTION FOR AN INTERRUPT BASED ON WILLINGNESS TO ACCEPT THE INTERRUPT AND ON PRIORITY - In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described. | 03-12-2009 |
20090132745 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER-READABLE PROGRAM - An information processing apparatus improves the efficiency of use of a program capable of dynamically interrupting another program with a process. The program capable of dynamically interrupting another program with a process is received via a network and applied to the other program. A setting is received indicating whether the predetermined program should be applied to the other program when, after the predetermined program is applied, a supply of power to at least a part of the information processing apparatus is terminated and then resumed. Reapplication necessity information indicating the setting is stored in a storage unit. The predetermined program is reapplied to the other program when, after the application of the predetermined program, the supply of power to the at least a portion of the information processing apparatus is terminated and then resumed, based on the reapplication necessity information. | 05-21-2009 |
20090138642 | COMPUTER-READABLE RECORDING MEDIUM HAVING COMMUNICATION PROGRAM RECORDED THEREON, COMMUNICATION APPARATUS, AND COMMUNICATION METHOD - A communication program causes a computer to perform communication processing of received packets in response to reception of interrupt processing, the interruption processing being a packet reception notification after the lapse of a predetermined holding time. The communication program causes the computer to perform a packet counting process of counting the number of received packets received per unit time, and a parameter value changing process of changing, based on a counting result of the packet counting process, a timer parameter value for determining the time packets are held before processing. | 05-28-2009 |
20090144473 | CONTROL AND COMMUNICATION UNIT BETWEEN A TERMINAL AND A MICROCIRCUIT CARD - A control and communication unit is provided between a terminal and at least one microcircuit card. The unit includes a control module for a number of input signals to the card; a module for generation of a number of time diagrams for the card communication protocols; a request generation module for transmission and reception of characters based on information received from the control module, the requests being transmitted to an external module; and an interruption generation module for creating an interruption in the case of an error in a time diagram or a character received or transmitted, based on information received from the control module and for processing the interruption without a loss of characters. The generation of an interruption does not cause an interruption in the process of request generation. | 06-04-2009 |
20090164683 | Read Status Controller - A controller in a processing system can detect programmable bit sequences sent from a host processor to an external device, such as a memory, indicating whether a response from the external device needs to be read. The controller can also read a response from the external device and act appropriately, e.g., determine if an error has occurred by comparing the device's actual response to one or more programmably determined responses. Upon reading a particular response, e.g., a response indicating an error, the controller can issue an interrupt request to the host processor for further action. The controller can also track which external device access caused a particular response to occur. | 06-25-2009 |
20090177828 | Executing Application Function Calls in Response to an Interrupt - Executing application function calls in response to an interrupt including creating a thread; receiving an interrupt having an interrupt type; determining whether a value of a semaphore represents that interrupts are disabled; if the value of the semaphore represents that interrupts are not disabled: calling, by the thread, one or more preconfigured functions in dependence upon the interrupt type of the interrupt; yielding the thread; and if the value of the semaphore represents that interrupts are disabled: setting the value of the semaphore to represent to a kernel that interrupts are hard-disabled; and hard-disabling interrupts at the kernel. | 07-09-2009 |
20090216929 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER - A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered. | 08-27-2009 |
20090292848 | Method and Apparatus for an Electric Meter - An improved meter and its operation is described. The meter can be a part of a larger automated meter reading process that allows for remote reading of the meter though power line communication. Using a microcomputer core, the meter processes incoming analog data and can calculate several relevant data values need by utility providers. The meter can also be used to monitor and detect tampering dry connect/voltage free devices, such as gas and water meters, connected to the meter. | 11-26-2009 |
20100077120 | EMBEDDED SYSTEM AND INTERRUPTION HANDLING METHOD - An embedded system and an interruption handling method are provided. A plurality of interruption requests are received, and corresponding service routines are triggered with priority control. In the embedded system, a memory device comprises a plurality of service routines stored at different entry addresses, each related to an interruption request. A processor receives an enable signal to initialize one of the service routines through a branch instruction. A control unit buffers the interruption requests to schedule executions of corresponding service routines. When a specific service routine is to be executed, the control unit provides the branch instruction pointing to entry address of the specific service routine and asserts the enable signal to the processor, such that the processor executes the branch instruction to initialize the specific service routine. | 03-25-2010 |
20100088446 | PRIORITIZING INTERRUPT CONTROLLER - A system comprises processing logic. The system also comprises a first interrupt controller coupled to the processing logic and configured to manage interrupts provided to the processing logic. The system further comprises a second interrupt controller coupled to the first interrupt controller. The second interrupt controller is programmable to distribute received interrupts to the first interrupt controller via different output ports. | 04-08-2010 |
20100217906 | Methods And Aparatus For Resource Sharing In A Programmable Interrupt Controller - Efficient techniques are described for identifying active interrupt requests to improve performance and reduce power requirements in a processor system. A method to identify active sampled interrupt requests begins with scanning groups of the sampled interrupt requests one group at a time to identify an active interrupt request in any scanned group. A group of interrupt requests is an M/R priority of N sampled interrupt requests, M is the number of priority levels, and R is a resource sharing factor. A group selection circuit is updated to a new group in response to having identified an active interrupt request to improve the latency in processing high priority interrupt requests. Also, groups having active interrupt requests may be identified by early detection or look ahead circuitry. The scanning of groups of interrupt requests may be stopped until the next interrupt request sample point has been reached to reduce power utilization. | 08-26-2010 |
20100274939 | RECONFIGURABLE PROCESSOR AND INTERRUPT HANDLING METHOD - An interrupt handling technology and a reconfigurable processor are provided. The reconfigurable processor includes a plurality of processing elements, and some of the processing elements are designated for interrupt handling. When an interrupt request occurs while the reconfigurable processor is executing a loop operation, the designated processing elements may process the interrupt request. The interrupt handling technology allows the interrupt request and the loop operation to be processed in parallel. | 10-28-2010 |
20100299471 | Microcontroller with an Interrupt Structure Having Programmable Priority Levels with each Priority Level Associated with a Different Register Set - Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks. | 11-25-2010 |
20110072181 | ABNORMAL STATUS DETECTING METHOD OF INTERRUPT PINS - An abnormal status detecting method of interrupt pins is provided. In the invention, an advanced configuration and power interface (ACPI) table is looked up for obtaining an interrupt status bit of each interrupt pin in a computer system. Afterwards, the interrupt status bit is continuously checked whether it is maintained at a specific value during a fixed time. When the interrupt status bit of one of the interrupt pins is maintained at the specific value during the fixed time, the interrupt pin is determined to be abnormal. | 03-24-2011 |
20110191513 | INTERRUPT CONTROL METHOD AND SYSTEM - An interrupt control system comprises: a central processing unit (CPU); a peripheral device; an interrupt controller, and an interrupt preprocessing circuit. The peripheral device optionally issues an interrupt request, and the interrupt controller generates and outputs a first interrupt request signal in response to the interrupt request. The interrupt preprocessing circuit generates and outputs two first interrupt acknowledgement signals to the interrupt controller in response to the first interrupt request signal. An interrupt vector is generated and outputted by the interrupt controller in response to the two first interrupt acknowledgement signals, and the interrupt vector is transmitted to the CPU through the interrupt preprocessing circuit. | 08-04-2011 |
20110231590 | SYSTEM AND METHOD FOR DYNAMIC, LOCAL RETRIGGERED INTERRUPT ROUTING DISCOVERY - In some embodiments, the invention involves a dynamic interrupt route discovery method with local APIC (Advanced Programmable Interrupt Controller) retriggering to accommodate architectures that are not PC/AT compatible. In a low power mobile device, General Purpose Input/Output (GPIO) pins are dynamically allocated and IRQs are retriggered by a GPIO driver to multiplex the requests to an appropriate device. Other embodiments are described and claimed. | 09-22-2011 |
20120084477 | Transactional Memory Preemption Mechanism - Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction. | 04-05-2012 |
20120221757 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions. | 08-30-2012 |
20130054860 | OPTIMISTIC INTERRUPT AFFINITY FOR DEVICES - A computing apparatus determines that a virtual processor of a guest has been moved from a first physical processor of a host to a second physical processor of the host. The computing apparatus identifies a device that is controlled by the virtual processor, wherein device interrupts for the device are forwarded to the virtual processor. The computing apparatus updates at least one of the device or an interrupt controller to cause at least one of the device or the interrupt controller to send the device interrupts to the second physical processor of the host, wherein the second physical processor of the host forwards the device interrupts to the virtual processor running on the second physical processor without generating an inter-processor interrupt. | 02-28-2013 |
20130054861 | PESSIMISTIC INTERRUPT AFFINITY FOR DEVICES - A computing apparatus identifies that a first physical processor of a host has forwarded information regarding a device interrupt for a device to a second physical processor executing at least one of a virtual processor that controls the device or an application thread that controls the device. After identifying that the first physical processor has forwarded the information regarding the device interrupt to the second physical processor and in response to determining that one or more update criteria have been satisfied, the computing apparatus updates at least one of the device or an interrupt controller to cause at least one of the device or the interrupt controller to send future device interrupts for the device to the second physical processor. | 02-28-2013 |
20130111091 | METHOD AND APPARATUS FOR CONTROLLING INTERRUPT IN PORTABLE TERMINAL | 05-02-2013 |
20130159580 | COOPERATED INTERRUPT MODERATION FOR A VIRTUALIZATION ENVIRONMENT - Generally, this disclosure describes systems (and methods) for moderating interrupts in a virtualization environment. An overflow interrupt interval is defined. The overflow interrupt interval is used for triggering activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment. | 06-20-2013 |
20130179615 | Increasing Turbo Mode Residency Of A Processor - In one embodiment, the present invention includes a method for accessing a task stored in an entry of a task queue that identifies the task and a first core of a processor on which the task has been scheduled, reassigning the task to a coldest idle core of the processor, and sending the task to the coldest idle core and maintaining the processor in a turbo mode. Other embodiments are described and claimed. | 07-11-2013 |
20140019656 | DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS - Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system | 01-16-2014 |
20140189184 | CREATING DYNAMIC FIXED FUNCTIONALITY FOR A HARDWARE DEVICE SYSTEM - One particular example implementation of an apparatus that includes logic, the logic at least partially comprising hardware logic to: trigger a particular interrupt based, at least in part, on input/output (I/O) activity when a predetermined state is activated on a platform; generate a system control interrupt based, at least in part, on a source associated with the particular interrupt; and route the system control interrupt to a custom system control interrupt handler. | 07-03-2014 |
20140250250 | Power-Optimized Interrupt Delivery - An apparatus, method, system, and computer-readable medium are disclosed. In one embodiment the apparatus is a processor. The processor includes thread remapping logic that is capable of tracking hardware thread interrupt equivalence information for a first hardware thread and a second hardware thread. The processor also includes logic to receive an interrupt issued from a device, wherein the interrupt has an affinity tied to the first hardware thread. The processor also includes logic to redirect the interrupt to the second hardware thread when the hardware thread interrupt equivalence information validates the second hardware thread is capable of handling the interrupt. | 09-04-2014 |
20160055106 | MECHANISM FOR INTER-PROCESSOR INTERRUPTS IN A HETEROGENEOUS MULTIPROCESSOR SYSTEM - Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a second processor being of a different processor type than the first processor, and an IPI circuit. The IPI circuit typically includes a first register associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor. | 02-25-2016 |
20160117272 | PROGRAMMING INTERRUPTION MANAGEMENT - The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming operation and modify the programming operation to program a portion of the memory array to an uncorrectable state in response to detecting the interruption. | 04-28-2016 |