| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710261000 | Multimode interrupt processing | 36 |
| 20080244137 | PROCESSOR COMPRISING A FIRST AND A SECOND MODE OF OPERATION AND METHOD OF OPERATING THE SAME - A processor comprises a first mode of operation and a second mode of operation. A state of the processor in the first mode of operation comprises a first plurality of variables. The first plurality of variables comprises a return address. A state of the processor in the second mode of operation comprises a second plurality of variables in addition to the first plurality of variables. The processor is configured to perform, in case of an interrupt or exception occurring during the second mode of operation, the steps of saving the second plurality of variables and the return address to a buffer memory, replacing the return address with an address of a trampoline instruction, and switching into the first mode of operation. These steps are performed independently of an operating system. The trampoline instruction is adapted to switch the processor from the first mode of operation to the second mode of operation, to read the second plurality of variables and the return address from the buffer memory and to jump to the return address. | 10-02-2008 |
| 20080263250 | Driver transparent message signaled interrupts - Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts. | 10-23-2008 |
| 20080270660 | Method and Device for Switching Over in a Computer System Having at Least Two Execution Units - A device and method for switching over in a computer system having at least two execution units are provided, in which switchover units are included which are designed in such a way that they switch between at least two operating modes, a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. A programmable interrupt controller is assigned to each execution unit, and a storage element is included, in which information is stored that describes at least parts of a configuration of at least one of these interrupt controllers. | 10-30-2008 |
| 20090089472 | Program memory test access collar - A memory access device includes logic to switch data from a processor memory bus to a memory bus in a first operational mode, and to switch data from a test bus to the memory bus in a second operational mode, and logic to switch address signals from the processor memory bus to the memory bus in the first operational mode. In the second operational mode the device accepts from the test bus a starting memory address for memory reads and writes, and automatically and independently of the test bus adjusts a memory address for reads and writes during burst memory operations. | 04-02-2009 |
| 20090144472 | METHOD AND APPARATUS FOR MAKING A PROCESSOR SIDEBAND INTERFACE ADHERE TO SECURE MODE RESTRICTIONS - In response to entering a secure mode a processor disables access to first predetermined processor information through a sideband interface, while maintaining access to second predetermined processor information through the sideband interface. In the processor, a first interface portion of the sideband interface may provide access to the first predetermined processor information and a second interface portion of the sideband interface may provide access to the second predetermined processor information. The first interface portion is enabled in response to a power-on sequence and is selectably enabled under software control after being disabled on entering the secure mode. The second and additional interface portions may provides access to information related to processor temperature, power management, or machine checks. | 06-04-2009 |
| 20090248934 | INTERRUPT DISPATCHING METHOD IN MULTI-CORE ENVIRONMENT AND MULTI-CORE PROCESSOR - Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor. | 10-01-2009 |
| 20090292847 | MICROPROCESSOR APPARATUS PROVIDING FOR SECURE INTERRUPTS AND EXCEPTIONS - An apparatus for executing secure code, having a microprocessor coupled to a secure non-volatile memory via a private bus a system memory via a system bus. The microprocessor executes non-secure application programs and a secure application program. The microprocessor accomplishes private bus transactions over the private bus to access the secure application program within the secure non-volatile memory. The private bus transactions are hidden from system bus resources and devices coupled to the system bus. The microprocessor includes normal interrupt logic and secure execution mode interrupt logic. The normal interrupt logic provides non-secure interrupts for interrupting the non-secure application programs when the microprocessor is operating in a non-secure mode. The secure execution mode interrupt logic provides secure interrupts when the microprocessor is operating in a secure mode, where the secure execution mode interrupt logic cannot be observed or accessed by the system bus resources or the non-secure application programs. | 11-26-2009 |
| 20090319712 | REDUCING CORE WAKE-UP LATENCY IN A COMPUTER SYSTEM - A power control unit (PCU) may reduce the core wake-up latency in a computer system by concurrently waking-up the remaining cores after the first core is woken-up. The power control unit may detect arrival of a first, second, and a third interrupt directed at a first, second, and a third core. The power control unit may check whether the second interrupt occurs within a first period, wherein the first period is counted after waking-up of the first core is complete. The power control unit may then wake-up the second and the third core concurrently if the second interrupt occurs within the first period after the wake-up activity of the first core is complete. The first period may at least equal twice the time required for a first credit to be returned and next credit to be accepted. | 12-24-2009 |
| 20100070668 | INTERRUPT CONTROL APPARATUS, INTERRUPT CONTROL SYSTEM, INTERRUPT CONTROL METHOD, AND INTERRUPT CONTROL PROGRAM - An interrupt control unit provides controls on an interrupt from an accelerator to a CPU based on a packet transmitted to or received from a controlled object. The interrupt control unit includes: a storage part for storing therein an interrupt control timing table in which a condition of switching a mode of the interrupt control is described; and an interrupt control mode switching part for switching the mode of the interrupt control to the CPU between a permission mode and a mask mode, based on the interrupt control timing table in the storage part. | 03-18-2010 |
| 20100082867 | Multi-thread processor and its interrupt processing method - A first exemplary aspect of an embodiment of the present invention is a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, and an interrupt controller that determines whether or not an input interrupt request signal is associated with one or more than one of the plurality of hardware threads, and when the input interrupt request signal is associated, assigns the interrupt request to an associated hardware thread. | 04-01-2010 |
| 20100106876 | MULTIPROCESSOR SYSTEM CONFIGURED AS SYSTEM LSI - A multiprocessor system includes a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor unit is specified and receiving an interrupt signal and an interrupt control circuit receiving the interrupt request signal from each of the plurality of processor units and transmitting the interrupt signal to each of the plurality of processor units, wherein, the interrupt control circuit transmits the interrupt signal to the interrupt-request destination processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is not in a low power consumption state and transmits the interrupt signal to another processor unit different from the processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is in the low power consumption state. | 04-29-2010 |
| 20100223411 | Network processing control device, program, and method - A network control device including a network controller for transmitting/receiving data through a network and storing received data in a storage and a network processor for processing data stored in the storage is provided with a usage information acquiring section for acquiring usage information indicating usage state of a CPU, a determining section for determining load state of the CPU from the usage information based on a determination condition, and a mode setting section for setting an interrupt mode to the network processor when the determined load state is low and setting a polling mode when the determined load state is high, the network processor processes data stored in the storage when receiving interrupt notification of the network controller during the interrupt mode, deters the interrupt notification of the network controller during the polling mode and processing data stored in the storage at predetermined intervals. | 09-02-2010 |
| 20110047309 | VIRTUAL-INTERRUPT-MODE INTERFACE AND METHOD FOR VIRTUALIZING AN INTERRUPT MODE - Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers. | 02-24-2011 |
| 20110145459 | ELECTRONIC POWER MANAGEMENT SYSTEM - An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output. The system further comprises a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs. The system further comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal. | 06-16-2011 |
| 20110264837 | SYNCHRONIZING PROCESSORS WHEN ENTERING SYSTEM MANAGEMENT MODE - A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, determine whether to exit the entry synchronization loop after the timeout value has been reached. | 10-27-2011 |
| 20110283033 | COMPUTER SYSTEM - A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor. | 11-17-2011 |
| 20120159028 | System Management Mode Inter-Processor Interrupt Redirection - A method, processor, and system are disclosed. In one embodiment method includes a first processor core among several processor cores entering into a system management mode. At least one of the other additional processor cores apart from the first processor core remain operational and do not enter the system management mode. Then, once in the system management mode, the first processor core responds to an inter-processor interrupt. | 06-21-2012 |
| 20130124768 | Host-Based Messaging Framework for PCIE Device Management - A method of routing data in an information handling system can include receiving a notification from a management controller at a basic input/output system (BIOS) that includes a system management interrupt (SMI) handler. The a notification can indicate that the management controller has a data packet bound for a peripheral component interconnect express input/output (PCIe I/O) device coupled to a secondary processor. The method can include generating a system management interrupt at the information handling system via the BIOS SMI handler in response to the notification. The method can also include retrieving the data packet from the management controller via the BIOS SMI handler and sending a payload associated with the data packet from the BIOS SMI handler to the PCIe I/O device. | 05-16-2013 |
| 20130151743 | NETWORK ADAPTOR OPTIMIZATION AND INTERRUPT REDUCTION - A method and system are disclosed for network adaptor optimization and interrupt reduction. The method may also build an outbound buffer list based on outgoing data and add the outgoing data to an outbound buffer queue. Furthermore, the method may set a buffer state from an empty state to a primed state to indicate that the outgoing data is prepared for transmitting and signal a network adaptor with a notification signal. | 06-13-2013 |
| 20130246678 | VIRTUAL SYSTEM MANAGEMENT MODE DEVICE AND CONTROL METHOD THEREOF - A virtual system management mode device, for processing a system management interrupt signal generated by a special process, includes a transformation unit, a control unit memory, and a control unit. The transformation unit transforms the system management interrupt signal into a virtual system management interrupt signal. The control unit memory stores a plurality of system management interrupt processes. The control unit executes one of the system management interrupt processes according to the virtual system management interrupt signal. | 09-19-2013 |
| 20140006667 | ADAPTIVE HARDWARE INTERRUPT MODERATION | 01-02-2014 |
| 20140122759 | Edge-Triggered Interrupt Conversion - In an embodiment, a system includes an interrupt controller, one or more CPUs coupled to the interrupt controller, a communication fabric, one or more peripheral devices configured to generate interrupts to be transmitted to the interrupt controller, and one or more interrupt message circuits coupled to the peripheral devices. The interrupt message circuits are configured to generate interrupt messages to convey the interrupts over the fabric to the interrupt controller. Some of the interrupts are level-sensitive interrupts, and the interrupt message circuits are configured to transmit level-sensitive interrupt messages to the interrupt controller. At least one of the interrupts is edge-triggered. The system is configured to convert the edge-triggered interrupt to a level-sensitive interrupt so that interrupts may be handled in the same fashion. | 05-01-2014 |
| 20140207988 | SYSTEM AND METHOD FOR SECURE SMI MEMORY SERVICES - In accordance with the present disclosure, a system and method are herein disclosed for providing secure SMI memory services, including the protection of SMM memory from surreptitious attacks by, for example, rootkits. Information handling systems are susceptible to attacks, especially attacks on SMM memory. In one example, an SMI handler corresponding to the SMI Driver associated with an SMI interrupt performs validation of a password. An SSMS driver allocates memory for the SMI handler to use with the validation process and also performs a secure erase of allocated memory blocks upon completion of all secure SMI Memory Services. By controlling the validation and secure erase process through the use of the SMI handler and SSMS driver, information leakage can be prevented resulting in system data integrity. | 07-24-2014 |
| 20140223059 | Write Transaction Interpretation for Interrupt Assertion - A method and circuit for a data processing system ( | 08-07-2014 |
| 20140223060 | Injecting Interrupts in Virtualized Computer Systems - Systems and methods for injecting interrupts in a virtualized computer system. An example method may comprise providing a data structure associating message destination addresses and virtual processor identifiers for a plurality of interrupt destination modes, receiving an interrupt message including a message destination address, looking up the message destination address in the data structure, and forwarding the interrupt message to a virtual processor associated by the data structure with the message destination address. | 08-07-2014 |
| 20140258580 | MOTOR CONTROL APPARATUS AND MOTOR CONTROL METHOD - A motor control apparatus includes: a driving control unit that performs driving control of a motor in accordance with a drive command; an interrupt control unit that starts and executes interrupt processing for performing the driving control at an interrupt cycle; a first processing unit that executes same first processing every time the interrupt processing starts; and a second processing unit that selects and executes a different piece of processing from second processing every time the interrupt processing starts. The interrupt control unit executes at least one piece of the first processing before executing the second processing in the interrupt processing. | 09-11-2014 |
| 20140289437 | EXPANDER INTERRUPT PROCESSING - In one example in accordance with aspects of the present disclosure, an expander is provided. The expander comprises a workload scheduling module to cause the expander to enter a first mode of operation where the expander processes interrupts, and further to enter a second mode of operation where the expander processes interrupts for up to a predetermined time period before responding to at least one of Serial Management Protocol (SMP) commands and Serial SCSI Protocol (SSP) commands with a retry message. | 09-25-2014 |
| 20140372650 | SYSTEM AND METHOD FOR GENERATING INTENTIONAL INTERRUPTIONS DURING GATHERINGS - Systems and methods for generating interruptions are provided. A method for generating interruptions, comprises generating a message for one or more recipients, detecting that a computing device is being used for a presentation, concluding, using a processor, that the one or more recipients are in an audience for the presentation, and after concluding that the one or more recipients are in the audience, interrupting the presentation with the message. | 12-18-2014 |
| 20140372651 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an information processing apparatus includes a banked register determiner and a saving register determiner. The banked register determiner is configured to hold register information indicating which of a banked register and a non-banked register a register which is used by the operating system is, receive an acquisition instruction for the non-banked or banked register and the information about the mode of the operating system, and return a list of the non-banked or banked registers. The saving register determiner is configured to acquire the mode in which the operating system is capable of operating, determine that saving of the banked register for the mode is necessary when another operating system is capable of operating in the mode, acquire a list of the banked registers, and acquire a list of the non-banked registers from the banked register determiner. | 12-18-2014 |
| 20150067214 | SINGLE-CORE WAKEUP MULTI-CORE SYNCHRONIZATION MECHANISM - A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep. | 03-05-2015 |
| 20150067215 | MULTI-CORE SYNCHRONIZATION MECHANISM WITH INTERRUPTS ON SYNC CONDITION - A microprocessor includes a plurality of processing cores, each comprising a respective interrupt request input and a control unit configured to receive a respective synchronization request from each of the plurality of processing cores. The control unit is configured to generate an interrupt request to all of the plurality of processing cores on their respective interrupt request inputs in response to detecting that the control unit has received the respective synchronization request from all of the plurality of processing cores. | 03-05-2015 |
| 20150067216 | Memory Controller and Memory Access Method - A memory controller ( | 03-05-2015 |
| 20160011880 | SERVICE PROCESSOR (SP) INITIATED DATA TRANSACTION WITH BIOS UTILIZING INTERRUPT | 01-14-2016 |
| 20160048392 | MICROCOMPUTER - A microcomputer includes: a central processing unit (CPU); a data transfer apparatus (DTC); and a storage apparatus (RAM). The data transfer apparatus includes a plurality of register files each including a mode register storing the transfer mode information, an address register to which the address information is transferred, and a status register (SR) representing information that specifies the transfer information set. The data transfer apparatus checks the information of the status register, to determine whether to use the transfer information set held in the register files or to read the transfer information set from the storage apparatus and to rewrite a prescribed one of the register files. The data transfer apparatus performs data transfer based on the transfer information set stored in one of the register files. | 02-18-2016 |
| 20160055108 | MANAGING MESSAGE SIGNALED INTERRUPTS IN VIRTUALIZED COMPUTER SYSTEMS - Systems and methods for managing message signaled interrupts in virtualized computer systems. An example method may comprise: intercepting, by a hypervisor running on a host computer system, a memory read operation initiated by a virtual machine with respect to a first interrupt mapping table, the first interrupt mapping table stored by a physical device associated with the virtual machine, the memory read operation specifying an offset relative to a base address of the first interrupt mapping table; reading at least part of the first interrupt mapping table; and returning, to the virtual machine, a value referenced by the offset within a second interrupt mapping table, the second interrupt mapping table residing in a memory of the host computer system. | 02-25-2016 |
| 20160378697 | PROVIDING DEDICATED RESOURCES FOR A SYSTEM MANAGEMENT MODE OF A PROCESSOR - In one embodiment, a processor includes a plurality of cores including a first core to be reserved for execution in a protected domain, the first core to be hidden from an operating system. The processor may further include a filter coupled to the plurality of cores, where the filter includes a plurality of fields each associated with one of the plurality of cores to indicate whether an interrupt of the protected domain is to be directed to the corresponding core. Other embodiments are described and claimed. | 12-29-2016 |
