| Entries |
| Document | Title | Date |
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| 20080228977 | Method and Apparatus for Dynamic Hardware Arbitration - A method and apparatus for dynamically arbitrating, in hardware, requests for a resource shared among multiple clients. Multiple data streams or service requests require access to a shared resource, such as memory, communication bandwidth, etc. A hardware arbiter monitors the streams' traffic levels and determines when one or more of their arbitration weights should be adjusted. When a queue used by one of the streams is filled to a threshold level, the hardware reacts by quickly and dynamically modifying that queue's arbitration weight. Therefore, as the queue is filled or emptied to different thresholds, the queue's arbitration weight rapidly changes to accommodate the corresponding client's temporal behavior. The arbiter may also consider other factors, such as the client's type of traffic, a desired quality of service, available credits, available descriptors, etc. | 09-18-2008 |
| 20080270659 | Governing access to a computing resource - Technologies are described herein for governing access to a computing resource. A proxy receives a request to access a computing resource. In response to the request, the proxy determines whether the request can be granted without consulting a governor for the computing resource. If the request cannot be granted without consulting the governor, the proxy transmits the request to a broker. The broker, in turn, transmits the request to a governor for the computing resource. The governor determines whether the requested access to the computing resource should be granted. The governor generates a response to the request and transmits the response to the broker. The broker, in turn, transmits the response to the proxy. The broker may also request notifications from the governor. | 10-30-2008 |
| 20090055565 | MEMORY INTERFACE AND METHOD OF INTERFACING BETWEEN FUNCTIONAL ENTITIES - A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed. | 02-26-2009 |
| 20090172226 | Data processing system and method for interconnect arbitration - A data processing system comprising a plurality of processing units (Dv | 07-02-2009 |
| 20090265495 | ACCESS RIGHT MANAGING METHOD FOR ACCESSING MULTIPLE PROGRAMS - Provided is an access right managing method for a resource of a storage system, in which a management computer stores access right definition information of the resource, and resource correspondence information including information on a management program which manages another resource related to the resource managed by the management program. In case of which receiving an updating request of an access right of the resource, the management computer updates an access right based on the updating request of the access right, selects a management program of the resource whose access right is requested to be updated based on the resource correspondence information, transmits an updating request of an access right for a relative resource to a management computer which executes the selected management program, and in case of which the access right updating request of the related resource is received, updates the access right of the relative resource. | 10-22-2009 |
| 20090319711 | SYSTEM AND METHOD FOR PROVISIONING A REMOTE LIBRARY FOR AN ELECTRONIC DEVICE - The disclosure provides a system and method of provisioning a resource to an electronic device. The method comprises: after a triggering event, receiving from a network a data transmission at the device, the data transmission containing access information relating to a resource in a library that is in a remote server from the device, the resource relating to an application operating on the device; extracting the access information from the data transmission at the device; presenting the access information for the resource in a graphical user interface (GUI) on a display of the device; and after a selection event is initiated on the device for the resource, initiating a second data transmission containing a copy of the resource to the device and integrating the resource into the application as an output generated by the application. | 12-24-2009 |
| 20100005209 | ARBITRATION DEVICE FOR ARBITRATING AMONG A PLURALITY OF MASTER DEVICES, ARBITRATION METHOD, AND VIDEO PROCESSING DEVICE INCLUDING THE ARBITRATION DEVICE - An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period. | 01-07-2010 |
| 20100115167 | Shared Resource Arbitration - Masters request access to a shared resource, such as a shared bus. Usage of the shared bus by each of the masters is monitored, a request to use the shared bus by one of the masters is received, and usage of the shared bus by the master is compared with a corresponding bandwidth threshold. The request is arbitrated if the usage of the shared bus by the master is below the bandwidth threshold, and the request to use the shared bus is granted to the master based on the arbitration. | 05-06-2010 |
| 20100325327 | PROGRAMMABLE ARBITRATION DEVICE AND METHOD THEREFOR - A system includes a plurality of sources to provide information access requests. An arbiter includes an assignment module to associate a first access request from the first source to one of the plurality of arbitration slots based upon assignment information at a storage location, and a dispatch module to determine one request of a plurality of requests received at the plurality of sources to be dispatched to a resource, memory controller by a dispatch module. | 12-23-2010 |
| 20100332709 | PERFORMANCE OPTIMIZATION SYSTEM, METHOD AND PROGRAM - Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small. The performance optimization system includes: a required-period-of-time measurement unit that measures a required period of time concerning a to-be-observed access; a required-period-of-time table holding unit that holds a required-period-of-time table that consists of a plurality of table entries in which stored are measured values of the required period of time for each of classification regions produced by dividing a memory region for each of types based on the to-be-observed access to store a measured value of the required period of time; a table entry selection unit that makes a selection as to in which table entry, out of a plurality of table entries for each of the classification regions that make up the required-period-of-time table, the measured value of the required period of time is stored on the basis of the to-be-observed access; and a cache miss observation unit that detects the occurrence of a cache miss associated with the to-be-observed access. | 12-30-2010 |
| 20110055443 | MEMORY CONTROL APPARATUS AND INFORMATION PROCESSING APPARATUS INCLUDING THE SAME - Provided is a memory control apparatus including: a monitoring unit that monitors, for each of the masters, a usable bandwidth indicating an amount of memory access data to be accessed per unit time in response to a corresponding one of the access requests from the master; a holding unit that holds a predetermined request bandwidth for each of the masters; a bandwidth determining unit that determines whether or not the usable bandwidth has reached the predetermined request bandwidth for each of the masters; and a control unit that issues an advanced refresh command to the memory based on a result of the determination by the bandwidth determining unit for each of the masters, regardless of timing of a refresh cycle. | 03-03-2011 |
| 20110119421 | MULTIPLE CONCURRENT ARBITERS - Plural arbiters arbitrate over a set of queues. The arbiters are constructed as a series of pipelined stages. Conflict detection logic detects conflicts among the arbiters in arbitrating across the queues, and, when a conflict is detected, the conflict detection logic alters processing related to conflicting queues in one arbiter when another arbiter has not passed a predetermined commit point in processing the queue. | 05-19-2011 |
| 20110246695 | CONTROLLING BANDWIDTH RESERVATIONS METHOD AND APPARATUS - Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology. | 10-06-2011 |
| 20120124263 | ALLOCATING GRANT CHANNEL RESOURCES - Grant channel resources are allocated based on the number of access terminals that use different types of transmission time intervals (TTIs) for data transmissions. For example, if the number of access terminals using a first type of TTI exceeds the number of access terminals using a second type of TTI, more grant channel resources are allocated to the access terminals that use the first type of TTI. | 05-17-2012 |
| 20120271976 | Variable Length Arbitration - In one embodiment, a method determines a plurality of categories for requests for a shared resource being shared by a plurality of entities. A request for the resource is received from an entity in the plurality of entities. The method determines a category in the plurality of categories for the received request. If the received request is determined to be in a first category, the method dispatches the received request to a first arbitration scheme configured to determine an arbitration decision in a first time cycle. If the received request is determined to be in a second category, the method dispatches the received request to a second arbitration scheme configured to determine an arbitration decision in a second time cycle of a different length from the first time cycle. | 10-25-2012 |
| 20130013834 | MULTI-CORE PROCESSOR SYSTEM, ARBITER CIRCUIT CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes multiple cores; shared memory accessed by the cores; and an arbiter circuit that arbitrates contention of right to access the shared memory by the cores. Each of the cores is configured to acquire for the core, a measured speed of access to the shared memory; calculate for the core, a response performance based on the measured speed of access and a theoretical speed of access for the core; calculate for the cores and based on the response performance calculated for each of the cores, ratios of access rights to access the shared memory, the ratios being calculated such that a ratio of access rights for a given core is larger than a ratio of access rights for another core whose response performance is higher than that of the given core; and notify the arbiter circuit of the calculated ratios of access rights. | 01-10-2013 |
| 20130111090 | QUEUE ARBITRATION USING NON-STALLING REQUEST INDICATION | 05-02-2013 |
| 20130290585 | Virtualized Instruction Extensions for System Partitioning - A method and circuit for a data processing system provide virtualized instructions for accessing a partitioned device (e.g., | 10-31-2013 |
| 20130326100 | Arbiter for Asynchronous State Machines - An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched. | 12-05-2013 |
| 20140115217 | FORMAL VERIFICATION OF ARBITERS - A computer-implement method, computerized apparatus and computer program product for formal verification of an arbiter design. The method comprising: performing formal verification of an arbiter design, wherein the arbiter design is based on an original arbiter design comprising a fairness logic and an arbitration logic, wherein the arbiter design comprising the arbitration logic and a portion of the fairness logic; and wherein the formal verification is performed with respect to a multi-dimensional Complete Random Sequence (CRS) having two or more dimensions. | 04-24-2014 |
| 20140181343 | Structured Block Transfer Module, System Architecture, and Method for Transferring - Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available. | 06-26-2014 |
| 20140281086 | Arbiter for Asynchronous State Machines - An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched. | 09-18-2014 |
