| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710119000 | Decentralized bus arbitration | 25 |
| 20110283032 | ARBITRATION DEVICE - An arbitration device including: a first measuring circuit to measure a first period; a second measuring circuit to measure a second period; a second selection circuit to select and output the first period or the second period according to a first selection signal; a first control circuit to output the first selection signal according to the first period and the second period; a third selection circuit to select a third data or either the first data or the second data according to a second selection signal; a third measuring circuit to measure a third period; a fourth measuring circuit to measure a fourth period; and a second control circuit to output the second selection signal according to either the selected first period or the selected second period and the third period and the fourth period. | 11-17-2011 |
| 20120290753 | CONNECTION METHOD FOR BUS CONTROLLERS AND COMMUNICATION SYSTEM - A connection method for bus controllers is provided which includes using a logic circuit in which if both signal levels of two input terminals are recessive, a signal level of an output terminal becomes recessive, and if at least one of the signal levels of the two input terminals is dominant, a signal level of the output terminal becomes dominant, defining one of the two bus controllers, which are subject to one-on-one connection, as a first controller, defining the other of the two bus controllers as a second controller, connecting a transmitting terminal of the first controller to one of the two input terminals of the logic circuit, connecting a transmitting terminal of the second controller to the other of the two input terminals of the logic circuit, and connecting receiving terminals of the first and second controllers to the output terminal of the logic circuit. | 11-15-2012 |
| 20130013832 | BUS MONITORING DEVICE, BUS MONITORING METHOD, AND PROGRAM - A bus monitoring device may include a measurement unit configured to measure a bandwidth of data on a common bus for a unit time, which is constant and predetermined, based on transfer information indicating a state of exchange of the data when a plurality of processing blocks connected to the common bus exchange the data via the common bus with a memory including an address space having a plurality of banks. | 01-10-2013 |
| 20130103870 | INPUT OUTPUT BRIDGING - In one embodiment, a system comprises a memory, and a first bridge unit for processor access with the memory. The first bridge unit comprises a first arbitration unit that is coupled with an input-output bus, a memory free notification unit (“MFNU”), and the memory, and is configured to receive requests from the input-output bus and receive requests from the MFNU and choose among the requests to send to the memory on a first memory bus. The system further comprises a second bridge unit for packet data access with the memory that includes a second arbitration unit that is coupled with a packet input unit, a packet output unit, and the memory and is configured to receive requests from the packet input unit and receive requests from the packet output unit, and choose among the requests to send to the memory on a second memory bus. | 04-25-2013 |
| 20140317323 | Method and Apparatus for Arbitration with Multiple Source Paths - A method and apparatus for arbitration. In one embodiment, a point in a network includes first and second arbiters. Arbitration of transactions associated with an address within a first range are conducted in the first arbiter, while arbitration of transactions associated with an address within a second range are conducted in the second arbiter. Each transaction is one of a number of different transaction types having a respective priority level. A measurement circuit is coupled to receive information from the first and second arbiters each cycle indicating the type of transactions that won their respective arbitrations. The measurement circuit may update a number of credits associated with the types of winning transactions. The updated number of credits may be provided to both the first and second arbiters, and may be used as a basis for arbitration in the next cycle. | 10-23-2014 |
| 20150113189 | Issuing Requests To A Fabric - In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed. | 04-23-2015 |
| 20160140064 | DISTRIBUTED INTERRUPT SCHEME IN A MULTI-PROCESSOR SYSTEM - Methods and systems are disclosed for routing and distributing interrupts in a multi-processor computer to various processing elements within the computer. A system for distributing the interrupts may include a plurality of logic devices configured in a hierarchical tree structure that distributes incoming interrupts to interrupt redistributors (redistribution devices). The system also includes plural processing elements, where each processing element has an associated bus address. A shared serial bus couples the redistribution devices and processing elements. Each of the redistribution devices is configured to transfer the incoming interrupts to at least one of the processing elements over the common bus, based on the bus address. | 05-19-2016 |
| 710120000 | Hierarchical or multilevel accessing | 4 |
| 20090106467 | MULTIPROCESSOR APPARATUS - Disclosed is a multiprocessor apparatus including a co-processor provided in common to a plurality of processors and including a plurality of resources and an arbitration circuit that arbitrates contention among the processors with respect to use of a resource in the co-processor by the processors through a co-processor bus, which is a tightly coupled bus, for each resource or each resource hierarchy according to instructions issued from the processors to the co-processor. Under control by the arbitration circuit, simultaneous use of a plurality of resources on a same hierarchy or different hierarchies in the co-processor by the processors through the tightly coupled bus is allowed. | 04-23-2009 |
| 20090106468 | Hierarchical Bus Structure and Memory Access Protocol for Multiprocessor Systems - A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus. | 04-23-2009 |
| 20110296068 | OPTIMIZED ARBITER USING MULTI-LEVEL ARBITRATION - An apparatus comprising a first sub-arbiter circuit and a second sub-arbiter circuit. The first sub-arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. The second sub-arbiter circuit may be configured to determine a winning channel received from the plurality of channel requests based on a second criteria. The second sub-arbiter may also be configured to optimize the order of the winning channels from the first sub-arbiter by overriding the first sub-arbiter if the second criteria creates a more efficient data transfer. | 12-01-2011 |
| 20150095538 | FACILITATING RESOURCE USE IN MULTICYCLE ARBITATION FOR SINGLE CYCLE DATA TRANSFER - Techniques are disclosed to provide arbitration between input ports and output ports of a switch. For each of at least one input port of a group of input ports, a respective request is received specifying for the respective input port to be allocated a clock cycle in which to send data to a group of output ports. A grant of the request of a primary input port is issued at each clock cycle, the primary input port including a first input port of the at least one input port. Upon a determination, subsequent to a first clock cycle count elapsing, that an input arbiter has not yet accepted any grant of the request of the primary input port, a grant is issued at each clock cycle, including alternating between issuing a grant of the request of the primary input port and of an alternate input port, respectively. | 04-02-2015 |
| 710121000 | Static bus prioritization | 4 |
| 20100174840 | PRIORITIZATION FOR CONFLICT ARBITRATION IN TRANSACTIONAL MEMORY MANAGEMENT - Embodiments of the present invention provide a method, system and computer program product for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management. In an embodiment of the invention, a method for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management can include setting different hardware registers with different priority values for correspondingly different transactions in a transactional memory system configured for transactional memory management according to respective priority values specified by priority assignment logic in external software support for the system. The method also can include detecting a conflict amongst the transactions in the system. Finally, the method can include applying conflict arbitration within the system based upon the priority values specified by the priority assignment logic in the external software support for the system. | 07-08-2010 |
| 20140013019 | BUS ARBITRATION APPARATUS, BUS ARBITRATION METHOD, AND COMPUTER-READABLE STORAGE MEDIUM - A bus arbiter ( | 01-09-2014 |
| 20140047147 | BUS CONTROL DEVICE, IMAGE PROCESSING APPARATUS, AND BUS CONTROL METHOD - A bus control device includes a plurality of bus masters classified into a plurality of groups according to a priority level, a plurality of group buses each group bus being connected to a corresponding group of bus masters and assigned with a priority level determined according to the priority levels of the corresponding group of bus masters, an upper priority bus that arbitrates a plurality of bus obtaining requests received from the plurality of bus maters via the plurality of group buses, a plurality of masks respectively provided for the plurality of bus masters to mask the bus obtaining request addressed to the corresponding group bus from the corresponding bus master, and a plurality of mask controllers respectively provided for the plurality of group buses to output at least one mask signal that controls operation of at least one corresponding mask connected to the corresponding group bus. | 02-13-2014 |
| 710122000 | Physical position bus prioritization | 1 |
| 20130097349 | Quality of Service Arbitration Method and Quality of Service Arbiter Thereof - A quality of service (QoS) arbitration method for an on-chip bus is disclosed. The bus arbitration method includes steps of classifying each of a plurality of requestors into one of a plurality of first QoS types; classifying the each of the plurality of requestors into one of a plurality of second QoS types corresponding to a plurality of service priorities according to a due date or a data rate of the each of the plurality of requestors and the one of the plurality of first QoS types; and choosing a requestor with a highest service priority among the plurality of requestors to service. | 04-18-2013 |
| 710123000 | Dynamic bus prioritization | 1 |
| 20110302345 | NETWORK ON CHIP (NOC) WITH QOS FEATURES - Quality-of-Service (QoS) is an important system-level requirement in the design and implementation of on-chip networks. QoS requirements can be implemented in an on-chip-interconnect by providing for at least two signals indicating priority at a transaction-level interface where one signal transfers information in-band with the transaction and the other signal transfers information out-of-band with the transaction. The signals can be processed by the on-chip-interconnect to deliver the required QoS. In addition, the disclosed embodiments can be extended to a Network-on-Chip (NoC). | 12-08-2011 |
| 710124000 | Time-slotted bus accessing | 8 |
| 20110185095 | ARBITRATION SCHEME FOR ACCESSING A SHARED RESOURCE - A processing system includes a shared resource, an arbitration module, and a requesting device for issuing requests to the arbitration module to access the shared resource to perform transactions on the shared resource. The arbitration module grants access to the requesting device for a fixed time duration. The fixed time duration comprises one of a plurality of time durations including a first and a second time duration; the second longer than the first. The requesting device prioritizes performance of the transactions on the shared resource based upon the fixed time duration and types of transactions to be performed. Transaction type comprises one of a plurality of types including a first type that requires a time duration that can be performed within the first time duration and a second type that requires a time duration that exceeds the first time duration but can be performed within the second time duration. | 07-28-2011 |
| 20140032804 | SCHEDULED PERIPHERAL COMPONENT INTERCONNECT ARBITER - Systems and methods are described for arbitrating access of a communication bus. In one embodiment, a method includes performing steps on one or more processors. The steps include: receiving an access request from a device of the communication bus; evaluating a bus schedule to determine an importance of the device based on the access request; and selectively granting access of the communication bus to the device based on the importance of the device. | 01-30-2014 |
| 20140325106 | METHOD FOR OPERATING A BUS SYSTEM FOR COMMUNICATION WITH A PLURALITY OF COMMUNICATION NODES, AND MOTOR VEHICLE - A method operates a bus system for communication with a plurality of communication nodes, in particular in a land vehicle and/or aircraft. A static, cyclically recurring time window of fixed length each communication node is assigned a time slot for transmission of user information of a byte count that can be specified at least once and fixed during the operation of the bus system. The time window has at least two cohesive sub-time windows. The same byte count is specified for all time slots of a sub-time window. | 10-30-2014 |
| 20140325107 | RECEPTION APPARATUS, INFORMATION PROCESSING APPARATUS AND METHOD OF RECEIVING DATA - A reception apparatus that receives data through a plurality of lanes and includes a plurality of buffers that store received data, the buffers being provided for each of the plurality of lanes; a speed difference controller outputs a first timing signal for adjusting timing among the lanes, based on a communication speed on the lanes and operational clocks for the transmission apparatus and the reception apparatus; a deskew controller that outputs a second timing signal for adjusting a skew among the lanes; and a controller that adjusts timing for reading the received data from the buffers, based on a value of the second timing signal and a difference between a read position for reading the received data from the buffers and a write position for writing the received data to the buffers, in the first timing signal, upon adjusting a frequency difference between the transmission apparatus and the reception apparatus. | 10-30-2014 |
| 20150095539 | FACILITATING RESOURCE USE IN MULTICYLE ARBITRATION FOR SINGLE CYCLE DATA TRANSFER - Techniques are disclosed to provide arbitration between input ports and output ports of a switch. For each of at least one input port of a group of input ports, a respective request is received specifying for the respective input port to be allocated a clock cycle in which to send data to a group of output ports. A grant of the request of a primary input port is issued at each clock cycle, the primary input port including a first input port of the at least one input port. Upon a determination, subsequent to a first clock cycle count elapsing, that an input arbiter has not yet accepted any grant of the request of the primary input port, a grant is issued at each clock cycle, including alternating between issuing a grant of the request of the primary input port and of an alternate input port, respectively. | 04-02-2015 |
| 20150347333 | INTERCOMPONENT DATA COMMUNICATION - A request to send a message from a first component, located on a first processor, to a second component, located on a second processor, is received. It is determined that the second processor can be communicated with via a first bidirectional communication path. It is determined that bandwidth is available on the first bidirectional communication path. It is determined that bandwidth is available on a second bidirectional communication path. In response to a determination that bandwidth is available on the second bidirectional communication path, a data path is created between the first component and the second bidirectional communication path and the request to send the message to the second component is granted. In response to a determination that bandwidth is not available on the first bidirectional communication path or on the second bidirectional communication path, the grant of the request to send the message to the second component is delayed. | 12-03-2015 |
| 20150347334 | INTERCOMPONENT DATA COMMUNICATION - A request to send a first message from a first component to a second component is received at an arbiter. The first component is located in a first time zone and the second component is located in a second time zone. The arbiter determines that the second component is located in the second time zone. It is determined that the second time zone can be communicated with via one or more communications channels in a first direction. It is determined whether bandwidth is available on the one or more communications channels in the first direction. If bandwidth is available on the one or more communications channels in the first direction, a data path between the first component and the one or more communications channels in the first direction is created and the request is granted. Otherwise, the grant of the request is delayed. | 12-03-2015 |
| 20150347340 | INTERCOMPONENT DATA COMMUNICATION - A request to send a message from a first component, located on a first processor, to a second component, located on a second processor, is received. It is determined that the second processor can be communicated with via a first bidirectional communication path. It is determined that bandwidth is available on the first bidirectional communication path. It is determined that bandwidth is available on a second bidirectional communication path. In response to a determination that bandwidth is available on the second bidirectional communication path, a data path is created between the first component and the second bidirectional communication path and the request to send the message to the second component is granted. In response to a determination that bandwidth is not available on the first bidirectional communication path or on the second bidirectional communication path, the grant of the request to send the message to the second component is delayed. | 12-03-2015 |
| 710125000 | Delay reduction | 1 |
| 20110060857 | SKEW MANAGEMENT IN AN INTERCONNECTION SYSTEM - An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced. | 03-10-2011 |
