| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710118000 | Delay reduction | 14 |
| 20080209095 | STRUCTURE FOR REDUCING LATENCY ASSOCIATED WITH READ OPERATIONS IN A MEMORY SYSTEM - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus. | 08-28-2008 |
| 20080215783 | STRUCTURE FOR DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYSTEM OPERATING IN VARIABLE LATENCY MODE - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm pre-computes return time data for data connected to DRAM buffer chips and stores the return time data in a table. The return time data is expressed as data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict. | 09-04-2008 |
| 20080263247 | Gap count analysis for the P1394a BUS - A method of optimizing communication over a high-speed serial bus by minimizing the delay between packets transmitted over the bus is disclosed. The method comprises: calculating the round trip delay between PHYs connected on the bus by pinging; a bus manager sending a configuration packet to all PHYs connected on the bus, the configuration packet containing a minimum gap_count parameter value; and all PHYs connected on the bus sending packets over the bus using the minimum gap_count parameter value as a delay between packets. | 10-23-2008 |
| 20090013115 | BUS COMMUNICATION APPARATUS THAT USES SHARED MEMORY - The present invention improves bus transfer efficiency in bus communication that uses a shared memory. A communication origin master | 01-08-2009 |
| 20090013116 | DATA COMMUNICATION METHOD, DATA TRANSMISSION AND RECEPTION DEVICE AND SYSTEM | 01-08-2009 |
| 20090043933 | Skew management in an interconnection system - An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced. | 02-12-2009 |
| 20090055564 | Method for data transmission - The invention relates to a method for data transmission in a serial bus system comprising a control unit and bus users. The method comprises steps: receiving a first data telegram by a bus user from the control unit, wherein the data telegram has a data field containing output data; reading out the data field intended for the bus user from the first data telegram; preparing input data as a response to the read out data field; checking whether a predefined criterion is met, wherein if the criterion is met a second data telegram is newly generated and the input data is attached to the second data telegram and if the criterion is not met, the input data is attached to a data telegram previously received from another bus user; and transmitting the input data to the control unit by the second data telegram. | 02-26-2009 |
| 20090259787 | NOISE REDUCTION METHOD BY IMPLEMENTING CERTAIN PORT-TO-PORT DELAY - A noise reduction method by implementing certain point-to-point delay is disclosed. In this regard a method is introduced comprising determining a frequency of a greatest noise on a high-speed data link when turning on a power delivery network, determining a delay time between a first port and a second port that minimizes the greatest noise, and turning on the second port after the delay time from turning on the first port. Other embodiments are also disclosed and claimed. | 10-15-2009 |
| 20090319709 | CIRCUIT, METHOD AND ARRANGEMENT FOR IMPLEMENTING SIMPLE AND RELIABLE DISTRIBUTED ARBITRATION ON A BUS - An arbitrator circuit for accessing a bus comprises a logic gate arrangement ( | 12-24-2009 |
| 20140025855 | MEMORY SUBSYSTEM AND COMPUTER SYSTEM - The present invention provides a computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other. The computer system | 01-23-2014 |
| 20140189181 | On-Chip Bus Arbitration Method and Device Thereof - A method and device for on-chip bus arbitration are disclosed. The method includes: dividing devices into a first level, a second level and a third level from high to low; and in each arbitration period, calculating remaining processing time of each real-time transaction, and upgrading a device making a request required to be processed immediately to the first level in the current arbitration period; monitoring bandwidth usage amount of devices of the first level and the second level respectively, and downgrading a device whose bandwidth usage amount exceeds a preset bandwidth threshold value to the third level in the current arbitration period; and in devices making requests for a bus use right, if a device of the highest level is the device of the first level, authorizing the device of the first level; and if it is not the device of the first level, authorizing a device making continuous requests. | 07-03-2014 |
| 20140310437 | Round Robin Arbiter Handling Slow Transaction Sources and Preventing Block - In an embodiment, an arbiter may implement a deficit-weighted round-robin scheme having a delayed weight-reload mechanism. The delay may be greater than or equal to a ratio of the fabric clock to a slower clock associated with one or more sources that have no transactions but that have unconsumed weights (or another measure of difference in transaction rate). If a transaction is provided from the one or more sources during the delay, the reload of the weights may be prevented. In some embodiments, the arbiter may be augmented to improve usage of the bandwidth on an interface in which some transactions may be limited for a period of time. The arbiter may implement a first pointer that performs round robin arbitration. If the first pointer is indicating a source whose transaction is temporarily blocked, a second pointer may search forward from the current position of the main pointer to locate a non-blocked transaction. | 10-16-2014 |
| 20140359181 | Delaying Bus Activity To Accomodate Memory Device Processing Time - A technique includes delaying bus activity targeting a memory device and indicating a command for the memory device to allow time for the memory device to complete processing the command. The delaying of the bus activity includes selectively generating an error signal on a memory bus. | 12-04-2014 |
| 20160162426 | OPTIMAL SAMPLING OF DATA-BUS SIGNALS USING CONFIGURABLE INDIVIDUAL TIME DELAYS - A method includes receiving a group of logic signals to be sampled at a common sampling timing. Individual time delays, which individually align each of the logic signals to the common sampling timing, are selected for the respective logic signals in the group. Each of the logic signals is delayed by the respective selected individual time delay, and the entire group of the delayed logic signals is sampled at the common sampling timing. | 06-09-2016 |
