| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710117000 | Time-slotted bus accessing | 44 |
| 20080215782 | Administration Device For Warranting Local Concentrated Access in Low-Band Width, Administration Method, and Animation Processing Apparatus Including the Administration Device - An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period. | 09-04-2008 |
| 20080256278 | Method and System for Bus Arbitration - A method and system for bus arbitration to be used in a system having a plurality of data handling units ( | 10-16-2008 |
| 20080270658 | PROCESSOR SYSTEM, BUS CONTROLLING METHOD, AND SEMICONDUCTOR DEVICE - Provided is a simply structured multiprocessor system which equally distributes access performance for accessing a shared memory among plural master units accessing the shared memory. The multiprocessor system includes plural master units PU | 10-30-2008 |
| 20080276024 | Method for Stabilizing Asynchronous Interfaces - A method and computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow for the holding of previous stable data during the transition. While the processing logic employed specifically applies to asynchronous logic, the logic can be extended to synchronous or untimed interfaces as well. Also disclosed is a programmable means to adjust the window delay. | 11-06-2008 |
| 20080282008 | System and Apparatus for Early Fixed Latency Subtractive Decoding - Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period. | 11-13-2008 |
| 20080313375 | Bus Station and System and Method of Maintaining Synchronizing of a Bus Station - A bus station circuit ( | 12-18-2008 |
| 20090024778 | Memory controller, bus system, integrated circuit, and control method of integrated circuit - An integrated circuit including: a bus system including a bus master connected to a bus; and a memory controller connected to the bus system and controlling a connection between the bus master and a memory, in which the bus system includes a counter counting a waiting time from a time the bus master outputs a memory access request until a time a connection between the bus master and the memory controller is established, and the memory controller controls a memory access based on the waiting time counted by the counter. | 01-22-2009 |
| 20090049217 | I/O-REQUEST PROCESSING SYSTEM AND METHOD - An I/O-request processing system which is capable of reducing the maximum value of the time required until the I/O request of each external device is registered. An I/O-request receiving section ( | 02-19-2009 |
| 20090106466 | DESIGN STRUCTURE FOR PIGGYBACKING MULTIPLE DATA TENURES ON A SINGLE DATA BUS GRANT TO ACHIEVE HIGHER BUS UTILIZATION - A design structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization is disclosed. In one embodiment of the design structure, a method in a computer-aided design system includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant. | 04-23-2009 |
| 20090119433 | DATA PROCESSING SYSTEM AND METHOD FOR MEMORY ARBITRATION - The present invention relates to a data processing system is provided which comprises at least one first processing unit (CPU), at least one second processing unit (PU), at least one memory module (MEM), and an interconnect. The memory module (MEM) serves to store data from said at least one first and second processing unit (CPU, PU). The interconnecting means couples the memory module (MEM) to the first and second processing units (CPU, PU). In addition, an arbitration unit (AU.) is provided for performing the arbitration to the memory module (MEM) of the first and second processing units (CPU, PU). The arbitration is performed on a time window basis. A first access time during which the second processing unit (PU) has accessed the memory module and a second access time which is still required by the second processing unit (PU) to complete its processing are monitored during a predefined time window by the arbitration unit (AU). The second access time is compared to the remaining access time in the time window and if the remaining access time is larger than the second access time, the arbitration unit (AU) allows said at least one first processing unit (CPU) to access the memory module in said time window. Otherwise, the arbitration unit (AU) restricts the access of the at least one first processing units (CPU) and allows the at least one second processing unit (PU) to access the memory module (MEM). | 05-07-2009 |
| 20090164681 | Portable Module Interface with Timeout Prevention by Dummy Blocks - Methods and systems for working around the timeout limitations of physical interface standards for detachable modules. By use of dummy data blocks to keep the bus active, the bus timeout requirements (in either direction) can be spoofed, to thereby permit more complex processing operations to be performed, which otherwise might not fit reliably within the timeout period. This permits a memory system to execute applications or process data for a time period that may exceed the bus timeout of a particular specification. A controller in the memory system deasserts the ready signal and holds the bus connecting the computer system in a “busy” state until the memory system is about to timeout. During a write operation, the controller receives dummy data blocks from the computer system before the write bus timeout period expires, causing the bus timeout period to be reset. During a read operation, the controller sends dummy data blocks to the computer system before the read bus timeout period expires, causing the bus timeout period to be reset. | 06-25-2009 |
| 20090210598 | MULTI-CORE DATA PROCESSOR - To provide a multi-core LSI capable of improving the stability of operation. A multi-core LSI comprises a plurality of CPUs coupled to a first shared bus, one or more modules coupled to a second shared bus, a shared bus controller coupled between the first shared bus and the second shared bus, for arbitrating an access to the module(s) by the CPUs, and a system controller that monitors whether or not a response signal to an access request signal of the CPUs is output from module to be accessed, wherein the system controller outputs a pseudo response signal to the first shared bus via the shared bus controller to terminate the access by the CPU while accessing if the response signal is not output from the module to be accessed after the access request signal is output to the second shared bus from the shared bus controller and before a predetermined time elapses. | 08-20-2009 |
| 20100057964 | METHODS AND CONTROLLERS FOR AFFILIATION MANAGMENT - Methods and systems for managing Serial Advanced Technology Attachment (“SATA”) affiliation transfers between a requesting controller and a granting controller of a storage system. After receiving an affiliation request from the requesting controller, the granting controller queries a number of commands that are queued locally at the granting controller. The granting controller grants the affiliation to the requesting controller after a period of time that is determined based on the queried number of commands that are queue locally. | 03-04-2010 |
| 20100070666 | SYSTEM, APPARATUS AND METHOD FOR GRANTING ACCESS TO A SHARED COMMUNICATIONS BUS - Systems, apparatuses and methods for timing access to a shared communications bus by a plurality of devices. Each of a plurality of nodes is successively provided an opportunity to gain access to a shared bus according to a time slot allocation referenced from a time reference. The successive time slot allocation occurs until one of the nodes has a message to send via the shared bus. The node that has the message to send transmits a frame onto the bus. A new time reference is established at each of the nodes based on an indication provided by the transmitted frame, whereby each of the nodes can then be afforded a new opportunity to gain access to the shared bus according to the time slot allocation referenced from the new time reference. | 03-18-2010 |
| 20100070667 | Arbitration Based Allocation of a Shared Resource with Reduced Latencies - A digital processing system employing multiple arbiters, all designed to allocate a resource to a same entity in response to a same condition. In an embodiment, the entities needing the resource may send a request to all the arbiters, and the specific entity to which the resource is allocated, receives indication of the allocation from a closest one of the arbiters. As a result, the latency in receipt of indication of allocation may be reduced. The features are described in the context of a bus as a resource. | 03-18-2010 |
| 20100095036 | Priority Based Bus Arbiters Avoiding Deadlock And Starvation On Buses That Support Retrying Of Transactions - A scheduler provided according to an aspect of the present invention provides higher priority for data units in a low priority queue upon occurrence of a starvation condition, and to packets in a high priority queue otherwise. The scheduler permits retransmission of a data unit in the lower priority queue when in the starvation condition, but clears the starvation condition when the data unit is retransmitted a pre-specified number of times. As a result, the data units in the higher priority queue would continue to be processed, thereby avoiding a deadlock at least in certain situations. | 04-15-2010 |
| 20100180058 | Communication System, Communication Apparatus, Communication Method, and Computer Program - In a WUSB communication environment in which isochronous transfer cannot be used, priority communication is performed in units of devices. A WUSB host manages assigning of a band of reserved one or more MASs in a superframe by using a device information management table, in which device information entries each describing, in a bitmap format, a MAS for which a transaction can be executed are each provided for a WUSB device. The WUSB host assigns at least some of the reserved one or more MASs only to a particular WUSB device. Only a WUSB device marked in a corresponding device information entry serves as a target of transaction scheduling. | 07-15-2010 |
| 20100217904 | INFORMATION PROCESSING APPARATUS, METHOD THEREOF, AND STORAGE MEDIUM - An information processing apparatus includes a plurality of modules connected in a ring shape via a bus, and each module processes a packet flowing in a single direction on the ring in a predetermined order. The module includes a communication unit for transmitting a packet received from a first direction in the ring via the bus to a second direction, a discrimination unit for discriminating a packet from among the packets received from the first direction as a processing packet to be processed by the module, and a processing unit which is connected with the communication unit one by one and configured to process the processing packet. The communication unit transmits the packet processed by the processing unit at an interval equivalent to processing time or more for a processing packet processed by a module in a latter stage in the predetermined order among packets transmitted by the communication unit to the second direction. | 08-26-2010 |
| 20110179208 | TIME DIVISION MULTIPLEXING BASED ARBITRATION FOR SHARED OPTICAL LINKS - A method for arbitration including selecting, for an arbitration interval corresponding to a timeslot, a sending node from a plurality of sending nodes in an arbitration domain, where the plurality of sending nodes include a plurality of source counters; broadcasting, by the sending node and in response to selecting the sending node, a transmitter arbitration request for the timeslot during the arbitration interval; receiving, by the plurality of sending nodes, the transmitter arbitration request; incrementing the plurality of source counters in response to receiving the transmitter arbitration request; and sending, during the timeslot, a data item from the sending node to a receiving node via an optical data channel. | 07-21-2011 |
| 20110252171 | REDUCING SIMULTANEOUS SWITCHING OUTPUTS USING DATA BUS INVERSION SIGNALING - An apparatus includes a plurality of data lines defining a data bus for communicating data. A controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector. | 10-13-2011 |
| 20120072630 | TIME AND EVENT BASED MESSAGE TRANSMISSION - A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus and to confirm a trigger condition. A module is configured to send a message over the communication bus when the trigger condition is confirmed. | 03-22-2012 |
| 20120331197 | Memory controller and method of operation of such a memory controller - A memory controller is for controlling access to a memory device of the type having a non-uniform access timing characteristic. An interface receives transactions issued from at least one transaction source and a buffer temporarily stores as pending transactions those transactions received by the interface that have not yet been issued to the memory device. The buffer maintains a plurality of ordered lists (having a number of entries) for the stored pending transactions, including at least one priority based ordered list and at least one access timing ordered list. Each entry being associated with one of the pending transactions, and ordered within its priority based ordered list based on the priority indication of the associated pending transaction. Arbitration circuitry performs an arbitration operation during which the plurality of ordered lists are referenced so as to select a winning transaction to be issued to the memory device. | 12-27-2012 |
| 20130117484 | TIME AND EVENT BASED MESSAGE TRANSMISSION - A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus and to confirm a trigger condition. A module is configured to send a message over the communication bus when the trigger condition is confirmed. | 05-09-2013 |
| 20130238826 | DEVICE AND METHOD FOR GLOBAL TIME INFORMATION IN EVENT-CONTROLLED BUS COMMUNICATION - In a method for exchanging data in messages between users of a CAN bus system, the users have their own time bases; a first user functioning as timer transmits a reference message having a specifiable identifier via the bus, which includes a first time information with regard to the time base of the first user; the at least second user, using its time base forms its own second time information as a function of the first time information of the first user in such a way that, from the deviation of the first and the second time information a correction value is ascertained, so that from the first time information of the first user as the timer, the global time for the bus system is yielded. | 09-12-2013 |
| 20140040518 | MEMORY INTERFACE - The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation. | 02-06-2014 |
| 20140143464 | SAS EXPANDER - A SAS expander includes a receiver module, a timer module and an arbitration module. The receiver module is to receive initiator requests which include initiator wait time values and specify requested targets. The timer module has timers to generate total wait time values representing length or time the initiators having been waiting for the specified requested targets. The timers are to be initialized with wait time values comprising the initiator request wait time values and user-defined wait time values. The arbitration module is to select an initiator request having the highest total wait time value from among the initiator requests requesting the same targets. | 05-22-2014 |
| 20140156893 | Can bus edge timing control apparatus, systems and methods - Structures and methods herein insert one or more parallel “recessive nulling” driver impedances across a controller area network (CAN) bus starting at the time of a dominant-to-recessive data bit transition and extending for a selected recessive nulling time period. Doing so increases a rate of decay of a CAN bus dominant-to-recessive differential signal waveform, permits a shortened recessive bit time period, and allows for increased CAN bus bandwidth. Various modes of operation are applicable to various CAN bus node topologies. Recessive nulling may be applied to only the beginning portion of a recessive bit following a dominant bit (“LRN mode”) or to the entire recessive bit time (“HRN mode”). And, some embodiments may apply LRN operations to some recessive CAN frame bits and HRN operations to others. | 06-05-2014 |
| 20140189180 | METHOD AND SYSTEM FOR CHANGING BUS DIRECTION IN MEMORY SYSTEMS - A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined. The commands are then categorized as either page movement commands or data movement commands. The page movement commands or data movement commands are sent to the memory device based upon a signal indicating a current direction of a data bus providing communication between the memory controller and the memory device and further based upon a priority level. | 07-03-2014 |
| 20140223057 | TIME AND EVENT BASED MESSAGE TRANSMISSION - A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus. A module is configured to send a message over the communication bus. | 08-07-2014 |
| 20150046617 | SYSTEM AND METHOD FOR SCALABLE TRACE UNIT TIMESTAMPING - An integrated circuit includes a trace subsystem that provides timestamps for events occurring in a trace source that does not natively support time stamping trace data. A timestamp inserter is coupled to such a trace source. The timestamp inserter generates a modified trace data stream by arranging a reference or references with the trace information from the trace source on a trace bus. A trace destination receives the modified trace data stream including the reference(s). In some embodiments, a timestamp inserter receives a timestamp request and stores a reference in a buffer. Upon later receipt of trace information associated with the request, the timestamp inserter inserts the reference, a current reference and the received trace information into the trace data stream. | 02-12-2015 |
| 20150074308 | CIRCUIT FOR USING SHARED MEMORY, AND METHOD OF STORING DETERMINATION RESULT OF ARBITRATION CONTENT OF ARBITRATOR OF THIS CIRCUIT - According to an embodiment, a circuit for using a shared memory is provided, which has a plurality of function circuits, a bus, an arbitrator, and a communication measuring device. Each of a plurality of the function circuits performs a prescribed calculation. The bus communicates an input/output signal of each of the function circuits. The arbitrator assigns a use right of the bus to each of the function circuits. The communication measuring device measures a communication time of each of the function circuits, determines whether or not the measured communication time is within a range of a reference communication time set for each of the function circuits, and stores this determination result in a determination result storage device accessible from outside. | 03-12-2015 |
| 20150127864 | HARDWARE FIRST COME FIRST SERVE ARBITER USING MULTIPLE REQUEST BUCKETS - A First Come First Server (FCFS) arbiter that receives a request to utilize a shared resource from a plurality of devices and in response generates a grant value indicating if the request is granted. The FCFS arbiter includes a circuit and a storage device. The circuit receives a first request and a grant enable during a first clock cycle and outputs a grant value. The grant enable is received from a shared resource. The grant value communicated to the source of the first request. The storage device includes a plurality of request buckets. The first request is stored in a first request bucket when the first request is not granted during the first clock cycle and is moved from the first request bucket to a second request bucket when the first request is not granted during a second clock cycle. A granted request is cleared from all request buckets. | 05-07-2015 |
| 20150363166 | TRANSLATION LAYER FOR CONTROLLING BUS ACCESS - A translation layer includes a plurality of first buffers and a controller to assert one or more ready signals corresponding to one or more of the plurality of first buffers in response to the one or more of the plurality of first buffers being less than full. The one or more of the plurality of first buffers receives data or control information from one or more corresponding components in response to the ready signal being asserted concurrently with one or more valid signals asserted by the one or more corresponding components. | 12-17-2015 |
| 20150363342 | Storage Module and Method for Determining Ready/Busy Status of a Plurality of Memory Dies - A storage module and method are provided for determining ready/busy status of a plurality of memory dies. In one embodiment, a bus has a ready/busy line that is shared among the plurality of memory dies, and a time-division multiplex signal on the shared ready/busy line is used to communicate the ready/busy status of each of the memory dies. In another embodiment, each of the memory dies sends its ready/busy status to the storage controller using a different one of a plurality of data lines in the bus. In yet another embodiment, each of the memory dies sends a pulse across the ready/busy line with a different pulse width. To avoid collisions, each memory die waits a different number of clock cycles before attempting to send its pulse status after determining that the shared ready/busy line is in use. | 12-17-2015 |
| 20150378953 | OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS - Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control. | 12-31-2015 |
| 20160019171 | TIME MULTIPLEXING AT DIFFERENT RATES TO ACCESS DIFFERENT MEMORY TYPES - A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is transferred over the bus at one rate when accessing one type of memory device and at a different rate when accessing another type of memory device. In addition, the memory controller may provide control information (e.g., command and address information) to the different types of memory devices at different rates and, in some cases, time multiplex the control information on a shared bus. | 01-21-2016 |
| 20160019176 | IMPLEMENTING DYNAMIC ADJUSTMENT OF I/O BANDWIDTH FOR VIRTUAL MACHINES USING A SINGLE ROOT I/O VIRTUALIZATION (SRIOV) ADAPTER - A method, system and computer program product are provided for implementing dynamic adjustment of Input/Output bandwidth for Virtual Machines of a Single Root Input/Output Virtualization (SRIOV) adapter. The SRIOV adapter includes a plurality of virtual functions (VFs). Each individual virtual function (VF) is enabled to be explicitly assigned to a Virtual Machine (VM); and each of a plurality of VF teams is created with one or more VFs and is assigned to a VM. Each VF team is enabled to be dynamically resizable for dynamic adjustment of Input/Output bandwidth. | 01-21-2016 |
| 20160103779 | METHODS AND SYSTEMS FOR SHARING INFORMATION BETWEEN PROCESSORS - Methods and systems for sharing access to a computer resource accessible by a bus between two controllers are provided. For example, a machine implemented method of sharing access to computer resources includes requesting access to a bus from a processor of a first controller to access a device shared with a processor of a second controller; waiting for a positive response from the second controller; when the positive response is received, accessing the bus for less than a first timeout period; resetting a timer before the timer reaches the first timeout period to extend access to the bus, when access is not complete and a total access time is less than a second timeout period; and releasing the bus when access is complete or the second timeout period has been reached. | 04-14-2016 |
| 20160132449 | NETWORK CONTROLLER - SIDEBAND INTERFACE PORT CONTROLLER - A network interface controller includes a media access controller and a host adapter. The host adapter includes a transmit route connected to receive an in-band packet from a host and further connected to transmit the in-band packet to the media access controller. The network interface controller also includes a sideband port controller connected to receive a sideband packet destined for a network from a sideband endpoint and further connected to transmit the sideband packet to the host adapter. The host adapter further includes a host buffer to store the in-band packet, a sideband buffer to store the sideband packet, and an arbiter connected to allow, at different times, the in-band packet to advance along the transmit route from the host buffer to the media access controller and the sideband packet to advance along the transmit route from the sideband buffer to the media access controller. | 05-12-2016 |
| 20160132450 | NETWORK CONTROLLER - SIDEBAND INTERFACE PORT CONTROLLER - A network interface controller includes a media access controller connected to receive an in-band packet and further connected to receive a sideband packet. The network interface controller includes a host adapter that includes a receive route connected to receive the in-band packet and the sideband packet from the media access controller, and further connected to transmit the in-band packet to a host. The network interface controller includes a sideband port controller comprising a sideband receive buffer. The host adapter further includes a first receive buffer to store the in-band packet and to store the sideband packet. The host adapter further includes an arbiter connected to allow, at a time, the in-band packet to advance from the first receive buffer along the receive route towards the host and further connected to allow, at a different time, the sideband packet to advance to the sideband receive buffer of the sideband port controller. | 05-12-2016 |
| 20160147685 | ARBITRATION IN AN SRIOV ENVIRONMENT - In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice. | 05-26-2016 |
| 20160147687 | ARBITRATION IN AN SRIOV ENVIRONMENT - In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice. | 05-26-2016 |
| 20160154753 | Computing architecture with peripherals | 06-02-2016 |
| 20170235693 | OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS | 08-17-2017 |
