Class / Patent application number | Description | Number of patent applications / Date published |
710116000 | Dynamic bus prioritization | 22 |
20090019202 | System and method for dynamic information handling system prioritization - Modular information handling systems supported in a modular chassis, such as blade information handling systems, have power allocation managed by dynamic and automated prioritization of power application to each modular information handling systems. A priority list of modular information handling systems is generated and updated by analysis of priority factors discovered from the modular information handling systems, such as with periodic polling of the modular information handling systems or detection of predetermined events at the information handling systems. | 01-15-2009 |
20090024777 | ARBITER AND ARBITRATION METHOD OF MULTIPLE DATA ACCESSES - There is provided a technique which reduces an average processing time of low-priority accesses with suppressing an average delay increase of a high-priority access processing even in a case where high-priority access request and a low-request access request are simultaneously generated to a shared access processing unit and high-priority accesses are continuously generated. And, there is provided an access arbitration equipment comprising: an issued access request retention unit; a first interval determination circuit; and a second interval determination circuit. In a case where the first interval determination circuit determines that an interval is generated between an issued access processing and a most prior access processing and a second interval determination circuit determines that no interval is generated between the issued access processing and a second-prior access request, the priority order of the most prior access request and the second-prior access request is changed. | 01-22-2009 |
20100057963 | REQUEST ARBITRATION APPARATUS AND REQUEST ARBITRATION METHOD - There is provided a request arbitration apparatus for arbitrating a plurality of request holding sections which hold requests having priorities when the requests are output from the plurality of request holding sections to the output device. The request arbitration apparatus includes: a setting section that sets the request holding section, which holds the highest priority request among all the requests held by the plurality of request holding sections, as a highest priority request holding section; and a control section that controls the highest priority request holding section so that the request held first among all the requests held by the highest priority request holding section is output to the output device. | 03-04-2010 |
20110022756 | Data Space Arbiter - A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data space arbiter is programmable in a non-default mode to raise a priority of any of the secondary bus masters to have a priority higher than the priority of the default bus master while maintaining the predetermined priority relationship to only those secondary bus masters for which the priority level also has been raised above the priority of the default bus master. | 01-27-2011 |
20120185627 | BUS HOST CONTROLLER AND METHOD THEREOF - A bus host controller and a method thereof are provided. If a terminal device coupled to the bus is a non-periodic device, the bus host controller places a higher priority on data packet transferring request than start-of-frame (SOF) packet transferring request. | 07-19-2012 |
20120254491 | PRIORITY ARBITRATION CONTROL WITHIN INTERCONNECT CIRCUITRY - Interconnect circuitry | 10-04-2012 |
20140006665 | RESOURCE REQUEST ARBITRATION DEVICE, RESOURCE REQUEST ARBITRATION SYSTEM, RESOURCE REQUEST ARBITRATION METHOD, INTEGRATED CIRCUIT, AND PROGRAM | 01-02-2014 |
20140019655 | SINGLE CYCLE ARBITRATION - An interconnect 6 within an integrated circuit 2 provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service). | 01-16-2014 |
20140201408 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A system can include at least one processor module, including an in-line module connector configured to physically connect the processor module to at least one in-line memory slot of a system memory bus; at least one memory; at least one offload processor mounted on the module, and configured to execute operations on data received over the system memory bus, and to output context data to the memory, and read context data from the memory; and hardware scheduling logic including an arbiter that arbitrates between conflicting data access requirements within the processor module, and a scheduler to order computing tasks, both arbiter and scheduler being mounted on the module and configured to control operations of the at least one processor. | 07-17-2014 |
20140201409 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A processor module can include an in-line module connector configured to physically connect to an in-line memory slot of a system memory bus; a data interface configured to receive write data from the system memory bus, via the in-line module connector, and according to a predetermined protocol; and at least one offload processor configured to process the write data according to instruction data within the write data; and wherein hardware scheduling logic mounted in the processor module include an arbiter that arbitrates between conflicting data access requirements within the processor module, and a scheduler to order computing tasks, both arbiter and scheduler being mounted on the in-line module and configured to control operations of the at least one offload processor. | 07-17-2014 |
20140201410 | METHOD AND APPARATUS FOR ADAPTING THE DATA TRANSMISSION SECURITY IN A SERIAL BUS SYSTEM - In a bus system that includes at least two subscribed data processing units that exchange messages via a bus in a serial data transmission, the transmitted messages are of a logical structure that includes a start-of-frame bit, an arbitration field, a control field, a data field, a CRC field, an acknowledge field and an end-of-frame sequence, the control field including a data length code, which contains information regarding the length of the data field. The CRC field of the messages can include any of two or more different numbers of bits depending on a value of an associated switchover condition (UB3). | 07-17-2014 |
20140223055 | Controlling Bus Access in a Real-Time Computer System - In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described. | 08-07-2014 |
20140223056 | Controlling Bus Access Priority in a Real-Time Computer System - In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described. | 08-07-2014 |
20140244875 | Priority Based Connection Arbitration in a SAS Topology to Facilitate Quality of Service (QoS) in SAS Transport - A method of priority based connection arbitration in a SAS topology is disclosed introducing a PRIORITY field to an SAS open Address Frame (OAF). As the expander arbitrates the multiple OAFs in competition for an Expander Link, it compares the PRIORITY fields of the arbitrating OAFs. The OAF with highest value of PRIORITY is awarded the destination connection path. In case of equal PRIORITY, the next arbitration is based on the value of Arbitration Wait Time (AWT). This priority based arbitration ensures high availability of SAS connection links to the SAS targets with high priority OAFs which in turn will lead to better quality of service for those SAS targets. PRIORITY field in the OAF is set by the SAS targets based on the current OAF priority and also set by directly attached SAS storage expanders through a modification of the OAF during transit through the expander. | 08-28-2014 |
20150058508 | Dynamic Shifting of Service Bus Components - Systems and methods are disclosed for processing messages using a dynamic messaging bus. An example system includes a plurality of services residing in a dynamic messaging bus including a plurality of sub-buses. Each service is assigned to a sub-bus of the plurality of sub-buses. The example system also includes a performance monitoring module that monitors a performance of one or more services executing on a sub-bus to which the respective one or more services is assigned. A first service is assigned to a first sub-bus and a second service is assigned to a second sub-bus. The example system further includes a swapping module that determines, based on the monitored performances of the first and second services, whether to swap the assignments of the first and second services such that the first service is assigned to the second sub-bus and the second service is assigned to the first sub-bus. | 02-26-2015 |
20150067213 | BUS ACCESS ARBITER AND METHOD OF BUS ARBITRATION - A bus access arbiter includes an access mode judgment unit and a round robin arbitration unit. The access mode judgment unit judges, when bus access is generated from a plurality of masters M0 and M1, whether an access mode of each of the masters that are connected is a sequential access mode or a single access mode. The round robin arbitration unit dynamically switches an access arbitration method for arbitrating the bus access according to the access mode. The access mode judgment unit includes an access interval count unit, a sequential access number count unit, and an access mode state register that stores a state of the judged access mode for each of the masters, and updates the state of the access mode based on an access interval and the number of sequential access. | 03-05-2015 |
20150081941 | SHARED RECEIVE QUEUE ALLOCATION FOR NETWORK ON A CHIP COMMUNICATION - A circuit arrangement, method, and program product for communicating data in a processing architecture comprising a plurality of interconnected IP blocks. Transmitting IP blocks may transmit messages to a shared receive queue for a first IP block. Receipt of the messages at the shared receive queue may be controlled based on receive credits allocated to each transmitting IP block. The allocation of receive credits for each transmitting IP block may dynamically managed such that the allocation of receive credits may be dynamically adjusted for each transmitting IP block based at least in part on message traffic associated with each transmitting IP block and/or a priority associated with each transmitting IP block. | 03-19-2015 |
20150370736 | SHARED RECEIVE QUEUE ALLOCATION FOR NETWORK ON A CHIP COMMUNICATION - A method for communicating data in a processing architecture comprising a plurality of interconnected IP blocks. Transmitting IP blocks may transmit messages to a shared receive queue for a first IP block. Receipt of the messages at the shared receive queue may be controlled based on receive credits allocated to each transmitting IP block. The allocation of receive credits for each transmitting IP block may dynamically managed such that the allocation of receive credits may be dynamically adjusted for each transmitting IP block based at least in part on message traffic associated with each transmitting IP block and/or a priority associated with each transmitting IP block. | 12-24-2015 |
20160034411 | Subsystem Peripheral Ownership Scheduling and Reconfiguration for Highly Integrated System on Chips - Herein disclosed are systems, methods, and apparatus for dynamic switching of bus ownership, and in particular, for dynamic switching of peripheral bus ownership as well as all subsystems and/or peripherals on the bus. A peripheral bus access manager is distributed across multiple subsystems and controls access to a peripheral bus controller. The peripheral bus access manager also determines which subsystem should own the bus and then arbitrates access to the peripheral bus controller in order to indirectly make a desired subsystem the peripheral bus owner. | 02-04-2016 |
20160041935 | ELECTRONIC DEVICE, COMMUNICATION CONTROL CIRCUIT, AND COMMUNICATION CONTROL METHOD - An electronic device includes a communication unit configured to be connected to another communication unit via a first number of transmission paths, where the first number is greater than or equal to two, and a control unit configured to determine communication quality in each of the first number of the transmission paths at a time of initiating communication with the other communication unit and to select a second number of transmission paths, where the second number is less than the first number, in descending order of the communication quality from among the first number of the transmission paths, thereby causing the communication unit to perform communication by using the second number of the transmission paths, which have better communication quality. | 02-11-2016 |
20160062937 | Arbitration Signaling within a Multimedia High Definition Link (MHL 3) Device - An apparatus for interfacing with a multimedia communication link comprises a half-duplex translation layer circuit operating in half-duplex and a full-duplex link layer circuit to communicate over a control bus of the multimedia communication link in full duplex. The apparatus further comprises an arbitration circuit communicatively coupled between the half-duplex translation layer circuit and the full-duplex link layer circuit, the arbitration circuit to control data flow between the half-duplex translation layer circuit and the full-duplex link layer circuit. The arbitration circuit provides interface and signaling rules for transmitting packets from the half-duplex translation layer circuit to the full-duplex link layer circuit, receiving packets via the full-duplex link layer circuit at the half-duplex translation layer circuit, and resolving conflict arising due to bidirectional data flow at the arbitration logic. | 03-03-2016 |
20160132447 | AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE - In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed. | 05-12-2016 |