| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710112000 | Bus request queuing | 24 |
| 20080294823 | CREATING A CHECKPOINT FOR A SOFTWARE PARTITION IN AN ASYNCHRONOUS INPUT/OUTPUT ENVIRONMENT - A computer implemented method, apparatus, and computer program product for creating a checkpoint for a software partition. A checkpoint request is received for creating the checkpoint for the software partition. Each process in a set of processes in the software partition is frozen to form a set of frozen processes. In an asynchronous input/output queue, the status of each input/output request sent by the set of frozen processes is set to “suspended” to form a set of suspended requests, wherein the set of suspended requests are not performed. The set of suspended requests are stored in the checkpoint to form stored requests. | 11-27-2008 |
| 20090006689 | COMMAND QUEUE MANAGEMENT OF BACK WATERED REQUESTS - Apparatus and method for command queue management of back watered requests. A selected request is released from a command queue, and further release of requests from the queue is interrupted when a total number of subsequently completed requests reaches a predetermined threshold. | 01-01-2009 |
| 20090083466 | MESSAGE HANDLER AND METHOD FOR CONTROLLING ACCESS TO DATA OF A MESSAGE MEMORY OF A COMMUNICATIONS MODULE - A method for controlling access to data of a message memory, and a message handler of a communications module having a message memory, in which data are input or output in response to an access; the message memory being connected to a first buffer configuration and a second buffer configuration, and the data being accessed via the first or the second buffer configuration; in the message handler, at least one first finite state machine being provided which controls the access to the message memory via the first buffer configuration, and at least one second finite state machine being provided which controls the access via the second buffer configuration, the at least one first finite state machine and the second finite state machine making access requests; and a third finite state machine being provided which assigns access to the message memory to the at least one first and the second finite state machine as a function of their access requests. | 03-26-2009 |
| 20090100206 | Memory and I/O Bridge - The present invention is directed to an improved memory and I/O bridge that provides an improved interface for communicating data between the data bus of the system processor and the memory controller. The memory and I/O bus bridge according to the present invention provides increased performance in the system. The memory and I/O bridge can include a deep memory access request FIFO to queue up memory access requests when the memory controller is busy. The memory and I/O bridge can include a memory write data buffer for holding and merging memory write operations to the same page of memory. The memory and I/O bridge can include a memory read data buffer for holding and queuing data and instructions read from memory, waiting to be forward to the data bus. The memory data read buffer can operate in one or more software selectable prefetch modes, which can cause one or more pages to be read in response to a single memory read instruction. The memory read data buffer can satisfy memory read request for data or instructions already held in the memory read buffer without reading the data or instructions from memory. The memory read data buffer can also provide for data coherency with respect the memory write data buffer and the external memory. The memory and I/O bridge can also include performance counters for tracking information about the performance of the memory and I/O bridge in order to tune the software operation and determine the optimum prefetch mode for a given application. | 04-16-2009 |
| 20090216927 | MANAGING RECOVERY AND CONTROL OF A COMMUNICATIONS LINK VIA OUT-OF-BAND SIGNALING - A computer program product, apparatus and method for managing recovery and control of a communications link via out-of-band signaling. An exemplary embodiment includes sending a command, sending an invalidate request to a buffer associated with the command and receiving a response to the invalidate request at least one of prior to the command reaching the recipient and after the command reaching the recipient. | 08-27-2009 |
| 20090300248 | MANAGING READ REQUESTS FROM MULTIPLE REQUESTORS - Techniques are described herein for expanding the range of data targeted in I/O requests made by clients, so that the expanded range results in aligned I/O operations within the file system. Data that is included in the expanded range, but was not actually requested by the client, is trimmed off the data chunk returned by the file system, so that the client receives only the data required by the client. The blocks that contain the partially-read data are cached, so that they can be provided to the clients in response to subsequent I/O requests, without having to retrieve the blocks again from the file system. The I/O requests of multiple clients are handled by a read scheduler that uses a single global queue for all such requests. When appropriate, the read scheduler creates companionship relationships between the requests, and services the “companion” requests based on the data returned for the requests with which the companion requests are associated. | 12-03-2009 |
| 20100023664 | BUS SYSTEM AND OPERATING METHOD THEREOF - An operating method applied to an out-of-order executive bus system includes: according to dependency constraints, linking requests using the bus system to form dependency request links having an order; and processing the order of the requests according to the dependency request links. In addition, a bus system is provided. The bus system includes a request queue and a dependency request link generator. The request queue receives and stores a newly received request including at least a link tag. The dependency request link generator generates N dependency request links according to dependency constraints of N link tags of the newly received request, where N is any positive integer. Each link tag of the newly received request is implemented to indicate a link relation with respect to an order of the newly received request and a plurality of unserved requests preceding the newly received request. | 01-28-2010 |
| 20100036984 | METHOD AND APPARATUS FOR PREVENTING BUS LIVELOCK DUE TO EXCESSIVE MMIO - The disclosure relates to a method and apparatus to efficiently address livelock in a multi-processor system. In one embodiment, the disclosure is directed to a method for preventing a system bus livelock in a system having a plurality of processors communicating respectively through a plurality of bus masters to a plurality of IO Controllers across a system bus by: receiving at an MMIO state machine a plurality of snoop commands issued from the plurality of processors, identifying a first processor and a second processor from the plurality of processors, each of the first processor and the second processor having a first number of snoop commands in the input queue and a second number of responses in the output queue, the first number and the second number exceeding a threshold; issuing a burst prevention response to the first processor and the second process. | 02-11-2010 |
| 20100312935 | DATA PROCESSING SYSTEM - In a hierarchical bus structure employing a fixed-priority bus access arbitration scheme, accurate arbitration of bus access requests can be carried out even in situations where priority levels are updated according to a system operation mode. In each of a plurality of superordinate hierarchical bus circuits, access requests from respective bus masters included in each corresponding bus master group are arbitrated according to priority levels assigned thereto, and based on the result of the arbitration, a priority communication signal PRA/PRB indicating a priority level of each access-request-permitted bus master is fed to a subordinate bus controller. In a subordinate hierarchical bus circuit, under control of the subordinate bus controller, access request arbitration is carried out according to the priority communication signal PRA/PRB to select a superordinate hierarchical bus circuit or bus master having the highest priority level. | 12-09-2010 |
| 20110093636 | Data processing apparatus and method for connection to interconnect circuitry - A data processing apparatus and method are provided for connection to interconnect circuitry, in order to enable the data processing apparatus to act as a master device to initiate transactions conforming to an interconnect protocol associated with the interconnect circuitry. The data processing apparatus has a main controller for executing a programmable sequence of instructions including a transaction sequence of instructions used to process a transaction to be initiated by the data processing apparatus. The transaction sequence of instructions is programmed dependent on the interconnect protocol. The data processing apparatus further has an interconnect interface unit comprising a plurality of queues including at least one send queue for issuing outbound payload information to the interconnect circuitry, and at least one receive queue for receiving inbound payload information from the interconnect circuitry. An interface controller is provided for pushing the outbound payload information on to the at least one send queue and popping the inbound payload information from the at least one receive queue, under the control of commands issued by the main controller when executing the transaction sequence of instructions. Further, the interconnect interface unit has an interconnect port for communicating with the interconnect circuitry in order to output outbound payload information from the at least one send queue and receive inbound payload information for placing on the at least one receive queue. Such an approach has been found to provide a very flexible mechanism for connecting the data processing apparatus to the interconnect circuitry using only a relatively small amount of hardware to implement the interconnect interface unit, whilst allowing the data processing apparatus to connect with interconnect circuitry using a variety of different interconnect protocols without the need to modify that hardware. | 04-21-2011 |
| 20110125947 | READ CONTROL IN A COMPUTER I/O INTERCONNECT - In one embodiment, a method for controlling reads in a computer input/output (I/O) interconnect is provided. A read request is received over the computer I/O interconnect from a first device, the request requesting data of a first size. Then it is determined whether fulfilling the read request would cause the total size of a completion queue to exceed a first predefined threshold. If fulfilling the read request would cause the total size of the completion queue to exceed the first predefined threshold, then the read request is temporarily restricted from being forwarded upstream | 05-26-2011 |
| 20110173359 | COMPUTER-IMPLEMENTED METHOD AND SYSTEM FOR SECURITY EVENT TRANSPORT USING A MESSAGE BUS - A computer-implemented device provides security events from publishers to subscribers. There is provided a message bus, configured to contain a plurality of security events. Also provided is a receiver unit, responsive to a plurality of publishers, to receive the plurality of security events from the publishers. There is also a queue unit, responsive to receipt of the security events, to queue the plurality of security events in the message bus. Also, there is a transport unit, responsive to the security events in the message bus, to transport the plurality of security events in the message bus to a plurality of subscribers. | 07-14-2011 |
| 20110276737 | METHOD AND SYSTEM FOR REORDERING THE REQUEST QUEUE OF A HARDWARE ACCELERATOR - The invention discloses a system and method for reordering the request queue of the hardware accelerator, wherein, the request queue stores therein a plurality of coprocessor request blocks (CRBs) to be input into the hardware accelerator. The system including: content addressable memory connected to the request queue for storing the state pointer of each CRB in the request queue at a same physical storage location in the request queue, receiving the state pointer of a new CRB in response to the new CRB asking to join in the request queue and outputting the physical storage location of a CRB in the request queue whose state pointer stored in the content addressable memory is the same as the state pointer of the new CRB; and CRB insertion module for receiving the physical storage location of a CRB in the request queue whose state pointer is the same as the state pointer of the new CRB and inputting the new CRB in the request queue and the CRB in the request queue whose state pointer is the same as the state pointer of the new CRB adjacently into the hardware accelerator in the order of entering the request queue. The system and method can improve the process efficiency of the hardware accelerator. | 11-10-2011 |
| 20120079154 | TRANSACTION REORDERING ARRANGEMENT - An embodiment of a transaction reordering arrangement is provided. The transaction reordering arrangement includes a queue into which respective responses to requests are writable and a controller configured to control a position in said queue to which said respective responses to said requests are written. The position is controlled such that the responses are read out of said queue in an order which corresponds to an order in which the requests are issued. | 03-29-2012 |
| 20120226841 | READ STACKING FOR DATA PROCESSOR INTERFACE - A gasket of a data processing device controls the number of released storage locations of a buffer where read and write access requests are stored so that more read access requests can be stored without a corresponding increase in the amount of space at the buffer to store write access requests. An interface of the gasket accepts new access requests from one or more requesting modules only when a number of released storage locations at a buffer associated with the interface (referred to as an outbound buffer) is above a threshold number. As long as the number of stored access requests at the outbound buffer are less than a threshold amount, a buffer location can be immediately released. In addition, the gasket is configured to issue read access requests from the outbound buffer without regard to whether the inbound buffer has space available. | 09-06-2012 |
| 20130282942 | Input Output Bridging - In one embodiment, a system includes a memory and a first bridge unit for processor access with the memory coupled with an input-output bus and the memory. The first bridge unit is configured to receive requests from the input-output bus to read or write data receive requests from the MFNU to free memory and choose among the requests to send to the memory on a first memory bus. The system also includes a second bridge unit for packet data access with the memory coupled with a packet input unit, packet output unit, and the memory. The second bridge unit is configured to receive requests to write packet data from the packet input unit, receive requests to read packet data from the packet output unit, and choose among the requests from the packet input unit and the packet output unit to send to the memory on a second memory bus. | 10-24-2013 |
| 20140281083 | ENHANCED QUEUE MANAGEMENT - A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue. | 09-18-2014 |
| 20140289435 | Issuing Requests To A Fabric - In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed. | 09-25-2014 |
| 20140325105 | MEMORY SYSTEM COMPONENTS FOR SPLIT CHANNEL ARCHITECTURE - In one form, a memory module includes a first plurality of memory devices comprising a first rank and having a first group and a second group, and first and second chip select conductors. The first chip select conductor interconnects chip select input terminals of each memory device of the first group, and the second chip select conductor interconnects chip select input terminals of each memory device of the second group. In another form, a system includes a memory controller that performs a first burst access using both first and second portions of a data bus and first and second chip select signals in response to a first access request, and a second burst access using a selected one of the first and second portions of the data bus and a corresponding one of the first and second chip select signals in response to a second access request. | 10-30-2014 |
| 20150074307 | METHOD AND SYSTEM FOR ACCESSING DATA - A method and a system for accessing data are provided. A management module is used for receiving multiple transmission data and multiple identification codes from application programs respectively and storing the transmission data to a queue according to a receiving order. One of the transmission data from the queue is obtained by the management module according to a delivering order, and the obtained transmission data is transferred to a corresponding device through an inter-integrated circuit (I | 03-12-2015 |
| 20150301962 | REORDER BUFFER PERMITTING PARALLEL PROCESSING OPERATIONS WITH REPAIR ON ORDERING HAZARD DETECTION WITHIN INTERCONNECT CIRCUITRY - A system-on-chip integrated circuit | 10-22-2015 |
| 20160070664 | MEMORY MAPPING IN A PROCESSOR HAVING MULTIPLE PROGRAMMABLE UNITS - The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units. | 03-10-2016 |
| 20160117277 | COLLABORATIVE HARDWARE INTERACTION BY MULTIPLE ENTITIES USING A SHARED QUEUE - A method for interaction by a central processing unit (CPU) and peripheral devices in a computer includes allocating, in a memory, a work queue for controlling a first peripheral device of the computer. The CPU prepares a work request for insertion in the allocated work queue, the work request specifying an operation for execution by the first peripheral device. A second peripheral device of the computer submits an instruction to the first peripheral device to execute the work request that was prepared by the CPU and thereby to perform the operation specified by the work request. | 04-28-2016 |
| 20160162188 | MULTIPLE I/O REQUEST PROCESSING IN A STORAGE SYSTEM - A mechanism is provided to optimize performance of a storage system. A plurality of I/O requests is received. A subset of the plurality of I/O requests is selected. The size of each I/O request of the subset of the plurality of I/O requests is less than a predetermined size, but the combined size of the subset of the plurality of I/O requests is greater than the predetermined size. Furthermore, the subset of the plurality of I/O requests is associated with a single logical unit number. A data transfer command which includes the subset of the plurality of I/O requests is generated. The data transfer command is transmitted. | 06-09-2016 |
