| Entries |
| Document | Title | Date |
|---|
| 20080201511 | Device Identification Coding of Inter-Integrated Circuit Slave Devices - Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate identification of inter-integrated circuit slave devices using device identification coding. The communications system includes a slave device having a device identification code identifying one or more parameters. Communications circuitry in the slave device is configured to communicate with a master device on the I2C serial data transfer bus using the communications protocol. In response to a transmission of a device identification address from the master device, the slave device is configured to transmit an ACKNOWLEDGE, and in response to a transmission of a slave device address and the device identification address from the master device, the slave device is configured to transmit the device identification code from the slave device to the master. | 08-21-2008 |
| 20080215779 | Slave Device with Latched Request for Service - Consistent with one example embodiment, communications systems ( | 09-04-2008 |
| 20080215780 | Simultaneous Control Of Multiple I/O Banks In An 12C Slave Device - Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers. The communications system includes a slave device having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers for loading of the single logic value into the two or more of bits of the selected registers in the second configuration. | 09-04-2008 |
| 20080215781 | SYSTEM INCLUDING BUS MATRIX - A system has a first chip using a first bus matrix, and a second chip including second and third bus matrixes connected to the first bus matrix. The second bus matrix is connected to a plurality of bus masters of the second chip and the third bus matrix is connected to a plurality of bus slaves of the second chip. | 09-04-2008 |
| 20080228976 | METHOD OF DETERMING REQUEST TRANSMISSION PRIORITY SUBJECT TO REQUEST SOURCE AND TRANSTTING REQUEST SUBJECT TO SUCH REQUEST TRANSMISSION PRIORITY IN APPLICATION OF FIELDBUS COMMUNICATION FRAMEWORK - A method of determining request transmission priority subject to request source and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective source and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time. | 09-18-2008 |
| 20080235420 | METHOD OF DETECTING MASTER/SLAVE RESPONSE TIME-OUT UNDER CONTINUOUS PACKET FORMAT COMMUNICATIONS PROTOCOL - A method of detecting master/slave response time-out under continuous packet format communications protocol, which calculates the time required for the slave device to respond to a Modbus request subject to Modbus TCP/UDP protocol. The method is to continuously send Modbus requests to a slave device through a detection device and to record each Modbus request sent time, and to have the slave device provide to the detection device a response for each Modbus request. By means of calculating the precise response time-out from the response time-outs which are gotten from the slave device responds to a predetermined number of Modbus requests, the user or manager can determine the response time-out required for the slave device precisely so as to give an EXECUTE instruction or command at the accurate time point. | 09-25-2008 |
| 20080235421 | Technique and apparatus to optimize inter-port memory transaction sequencing on a multi-ported memory controller unit - An apparatus that includes a multi-ported memory controller unit to control access to a memory external to the memory controller and comprising port interfaces coupled to the masters. Each master is capable of generating a transaction request with the memory. The apparatus also includes a transaction sequence logic to communicate with the masters using sideband signals to receive the transaction request and apply rules to control access to the memory by the masters | 09-25-2008 |
| 20080244131 | ARCHITECTURE FOR CONFIGURABLE BUS ARBITRATION IN MULTIBUS SYSTEMS WITH CUSTOMIZABLE MASTER AND SLAVE CIRCUITS - An integrated multibus system includes a first and second master devices coupled to first and second master busses. A slave device is coupled to the first and second master busses through a first multiplexer, a first address decoder coupled to the first master bus having an output associated with the slave device, a second address decoder coupled to the second master bus and having an output associated with the slave device. A first arbiter circuit multiplexer has an output coupled to a select input of the first multiplexer. A first arbiter circuit is coupled to the outputs of the first and second address decoders, the first arbiter circuit having an output that is a predetermined function of the address decoder outputs and is coupled to an input of the first arbiter circuit multiplexer. A configurable logic area has a first net coupled to an input of the arbiter circuit multiplexer. | 10-02-2008 |
| 20080244132 | DATA TRANSMISSION METHODS - Data transmission systems and methods. The data transmission system comprises a bus, a slave, a master, and a master interface. The master transmits a request comprising transfer information comprising a start address and a length. The master interface receives the request from the master. The master interface determines a burst type of a first burst according to the transfer information, and transmits the first burst with the burst type to the slave via the bus, where the first burst is aligned to at least one address boundary of the slave. The master interface receives data corresponding to the first burst from the slave, and transmits the data to the master. | 10-02-2008 |
| 20080256277 | Processing apparatus and processing module - A processing apparatus has a master processing module and a plurality of slave processing modules. The master processing module has a master recording unit and a slave recording unit recording part of the data recorded in the master recording unit. The slave processing modules access the master processing module when it is necessary to access the data recorded in the master recording unit. When the data to be accessed from one slave processing module is recorded in the slave recording unit, the master processing module transmits the data to be accessed, from the slave recording unit to the one slave processing module. In the processing apparatus such as a base transceiver station communicating with transceivers such as mobile telephones, a reduction in the overall cost of the apparatus and an efficient internal communication are realized, and the overall processing time is reduced. | 10-16-2008 |
| 20080270654 | Bus System for Selectively Controlling a Plurality of Identical Slave Circuits Connected to the Bus and Method Therefore - A bus system (BS) for selectively controlling a plurality of identical slave circuits (slave A) comprises a bus (B) having a clock line (CLOCK) and at least one data line (DATA). The bus system (BS) includes at least one master circuit ( | 10-30-2008 |
| 20080270655 | SERIALIZATION OF DATA FOR COMMUNICATION WITH SLAVE IN MULTI-CHIP BUS IMPLEMENTATION - Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a slave in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from a bus matrix to the shift registers for serialization and communication to the slave, where the mechanism provides deserialized information received from the shift registers to a bus matrix. The mechanism inserts one or more wait cycles in communication with the matrix during the serialization and deserialization. | 10-30-2008 |
| 20080270656 | SERIALIZATION OF DATA FOR COMMUNICATION WITH DIFFERENT-PROTOCOL SLAVE IN MULTI-CHIP BUS IMPLEMENTATION - Bus communication for components of a system on a chip. In one aspect of the invention, a system including bus communication to a slave includes a bridge operative to interface a first bus protocol to a bus matrix that uses a second bus protocol. A first serializer coupled to the bridge serializes information received from the bridge and sends the serialized information over a communication bus. A second serializer coupled to the communication bus receives the serialized information and deserializes the serialized information. A slave uses the first protocol and is coupled to the second serializer, where the deserialized information is provided to the slave, and the slave provides a response to the information from the bridge. | 10-30-2008 |
| 20080276023 | Slave Bus Subscriber for a Serial Data Bus - The invention relates to a slave bus subscriber for a serial data bus with a master bus subscriber, wherein the slave subscriber recognizes the bit rate of a data packet received over the data bus, whose header has a sync break field, a sync field and an ID field, with the help of the header of the data packet in such a manner that the periods between falling edges of bits having known bit intervals at least of the sync field and of the sync break field are evaluated and the bit rate is determined from the evaluated periods. | 11-06-2008 |
| 20080282007 | METHOD AND SYSTEM FOR CONTROLLING TRANSMISSION and EXECUTION OF COMMANDS IN AN INTEGRATED CIRCUIT DEVICE - A method and system for controlling transmission and execution of commands in an integrated circuit (IC) device provide transmission of commands and acknowledgements in an order of their priorities. Priority levels of the commands and acknowledgements are defined based on pre-assigned levels of precedence of the respective master and slave devices. In one application, the invention is used to increase performance of IC devices employing an Advanced eXtensible Interface (AXI). | 11-13-2008 |
| 20080288686 | MAIN DEVICE REDUNDANCY CONFIGURATION AND MAIN DEVICE REPLACING METHOD - A networking system architecture includes a plurality of main devices, one of the main devices acts as a master main device, and the other main devices act as slave main devices. If the master main device malfunctions, one of the slave main devices substitutes for the master main device to act as a new master main device. Priorities are set to the main devices, respectively If a current master main device malfunctions, the current master main device may be replaced by a new master main device having the highest priority among the other main devices. | 11-20-2008 |
| 20080288687 | INFORMATION PROCESSING DEVICE AND PROCESSOR - A semiconductor device including: a first slave device; a first master device outputting a first request control signal and a first access address signal; a second master device outputting a second request control signal and a second access address signal; a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and a range setting register holding an address range of which an access of the first master device is permitted, wherein the system bus blocks the first request control signal if the first access address signal is out of the address range. | 11-20-2008 |
| 20080288688 | Bus system and method of arbitrating the same - A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one transfer mode selection circuit. The at least one bus master device may generate a burst cycle control signal, a transfer start signal and a bus control request signal for requesting control of the bus, and may be activated in response to a bus control grant signal, so as to exchange data via the bus. The bus arbiter may generate the bus control grant signal in response to the bus control request signal and provide the bus control grant signal to the bus master device. The at least one transfer mode selection circuit may convert a burst mode into a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed. | 11-20-2008 |
| 20080294821 | Series-Connected Control System - A control system includes a host device and a string of slave devices coupled in series. The host device includes a first transmission unit operable to transmit an encoded control signal provided by a first processing module, and to receive an encoded feedback signal for subsequent decoding by the first processing module. Each of the slave devices includes: a driven member responsive to a driving signal for generating an event; a driving unit operable to provide the driving signal; a detection unit generating an initial feedback signal based on the event; a second processing module capable of decoding the encoded control signal so as to drive the driving unit when an address code in the encoded control signal corresponds to the slave device, and of generating the encoded feedback signal; and a second transmission unit operable to receive the encoded control signal, and to transmit the encoded feedback signal. | 11-27-2008 |
| 20080294822 | DYNAMICALLY CHANGING PCI CLOCKS - A method, apparatus and computer-usable medium are presented for dynamically selecting a clock signal used by a peripheral device that is coupled to a motherboard. When the motherboard is powered off, a clock selector sends the peripheral device an internal clock signal from the peripheral device's own internal clock controller. When the motherboard powers up, the clock selector sends the peripheral device an external clock signal from the motherboard. | 11-27-2008 |
| 20080301344 | SYSTEM FOR EXPANDABLY CONNECTING ELECTRONIC DEVICES - An exemplary system for expandably connecting electronic devices includes a master device, a first slave device, and a second slave device. The first and second slave device each has a control chip and an address setting module. The control chip includes a bus interface connected to the master device via a common bus. The address setting module has a counter unit. The master device sets a first address for the control chip and the counter unit of the first slave device, the counter unit of the first slave device calculates the first address and sends a calculated address to the control chip and the counter unit of the second slave device as a second address of the second slave device. The first address and the second address are different from each other, thus a plurality of slave devices can connected to the master device via a common bus. | 12-04-2008 |
| 20080307134 | I2C bus interface and protocol for thermal and power management support - A method, apparatus and computer instructions are provided for controlling communications between controller devices over an I | 12-11-2008 |
| 20080307135 | High performance programmable logic system interface and chip - A chip with a high performance programmable logic system interface, including a first internal device, a second internal device and a bus master, is provided. The first internal device, which is integrated into the chip, communicates with an external device by a first set of internal buses and a first set of external buses. The second internal device, which is integrated into the chip, communicates with the external device by a second set of internal buses and a second set of external buses. The bus master is configured to control the first set of internal buses, the first set of external buses, the second set of internal buses and the second set of external buses. The first internal device and the second internal device communicate with the bus master simultaneously. | 12-11-2008 |
| 20080307136 | Arbitration of Memory Transfers in a DSP System - Disclosed are various embodiments for arbitration of memory transfers in a digital signal processing system. In one embodiment, a digital signal processing system includes a plurality of DSP's having an external memory. The DSP's are further configurable to act as a master processor and a slave processor relative to another DSP. The system also includes an arbiter configured to maintain DSP status data and arbitrate requests between master processors and slave processors in the system. | 12-11-2008 |
| 20080307137 | DATA PROCESSING SYSTEM, METHOD AND INTERCONNECT FABRIC FOR SYNCHRONIZED COMMUNICATION IN A DATA PROCESSING SYSTEM - A data processing system includes a plurality of processing units, including at least a local master and a local hub, which are coupled for communication via a communication link. The local master includes a master capable of initiating an operation, a snooper capable of receiving an operation, and interconnect logic coupled to a communication link coupling the local master to the local hub. The interconnect logic includes request logic that synchronizes internal transmission of a request of the master to the snooper with transmission, via the communication link, of the request to the local hub. | 12-11-2008 |
| 20080313373 | ELECTRONIC APPARATUS AND DATA SENDING/RECEIVING METHOD THEREOF - An electronic apparatus to allow data to be sent and received between a master unit and a slave unit through a peripheral component interconnect (PCI) bus is provided. Each of the master unit and the slave unit comprises a data interface having a plurality of pins through which request data is sent to and received from an external device, and additional pins through which size information of the request data is sent to and received from the external device. If the master unit sends address information and the size information of the request data to the slave unit through the plurality of pins and the additional pins, the slave unit processes data of an address corresponding to the received address information according to size corresponding to the size information. | 12-18-2008 |
| 20080313374 | SERVICE INTERFACE TO A MEMORY SYSTEM - A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module. | 12-18-2008 |
| 20090013114 | Master Slave Interface - Implementations related to systems, devices, and methods that make use of a master slave arrangement are described. | 01-08-2009 |
| 20090024776 | HIGH DATA RATE SERIAL PERIPHERAL INTERFACE - An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. | 01-22-2009 |
| 20090031065 | Repeater for a bidirectional serial bus - A digital bit-level repeater for joining two wired-AND buses such as the I | 01-29-2009 |
| 20090037629 | MASTER SLAVE CORE ARCHITECTURE WITH DIRECT BUSES - A radio frequency (RF) integrated circuit (IC) operable to support wireless communications is provided. This RF IC includes a number of master components, a number of slave components, and a direct master slave bus. The master components may include a number of processing modules where each processing module is operable to support one or more functions of the RF IC. The direct master slave bus may couple at least one master component to at least one slave component based on mode of operation of the RF IC. | 02-05-2009 |
| 20090043932 | Method and Device for Enumeration - An embodiment of the invention describes a method for enumeration. The method includes assigning a second number to a device of a plurality of devices, wherein each device of the plurality of devices has a different unique first number. The method includes comparing at least portions of the first numbers and assigning a second number to one of the plurality of devices depending on the result of the comparison. | 02-12-2009 |
| 20090063739 | Systems, and/or Devices to Control the Synchronization of Diagnostic Cycles and Data Conversion for Redundant I/O Applications - Certain exemplary embodiments can provide a first analog input module adapted to, via a sent synchronization signal, automatically terminate a diagnostic cycle of a second analog input module. The synchronization signal can be adapted to cause an initiation of a data conversion cycle at the second analog input module. | 03-05-2009 |
| 20090070506 | ELECTRONIC SYSTEM AND METHOD - A method operating an electronic system including sending or receiving a signal is disclosed. One embodiment includes changing a parameter of a signal from a first value to a second value after a first time duration if a logic zero is to be transmitted, and changing the parameter of the signal from the first value to the second value after a second time duration if a logic one is to be transmitted. | 03-12-2009 |
| 20090070507 | Back-Off Timing Mechanism - Systems and methods for implementing back-off timing for retries of commands sent from a master device to a slave device over a split-transaction bus. One embodiment includes a buffer having entries for storing each pending command and associated information, including a number of retries of the command and a static pseudorandom timer expiration value. The timer expiration value of each entry is compared to a running counter according to a mask associated with the number of retries of the command corresponding to the entry. When the unmasked bits of the two values match, the command is retried. In one embodiment, the same portion of the buffer entry that is used to store the number of retries and the timer expiration value is alternately used to store a slave-generated tag that is received with an acknowledgment response. | 03-12-2009 |
| 20090077289 | BUS INTERCONNECT WITH FLOW CONTROL - A method of operating a bus interconnect coupled to bus masters and bus slaves is provided. The method includes receiving a request from a bus master to perform a bus transaction associated with a transaction ID with a bus slave of the plurality of bus slaves, the bus transaction being a first type of bus transaction. The method further includes performing the transaction if a resource allocation parameter allocated to the bus master meets a first threshold. The method further includes if the resource allocation parameter does not meet the first threshold, performing the data transaction only if the transaction meets a condition of a set of at least one condition, wherein a condition of the set of at least one condition includes that the transaction ID of the transaction is not a transaction ID of any outstanding bus transaction of the first type requested by the bus master. | 03-19-2009 |
| 20090077290 | CONTROLLER FOR PROCESSING APPARATUS - A computer apparatus comprises a master module and a slave module such that the master module is able to send a functional request to the slave module for the execution by the slave module of a requested function. The master module comprises dynamic voltage scaling (DVS) means operable to establish a DVS control scheme for the master processing module, and DVS liking means operable to relate the DVS control scheme to the slave processing module. | 03-19-2009 |
| 20090077291 | COMMUNICATION STEERING FOR USE IN A MULTI-MASTER SHARED RESOURCE SYSTEM - New approaches for providing communication between multiple masters ( | 03-19-2009 |
| 20090083464 | INTERFACE UNIT AND COMMUNICATION SYSTEM HAVING A MASTER/SLAVE STRUCTURE - An interface unit is provided for a communication system comprising a master unit and a plurality of slave units serially connecting the master unit via a double ring structure comprising a first communication path and a second communication path. The interface unit comprises a first switching unit, which is configured to output information signals received by the master unit as a first information signal to the first communication path and as a second information signal to the second communication path; and a second switching unit, which is configured to forward the first information signal circulating on the first communication path and second information signal circulating on the second communication path to the master unit. | 03-26-2009 |
| 20090083465 | Method for Automatic Configuration of a Process Control System and Corresponding Process Control System - A process control system and a method for automatic configuration of the system are described. The system includes a master and at least one slave, whereby the master controls the at least one slave, which is connected to and communicates with the master via a bus system, and processes data received from the at least one slave. The master automatically identifies the at least one slave via the bus system, and subsequently automatically generates a slave configuration for setting up the slave according to its identification such that the slave is ready to be operated in the process control system. | 03-26-2009 |
| 20090089469 | Parallel burunig system and method - A parallel burning system and method is for burning chips of various different bus types in parallel. A computer compiles configuration information according to corresponding connection relations between the chips and the micro controller units, and transmits the configuration information, burning command and burning data to a master micro controller unit of the micro controller units. The master micro controller unit distributes the burning data to slave micro controller units of the micro controller units based on the analyzed configuration information, and controls each slave micro controller unit to activate its burning operation. Then, the slave micro controller units burn the burning data onto the chips connected thereto, and transmit the burning results back to the master micro controller unit after completion of the burning operations. Finally, the master micro controller unit transmits the burning results back to the computer after completion of all the burning operations. | 04-02-2009 |
| 20090113097 | Method and Apparatus for Attaching Multiple Slave Devices to a Single Bus Controller Interface While Supporting Command Pipelining - In a method and apparatus associated with a bus controller, a set of mechanisms are selectively added to the bus controller, as well as to slave devices connected to the bus controller. A mechanism is also added to one or more master devices connected to the bus controller, in order to provide the master devices with a transaction ordering capability. The added mechanisms collectively achieve the objective of supporting connection of multiple slave devices to a common controller interface, and at the same time allowing pipelined operation of the slave devices. One embodiment of the invention is directed to a method for use with a bus and an associated bus controller, wherein the bus controller has respective master and slave interfaces for use in selectively interconnecting master devices and slave devices. The method comprises the steps of connecting one or more of the master devices to one of the master interfaces, and connecting each of a plurality of slave devices to the same one of the slave interfaces. The method further comprises operating a connected master device to send multiple commands to a selected one of the connected slave devices in accordance with a command pipelining procedure. | 04-30-2009 |
| 20090113098 | Method and Apparatus for Maintaining Memory Data Integrity in an Information Handling System Using Cache Coherency Protocols - An information handling system includes a processor integrated circuit including multiple processors with respective processor cache memories. Enhanced cache coherency protocols achieve cache memory integrity in a multi-processor environment. A processor bus controller manages cache coherency bus interfaces to master devices and slave devices. In one embodiment, a master I/O device controller and a slave I/O device controller couple directly to the processor bus controller while system memory couples to the processor bus controller via a memory controller. In one embodiment, the processor bus controller blocks partial responses that it receives from all devices except the slave I/O device from being included in a combined response that the processor bus controller sends over the cache coherency buses. | 04-30-2009 |
| 20090119429 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to an aspect of the invention includes a plurality of master devices which issue data transfer requests, at least one slave device which performs data transfer in accordance with the data transfer requests, and a network which arbitrates the plurality of data transfer requests respectively issued from the plurality of master devices, and informs the slave device of the arbitration result, thereby performing data transfer between the master devices and the slave device, wherein when issuing the data transfer request, the master device informs the network of a period which extends from the issuance of the data transfer request to the start of the data transfer. | 05-07-2009 |
| 20090119430 | SEMICONDUCTOR DEVICE - The router which relays a transfer request and a reply between master and slave components has request-control circuits provided therein. The request-control circuits judge the slave component to transfer a request from each master component to, and arbitrate the conflict between requests to one slave component. Further, for the router, a slave-component-allocation-control circuit which variably allocates the slave components to be connected to the request-control circuits to the request-control circuits is adopted. In case that a slave component in connection with one request-control circuit is subjected to no access, changing the allocation of the slave component in connection with the one request-control circuit makes possible to utilize the resource of the one request-control circuit. | 05-07-2009 |
| 20090119431 | Multi-purpose flight attendant panel - A flight attendant panel, in which a plurality of computer units can be coupled to a common input/output device by a circuitry. One of the computer units is designated as the master computer unit and controls the circuitry in order to specify which of the computer units should be coupled to the input/output device. The actuation of a switch makes it possible to once again return the flight attendant panel into an original state, in which the master computer unit is coupled to the input/output device by the circuitry. | 05-07-2009 |
| 20090125657 | SERIAL PERIPHERAL INTERFACE CIRCUIT - An exemplary serial peripheral interface circuit includes a host, a plurality of slaves, and a decoder. A data output terminal, a data input terminal, and a serial clock terminal of the host are connected to a data input terminal, a data output terminal, and a serial clock terminal of each slaves respectively. A slave select terminal of the host is connected to a data receive terminal of the decoder. GPIO pins of the hot are connected to corresponding input terminals of the decoder correspondingly. A select terminal of each slave is connected to a corresponding output terminal of the decoder. The address generated by the GPIO pins controls the decoder, so that the select terminal of the host can be connected to a corresponding slave device via the decoder. | 05-14-2009 |
| 20090125658 | CWUSB HOST MANAGEMENT SYSTEM - Universal Serial Bus (USB) is a Master/Salve or Host/Device system in which there is only one host and one or more devices connected by cables to the host. To connect a USB device to a different host controller (say another PC), the user unplugs the USB cable and establishes the connection physically by plugging the cable into the new host controller interface. Certified Wireless USB (CWUSB), a logical extension to the USB, preserves the USB connection model, except that the link between the host and the device is now using a wireless technology. A wireless device is usually connected to only one wireless host at a given point of time, even though several wireless hosts may be co-located in the same physical neighborhood. The connection between the wireless host and device is initiated by the device. A device usually selects a wireless host from a stored set of known hosts that have established a trusted relationship with the device. If more than one wireless host is operating in the same neighborhood, there is no well known established procedure for the device to select a particular wireless host to establish a connection. | 05-14-2009 |
| 20090125659 | Inter-Integrated Circuit (12C) Slave with Read/Write Access to Random Access Memory - A program and device for data access via an inter-integrated circuit (I2C) protocol are provided, which includes receiving an I2C read command at an I2C slave device from an I2C master device, and the I2C read command at the I2C slave device is altered such that the I2C read command causes stored data to be read from a storage device, being external to the I2C slave device, in place of reading from internal memory of I2C slave device. An I2C write command having master data and a slave device register address is intended to write to the internal memory of the I2C slave device, and I2C write command at the I2C slave device is altered such that the I2C write command causes the master data to write to the storage device, being external to the I2C slave device, in place of writing to internal memory of the I2C slave device. | 05-14-2009 |
| 20090132743 | Data Path Master/Slave Data Processing Device Apparatus - An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave. | 05-21-2009 |
| 20090138641 | Device, System, and Method of Handling Delayed Transactions - Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit. | 05-28-2009 |
| 20090144471 | Serial bus device with address assignment by master device - The present invention offers a daisy chain serial bus system. For bus construction, the slave device has a first data transmission port to transfer serial data with its upward connected device and a second data transmission port to transfer serial data with its downward connected device. The most upward slave device is connected to a master device. In each slave device, the input data from a first data transmission port is transferred to a data input gate in a second data transmission port. There is a control register in each slave device to control the data input gate of the second data transmission port. After the bus system has been started, only the slave device connected to the master device can receive the data from the master device, so that the master device can assign the first device address to the slave device connected to it, then, the master device can assign the second device address to the slave device next connected to the first slave device on the bus. By this way, the master device can assign the device address to each slave device on the bus one by one. | 06-04-2009 |
| 20090150587 | MASTER-SLAVE DEVICE COMMUNICATION CIRCUIT - A master-slave device communication circuit includes a master device, a bus, and a slave device having a bus switch connected to the master device via the bus, and a status detecting circuit. The status detecting circuit includes a power input terminal and a detecting signal output terminal. A power terminal of the master device is connected to the power input terminal of the status detecting circuit. The detecting signal output terminal is connected to the bus switch and a trigger pin of the master device. When the master device supplies power to the slave device via the power terminal thereof, the detecting signal output terminal transmits a control signal to control the bus switch to turn on the bus and trigger the master device to communicate with the slave device after a delay time. | 06-11-2009 |
| 20090150588 | Hard Disk Drive Cache Memory and Playback Device - A NOR emulating device using a controller and NAND memories can be used in a computer system in placed of the main memory or in place of the BIOS NOR memory. Thus, the emulating device can function as a bootable memory. In addition, the device can act as a cache to the hard disk drive. Further, with the addition of an MP3 player controller into the device, the device can function as a stand alone audio playback device, even while the PC is turned off or is in a hibernating mode. Finally with the MP3 player controller, the device can access additional audio data stored on the hard drive, again with the PC in an off mode or a hibernating mode. Finally, the device can function to operate the disk drive, even while the PC is off or is in a hibernating mode, and control USB ports attached thereto. | 06-11-2009 |
| 20090157928 | MASTER AND SLAVE DEVICE FOR COMMUNICATING ON A COMMUNICATION LINK WITH LIMITED RESOURCE - A master device for communicating with a number of slave devices through a communication link having a limited resource. The master device comprises a transceiver adapted for communicating with the slave devices on the communication link and a controller adapted for detecting the number of slave devices. The controller is adapted for determining an individual resource associated with a slave device to be consumed from the communication link, wherein a sum of the individual resources of all slave devices is lower than the limited resource and wherein the transceiver is adapted for assigning the individual resources to the associated slave devices. | 06-18-2009 |
| 20090157929 | DATA ARBITRATION ON A BUS TO DETERMINE AN EXTREME VALUE - A system includes a master device and a plurality of slave devices. The master device initiates a bus transaction having an arbitration data field for processing by a subset of the slave devices. Each slave device of the subset arbitrates a corresponding data value for the arbitration data field via the multiple-access bus such that an extreme data value of the data values of the slave devices of the subset is transmitted via the multiple-access bus for the arbitration data field. The slave device can arbitrate its data value by providing the data value for serial transmission via a data line of the multiple-access bus and monitoring the data line. In response to determining that a bit value of the data value being provided does not match the state of the data line, the slave device terminates provision of the data value, thereby ceasing arbitration of its data value. | 06-18-2009 |
| 20090157930 | MULTI-CHANNEL COMMUNICATION CIRCUIT - A multi-channel communication circuit includes a master device, a plurality of slave devices, and a multiplexer (MUX). A transmitting pin and a receiving pin of a serial interface of the master device are respectively connected to two data input pins of the MUX. Two control pins of the serial interface of the master device are connected to two selecting pins of the MUX. Four pins of the serial interface of the master device are connected to a power pin of the MUX. A transmitting pin and a receiving pin of a serial interface of each slave device are respectively connected to two data output pins of the MUX, the master device communicates with one slave device via transmitting a corresponding selecting signal to the two selecting pins of the MUX to select one slave device. | 06-18-2009 |
| 20090157931 | IIC BUS COMMUNICATION SYSTEM, SLAVE DEVICE, AND METHOD FOR CONTROLLING IIC BUS COMMUNICATION - Multiple master devices and multiple slave devices are connected in parallel to two bus lines including a SCL line | 06-18-2009 |
| 20090157932 | IIC BUS COMMUNICATION SYSTEM, SLAVE DEVICE, AND METHOD FOR CONTROLLING IIC BUS COMMUNICATION - Multiple master devices and multiple slave devices are connected in parallel to two bus lines including a SCL line | 06-18-2009 |
| 20090157933 | Communication bus power state management - Methods and apparatus to manage communication bus power states are described. In one embodiment, an apparatus comprises a bus including a master node and at least a first slave node, logic to transmit a first power state change request from the master node to the first slave node, logic to receive the first power state change request in the first slave node, and logic to designate the first slave node as the master node when the first slave node denies the first power state change request. | 06-18-2009 |
| 20090164680 | ACCESS, MONITORING AND COMMUNICATION DEVICE AND METHOD - An access, monitoring and communication device and method for at least one protected local area of buildings, rooms or properties is described. The device includes at least one master unit having the following components: a monitor, a camera, a loudspeaker, a microphone, at least one function key, a controller, a memory and a signal and data transmission device with a network interface for signal transmission to and from at least one distant station via an IP network. As an additional component, the master unit comprises a reader for reading ID numbers stored on ID cards as an identification feature. | 06-25-2009 |
| 20090177821 | Cache Intervention on a Separate Data Bus When On-Chip Bus Has Separate Read and Write Data Busses - Computer implemented method, system and computer usable program code for processing a data request in a data processing system. A read command requesting data is received from a requesting master device. It is determined whether a cache of a processor can provide the requested data. Responsive to a determination that a cache of a processor can provide the requested data, the requested data is routed to the requesting master device on an intervention data bus of the processor separate from a read data bus and a write data bus of the processor. | 07-09-2009 |
| 20090177822 | Device, System, and Method of Handling Transactions - Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme. | 07-09-2009 |
| 20090177823 | METHOD AND SYSTEM FOR SETTING DATA COMMUNICATION ADDRESSES - A system for setting addresses includes a master device, a plurality of slave devices, and a bus. The master device includes a broadcasting module, a reading module, a responding module, an address assigning module, and a first judging module. Each slave device includes a performing module and a requesting module. The broadcasting module is configured to send messages to the slave devices. The performing module is configured to put the slave device be in an address setting mode. The reading module is configured to read a time assignment for each slave device from a timing module. The requesting module is configured to send an address request. The responding module is configured to respond to the address request. The address assigning module is configured to assign an address to the slave device. The first judging module is configured to check if all the time windows for the slave devices have elapsed. | 07-09-2009 |
| 20090177824 | METHOD AND SYSTEM FOR SETTING DATA COMMUNICATION ADDRESSES - A system for setting data communication addresses includes a master device, a plurality of slave devices, and a bus. The master device is connected to the slave devices via the bus. Each of the slave devices includes a control signal pin and an ID_Set Flag. The master device controls the enable status of the control signal pins and the logical values of the slave devices to set addresses for the slave devices. | 07-09-2009 |
| 20090177825 | FAST AND COMPACT CIRCUIT FOR BUS INVERSION - A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch. | 07-09-2009 |
| 20090182920 | AUTOMATIC SERIAL INTERFACE ADDRESS SETTING SYSTEM - An automatic address setting system includes a master device, a plurality of slave devices are connected to the master device via a bus, a direct current (DC) power source, and a plurality of resistors connected in series between the DC power source and ground. Each of the slave devices includes an analog to digital (A/D) conversion pin. A node between every two adjacent resistors is exclusively connected to the A/D conversion pin of a corresponding slave device. Voltages at the A/D conversion pins of the slave devices are changed to different address signals of the slave devices. | 07-16-2009 |
| 20090182921 | GENERAL PURPOSE INTERFACE CONTROLLER OF RESOURE LIMITED SYSTEM - The invention discloses a general purpose interface controller, including a slave interface controller and a master interface controller, used to exchange data among master devices and slave devices in an electronic device. The slave interface controller receives data and a first control signal from one of the master devices, and converts the first control signal to a request signal. The master interface controller receives the data and the request signal from the slave interface controller, converts the request signal to a second control signal recognized by at least one of the slave devices, and forwards the data and the second control signal to the slave device. | 07-16-2009 |
| 20090193165 | COMMUNICATION CIRCUIT OF SERIAL PERIPHERAL INTERFACE DEVICES - A communication circuit of a serial peripheral interface (SPI) device includes a master device and a plurality of slave devices. One of the slave devices includes a plurality of general purpose input/output (GPIO) pins. The chip select terminal of the master device is connected to the control terminal of the slave device having the GPIO pins. The GPIO pins respectively are connected to the control terminals of other slave devices. The slave device having the GPIO pins receives an instruction having an address signal from the master device and compares the addresses are identical, the slave device having the GPIO pins communicates with the master device. Otherwise the slave device transmits the address signal to the control terminals of the other slave devices through the GPIO pins. The other slave devices compare the address signal with their own address. The slave device having the identical address communicates with the master device. | 07-30-2009 |
| 20090193166 | DEVICE AND METHOD FOR ADDRESSING, AND CONVERTER - It is provided to implement a different number of logical slaves in a field device for use in an AS interface network as a function of the assigned address, which slaves may be addressed using the assigned address in the standard or in the expanded addressing mode. Thus, in a field device, it is possible to provide slaves having different profiles, via which different data types may be exchanged. Furthermore, a method is provided, with which a field device having different slaves is able to be addressed in a simple manner while avoiding double addressing. | 07-30-2009 |
| 20090210595 | Data transfer between devices within an integrated circuit - An integrated circuit | 08-20-2009 |
| 20090210596 | SLAVE APPARATUS AND SYSTEM AND METHOD FOR DATA TRANSMISSION - In a data transmission system having a plurality of apparatuses connected to one another in a cascade, each slave apparatus has an identification number retention section retaining the same identification number as the other slave apparatuses, a receiver receiving data accompanied by an apparatus number, a judgment section judging that the data is destined for itself when the apparatus number coincides with the identification number, while judging that the data is destined for another slave apparatus when the apparatus number does not coincide with the identification number, and a transmitter changing the apparatus number by subtracting or adding when the data is judged to be destined for another slave apparatus, and transmitting the data to another lower-ranked slave apparatus. Thereby, data transmission can be accomplished without automatically setting an apparatus number to each of the plural apparatuses. | 08-20-2009 |
| 20090210597 | METHOD FOR LOGIC CHECKING TO CHECK OPERATION OF CIRCUIT TO BE CONNECTED TO BUS - To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is easy to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter. | 08-20-2009 |
| 20090222606 | COMMUNICATION SYSTEM AND METHOD FOR OPERATION THEREOF - A communication system comprises a multiplicity of slave units and a master unit. The slave units are coupled to one another via a first communication path and a second communication path, the first communication path and the second communication path operating in opposite directions to one another, and a master unit, the master unit being coupled to the multiplicity of slave units via the first communication path and the second communication path. The master unit comprises a transmit control unit, the transmit control unit separately transmitting an information signal with a data field which has for each slave unit an associated data area, on the first communication path as a first information signal and on the second communication path as a second information signal. The master unit further comprises a receive control unit, the receive control unit superimposing the data field of the first information signal circulated on the first communication path and the data field of the second information signal circulated on the second communication path. | 09-03-2009 |
| 20090240858 | WIRELESS COMMUNICATION APPARATUS - A wireless communication apparatus including a master unit and a slave unit. The master unit includes a transmitter configured to transmit a beacon periodically and a receiver. A detector is provided that is configured to output a detected signal, and the slave unit is configured to receive the detected signal from the detector. The slave unit includes a receiver configured to receive the beacon periodically at a receiving timing determined based on the beacon, and a transmitter configured to transmit the detected signal to the master unit receiver at a transmitting timing determined based on the beacon if a value of the detected signal changes by a threshold amount. | 09-24-2009 |
| 20090240859 | AUTOMATIC ADDRESS SETTING SYSTEM - An automatic address setting system and method includes a master device, first and second slave devices. Each slave device includes a peripheral interface controller (PIC), a counter, and a pulse generator. When the first slave device is connected to the master device, the pulse generator generates a first pulse signal to the master device and the corresponding counter. The counter sends an address signal to the corresponding PIC as an identification address of the PIC. When the second slave device is subsequently connected to the master device, the pulse generator generates a second pulse signal to the master device, and the counters of the first and second slave devices. The counter sends an address signal to the corresponding PIC as an identification address of the PIC. The counter of the first slave device changes the identification address of the first slave device. | 09-24-2009 |
| 20090248932 | BI-DIRECTIONAL SINGLE CONDUCTOR INTERRUPT LINE FOR COMMUNICATION BUS - A bi-directional single conductor interrupt line is used in conjunction with a master only initiated data communication bus, to allow a slave device to submit a slave service request to a master device and to acknowledge master service requests from the master device. When not submitting a master service request, the master device maintains an interrupt line voltage at an idle state voltage by setting the interrupt line voltage through a pull resistor. The slave and master devices submit service requests by respectively driving or pulling the interrupt line voltage from the idle voltage to the service request voltage. The slave responds to a master service request or initiates the master servicing of a slave service request by subsequently driving the interrupt line back to the idle state voltage giving a slower slave ample time to prepare for a pending master initiated data transaction. The master detects the change in the interrupt line voltage from the request to the idle state and communicates to the now readied slave device through the data communication bus. | 10-01-2009 |
| 20090248933 | MASTER/SLAVE COMMUNICATION SYSTEM - A master includes a unit configured to register, for each slave, an expected communication time needed to exchange control data; a unit configured to register a slave in which a communication error is detected during exchange of the control data in a communication period; and a unit configured to re-execute exchange of the control data with the registered slave in the same communication period as that in which the communication error is detected. The unit configured to re-execute exchange of control data calculates a remaining resending time that can be used to re-execute exchange of the control data and, when the remaining resending time is longer than the expected communication time of the registered slave, resends the control data. | 10-01-2009 |
| 20090259785 | DIRECT DATA TRANSFER BETWEEN SLAVE DEVICES - In one aspect, a method of transferring data over a plurality of communication lines is described. A first command is sent from a master device coupled with the communication lines to a first destination slave device coupled with the communication lines instructing the first destination slave device to listen to and write data from the communication lines starting at a first time. A second command is sent from the master device to a second source slave device coupled with the communication lines instructing the second source slave device to read and output first data onto the communication lines starting at or after the first time. In this way, the first data output from the second source slave device beginning at the first time is stored by the first destination slave device beginning at the first time without requiring first transferring the data to the master device or any other device. | 10-15-2009 |
| 20090259786 | DATA TRANSFER SYSTEM AND METHOD FOR HOST-SLAVE INTERFACE WITH AUTOMATIC STATUS REPORT - In a host-slave data transfer system, the slave device transmits data regarding its status and buffer conditions to the host using tailers inserted into the data being transferred to the host. The slave device has a plurality of buffers, a buffer management circuit which manages the buffers and obtains buffer condition information (e.g. amount of available buffer space, amount of buffered data to be transferred to the host), a detection circuit which collects interrupt status of the slave, a processing circuit which generates headers or tailers containing the buffer conditions information and interrupt status, and a merging circuit which merges multiple data segments received from the data-source/data-destination device and associated headers and tailers to generate a stream of merged data. The host obtains the buffer condition information from the tailers, and uses it to determine the amount of data to transmit or receive from the slave. | 10-15-2009 |
| 20090265494 | DATA TRANSMISSION AND RECEPTION SYSTEM, MASTER DEVICE, AND SLAVE DEVICE - A master device for performing data transmission and reception with a slave device includes: a data transmission and reception circuit for performing transmission of data to the slave device and reception of data from the slave device via a first transmission path in a time division manner; and a control circuit wherein when data is transmitted or received, the control circuit provides a clock signal synchronous with the data to the slave device via a second transmission path, the control circuit provides a signal for setting a state of the slave device, to the slave device via a third transmission path while setting the clock signal at a first level, and the control circuit provides a signal for serving as a trigger for the slave device performing a predetermined operation, to the slave device via the third transmission path while setting the clock signal at a second level different from the first level. | 10-22-2009 |
| 20090282177 | APPARATUS AND METHOD FOR SIGNAL TRANSMISSION IN EMBEDDED SYSTEM - An apparatus and a method for signal transmission in an embedded system. The apparatus comprises: a master control chip, embedded in the embedded system and comprising a controller and a plurality of I/O pins; a plurality of slave chips; and a bus having one end coupled to the plurality of I/O pins and the other end coupled to one of the plurality of slave chips; wherein data or signals are bi-directionally transmitted. The method comprises steps of: transmitting a control signal from a master control chip to a slave chip; starting an operation by the slave chip after receiving the control signal; transmitting a data signal and a command signal to the master control chip from the slave chip; processing the data signal according to the command signal by the master control chip; and transmitting another control signal from the master control chip to the slave chip to terminate the operation. | 11-12-2009 |
| 20090287865 | Interconnect - A method, an interconnect and a system for processing data is disclosed. The method comprises the steps of: a) receiving a request to perform a data transaction between a master unit and a slave unit, b) receiving an indication of a quality of service requirement associated with said data transaction; c) determining an interconnect quality of service level achievable when transmitting said data transaction over the interconnect logic having regard to any other pending data transactions which are yet to be issued; d) determining a slave quality of service level achievable when responding to said data transaction once received by said slave unit from said interconnect logic; and e) determining whether the combined interconnect quality of service level and the slave quality of service level fails to achieve the quality of service requirement and, if so, reordering the pending data transactions to enable the quality of service requirement of each data transaction to be achieved. Hence, arbitration between data transactions occurs prior to those transactions being provided to the interconnect. It will be appreciated that this enables pending data transactions to be systematically reordered and the quality of service level for each of these reordered data transactions to be accurately calculated to ensure that the quality of service requirement for each of those data transactions is achieved. Accordingly, this enables all aspects of quality of service to be budgeted together and true end-to-end quality of service may be determined for each data transaction. | 11-19-2009 |
| 20090287866 | Systems And Methods To Interface Diverse Climate Controllers And Cooling Devices - A method includes storing information regarding protocols required by a plurality of climate controllers and a plurality of cooling devices. A request message is received from a first of the climate controllers, the request message being addressed to a specific cooling device. A protocol required by the specific cooling device is determined using the stored information regarding protocols required by the cooling devices. The request message is converted to the protocol required by the specific cooling device. A response message is queued from the specific cooling device if the time period allowed for responding to the first climate controller has expired. The queued response message is sent to the first climate controller when a subsequent request message is received from the first climate controller. | 11-19-2009 |
| 20090287867 | BUS SIGNAL CONTROL CIRCUIT AND SIGNAL PROCESSING CIRCUIT HAVING BUS SIGNAL CONTROL CIRCUIT - A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present. | 11-19-2009 |
| 20090287868 | MASTER DATA MANAGEMNT SYSTEM WITH IMPROVED DATA STRUCTURE AND STORAGE MEDIUM STORING THE MASTER DATA - Disclosed is a master data management (MDM) system having a unit master data storage and a unit master data update unit. The unit master data storage stores a plurality of pieces of unit master data having a data structure, in which master data is classified into the plurality of pieces of unit master data, a plurality of unique identifiers (IDs) are assigned respectively to the plurality of pieces of unit master data, and data items belonging to the master data each belongs to a corresponding one of the plurality of pieces of unit master data such that a data item belonging to a piece of unit master data does not belong to another piece of unit master data. The unit master data update unit may provide a user interface allowing one of creation, deletion, and correction of a record composed of data item fields belonging to each unit master data, and reflect the result of the creation, deletion, or correction performed through the user interface in the unit master data storage. | 11-19-2009 |
| 20090292843 | Controlling passthrough of communications between multiple buses - A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus. | 11-26-2009 |
| 20090292844 | Multiprocessor gateway - A multiprocessor gateway for multiple serial buses includes: multiple communication modules that are each provided for connection of one serial bus; multiple processors for processing data that are transferred in word-based fashion, via an internal system bus appurtenant to the respective processor, between the processor and the communication modules, the internal system buses of the multiprocessor gateway being connected to the communication modules, which have a respective appurtenant interface unit for each system bus, each processor exchanging data, via its appurtenant system bus and the interface unit, appurtenant to the system bus, of a communication module, with the serial bus connected to the communication module, independently of the other processors and without waiting time. | 11-26-2009 |
| 20090292845 | Communication System Having a Master/Slave Structure - A communication system comprising a master unit and a plurality of slave units. In error mode, e.g. when a path error or a complete failure of a subscriber occurs, data transmission is carried out in a loop, starting from the master unit, via a first communication path and a second communication path. | 11-26-2009 |
| 20090300247 | INTERFACE TRANSMISSION DEVICE AND METHOD - An interface transmission device and method are disclosed. The interface device, located in a first device, includes a transmission interface and a receiving circuit. The transmission interface receives an initialization signal and an interface signal. The receiving circuit receives the initialization signal through the transmission interface, and acquires a bit length of the interface signal according to the initialization signal. Thereby, the first device resolves the interface signal according to the bit length. | 12-03-2009 |
| 20090307400 | Method for Operating a Lin Bus - A method for operating a LIN bus, whose specifications in normal operation are described by a LIN bus in which an alternative communications protocol is tunneled through the LIN protocol, for carrying out a special operation. | 12-10-2009 |
| 20090307401 | CIRCUIT AND METHOD FOR BRIDGING MULTIPLE SOURCE AHB SLAVES TO A TARGET AHB SLAVE - A circuit and method for bridging multiple source Advanced High-performance Bus (AHB) slaves to a target AHB slave are provided. The circuit uses multiple slave controllers and a multiplexing device to handle signals between the multiple source AHB slaves and the target AHB slave to avoid conflicts between the multiple source AHB slaves to access the target AHB slave. | 12-10-2009 |
| 20090307402 | METHOD AND SYSTEM FOR A RFIC MASTER - Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index. | 12-10-2009 |
| 20090319707 | Control of master/slave communication within an integrated circuit - An integrated circuit | 12-24-2009 |
| 20090327550 | EMBEDDED SYSTEM AND HARDWARE SETTING METHOD - An embedded system is provided, comprising a non-volatile memory, at least one slave unit and a master controller. The non-volatile memory comprises at least one hardware setting value and at least one identification number. All of the non-volatile memory, slave unit and the master controller are coupled to a bus. The master controller broadcasts an identification number through the bus to identify the non-volatile memory. Then, the master controller retrieves the slave identification numbers and the hardware setting values through the bus from the non-volatile memory. | 12-31-2009 |
| 20100005208 | Efficient Execution of Memory Barrier Bus Commands - The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier. | 01-07-2010 |
| 20100011139 | NETWORK APPARATUS AND METHOD FOR COMMUNICATION BETWEEN DIFFERENT COMPONENTS - The present invention discloses a method for communication among different components, including integrating a Network Forwarding Component (NFC) for forwarding messages and at least one Independent Application Component (IAC) for performing other service processing into one network device; setting at least one cooperation mode in the NFC and each of the at least one IAC; and communicating with each other, by the NFC and the at least one IAC, according to the at least one cooperation mode. The cooperation mode may be any or any combination of a host mode, a mirror mode, a redirection mode and a pass-through mode. According to the present invention, the NFC and the IAC may communicate according to the cooperation mode so as to ensure that the NFC and the IAC can cooperate to provide various service capabilities including message forwarding and other additional service capabilities. | 01-14-2010 |
| 20100023663 | METHOD AND DEVICE FOR DETECTING BUS SUBSCRIBERS - In order to register the order of bus subscribers ( | 01-28-2010 |
| 20100030937 | Method and system for redundantly controlling a slave device - The disclosure provides a control and data transmission installation for redundantly controlling a slave device, which may be a field transmitter. The effect achieved by the control and data transmission installation is that essentially seamless control of a field transmitter can be assured even when a control device fails. The control and data transmission installation has at least two control devices and at least one slave device which are connected to one another by a communication network. The slave device contains addressable output interfaces for receiving output and status data. Each control device has a device for producing and transmitting status and output data for a separate output interface of the slave device, and the slave device has an evaluation device which controls the forwarding of received output data for further use in response to the status signals received from the control devices. | 02-04-2010 |
| 20100049891 | Method and device for synchronizing two bus systems and arrangement composed to two bus systems - A device for synchronizing at least two bus systems, having a first communications module for a first bus system and a second communications module for a second bus system, wherein in the first communications module first trigger information is present by which a trigger signal is triggered in the first bus system, characterized in that the device is configured in such a manner that the first and second communications modules are connected to each other and the first trigger information is transmitted to the second communications module, and the second communications module is configured in such a manner that a time information value is determined from the first trigger information and that time information value is compared with a second time mark of the second bus system, a time difference being determined and the next reference message being triggered in the second bus system in dependence upon the second time mark and the time difference. | 02-25-2010 |
| 20100057959 | Method as well as system for the transmission of cyclic and acyclic data - One purpose of the invention is to identify a way of transmitting data by means of a transmission channel which effectively counteracts disadvantages previously resulting from a ring structure and a linear structure, and combines advantages of the one topology group with advantages of the other topology group. For this purpose the invention proposes a method for the transmission of cyclic and acyclic data by means of a transmission channel between at least two user devices connected to the transmission channel, with a protocol-specific cyclic data transmission being carried out at least between one user device functioning as a master and at least one user device functioning as a slave, and which is characterized in that, during an impending transmission cycle, data to be transmitted is checked against corresponding data of a preceding cycle with regard to redundancy and currency and in that upon detection of an impending transmission cycle for which redundant data without new information content is provided, acyclic data is inserted in lieu of said data in the data field provided for said data. | 03-04-2010 |
| 20100057960 | SECURE INFORMATION PROCESSING - Apparatus, systems, and methods may operate to receive from a requesting device, at a memory device, a request to access a memory domain associated with the memory device, and to deny, by the memory device, the request if the memory domain comprises any part of a secure domain, and the requesting device has not asserted a secure transfer indication. Additional operations may include granting the request if the memory domain comprises some part of the secure domain and the requesting device has asserted the secure transfer signal, or if the memory domain comprises only a non-secure domain. Additional apparatus, systems, and methods are disclosed. | 03-04-2010 |
| 20100057961 | NETWORK DEVICE AND DATA TRANSMITTING METHOD - A network device includes a data bus, a plurality of signal control lines, a plurality of line cards, and a management card. The plurality of line cards corresponds to the plurality of signal control lines and each line card connects to one corresponding signal control line. The management card transmits data to the line cards by way of the data bus and transmits control signals to the line cards by way of the signal control lines. The plurality of line cards accept the data from the management card by way of the data bus according to the control signals from the signal control lines. | 03-04-2010 |
| 20100064083 | COMMUNICATIONS DEVICE WITHOUT PASSIVE PULLUP COMPONENTS - A dual-wire communications bus circuit, compatible with existing two-wire protocols, includes a first and second part of the communications bus circuit to couple to a communications bus. The bus has a first line for carrying data signals from a master device to a slave device and a second line to carry a clock signal between the devices. To improve data throughout and reduce noise, an active pullup device is located in at least one part of the communications bus circuit, the active pullup device in the first part of the of the communications bus circuit couples to the first line and an optional active pullup device in the second part couples to the second line of the communications bus. Each active pullup device may provide a high logic level on one of the communications bus lines. | 03-11-2010 |
| 20100077119 | Method and Devices for Data Transfer - A storage apparatus is proposed for facilitating wireless communication between a computer device and one or more external portable electronic devices, or between those external devices. The storage apparatus includes a wireless transceiver for entering communication with any one of the devices. When the storage apparatus is communicating with any of the devices, it can transmit tot hat device any data stored in its memory for transmission to that device. Furthermore, the storage apparatus can receive from that device, and transmit to its memory, data to be relayed to another of the devices. | 03-25-2010 |
| 20100082863 | I/O AND MEMORY BUS SYSTEM FOR DFPs AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES - A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading). | 04-01-2010 |
| 20100088441 | MULTI-PROCESSOR CONTROLLER FOR AN INVERTER IN AN ELECTRIC TRACTION SYSTEM FOR A VEHICLE - A multi-processor controller is provided. The multi-processor controller can be used to control the operation of an inverter in a vehicle-based electric traction system. The multi-processor controller includes a master processor device having three serial peripheral interfaces (SPIs), and three slave processor devices coupled to the master processor device via the SPIs. The master processor device issues commands to the slave processor devices to control operation of the inverter. | 04-08-2010 |
| 20100088442 | Communications entity for communications via a bus-oriented communications network - The invention relates to a communications entity for communications via a bus-oriented communications network with a control device ( | 04-08-2010 |
| 20100095035 | POLYHEDRAL ASSEMBLY, MASTER-SLAVE BASED ELECTRONIC SYSTEM USING THE SAME AND ADDRESSING METHOD THEREOF - A polyhedral is provided. The surface of the polyhedral is formed by connection of a plane having a plurality of hexagons and a plane having a plurality of quadrilaterals. There are six hexagonal connected to form a ring covering the surface of the polyhedral. On the surface of the polyhedral, any two connected hexagons form a contained angle of 120 degrees. The polyhedral has a light source and an electric control circuit disposed therein. A plurality of polyhedron can be connected into a multi-media light assembly having a numerical display function or a clock function. | 04-15-2010 |
| 20100115166 | CONTROL OF AN ACTUATOR-SENSOR-INTERFACE COMPATIBLE DEVICE USING A REMOTE INTELLIGENCE DEVICE - A communication network that includes a master device, an actuator-sensor-interface (AS-I) communication bus, a device configured to be monitored and controlled, and a slave device in communication with the master device via the AS-I communication bus. The device that is configured to be monitored and controlled, is operatively connectable to the slave device, and the slave device is configured to receive commands from the master device via the AS-I communication bus, and to execute the commands to control the device. | 05-06-2010 |
| 20100122000 | Method for Accessing a Data Transmission Bus, Corresponding Device and System - The invention relates to a bus, which is connectable to a primary master and to secondary masters, the bus being suitable for the transmission of data between the peripherals. In order to ensure a minimum rate and/or maximum latency between the secondary masters, when the primary master uses a small time fraction available on the bus, said primary master is provided with the highest priority and comprises means for wirelessly accessing to a medium. The inventive method for accessing to the bus consists in authorising the primary master to access to the bus upon the request thereof and in selecting the access to the bus for the secondary masters when the primary master peripheral does not request said access to the bus. | 05-13-2010 |
| 20100122001 | TECHNIQUE FOR INTERCONNECTING INTEGRATED CIRCUITS - Two integrated circuit die each having a processing core and on-board memory are interconnected and packaged together to form a multi-chip module. The first die is considered primary and the second die is considered secondary are connected through an interposer. The first and second die may be the same design and thus have the same resources such as peripherals and memory and preferably have a common system interconnect protocol. The core of the second die is disabled or at least placed in a reduced power mode. The first die includes minimal circuit for interconnecting to the second die. The second die has some required interface circuitry and an address translator. The result is that the core of the first die can perform transactions with the memory and other resources of the second integrated circuit as if the memory and other resources were on the first die. | 05-13-2010 |
| 20100122002 | AUTOMATIC ON-DEMAND PRESCALE CALIBRATION ACROSS MULTIPLE DEVICES WITH INDEPENDENT OSCILLATORS OVER AN I2C BUS INTERFACE - A system and method for synchronizing otherwise independent oscillators private to I | 05-13-2010 |
| 20100122003 | RING-BASED HIGH SPEED BUS INTERFACE - A communication system management interface includes a control master; and one or more slaves under management by the control master; wherein each device, either the control master or slave, has at least an input signal connected to an output signal of another device to form a daisy-chain. | 05-13-2010 |
| 20100138575 | DEVICES, SYSTEMS, AND METHODS TO SYNCHRONIZE SIMULTANEOUS DMA PARALLEL PROCESSING OF A SINGLE DATA STREAM BY MULTIPLE DEVICES - Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream. | 06-03-2010 |
| 20100138576 | DATA TRANSMISSION METHOD BETWEEN MASTER AND SLAVE DEVICES - A method for transmitting data frames between a master device and one or more slave devices via a bus system having at least one request line for transmitting request data frames from the master device to the slave devices, a response line for transmitting response data frames from the slave devices to the master device and at least one selection line for activating the slave devices, the request data frames and the response data frames being transmitted together with at least one address bit for addressing one of the slave devices, the useful data bits and at least one length-indicating bit for indicating the data frame length. | 06-03-2010 |
| 20100138577 | APPARATUS AND METHOD FOR WRITING BITWISE DATA IN SYSTEM ON CHIP - An apparatus and a method for writing bitwise data in a System On Chip (SOC) are provided. In the method, a master determines whether a size of data to be written on a slave is equal to or smaller than half of a size of data transmittable at a time. If it is determined that the data is equal to or smaller than half of the size of the data transmittable at a time, the master transmits the data to the slave via a bus. The master transmits a signal representing a bit at which the data is to be written via a bus lane not used for the data transmission. | 06-03-2010 |
| 20100146173 | ESTABLISHING COMMUNICATION OVER SERIAL BUSES IN A SLAVE DEVICE - In accordance with an aspect of the present invention, a slave device enters a state suitable for establishing communication with a host device only if additional information is received on a serial bus after receiving a reset signal on the same bus. Such a feature may avoid or reduce disruption to applications executing on a slave device when false reset signals are received, for example, when the slave device is connected to a dumb charger on a USB interface for charging. | 06-10-2010 |
| 20100146174 | Method for Protecting Against External Interventions into a Master/Slave Bus System and Master/Slave Bus System - The method serves for protecting against external interventions into a master/slave bus system. The master/slave bus system contains at least one slave and at least one authorized master for outputting an authentic command. The authentic command instructs the slave to carry out a function. Accordingly, the authenticity of the command which has been transmitted over the bus is checked. The execution of the function is enabled only in the event of a positive check result. | 06-10-2010 |
| 20100146175 | DATA DRIVING APPARATUS AND DISPLAY DEVICE USING THE SAME - A display device includes; a signal controller which outputs a master image signal having first data information and second data information, a master data driver which samples the first data information and the second data information from the master image signal using a first sampling clock signal, generates a slave clock signal using the master image signal, and generates a slave image signal, which corresponds to the second data information, using the slave clock signal, and a slave data driver connected to the master data driver in a cascade manner, wherein the slave data driver samples the second data information from the slave image signal. | 06-10-2010 |
| 20100146176 | DATA TRANSMISSION METHOD, SERIAL BUS SYSTEM, AND SWITCH-ON UNIT FOR A PASSIVE STATION - In a serial bus system data in the form of telegrams, representing process images of control tasks of the active station, are transmitted to the connected passive stations, and the process data are allocated to the process images in the passive station. | 06-10-2010 |
| 20100153600 | SYSTEM, APPARATUS, AND METHOD FOR BROADCASTING USB DATA STREAMS - Exemplary embodiments are directed to broadcasting data on a USB system. The system includes a USB host and multiple broadcast-capable USB devices. Each USB device includes at least a default control endpoint for receiving control information and an isochronous sink endpoint for receiving a broadcast stream. The USB host programs a shared device address to an address register of each USB device such that all broadcast-capable USB devices programmed to that shared device address will accept the broadcast stream. One of the USB devices at the shared device address is set as a primary broadcast slave that will respond to non-isochronous transfers to the shared device address. All other USB devices with the shared device address are set to secondary slaves that ignore non-isochronous transfers to the shared device address. | 06-17-2010 |
| 20100153601 | METHOD FOR PREVENTING TRANSACTION COLLISION ON BUS AND COMPUTER SYSTEM UTILIZING THE SAME - A computer system is provided. The computer system includes a bus, a first master device, a second master device and a processor. The bus has a data line and a clock line. The first master device is coupled to the bus, detects a start phase of a first transaction on the data line, issues an interrupt message upon the detection of the start phase, and triggers a second transaction in response to a transaction indication message. The processor is coupled to the first master device, receives the interrupt message, and transmits the transaction indication message after a predetermined time interval upon reception of the interrupt message. The second master device is coupled to the bus and triggers the first transaction. The first transaction is finished within the predetermined time interval. | 06-17-2010 |
| 20100153602 | COMPUTER SYSTEM AND ABNORMALITY DETECTION CIRCUIT - A computer system includes multiple modules that perform communication via a bus, and abnormality detection circuits that monitor signals on the bus related to communication between the modules to detect a hang-up, wherein each of the abnormality detection circuits is arranged to correspond to a part of the multiple modules, and, when detecting the hang-up, generates and outputs a signal instructing reactivation only of the corresponding module. | 06-17-2010 |
| 20100169525 | PIPELINED DEVICE AND A METHOD FOR EXECUTING TRANSACTIONS IN A PIPELINED DEVICE - A pipelined device and method for executing transactions in a pipelined device, the method includes: setting limiter thresholds that define a maximal amount of pending transaction requests to be provided from one pipeline stage to another pipeline stage; executing an application while monitoring the performance of a device that comprises pipeline limiters; wherein the executing includes: selectively transferring transaction requests from one stage of the pipeline to another in response to the limiter thresholds, arbitrating between transaction requests at a certain pipeline stage, and executing selected transaction requests provided by the arbitrating. | 07-01-2010 |
| 20100169526 | SLAVE AND COMMUNICATING METHOD BETWEEN A MASTER AND THE SAME - A slave and a communicating method between a slave and a master that includes checking whether the command to be sent is one of a write command and a read-out command if the master attempts to send a command to the slave, determining whether a processing of a previous command sent by the master is entirely completed if the command to be sent is the write command, and sending an acknowledgement signal that allows a transfer of the command to the master if the processing of the previously sent command is determined as one of entirely completed and the command to be sent is determined as the read-out command. The master sends the command to the slave in response to the acknowledgement signal sent by the slave. | 07-01-2010 |
| 20100169527 | DATA PATH MASTER/SLAVE DATA PROCESSING DEVICE - An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave. | 07-01-2010 |
| 20100174839 | MAIN BOARD SYSTEM AND METHOD FOR SETTING MAIN BOARD SYSTEM - A method for setting a main board system is disclosed. According to the method, a first pin setting signal is received, and a board module is determined if it is a master module or a slave module according to the received first pin setting signal. Then, a potential of a third pin is detected when the board module is the slave module, and the master module is determined whether it exists according to the detected potential of the third pin. After that, the slave module enters a first mode if the master module doesn't exist, and the slave module enters a second mode if the master module exists. | 07-08-2010 |
| 20100199007 | Direct Slave-to-Slave Data Transfer on a Master-Slave Bus - A method and system for transferring data between two slave devices. A system includes a master device and first and second slave devices coupled to the master device by a peripheral bus. The master device is configured to configure the first slave device as a source for a read operation, configure the second slave device as a target for a write operation, provide a clock signal to both the first slave device and the second slave device, and initiate a read operation of the first slave device. Initiation of the read operation causes the first slave device to provide data onto the peripheral bus. Responsive to the master device initiating the read operation, the second slave device receives the data provided on the peripheral bus by the first slave device. The master device is configured to ignore the data provided on the peripheral bus by the first slave device. | 08-05-2010 |
| 20100199008 | System and method for implementing a remote input device using virtualization techniques for wireless device - Systems and methods for implementing a remote input device using virtualization techniques for wireless devices are described. In one aspect, the system may comprise a wireless device that includes a processor, a memory, input hardware, and a protocol slave adapted to communicate with the input hardware; and a removable media device that includes a memory, a processor, and a protocol master adapted to communicate with the protocol slave of the wireless device. In another embodiment, the method may comprise emulating a hardware interface on a removable media device; mapping input hardware of a wireless device to the interface; mapping a processor of the media device to the input hardware; wrapping and sending input hardware commands from a protocol master of the media device to a protocol slave of the wireless device; and executing the commands on the input device. | 08-05-2010 |
| 20100199009 | SERIAL DATA COMMUNICATION SYSTEM AND SERIAL DATA COMMUNICATION METHOD - When transmitting serial data from a master device to a slave device, it is possible to promptly detect a communication error if any occurs. Serial data transmitted from the master device to the slave device has two or more continuous bytes of dummy data having an identical structure. When the slave device recognizes the dummy data, communication error processing is executed. Assume that the serial data is shifted by an affect of a noise. In this case, “a text end control code (ETX)” is also shifted and the serial data cannot be recognized and no data reception end process is executed. However, during a period after this, a part of the first dummy data and a part of the second dummy data are received and one dummy data is recognized. Thus, the slave device can promptly execute the communication error processing. | 08-05-2010 |
| 20100205340 | METHOD OF DETERMINING REQUEST TRANSMISSION PRIORITY SUBJECT TO REQUEST CONTENT AND TRANSMITTING REQUEST SUBJECT TO SUCH REQUEST TRANSMISSION PRIORITY IN APPLICATION OF FIELDBUS COMMUNICATION FRAMEWORK - A method of determining request transmission priority subject to request content and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective content, and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time. | 08-12-2010 |
| 20100211710 | DATA ACCESSING SYSTEM - A data accessing system bridges a first master device and a second master device to a first slave device and a second slave device. The data accessing system includes a register, a first multiplexer, a second multiplexer and a control unit. The amount of data that the first master device can process each cycle is less than which of the second slave device. The data accessing system can solve the problem when the first master device writes data to the second slave device via merging two different data. Also, the data accessing system can solve the problem when the first master device reads data to the second slave device via extracting part of the data. | 08-19-2010 |
| 20100211711 | Method, bus components, and control system for ethernet-based control of an automation system - A method is disclosed in which data is exchanged via a bus coupler ( | 08-19-2010 |
| 20100217903 | SIMULTANEOUS CONTROL OF MULTIPLE I/O BANKS IN AN I2C SLAVE DEVICE - Consistent with one example embodiment, communications systems ( | 08-26-2010 |
| 20100223409 | BUS ARBITRATION APPARATUS AND METHOD - A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A | 09-02-2010 |
| 20100223410 | Reduced Instruction Set Baseband Controller - In wireless communications such as in the Bluetooth communication system, an execution unit sequentially receives software instructions for execution. Prior to completing each instruction, the execution unit issues an interrupt indicating the upcoming completion of the instruction execution and awaits receipt of the next instruction. A Link Manager issues limited instructions, and a Link Controller includes a hardware execution unit for executing the limited instructions. A processing unit in the Link Manager performs remaining functions under control of a software program. | 09-02-2010 |
| 20100235555 | SOFTWARE LAYER FOR COMMUNICATION BETWEEN RS-232 TO I2C TRANSLATION IC AND A HOST - A host controller ( | 09-16-2010 |
| 20100235556 | MULTI-DISPLAY DIGITAL PHOTO FRAME - A multi-display digital photo frame is provided. The multi-display digital photo frame includes an user input unit, a memory, at least two displays, and an appropriate number of processors, wherein the number of the processors is equal to the number of the displays, each of the processors is connected with a display, and is configured for controlling the corresponding display. | 09-16-2010 |
| 20100241773 | REAL-TIME INDUSTRIAL ETHERNET ETHERCAT COMMUNICATION CONTROL - A real-time industrial Ethernet EtherCAT system including a communication master and a plurality of slave nodes, wherein one slave node acts as a logic control master and the further slave nodes act as logic control slaves, and wherein a communication flow is as follows: the communication master sends a data fetching frame, when the data fetching frame passes through the logic control master, the logic control master inputs control data for the logic control slaves into the data fetching frame, when the data fetching frame passes through the logic control slaves, each logic control slave inputs status data into the data fetching frame, after return of the data fetching frame to the communication master, the communication master sends a data sending frame with output data, said output data being reorganized according to the control relationship between the logic control master and the logic control slaves by the communication master, when the data sending frame passes through the logic control master, the logic control master gets the status data of the logic control slaves from the data sending frame, and when the data sending frame passes through the logic control slaves, each logic control slave gets command data from data sending frame. | 09-23-2010 |
| 20100250804 | METHOD FOR IC COMMUNICATION SYSTEM - A method of optimizing the usage of communication buses is disclosed. In this method, a slave may function, when necessary, as a ‘pseudo-master’. This allows direct communication between slaves, one of which functions as a ‘pseudo-master’. This hence relieves the Master device of the load required as an intermediary for the communication of said slaves. | 09-30-2010 |
| 20100250805 | COMMUNICATION PROTOCOL - One aspect relates to a communication protocol for communicating between one or more entities, such as devices, hosts or any other system capable of communicating over a network. Another aspect relates to a system architecture that permits more than one slave system (e.g., a slave device) to be connected to a master system (e.g., a master device) in a communication system implementing a master/slave protocol. In one aspect, a pass-through device is provided that facilitates communication and authentication to one or more downstream slave devices. Yet another aspect relates to a star-based configuration of slave devices coupled to the master, and protocols for communicating and authenticating slave devices. Another aspect relates to a protocol that allows communication between entities without a priori knowledge of the communication protocol. In such a protocol, for example, information describing a data structure of the communication protocol is transferred between communicating entities. Further, an authentication protocol is provided for providing bidirectional authentication between communicating entities. In one specific example, the entities include a master device and a slave device coupled by a serial link. In another specific example, the communication protocol may be used for performing unbalanced transmission between communicating entities. | 09-30-2010 |
| 20100250806 | DEVICE AND METHOD FOR MANAGING ACCESS REQUESTS - A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request. | 09-30-2010 |
| 20100250807 | SWITCH SYSTEM, SUB-SWITCH AND METHOD OF CONTROLLING SWITCH SYSTEM - A switch system has a master sub-switch and a slave sub-switch, the master sub-switch having a first bridge for transmitting the received packet via the first bus, a second bridge for transmitting the packet when the address information of the second bridge matches with the address information included in the packet, and a third bridge for receiving the packet from the first bridge and transmitting the packet to the slave sub-witch, the slave sub-switch having a fourth bridge for receiving the packet from the third bridge and transmitting the packet, and a fifth bridge for receiving the packet from the fourth bridge, and transmitting the packet when the address information of the fifth bridge matches with the address information included in the packet, wherein the master sub-switch has a table including address information of the fifth bridge, and transmits the packet to the fifth bridge in reference to the table. | 09-30-2010 |
| 20100262735 | TECHNIQUES FOR TRIGGERING A BLOCK MOVE USING A SYSTEM BUS WRITE COMMAND INITIATED BY USER CODE - A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command (via the system bus) process the specific request-type command when the core permission controls are the same as the respective slave permission controls. | 10-14-2010 |
| 20100262736 | COMMUNICATION METHOD AND MASTER-SLAVE SYSTEM FOR A FIELD BUS CONFIGURED ACCORDING TO THE AS-INTERFACE STANDARD - A communication method and a master-slave system, for a field bus configures according to the AS-interface standard, are disclosed. Such a master-slave system for a field bus configured according to the AS-interface standard connects a master to a number of slaves. This field bus forms a first communication channel for the master and the slaves. In at least one embodiment, the master communicates with the slaves in sequence via telegrams, which are each uniquely associated with one of the slaves. Between the master and slaves a second communication channel is provided in at least one embodiment, via which one of the telegrams may be repeated, in addition to the first communication channel, if the communication of said telegram via the first communication channel has failed. | 10-14-2010 |
| 20100281198 | Bus relay device and bus control system - A combination includes a first bus master coupled to a first bus to output a first signal group including at least one of signals onto the first bus, a second bus master coupled to the first bus to output a second signal group including at least one of signals onto the first bus, an interconnect section coupled between the first bus and a second bus to receive the first and second signal groups and to output a third signal group including at least one of signals onto the second bus, and a bridge section coupled between the second bus and a third bus to receive the third signal group and to output a fourth signal group including at least one of signals onto the third bus free from performing a selecting operation for the third signal group. | 11-04-2010 |
| 20100287318 | I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES - A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading). | 11-11-2010 |
| 20100293313 | SYSTEMS AND METHODS FOR A CORE MANAGEMENT SYSTEM FOR PARALLEL PROCESSING OF AN EVOLUTIONARY ALGORITHM - Systems and methods are provided for a core management system for parallel processing of an evolutionary algorithm. The systems and methods may include identifying, for a processing environment, a plurality of arriving processors available for utilization; configuring a first number of the plurality of arriving processors as master processors for the processing environment; configuring a respective second number of the plurality of arriving processors as slave processors, where each master processor is assigned one or more of the slave processors for the processing environment, where each master processor maintains timing data associated with available processing resources at the respective master processor, where each master processor is operative to calculate a respective target number of slaves based upon the respective timing data; and reconfiguring a current number of slave processors assigned to one or more respective master processors based upon the respective timing data calculated for the one or more respective master processors. | 11-18-2010 |
| 20100306431 | Dynamic Address Change for Slave Devices on a Shared Bus - A master/slave data communication system in which a master device communicates with the slave devices by uniquely addressing each of the slave devices. In order to enhance the security of the data communication system, each slave device includes an address generator for generating unique addresses. Periodically, the master device requests that one or more slave device change its address. In response to the request, the addressed slave device increments its address generating algorithm to provide a new slave address. The master device also includes an algorithm that is synchronized with the slave address generating algorithm, whereby when the slave changes its address, it need not transmit the new slave address to the master device over the bus. | 12-02-2010 |
| 20100325326 | DEVICE INFORMATION MANAGEMENT SYSTEM AND DEVICE INFORMATION MANAGEMENT METHOD - A device information management system for managing device information of various peripheral devices is disclosed. The system includes a central processing unit, a logic controller connected with the central processing unit, a first device connected with the logic controller, wherein the first device has a device information stored in a memory unit for identifying the first device, and a second device connected with the first device, wherein the first device outputs an access command to the second device and the second device accesses the memory unit to retrieve the device information of the first device according to the access command. | 12-23-2010 |
| 20110016243 | METHOD AND DEVICE OF LOAD-SHARING IN IRF STACK - The present invention provides a method and device of load-sharing in an IRF stack. The method includes: the Master device checking a congestion state of the main path, obtaining a path for forwarding service flow according the congestion state of the main path, where the path is the main path or a backup path, and forwarding the service flow to the egress device through the main path or the backup bath to implement the load-sharing in the IRF stack. In the embodiments of the present invention, by checking the congestion states of main path and the backup path in real-time, the load-sharing of the IRF stack is implemented. When new service flow is added, the data may be forwarded through another path, which can improve the efficiency of member devices in the IRF stack and solve the problem of forwarding bottleneck to which the member devices face. | 01-20-2011 |
| 20110016244 | INFORMATION PROCESSING DEVICE AND PROCESSOR - A semiconductor device including: a first slave device; a first master device outputting a first request control signal and a first access address signal; a second master device outputting a second request control signal and a second access address signal; a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and a range setting register holding an address range of which an access of the first master device is permitted, wherein the system bus blocks the first request control signal if the first access address signal is out of the address range. | 01-20-2011 |
| 20110029703 | ELECTRONIC DEVICE CAPABLE OF AUTOMATICALLY SWITCHING BETWEEN A MASTER MODE AND A SLAVE MODE - An electronic device, includes a USB interface, a processing unit, a master-slave select triggering circuit, a controlling unit, a selection circuit and a switching circuit. The master-slave selection triggering circuit including an input port, a first output port and a second output port. The master-slave select triggering circuit is used to detect the type of external electronic devices connected to the USB interface, if the external electronic device is a master device, the first and second output port output a slave triggering signal, the controlling unit switches off the switching circuit t and the selection circuit selects the processing unit into slave mode; if the external electronic device is the slave device, the first and second output port output a master triggering signal, the controlling unit switches on the switching circuit and the selection circuit select the processing unit into master mode. | 02-03-2011 |
| 20110029704 | COMMUNICATION SYSTEM HAVING A PLURALITY OF COMMUNICATION NODES - A certain ECU transmits a reference message for requiring the other ECUs to transmit data. After transmission of the reference message, each of all the ECUs transmits priority information of its transmit message onto a communication bus, and then detects whether some priority information transmitted from the other ECUs has a higher priority than its own transmitted priority information. If there is detected no priority information of a higher priority than its own transmitted priority information, it transmits a message associated therewith, and then is prohibited to transmit data of the same priority until receiving a next reference message. | 02-03-2011 |
| 20110029705 | MULTI-DROP SERIAL BUS WITH LOCATION DETECTION AND METHOD - A multi-drop serial bus to connect a master device to a plurality of slave devices on a data line includes a voltage divider network, comprising divider resistors in series on the data line between slave devices, and a voltage sensing device, connected to the data line, configured to detect a voltage order of signals from the slave devices, indicating a position of connection of each slave device. | 02-03-2011 |
| 20110029706 | ELECTRONIC DEVICE AND METHOD FOR CONTROLLING AN ELECTRONIC DEVICE - An electronic device is provided. The electronic device comprises at least one master network interface (MNI) with in a credit count unit (CC) for counting received credits and a first buffer unit (FIFO). The electronic device furthermore comprises at least one slave network interface (SNI) which comprises a threshold unit (TU) and at least one second buffer unit (FIFO). The electronic device furthermore comprises an interconnect (N) for coupling the at least one master network interface (MNI) and the at least one slave network interface (SNI). The slave network interface (SNI) is adapted to send a number of credits via the interconnect (N) to the master network interface (MNI) if the available amount of space or credits in the at least one second FIFO buffer (FIFO) reaches a threshold value stored in the threshold unit (TU). The slave network interface (SNI) is adapted to send the available credits via the interconnect (N) to the master network interface (MNI) if a predetermined time interval has lapsed or if an event from an external event generator is received even if the number of credits is below the threshold value stored in the threshold unit (TU). | 02-03-2011 |
| 20110035523 | Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure - A communication infrastructure for a data processing apparatus, and a method of operation of such a communication infrastructure are provided. The communication infrastructure provides first and second switching circuits interconnected via a bidirectional link. Both of the switching circuits employ a multi-channel communication protocol, such that for each transaction a communication path is established from an initiating master interface to a target slave interface, with that communication path comprising m channels. The m channels comprise one or more forward channels from the initiating master interface to the target slave interface and one or more reverse channels from the target slave interface to the initiating master interface, and handshaking signals are associated with each of the m channels. The bidirectional link comprises n connection lines, where n is less than m, the bidirectional link supporting a first communication path from the first switching circuit to the second switching circuit and a second communication path in an opposite direction from the second switching circuit to the first switching circuit. Control circuitry is used to multiplex at least one forward channel of the first communication path and at least one reverse channel of the second communication path, with the multiplexing being performed in dependence on the handshaking signals associated with the channels to be multiplexed. This allows the 2 | 02-10-2011 |
| 20110040912 | APPARATUS AND METHOD FOR MULTIPLE ENDIAN MODE BUS MATCHING - Apparatus and method for bus matching. The method includes: receiving data transfer characteristics at a first endian mode and at a second endian mode; determining a connectivity of multiple devices to an interfacing bus in response to the data transfer characteristics and in response to a relationship between a width of the interfacing bus and a width of each device interface; wherein at least one device interface is connected in parallel to multiple interfacing bus portions; and configuring a control logic such as to provide control signals representative of a transfer of data over the interfacing bus; whereas the control logic is configured in response to the connectivity. The apparatus includes: an interfacing bus characterized by an interfacing bus width; a master device, connected to the interfacing bus, whereas the master device includes a master device interface; multiple slave devices, each slave device connected to the interfacing bus and includes a slave device interface; wherein at least one slave device interface is connected in parallel to multiple interfacing bus portions; and control logic, connected to the interfacing bus and to the master device, the control logic is adapted to provide control signals representative of a transfer of data over the interfacing bus; whereas the control logic is configured in response to a connectivity of the multiple slave devices to the interfacing bus; whereas said connectivity is responsive to data transfer characteristics and is responsive to relationships between a width of the interfacing bus and a width of each device interface. | 02-17-2011 |
| 20110055442 | LINEAR OR ROTATIONAL MOTOR DRIVER IDENTIFICATION - A mechanism for assigning unique addresses to identical devices attached to a serial bus is presented. Each device has at least one output and is provided with a storage device to provide a configurable portion of a bus address having a fixed portion and a configurable portion. The device is further provided with circuitry, coupled to the storage device and the output, to determine a state of the output and use the state to configure the configurable portion. Once the configurable portion is configured, the bus address uniquely identifies the device. Such configuration allows more than one such device to be coupled to the same serial bus, e.g., an I | 03-03-2011 |
| 20110060856 | SPI CONTROL DEVICE AND METHOD FOR ACCESSING SPI SLAVE DEVICES USING THE SAME - A method for accessing serial peripheral interface (SPI) slave devices using an SPI control device determines an SPI slave device to be operated, sets an operation type of the determined SPI slave device, and further sets a clock rate, a clock phase, and a clock polarity of the determined SPI slave device. The method further generates a clock signal according to the clock rate, the clock phase, and the clock polarity of the determined SPI slave device, and performs a read operation or a write operation on the determined SPI slave device according to the clock signal. | 03-10-2011 |
| 20110066780 | Data processing apparatus and method for measuring a value of a predetermined property of transactions - A data processing apparatus and method for measuring a value of a predetermined property of transactions are provided. The data processing apparatus has initiator circuitry for initiating transactions, recipient circuitry for handling each transaction initiator by the initiator circuitry, and a communication path interconnecting the initiator circuitry and the recipient circuitry via which the transactions are propagated between the initiator circuitry and the recipient circuitry. Measurement circuitry is coupled to the communication path for measuring a value of a predetermined property of the transactions, such as the latency of those transactions. The measurement circuitry has active transaction count circuitry for maintaining an indication of the number of transactions in progress, and accumulator circuitry for maintaining an accumulator value which is increased dependent on the number of transactions in progress. Further, a value register is provided for maintaining an estimate of the value of the predetermined property. Each time a transaction in progress reaches a predetermined point, for example a transaction end point, the accumulator value is decreased dependent on the estimate currently stored in the value register, and further the estimate stored in the value register is updated dependent on the accumulator value. Via this feedback mechanism, the estimate stored in the value register quickly settles to the actual value of the predetermined property being measured, and accordingly such measurement circuitry provides a simple, low cost and flexible mechanism for measuring the value of a predetermined property of transactions. | 03-17-2011 |
| 20110066781 | METHOD FOR ASSIGNING ADRESSES TO INJECTORS - A method for assigning addresses to injectors of an internal combustion machine, wherein, prior to the starting procedure, an electronic motor control device selects a first injector by activating the first injector by a first control line from the electronic motor control device. The electronic motor control device is arranged on a data bus to which the electronic motor control device and all injectors are connected. A first address value is placed on the motor control device and the first injector assumes the first address value as the address assigned to it. | 03-17-2011 |
| 20110072176 | METER SYSTEM WITH MASTER/SLAVE METERS - A meter system includes a CAN-Bus, a master meter, a slave bus, and a slave meter. The master meter includes a first CAN module, a master display, a master communication interface, and a master processor. The master meter is for receiving a signal transmitted from the CAN-Bus and for transforming the signal to a message signal, so as to control the master display to display the corresponding information or to transfer the message signal to the salve bus. The slave meter includes a slave communication interface, a slave display, and a slave processor. The slave meter is for receiving the message signal transmitted from the slave bus and for controlling the slave display to display the corresponding information. | 03-24-2011 |
| 20110078350 | METHOD FOR GENERATING MULTIPLE SERIAL BUS CHIP SELECTS USING SINGLE CHIP SELECT SIGNAL AND MODULATION OF CLOCK SIGNAL FREQUENCY - A system includes a serial bus having an electrical net for conveying a clock signal, and a master device and a plurality of slave devices coupled to the serial bus. The master device modulates a clock signal on its output on an electrical net according to first and second manners to select respective first and second of the slave devices. The first manner is distinct from the second manner. In alternate embodiments, the first and second manners are: (1) different frequencies of the clock signal; and (2) pulse trains on the clock signal with different predetermined numbers of clock edges prior to the assertion of a single slave select signal from the master device. In alternate embodiments: (1) each slave detects the first and second manners directly from the master; and (2) a distinct device detects the first and second manners from the master device and generates individual slave selects. | 03-31-2011 |
| 20110078351 | INFORMATION PROCESSOR SYSTEM - In an information processor system including a memory device (MEMO), a memory control device (SL | 03-31-2011 |
| 20110082955 | I2C/SMBus Ladders and Ladder Enabled ICs - I2C/SMBus ladders and ladder enabled ICs (devices) to enable daisy-chained I2C/SMBus communication. The devices are particularly useful in monitoring and/or servicing high-voltage battery stacks and other voltage stacks. The devices are powered from a respective voltage increment in the voltage stack, and include level shifting circuitry so as to be operative with an input voltage up to the breakdown voltage of the level shifting circuitry. Various features are disclosed, including but not limited to a unique data line drive, capacitive coupling between devices in a daisy chain with line clamps for circuitry protection and capacitive coupling charge wiping, and clock stretching to accommodate chain latency. | 04-07-2011 |
| 20110082956 | Information processing system and control method thereof - A control method of an information processing system including an address/data bus, the control method including: asserting a write enable signal indicating a write operation no later than an assertion of a latch control signal indicating an address latch timing in the write operation; asserting an output enable signal indicating a read operation after the address latch timing in the read operation; determine whether the write enable signal is asserted when the latch control signal is asserted; and starting the read or write operation according to the determined result no later than the address latch timing. | 04-07-2011 |
| 20110082957 | SLAVE DEVICE FOR AN IIC BUS COMMUNICATION SYSTEM CAPABLE OF SUPRESSING FREEZE OF IIC BUS COMMUNICATION - Multiple master devices and multiple slave devices are connected in parallel to two bus lines including a SCL line | 04-07-2011 |
| 20110093635 | Communication centralized control system and communication centralized control method - Disclosed herein is a communication centralized control system including one master device; a communication bus; and a plurality of slave devices configured to be connected to the master device by the communication bus, wherein the master device and the plurality of slave devices are capable of bidirectional communication via the communication bus, and different channels are allocated to at least polling communication from the master device to the slave devices and interrupt communication from the slave devices to the master device, and communication is carried out with multiplexing on the same line. | 04-21-2011 |
| 20110099310 | CONTROLLING PASSTHROUGH OF COMMUNICATION BETWEEN MULTIPLE BUSES - A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus. | 04-28-2011 |
| 20110099311 | COMMUNICATION SYSTEM, COMMUNICATION APPARATUS, CONTROL METHOD THEREFOR, AND COMPUTER PROGRAM - In a communication system, one of a plurality of communication apparatuses that acts as a host controls data transmission and the other communication apparatuses that act as devices perform data transmission under control of the host over a predetermined communication interface. The communication apparatuses have both host and device roles, and are configured to exchange the host and device roles by using a predetermined communication protocol are connected to the predetermined communication interface. A first apparatus acts as a host and a second apparatus as a device. The second apparatus transmits information concerning the second apparatus to the first apparatus. The first apparatus compares the transmitted information with information concerning the first apparatus to determine whether or not to switch the host and device roles according to a predetermined criterion. In response to an affirmative determination, the host and device roles are switched by using the predetermined communication protocol. | 04-28-2011 |
| 20110106991 | Bus system and bus control method - A bus system in accordance with an exemplary aspect of the present invention includes a bus master that performs a preparation for a next access after receiving a write response signal indicating a write result of data in a write access; a bus slave that writes data indicated by a write data signal according to an output of the write data signal from the bus master in the write access, and outputs an authentic write response signal in the writing to the bus master; a bus that connects the bus master and the bus slave, and includes a register slice; and a signal generating unit that outputs a dummy write response signal to the bus master when an end of the write data signal output from the bus master is detected. | 05-05-2011 |
| 20110106992 | APPARATUS AND METHOD FOR SCALING DYNAMIC BUS CLOCK - An apparatus and a method for scaling a dynamic bus clock are provided. The apparatus for scaling the dynamic bus clock includes at least one master module, at least one slave module, a bus for delivering data transmitted and received by the at least one master module and the at least one slave module, a bus frequency controller for determining a bus clock frequency by considering activity information of the at least one master module, and a clock generator for generating the frequency as determined by the bus frequency controller and providing the generated frequency to the at least one master module, the at least one slave module, and the bus. | 05-05-2011 |
| 20110113171 | ACKNOWLEDGEMENT MANAGEMENT TECHNIQUE FOR SUPPORTED COMMAND SET OF SMBUS/PMBUS SLAVE APPLICATIONS - A slave device has an input/output adapted for connection to a serial data line of an I | 05-12-2011 |
| 20110119419 | Apparatus and Method for Polling Addresses of One or More Slave Devices in a Communications System - An address polling method and system for communicating unique slave address values to a master device over a shared bus. The method includes receiving a request signal from the master device requesting that a slave address from each slave device coupled to the data line be sent to the master; causing, in a serial manner, the data line to be placed in logic states corresponding to bit values in a first slave address; and upon the data line being placed in a logic state that is different from a corresponding bit value of the first slave address, determining that another slave device is placing its slave address on the data line and temporarily entering an idle state until such other slave device has finished communicating its slave address to the master device. | 05-19-2011 |
| 20110119420 | ELECTRONIC DEVICE - A communication system enabling protection at times of serial communication failure without providing a watchdog timer for each of multiple slave control units is provided in a configuration in which a master control unit and multiple slave control units are connected by serial communication. A communication system provided with multiple slave control units | 05-19-2011 |
| 20110125945 | COMMUNICATIONS MODULE APPARATUS, INTEGRATED CIRCUIT AND METHOD OF COMMUNICATING DATA - A communications module apparatus for an automotive network comprises an input for receiving data to be transmitted. The apparatus also comprises a first output for coupling to a first bus line and a second output for coupling to a second bus line. An alternating voltage signal transmission circuit for transmitting at least part of the received data is also provided. The alternating voltage signal transmission circuit is coupled to the first output and the second output. | 05-26-2011 |
| 20110138090 | COMMUNICATING ON AN ELECTRICAL BUS - Method and apparatus for communicating on an electrical bus by generating a master logical signal on the electrical bus in the form of a pulse-width modulation signal. Generating a slave logical signal on the electrical bus in the form of a current signal. Reading the slave logical signal by sampling the magnitude of the current signal on the electrical bus, wherein magnitude of the current on the electrical bus is sampled at a point in the bit time when the voltage on the electrical bus has remained constant for a period longer than the shortest time that the voltage remains at any level during the bit time. | 06-09-2011 |
| 20110153889 | COUPLING DEVICES, SYSTEM COMPRISING A COUPLING DEVICE AND METHOD FOR USE IN A SYSTEM COMPRISING A COUPLING DEVICE - The invention relates to coupling devices, a system comprising a coupling device and a method for use in a system comprising a coupling device. | 06-23-2011 |
| 20110153890 | Methods and Apparatus for Providing Data Transfer Control - A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other. | 06-23-2011 |
| 20110153891 | COMMUNICATION APPARATUS AND COMMUNICATION CONTROL METHOD - A communication apparatus including a master device ( | 06-23-2011 |
| 20110161538 | Method and System for Implementing Redundant Network Interface Modules in a Distributed I/O System - A method and system is disclosed for implementing redundant master NIMs ( | 06-30-2011 |
| 20110173357 | ARBITRATION IN CROSSBAR INTERCONNECT FOR LOW LATENCY - A system and method and computer program product for reducing the latency of signals communicated through a crossbar switch, the method including using at slave arbitration logic devices associated with Slave devices for which access is requested from one or more Master devices, two or more priority vector signals cycled among their use every clock cycle for selecting one of the requesting Master devices and updates the respective priority vector signal used every clock cycle. Similarly, each Master for which access is requested from one or more Slave devices, can have two or more priority vectors and can cycle among their use every clock cycle to further reduce latency and increase throughput performance via the crossbar. | 07-14-2011 |
| 20110173358 | EAGER PROTOCOL ON A CACHE PIPELINE DATAFLOW - A master device sends a request to communicate with a slave device to a switch. The master device waits for a period of cycles the switch takes to decide whether the master device can communicate with the slave device, and the master device sends data associated with the request to communicate at least after the period of cycles has passed since the master device sent the request to communicate to the switch without waiting to receive an acknowledgment from the switch that the master device can communicate with the slave device. | 07-14-2011 |
| 20110179207 | VARIABLE-FREQUENCY BUS ADAPTER, ADAPTING METHOD AND SYSTEM - A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication according to a dynamic frequency scaling (DFS) request signal sent by a bus side; blocking a current bus transfer according to the bus blocking indication; and feeding back a DFS response signal to the bus side after blocking the current bus transfer, where the DFS response signal is adapted to enable the bus side to perform a DFS operation. In the method, the bus transfer is temporarily blocked during the DFS, so that undesired influence on peripheral components caused by unstable bus block during the bus DFS is reduced without increasing the number of clock domains of the system or modifying the peripheral components, thus reducing the complexity of the implementation of the system, and improving the applicability of dynamic voltage frequency scaling (DVFS). | 07-21-2011 |
| 20110185093 | COMMUNICATION SLAVE AND COMMUNICATION NETWORK SYSTEM - In a communication network system in which a master and a plurality of communication slaves are coupled through a high-potential side bus and a low-potential side bus in a daisy-chain manner, each of the communication slaves includes a control circuit, a resistance element, and a potential difference detecting portion. The control circuit controls communication with the master. The resistance element is inserted into the high-potential side bus at a portion located downstream of a point where the control circuit is coupled with the high-potential side bus. The potential difference detecting portion detects a potential difference between an upstream terminal of the resistance element and the low-potential side bus. The control circuit sets an ID value for communicating with the master in accordance with the potential difference detected by the potential difference detecting portion. | 07-28-2011 |
| 20110191512 | Single Pin Read-Write Method And Interface - A method of communicating on a single serial line between two devices is disclosed. The method includes combining a data stream and a clock to form a three-voltage level stream such that the third voltage level records the transitions of the clock while the serial data is either high or low. Either the first or the second device can send a combined stream on the line. The method further includes, in some embodiments, the second device driving the same voltage levels as those transmitted by the first device and the first device sensing current on the single serial line to determine that the second device has received data from the first device. | 08-04-2011 |
| 20110197000 | MASTER-SLAVE DEVICE COMMUNICATION CIRCUIT AND ID ADDRESS SETTING METHOD THEREOF - A master-slave communication circuit includes a master device, a number of slave devices, and a bus providing communication channels between the master device and the slave devices. Each slave device includes an identification (ID) address setting unit, a plug-in detecting pin, and a plug-out detecting pin. The identification (ID) address setting unit is connected to the bus to receive an ID address setting signal transferred from the master device, and set an ID address to the corresponding slave device. The master sets the ID addresses of the slave devices according to voltage levels of the plug-in detecting pin and the plug-out detecting pin, to make the ID addresses of the slave devices connected to the bus are different. | 08-11-2011 |
| 20110197001 | MASTER-SLAVE DEVICE COMMUNICATION SYSTEM - A master-slave communication system includes a master device, a plurality of slave devices, and a bus providing communication channels therebetween. The master device includes a first micro control unit (MCU), a first power supply module, and an address setting module. Each slave device includes a second MCU and a second power supply module connected to the first power supply module through the address setting module. The address setting module detects a current output from the first power supply module, and outputs an ID address setting signal which is directly proportional with the current to the first MCU and the second MCU of a new slave device, the second MCU of the new slave device sets an ID address according to the ID address setting signal, the first MCU records the ID address as the ID address of the new slave device according to the ID address setting signal. | 08-11-2011 |
| 20110197002 | SYSTEM BUS MONITORING METHOD, SYSTEM BUS MONITOR, AND SYSTEM ON CHIP - In the field of system bus technology, a system bus monitoring method, a system bus monitor, and a System On Chip (SOC) are provided, so as to more accurately monitor an average transmission efficiency of a system bus. The system bus monitoring method includes: accepting a pre-configured monitoring time; monitoring a system bus in real time during the monitoring time to determine an effective transmission time of the system bus; and determining a ratio of the effective transmission time to the monitoring time as an average transmission efficiency of the system bus. The present invention is applicable in monitoring of the performance of the system bus. | 08-11-2011 |
| 20110202697 | Information Processor and Information Processing Method - An information processor includes: a plurality of master cores, a plurality of slave cores, a plurality of slave adapters each connected to a respective slave core of the plurality of slave cores, and an interconnected network for connecting the master cores and slave adapters by way of a plurality of router nodes. The slave adapters compare a first access request transmitted by a first master core among the plurality of master cores and a second access request transmitted by a second master core other than the first master core among the plurality of master cores based on a request from the first master core and a request from the second master core, and transmit the first access request or the second access request to the slave core that is connected to the slave adapter when the first access request and the second access request match. | 08-18-2011 |
| 20110202698 | APPARATUS AND METHOD FOR INCREASED ADDRESS RANGE OF AN I2C OR I2C COMPATIBLE BUS - An integrated circuit (IC) configured to operate as a slave on an inter-integrated circuit (I | 08-18-2011 |
| 20110208886 | COMMUNICATION SLAVE - A communication slave used in a communication network system includes a control device, a capacitive element, a voltage determining portion, and a time measuring portion. The control device controls communication with a master. The capacitive element is coupled between a high-potential side bus and a low-potential side bus. The voltage determining portion determines whether a voltage between the buses exceeds a threshold voltage. The time measuring portion measures a time from when a charge of the capacitive element through the buses is started to when the voltage determining portion determines that the voltage exceeds the threshold voltage. The control device sets an ID value for communicating with the master based on a length of the time measured by the time measuring portion. | 08-25-2011 |
| 20110219156 | BUS ARBITRATION APPARATUS AND METHOD - A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A | 09-08-2011 |
| 20110225333 | Interconnect Coupled to Master Device Via at Least Two Different Connections - An interconnect coupled to a master device via at least two different connections is disclosed. In a particular embodiment, a system is disclosed that includes a first interconnect and a second interconnect coupled to the first interconnect. The first interconnect is coupled to a first master device via a single connection and the first interconnect is coupled to a second master device via at least two different connections. The second interconnect is coupled to a memory via a memory controller. | 09-15-2011 |
| 20110225334 | PROCESSOR BUS BRIDGE FOR NETWORK PROCESSORS OR THE LIKE - Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a command from a first bus, the command having an identification field having a value. The command is then entered into a buffer in the bridge unless another command having the same identification field value exists in the buffer. Once the command with the same identification field value is removed from the buffer, the received command is entered into the buffer. Next, the buffered command is transmitted over a second bus. A response to the command is eventually received from the second bus, the response is transmitted over the first bus, and the command is then removed from the buffer. By not entering the received command until a similar command with the same identification value is removed from the buffer, command ordering is enforced even though multiple commands are pending in the buffer. | 09-15-2011 |
| 20110231588 | Requests and data handling in a bus architecture - The present invention relates to improved methods for processing requests and sending data in a bus architecture. The present invention further relates to an improved bus architecture for processing requests and data. There is provided a method for processing read requests in a bus architecture comprising at least one master device connected to at least two slave devices via a bus. The architecture comprises an allocator for allocating incoming requests from the master device to a target slave device and an optimiser for each slave device. Each optimiser is for buffering incoming requests for the respective slave device. The method comprising the steps of: a) the master device sending a read request for a first slave device to the bus; b) the allocator generating a current-state indicator associated with the read request. The current-state indicator has an initial value, The method further comprises c) the allocator generating a priority indicator associated with the read request; d) the allocator sending the read request, the current-state indicator and the priority indicator to the optimiser of the first slave device; e) the optimiser of the first slave device receiving the read request, the current-state indicator and the priority indicator. Finally, if the initial value of the current-state indicator equals the value of the priority indicator, the method comprises processing the read request; or if the initial value of the current-state indicator does not equal the value of priority indicator, the method comprises deferring processing of the read request until a later time. | 09-22-2011 |
| 20110231589 | ARBITRATOR AND ARBITRATING METHOD APPLIED TO SYSTEM MANAGEMENT BUS SYSTEM - A system management bus (SM Bus) system includes an arbitrator; a slave device connected to the arbitrator via an SM Bus; a first master device connected to the arbitrator capable of sending a first start command for communicating with the slave device; and a second master device connected to the arbitrator capable of sending a second start command for communicating with the slave device. The arbitrator set the first master device to have a priority, and when the first start command is being executed and the arbitrator receives the second start command, the arbitrator confirms whether the SM Bus is busy or not after a second predetermined time, and if the SM Bus is not busy, the arbitrator transmits the second start command to the slave devices via the SM Bus. | 09-22-2011 |
| 20110238875 | MASTER/SLAVE DEVICE SYSTEM - A master/slave device system includes a baseboard, a master device connected to the baseboard, and at least one slave device communicatively connected to the master device. The baseboard provides a power source. A switch connects the power source and the at least one slave device. The switch is capable of being switched on when a predetermined time is reached. The at least one slave device is capable of automatically setting an address at the moment the switch is switched on. The master device is capable of identifying the at least one slave device using the address. | 09-29-2011 |
| 20110238876 | APPARATUS AND METHOD FOR CONFIGURING A BUS SYSTEM - The present invention relates to an apparatus for configuring a bus system which includes a plurality of participants as well as a bus master and a safety monitor having an input unit by means of which suitable configuration information can be entered and/or selected for the configuration of the bus system and having a configuration unit configured to configure both the bus master and also the safety monitor by means of at least a piece of identical common configuration information input or selected via the input unit. The invention further relates to a method which can be carried out by the apparatus in accordance with the invention. | 09-29-2011 |
| 20110246692 | Implementing Control Using A Single Path In A Multiple Path Interconnect System - A method and circuit for implementing control using a single path in a multiple path interconnect system, and a design structure on which the subject circuit resides are provided. Control TL messages include control information to be transferred between a respective source transport layer of a source interconnect chip and a destination transport layer of a destination interconnect chip. Each transport layer (TL) includes a TL message port identifying a port used to send and receive control TL messages for a pair of source TL and destination TL. The respective TL message port of the pair of source TL and destination TL defines the single path used for control messages. | 10-06-2011 |
| 20110246693 | System For Synchronizing Hierarchically Combined Motion Control - There is provided a system for synchronizing hierarchically combined motion control, whereby small-scale, large-scale and remote control networks are controlled by a single control system, using a bus arbiter. | 10-06-2011 |
| 20110258353 | Bus Arbitration Techniques to Reduce Access Latency - A method of arbitrating requests from bus masters for access to shared memory in order to reduce access latency, comprises looking ahead into currently scheduled requests to the shared memory and predicting latency of the requests based on characteristics of the currently scheduled requests, such as increasing page hit rate, or balancing read and write traffic. The requests are scheduled based at least in part on the predicted latency. | 10-20-2011 |
| 20110271023 | SYSTEM FOR CONNECTING ELECTRONIC DEVICES - A system includes a master device and a number of slave devices connected to the master device via a bus. Each slave device includes a control unit, a switch unit, and a lock unit. When a new slave device is connected to the system, the control unit of the new slave device transmits a request signal to the master device. The master device detects whether the master device is communicating with the already connected slave devices after receiving the request signal, and outputs an enable signal to the new slave device according to the detected result. The control unit of the new slave device controls the lock unit of the new slave device to turn on and turn off the switch unit of the new slave device according to the enable signal. | 11-03-2011 |
| 20110271024 | SEMICONDUCTOR DEVICE - The router which relays a transfer request and a reply between master and slave components has request-control circuits provided therein. The request-control circuits judge the slave component to transfer a request from each master component to, and arbitrate the conflict between requests to one slave component. Further, for the router, a slave-component-allocation-control circuit which variably allocates the slave components to be connected to the request-control circuits to the request-control circuits is adopted. In case that a slave component in connection with one request-control circuit is subjected to no access, changing the allocation of the slave component in connection with the one request-control circuit makes possible to utilize the resource of the one request-control circuit. | 11-03-2011 |
| 20110276735 | INTERCONNECT, BUS SYSTEM WITH INTERCONNECT AND BUS SYSTEM OPERATING METHOD - Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master. | 11-10-2011 |
| 20110276736 | METHOD AND SYSTEM FOR A RFIC MASTER - Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index. | 11-10-2011 |
| 20110283031 | SYSTEM ON CHIP AND OPERATING METHOD THEREOF - A system on chip comprises a bus electrically connected with a master intellectual property (IP) block, a slave IP block, and a default slave IP block. An IP block control part is configured to generate a control signal for activating or inactivating the slave IP block. When a call signal on the slave IP block is received from the master IP block, the bus is configured to transfer the received call signal to either one of the slave IP block and the default slave IP block according to the received call signal and the control signal. | 11-17-2011 |
| 20110289248 | Isolated communication bus and related protocol - A system includes a master device and multiple slave devices. The system also includes multiple bus interfaces forming a communication bus that couples the master and slave devices. Each bus interface includes a primary interface unit configured to communicate over first and second buses, where the first and second buses form a portion of the communication bus. Each bus interface also includes a secondary interface unit configured to communicate with the primary interface unit and to communicate with one of the slave devices over a third bus. Each bus interface further includes an isolator configured to electrically isolate the primary interface unit and the secondary interface unit. The primary interface unit is configured to receive multiple commands over the first bus, execute a first subset of commands, transmit a second subset of commands over the second bus, and transmit a third subset of commands over the third bus. | 11-24-2011 |
| 20110296066 | SYSTEM ON CHIP AND TRANSMISSION METHOD UNDER AXI BUS - A system on chip (soc) and A transmission method under Advanced eXtensible Interface (AXI) bus are disclosed. The system includes a master device, a first extending module, a first interconnection structure, a first subtracting module, a second interconnection structure, and a slave device. The first extending module is configured to add N bits into an identifier (ID) carried in a transmission request, where N is equal to a sum of bits added by all interconnection structures in a longest loop of a system into the ID carried in the transmission request that passes through the interconnection structures. The first subtracting module is configured to subtract M bits from the ID carried in the transmission request output by the first interconnection structure when a slave device to be accessed by the master device is not a slave device connected with the first interconnection structure, where M is equal to the number of bits added by the first interconnection structure into the ID carried in the transmission request that passes through the first interconnection structure. The embodiments reduce costs and avoid the problems caused by ID compression. | 12-01-2011 |
| 20110296067 | AUTOMATIC ADDRESSING SCHEME FOR 2 WIRE SERIAL BUS INTERFACE - An automatic addressing bus system and method of communication comprising a main and an end device, wherein the respective bus controllers used in the main and end devices comprise multi-master capability. The main controlling device has an address known to the end device to be connected, the end device is able to actively initiate the address allocation procedure, without the need for user interaction. The method and system of the present system may be implemented using such known bus systems such as 2-wire serial buses, in particular I | 12-01-2011 |
| 20110302344 | I2C ADDRESS TRANSLATION - Embodiments of the present invention relate to systems, devices and methods for translating I2C addresses. In accordance with an embodiment, a method for translating an I2C address includes receiving an original I2C address from a first I2C compatible device via an I2C-bus to which the first I2C compatible device is connected. The method also includes translating the original I2C address to a translated I2C address, and outputting the translated I2C address to a second I2C compatible device via a secondary side of the I2C-bus to which the slave device is connected. The original I2C address can be translated to the translated I2C address by subtracting an offset value from (or adding an offset value to) the original I2C address to produce the translated I2C address. Such an offset value can be specified using pin strapping, or by storing the offset value in a register or non-volatile memory that is programmable via the-I2C bus. Alternatively, a look-up-table, that is programmable via the I2C-bus, can be used to perform the I2C address translation. | 12-08-2011 |
| 20110314197 | DATA PROCESSING SYSTEM - Each of a plurality of master devices outputs a speed grade signal indicating a data transfer speed with a data transfer request. An arbiter arbitrates transfer requests and speed grade signals from the plurality of master devices. A clock enable generation circuit generates a clock enable signal with a varying ratio of a valid level according to the speed grade signal arbitrated by the arbiter. A slave device operates upon receiving a clock signal when the clock enable signal is at the valid level, and transfers data according to the transfer request arbitrated by the arbiter. Accordingly, the frequency of the clock signal which causes the slave device to operate may be changed for each transfer request, and a fine control of the power of the slave device may be easily performed. As a result, power consumption of the data processing system may be finely controlled. | 12-22-2011 |
| 20110320658 | INFORMATION PROCESSING SYSTEM - An interrupt control circuit asserts a remap signal in response to an interrupt request from a low-speed slave to a processor, and reads information stored in an information register of the low-speed slave. The interrupt control circuit writes the read information into a buffer exclusively for interrupt processing. A switch circuit supplies a read access request which is a request from the processor to the information register to the low-speed slave during negation of the remap signal, and supplies the read access request to the buffer via the interrupt control circuit in order to read the information from the buffer during assertion of the remap signal. By accessing to the buffer exclusively for the interrupt processing instead of the information register in response to the read access request from the processor, the interrupt processing time may be shortened. | 12-29-2011 |
| 20120005385 | COMMUNICATION CIRCUIT OF INTER-INTEGRATED CIRCUIT DEVICE - A communication circuit of an Inter-Integrated Circuit (I2C) includes a master device, a switch circuit, first and second groups of slave devices. Each slave device includes a data signal pin and a clock signal pin, which are connected to the switch circuit. The master device includes a data signal pin, a clock signal pin, and a general purpose input output (GPIO) pin, which are connected to the switch circuit. The GPIO pin of the master device outputs a control signal to the switch circuit, to allow communication between the first group of slave devices and the master device or communication between the second group of slave devices and the master device. | 01-05-2012 |
| 20120011291 | Apparatus and method for controlling issuing of transaction requests - Transaction requests requesting a service from the slave device are received from a master device at a transaction interface. The transaction requests are selectively issued to the bus system under control of an issue control circuit. A target outstanding transaction value N.x is received at a control interface. The target outstanding transaction value has an integer portion N and a fractional portion x. The issue control circuit controls the transaction interface to issue the transaction requests to the bus system in dependence upon the target outstanding transaction value so that a time averaged number of outstanding transaction requests corresponds to the target outstanding transaction value. | 01-12-2012 |
| 20120017016 | METHOD AND SYSTEM FOR UTILIZING LOW POWER SUPERSPEED INTER-CHIP (LP-SSIC) COMMUNICATIONS - Inter-chip connectivity may be provided in a computing device, which may comprise a USB host and at and at least one USB device embedded within the computing device, based on Universal Serial Bus version 3.0 (USB3.0) interface. In this regard, internal communication of data between the USB host and embedded USB device may be performed via USB3.0 SuperSpeed signals. The USB host and/or the USB3.0 interface may be configured to enable USB3.0 internal communication of data, and to reduce power consumption during the internal communication of data compared to external USB3.0 communications. Configuration of the USB3.0 interface for internal communication of data may comprises modifying and/or adjusting physical (PHY) layer, link layer, and/or protocol layer related parameters, functions, resources, and/or operations. The USB3.0 SuperSpeed signals may be communication using scalable low voltage signaling (SLVS). In this regard, Input/Output (IO) Swing may be set based on loopback training sequence. | 01-19-2012 |
| 20120023277 | Method for Operating an Automation Device - A method for operating an automation device comprising at least one master unit and at least one slave unit that is connected by a first bus, wherein messages are transmitted over the first bus while controlling a technical process. The messages comprise a process image data area for planned field devices, which are connected to the at least one slave unit by a second bus, and a planned reserved process image data area that is intended for possible expansions of the automation device with further field devices is connectable to the at least one slave unit. In accordance with the invention, the method is used to expand the automation device with field devices, i.e., field devices that comply with the Fieldbus Foundation specification, during control operation (RUN operation). | 01-26-2012 |
| 20120030389 | MICROCOMPUTER - Disclosed is a microcomputer that can gain bus access irrespective of the magnitude relationship between the frequency of a bus master and the frequency of a bus slave. A CPU operates in accordance a first clock, which has a variable frequency. A timer operates in accordance with a second clock. A frequency conversion logic circuit is coupled to the CPU through a main bus and coupled to the timer through a peripheral I/O bus. When the first clock is higher in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the timer by using a first synchronization signal, which indicates the change timing of a bus control signal for the peripheral I/O bus. When the first clock is lower in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the CPU by using a second synchronization signal, which indicates the change timing of a bus control signal for the main bus. Therefore, bus access can be gained irrespective of the magnitude relationship between the frequencies of the CPU and timer. | 02-02-2012 |
| 20120030390 | Device for Manipulating Interface Signals - A device for manipulating interface signals includes a slave interface, which is connectable to a master interface of a control device, a master interface, which is connectable to a slave interface of a measuring device, and a circuit configuration, which is supplied with at least one data-input signal per interface, and which outputs a corresponding data-output signal per data-input signal to the respective other interface. The circuit configuration includes at least one manipulation unit, to which a data-input signal and a substitute-data signal are supplied and which outputs a corresponding data-output signal, as well as a protocol unit, to which at least one protocol-relevant interface signal is supplied and which, based on manipulation rules and information received with the at least one protocol-relevant interface signal, chooses when the at least one manipulation unit outputs the corresponding data-input signal or the substitute-data signal as data-output signal. | 02-02-2012 |
| 20120030391 | METHOD AND SYSTEM FOR MEMORY ATTACK PROTECTION TO ACHIEVE A SECURE INTERFACE - A slave device may receive commands from a host device communicatively coupled to the slave device, via a secure interface configured between the slave device and the host device over that coupling. An integrated memory within the slave device may be configured into a plurality of memory portions or regions based on the received commands. The memory regions may be utilized during operations associated with authentication of subsequent commands from the host device. A first memory region may enable storage of encrypted host commands and data. A second region may enable storage of decrypted host commands and data. A third region may enable storage of internal variables and/or intermediate results from operations performed by the slave device. Another region may comprise internal registers that enable storage of information only accessible to the slave device. Access to some of the memory regions may be controlled and/or restricted by the slave device | 02-02-2012 |
| 20120036297 | HYBRID IN-VEHICLE INFOTAINMENT NETWORK - A hybrid in-vehicle infotainment network includes a core high-speed network having a number of high-speed nodes, each of which may be connected to at least one other high-speed node via a high-speed backbone link. At least some high-speed nodes may be hybrid nodes. Hybrid nodes may communicate with one or more low-speed devices via one or more low-speed links. Each hybrid node, along with any connected low-speed devices, forms a respective local low-speed network. In some embodiments, hybrid nodes may conform with a 1394 specification for high-speed backbone link communications and may conform with a universal serial bus (USB) specification for low-speed link communications. Communications via the high-speed backbone links and the low-speed links may use a common application layer having defined therein a same maximum packet size and a same set of commands and vendor-specific identifiers. | 02-09-2012 |
| 20120042105 | BUS ARBITRATION APPARATUS - An arbitration circuit | 02-16-2012 |
| 20120066423 | INTER-INTEGRATED CIRCUIT BUS MULTICASTING - A master node selects a plurality of slave nodes that share a common slave address to receive a data communication. The master node multicasts the data communication to the plurality of selected slave nodes via an inter-integrated circuit bus having a serial data line and a serial clock line. | 03-15-2012 |
| 20120072628 | REMOTE MULTIPLEXING DEVICES ON A SERIAL PERIPHERAL INTERFACE BUS - A serial peripheral interface (SPI) bus and method of communicating over an SPI bus to multiple slave devices without requiring the master device to have an independent slave select pin for each slave device. The SPI bus comprises an SPI master device coupled to an SPI multiplex slave device and a plurality of SPI non-multiplex slave devices. The SPI multiplex slave device includes an independent slave select (SS) output pin coupled to each one of the SPI non-multiplex slave devices for sending an activation signal to a selected SPI slave device in response to receiving a command from the master device containing identification of the selected SPI slave device. | 03-22-2012 |
| 20120072629 | COMMUNICATION SYSTEM, MASTER DEVICE AND SLAVE DEVICE, AND COMMUNICATION METHOD - A communication system includes a master device and slave devices. Each slave device includes a request signal generation part configured to, when data to transmit is generated, generate a request signal indicating a transmission request to a master device; and a transmission part configured to transmit the request signal to the master device. The master device includes a request signal reception part configured to receive the request signals from the slave devices; a selection part acting configured to select one of the slave devices according to the request signals received by the reception part; a transmission part configured to transmit a signal indicating to allow data transmission to the slave device selected by the selection part; and a data reception part configured to receive data from the selected slave device. | 03-22-2012 |
| 20120079150 | Bus system and deadlock avoidance circuit thereof - Disclosed herein is a deadlock avoidance circuit including: a previous-transaction-information management section; a transaction-issuance-termination determination section; and a response-outputting control section. | 03-29-2012 |
| 20120079151 | IDENTIFICATION, BY A MASTER CIRCUIT, OF TWO SLAVE CIRCUITS CONNECTED TO A SAME BUS - A method of communication between a master circuit and two slave circuits over a serial bus wherein: the two slave circuits simultaneously transmit their associated identifiers; the two slave circuits simultaneously transmit the inverse of these identifiers; and each slave circuit exploits the combinations present on the bus to determine an order of communication between the two circuits. | 03-29-2012 |
| 20120079152 | METHOD FOR CONNECTING SLAVE CARDS TO A BUS SYSTEM - A method for connecting slave cards to a first bus system and a system for implementing the method are described. In the method, signals are transferred from the slave cards to a CPU via the first bus system, a master being assigned to each slave card, and the signals being transferred from each slave card via the assigned master. | 03-29-2012 |
| 20120079153 | COMMUNICATION METHOD AND DEVICE FOR A MOTOR VEHICLE - A communication method is implemented in an on-board network between a master station (M) and a plurality of slave stations (S1, S2, S3, S4), of the type of those compatible with the standard Local Interconnect Network (LIN) protocol in which data frames are sent by the slave stations on a serial bus in response to the sending by the master station of identifiers representative of the required content of the frames. All or part of each of the specific data frames attached to the same predetermined identifier is formed sequentially by each of the slave stations. This enables an optimisation of the load on a LIN network, thus enabling use of this economical standard for all “passenger compartment functions”, and in particular for the management of AFS type advanced lighting systems. | 03-29-2012 |
| 20120084475 | BUS ARBITRATION APPARATUS AND BUS ARBITRATION METHOD - It may be difficult to give bus right to a bus master that cannot output a bus request signal when a bus arbitration apparatus is ready to grant bus permission precisely in a ratio of a preset number of times of the bus acquisition. The bus arbitration apparatus operates to wait until bus request signals of bus masters that have not performed transfers of the preset number of times of the bus acquisition are output while a bus slave operates. | 04-05-2012 |
| 20120084476 | ADVANCED TELECOMMUNICATIONS COMPUTING ARCHITECTURE EXCHANGE SYSTEM, ADVANCED TELECOMMUNICATIONS COMPUTING ARCHITECTURE EXCHANGE METHOD, AND COMMUNICATION APPARATUS - An ATCA exchange system is disclosed according to the embodiments of the present invention. The ATCA exchange system includes: a master exchange shelf, including a first node board and a hub board; and a slave exchange shelf, including a second node board and an I/O transfer board. The I/O transfer board includes an exchange interface, and in the slave exchange shelf, the I/O transfer board is connected to the second node board through the exchange interface. The I/O transfer board is connected to the hub board by using an external communication link through the exchange interface, so that data of the second node board reaches the hub board through the I/O transfer board when the data needs to be exchanged, so as to complete data exchange through the hub board. According to the embodiments of the present invention, the manufacturing cost can be reduced. | 04-05-2012 |
| 20120089758 | System On Chip Keeping Load Balance And Load Balancing Method Thereof - At least one example embodiment discloses a System on Chip (SoC). The SoC includes a master block, a plurality of slave blocks configured to operate in response to a request from the master block, and an interconnect block configured to deliver transactions occurring in the master block to the plurality of slave blocks through a plurality of transfer paths. The interconnect block is configured to monitor load information of the plurality of transfer paths and select one of the plurality of transfer paths according to the load information. | 04-12-2012 |
| 20120096200 | BUS SYSTEM AND OPERATING METHOD THEREOF - A system-on-chip bus system and an operating method of the same are provided. The bus system includes a master device, a slave device and an interconnector coupled between the master device and the slave device. The interconnector includes a synchronization/compaction block to control traffic provided from a master device to a slave device. When a write request traffic and a corresponding write data traffic are all provided from the master device, the synchronization/compaction block may transfer the two traffics to the salve device. | 04-19-2012 |
| 20120096201 | Cooperative Writes over the Address Channel of a Bus - A method of communicating over a bus is disclosed. The bus includes a write address channel, a write channel, and a read address channel. The method includes sending an address from a sending device to a receiving device via the write address channel. The method further includes concurrently sending a portion of a payload to the receiving device via the write channel and another portion of the payload to the receiving device via the read address channel. When sending multiple sequential portions of the payload via the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the read address channel by sending a first sequential portion of the multiple sequential portions via the write channel and sending a subsequent sequential portion of the multiple sequential portions via the read address channel. | 04-19-2012 |
| 20120096202 | AUXILIARY WRITES OVER ADDRESS CHANNEL - A method for communicating via a bus including a first channel, a second channel, and a third channel is disclosed. The method includes addressing a slave device via the first channel, receiving from the slave device via the second channel, and writing to the slave device via the third channel. The method further includes selecting between first and second bus transmission modes. In the first bus transmission mode, payload write data is to be sent to the slave device via the first channel or the third channel. In the second bus transmission mode, during a first clock cycle, second payload write data associated with a second write operation is to be sent to the slave device via the first channel and first payload write data associated with a first write operation is to be concurrently sent to the slave device via the third channel. | 04-19-2012 |
| 20120096203 | Method and Apparatus for Realizing Remote Access of Terminal to USB Device - An apparatus and method for realizing remote access to a Universal Serial Bus (USB) device are provided. The apparatus includes a USB Hub, an application processor, and a power adapter. The USB Hub is configured to receive a USB service access request sent by a remote terminal and forwarded by a wireless Internet data card, and to forward the USB service access request to the application processor. The application processor is configured to receive the USB service access request, to authenticate the remote terminal according to the USB service access request, and to permit the remote terminal to access a USB device connected to the USB Hub after the authentication is passed. The power adapter is configured to provide an operational power supply to the USB Hub and the application processor. | 04-19-2012 |
| 20120102248 | MASTER-SLAVE COMMUNICATION OVER A SINGLE-WIRE BUS BETWEEN A MASTER CIRCUIT AND AT LEAST TWO SLAVE CIRCUITS - A method of transmission over a serial bus, between a master circuit and two slave circuits, wherein each slave circuit makes the transmission of a first one of two binary states depend on the absence of a transmission of the second binary state by the other slave circuit. | 04-26-2012 |
| 20120102249 | Arbitrating Bus Transactions on a Communications Bus Based on Bus Device Health Information and Related Power Management - Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices. | 04-26-2012 |
| 20120102250 | BUS SYSTEM - A bus system includes a master transferring write data internally via a first write data channel and an address internally via a first address channel; and a bus transferring the write data and the address to a slave from the master via one channel. | 04-26-2012 |
| 20120117286 | Interface Devices And Systems Including The Same - An interface device includes a transaction management unit, a buffer unit and a selection circuit. The transaction management unit selectively splits a transaction of a master device into a first sub-transaction and at least one remaining sub-transaction based on a size of the transaction. The buffer unit stores the remaining sub-transaction. The selection circuit selects one of the first sub-transaction and an output of the buffer unit in response to a select control signal. | 05-10-2012 |
| 20120117287 | COMMUNICATION SYSTEM, MASTER NODE, AND SLAVE NODE - In a communication system, a bus allows information to be communicated thereon as signals. Each of the signals has an electrical dominant level thereon and an electrical recessive level thereon. The electrical dominant level is asserted on the bus in priority to the electrical recessive level. Each of a master node and at least one autonomous communicating slave node detects that the bus is in an idle state when the electrical recessive level on the bus is continued for a predetermined period or more, transmits a corresponding header via the bus after detection of the bus being in the idle state, and performs arbitration on the bus based on the corresponding header. | 05-10-2012 |
| 20120124260 | CLOSED LOOP DYNAMIC INTERCONNECT BUS ALLOCATION METHOD AND ARCHITECTURE FOR A MULTI LAYER SoC - A closed loop dynamic interconnect bus allocation method and architecture for a multi layer SoC is disclosed. In one embodiment, a system on chip (SoC) includes multiple masters, multiple slaves, multiple buses, and an interconnect module coupled to multiple masters and multiple slaves via multiple buses. The interconnect module includes an arbiter. The SoC also includes an inner characteristic bus coupled to the plurality of masters, the plurality of slaves and the interconnect module. The interconnect module receives on-chip bus transactions substantially simultaneously from the multiple masters to be processed on one or more of the multiple slaves via the multiple buses. The interconnect module also receives inner characteristic information of the on-chip bus transactions via the inner characteristic bus. Further, the interconnect module allocates the received on-chip bus transactions from the multiple masters to associated one or more of multiple slaves based on the received inner characteristic information. | 05-17-2012 |
| 20120124261 | MICROCONTROLLER INCLUDING FLEXIBLE CONNECTIONS BETWEEN MODULES - A microcontroller includes a system bus matrix to connect various modules. The microcontroller also includes direct connections between modules. For example, the microcontroller may include a direct connection between a data processing module and a memory controller module to improve the transfer rate for data that is processed by the data processing module. | 05-17-2012 |
| 20120124262 | APPARATUS AND METHOD FOR ARBITRATING BUS - A bus arbitration apparatus and method are provided. A plurality of masters may be classified into master types based on master characteristics, and bus arbitration may be performed. Thus, it is possible to prevent a bus from being distributed to a predetermined master, and it is possible to improve overall performance of a bus system by solving a problem of unbalanced distribution of performance between the plurality of masters. | 05-17-2012 |
| 20120131246 | SYSTEM-ON-CHIP AND DATA ARBITRATION METHOD THEREOF - A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response to the request, and an interconnector configured to include a slave interface for providing the request to one or more master interfaces and for supplying response data to the first master device based on operation characteristics of the first master. | 05-24-2012 |
| 20120131247 | APPARATUS FOR PERIPHERAL DEVICE CONNECTION USING SPI IN PORTABLE TERMINAL AND METHOD FOR DATA TRANSMISSION USING THE SAME - In one embodiment, an apparatus for peripheral device connection using a Serial Peripheral Interface (SPI) in a portable terminal is provided and a method for data transmission using the same. The apparatus includes an SPI controller for activating each of slaves by independently assigning at least one serial data line to each of the slaves that reads/writes data from/to each of the slaves through at least one serial control line, a slave unit including at least one slave which under the control of the SPI controller, reads out data from the buffer and then performs data transmission between the slaves, and a buffer for temporarily storing the data to be transmitted in order to transmit data between the slaves which may have different data processing speeds and different data transmission speeds. | 05-24-2012 |
| 20120137033 | MONITOR CIRCUIT, BUS SYSTEM, AND BUS BRIDGE - By connecting, to a bus bridge according to a configuration of a bus system, a monitor circuit including an activation control circuit generating a counter activation signal from an input monitor activation signal, a counter circuit, activated by the counter activation signal, counting the transfer number using a signal of bridge transfer completion indicating an issuance of one transfer from a bus bridge, and outputting a count completion signal when the transfers of the same number as that stuck in the bus bridge indicated by the signal of the transfer number stuck in the bridge is issued when being activated, and a completion control circuit outputting a monitor completion signal upon receiving the count completion signal from the counter circuit, consistency of data may be guaranteed in any bus system without changing the configuration of the bus bridge based on the number of masters accessing the bus bridge. | 05-31-2012 |
| 20120137034 | COMMUNICATION SYSTEM, MASTER NODE, AND SLAVE NODE - In a node communicably coupled to alternative nodes through a bus, a transmitting unit receives first designation information from an alternative node. When the first designation information designates the node, the transmitting unit successively transmits, on the bus, the first designation information and data. When a request of an active communication occurs in the node, a request unit determines whether to receive a former part of the first identification information indicative of start timing of an active communication mode on the bus. When determining to receive the former part of the first identification information, the request unit transmits, on the bus, collision information at a timing that allows the collision information to collide with a latter part of the first identification information, resulting in rewrite of the first identification information based on bus arbitration, and transmits second designation information meeting the request of the active communication. | 05-31-2012 |
| 20120144079 | INTERCONNECTION APPARATUS AND CONTROLLING METHOD THEREFOR - An interconnection apparatus includes: a buffer; a request processing section; a response processing section; and an interconnection section. | 06-07-2012 |
| 20120144080 | Method and Device for Monitoring Running State of Card - A method and an apparatus for monitoring single board running state are disclosed in the present invention. The above method comprises: establishing an Module Management Controller (MMC) communication channel between a slave board and a master control board when the slave board is powered up; and the slave board reporting running state information of the slave board to the master control board by the MMC communication channel according to one or more preset monitor information points. In the present invention, by the MMC function channel under the uTCA architecture, the slave board reports the master control board the running state of the working process from the moment of being powered-up to the time when the system runs stably, which solves the problem in the conventional art that the monitoring on the single aboard is incomprehensive and can record the running state of the slave board completely. | 06-07-2012 |
| 20120151108 | DATA PROCESSING SYSTEM - A transfer canceler is provided on a bus connecting a master and a slave together. The transfer canceler interrupts the bus so that an invalid command flowing through the bus does not reach the slave when the master is in the reset state, and at the same time, generates and receives data to and from the slave corresponding to an access request command which has been output to the slave on behalf of the master disabled by resetting. In addition, in order to more quickly complete a process which has been issued to the slave, a circuit is additionally provided which temporarily changes an arbitration priority level or an operating frequency of the slave. | 06-14-2012 |
| 20120159024 | SEMICONDUCTOR APPARATUS - According to one embodiment, a semiconductor apparatus including a slave device which includes a plurality of slave interfaces, an adjustment unit, a processing unit, and a processing unit. The plurality of slave interfaces are connected to the bus to receive transmission instructions from master devices at the first frequency. The adjustment unit decides a processing sequence of the transmission instructions which are received through the plurality of slave interfaces according to priority information. On priority information, a plurality of master devices are prioritized in a sequence depending on association of processing content among the plurality of master devices. The processing unit performs a data transmission process corresponding to a transmission instruction at a second frequency according to the processing sequence decided by the adjustment unit. The transmission instruction instructs to transform data to/from a module. The second frequency is higher than the first frequency. | 06-21-2012 |
| 20120159025 | Method and Device for Communication between a Master and a Number of Slaves According to a Serial Communication Protocol, in particular of the Open Drain Type - According to one implementation, the slave identifier bits are tested recursively in groups of p bits. For these p bits, each slave will recognize, in its p corresponding identifier bits, one combination out of the 2p possible combinations. The slaves respond simultaneously ( | 06-21-2012 |
| 20120159026 | SYNCHRONOUS CONTROL SYSTEM INCLUDING A MASTER DEVICE AND A SLAVE DEVICE, AND SYNCHRONOUS CONTROL METHOD FOR CONTROLLING THE SAME - The present invention relates to a method of synchronous control for a synchronous control system provided with a master device and at least one slave device connected via a communications network. The master device transmits first time data to the master device and the at least one slave device upon detection of generation of a synchronization signal, the first time data indicating a time at which the synchronization signal is generated. The master device transmits second time data to the at least one slave device upon reception of the first time data, the second time data indicating a time at which the first time data is received. Each of the at least one slave device calculates, upon reception of the first time data and the second time data, an estimated generation time at which the synchronization signal is estimated to be generated by subtracting time elapsed between the time indicated by the first time data and the time indicated by the second time data from time at which the first time data was received. Each of the at least one slave device controls synchronization with the master device based on the estimated generation time. | 06-21-2012 |
| 20120166694 | Using Identification in Cache Memory for Parallel Requests - In an exemplary computer system having one or more masters configured to the same slave memory using a protocol, such as the AMBA AXI protocol, a master provides an ID field to the memory as part of a data request, where the ID field has a line ID sub-field that represents a line ID value that uniquely identifies a particular cache line (or subset of cache lines) in the master, where the memory returns the line ID value back to the master along with the retrieved data. The master uses the line ID value to identify the cache line into which the retrieved data is to be stored. In this way, the master does not need to maintain a queue of address buffers to retain the addresses for data requests currently being processed, where the size of the queue limits the number of parallel in-service data requests by the master. | 06-28-2012 |
| 20120166695 | COMMUNICATIONS ARCHITECTURE FOR PROVIDING DATA COMMUNICATION, SYNCHRONIZATION AND FAULT DETECTION BETWEEN ISOLATED MODULES - An electronic system includes a master module having a first control unit having one or more first serial interfaces and being programmed to output a first data signal and a first clock signal through the one or more first serial interfaces, and a slave module having a second control unit, the second control unit having a second serial interface. The slave module receives the first clock signal through the second serial interface, and the second control unit is programmed to monitor the slave module for a fault condition and output a second clock signal through the second serial interface which is (i) the same as the first clock signal if a fault condition on the slave module is not detected, and (ii) a modified clock signal having a predetermined format through the second serial interface if a fault condition on the slave module is detected. | 06-28-2012 |
| 20120179848 | Electrical Circuit For Transmitting Signals Between Two Masters And One Or More Slaves - An electrical circuit for transmitting signals between two masters and one or more slaves is described. The two masters and the slave or slaves are connected to one another via a bus system. At least one master data signal can be generated by each of the two masters, which signal can be received by the slave or slaves. A three-state gate is present at each of the outputs of the two masters at which the respective master data signal is present. The three-state gates are effective either as closed or as open switches. The three-state gates are activated in such a way that the three-state gate associated with the one of the two masters acts as a closed switch, and the three-state gate associated with the other of the two masters acts as an open switch. | 07-12-2012 |
| 20120179849 | PROGRAMMABLE CONTROLLER - A programmable controller includes a master unit and a plurality of slave units connected to a system bus in a daisy chain. The master unit transmits a batch of transmission frames addressed to different slave units consecutively a predetermined plurality of times, without waiting to receive the response from the slave units. Thus, the transmission frames can be transmitted reliably. | 07-12-2012 |
| 20120191889 | Method to differentiate identical devices on a two-wire interface - Systems and methods for providing a differentiation of two identical slave devices on a same I | 07-26-2012 |
| 20120191890 | I2C MULTI-SLOT CIRCUIT SYSTEM AND METHOD FOR TRANSMITTING I2C SIGNALS - An I2C multi-slot circuit system includes a plurality of I2C slots for receiving a plurality of slave processors, a CPU, a logic control unit, and a I2C switch unit. The CPU determines an address of one of the I2C slots which to-be-transmitted data will be transmitted to, and generates a first logic control signal according to the determined address. The logic control unit enables the one of the I2C slots which the to-be-transmitted data will be transmitted to according to the first logic control signal. The I2C switch unit receives and transmits I2C signal converted from the to-be-transmitted data by the CPU to the I2C slot. A related method is also provided. | 07-26-2012 |
| 20120210029 | INTERFACE DEVICE AND SYSTEM INCLUDING THE SAME - An interface device includes a request queue and a request queue manager. The request queue includes multiple elements configured to receive corresponding requests from at least one master device and to indicate whether the corresponding requests are included using corresponding occupying bits. The request queue manager is configured to manage the request queue at least based on the occupying bits. | 08-16-2012 |
| 20120210030 | AUTOMATION SYSTEM AND METHOD FOR OPERATING AN AUTOMATION SYSTEM - An automation system has a first automation controller and a redundant second automation controller. The automation system further includes at least one peripheral unit and a bus system interconnecting the two automation controllers and the at least one peripheral unit. The peripheral unit is connected to the bus system through a bus interface unit. The bus interface unit has a first bus controller associated with the first automation controller, a second bus controller associated with the second automation controller, and a switching unit for switching between the two bus controllers. A method for operating the automation system selects one of the two automation controllers for controlling the automation system, depending on the situation. | 08-16-2012 |
| 20120215955 | System on Chip Comprising Interconnector and Control Method Thereof - A system on chip includes a plurality of master devices, a plurality of slave devices that supply data in response to requests of the plurality of master devices and pointer update logic configured to process the requests from the plurality of master devices sequentially in a pipeline manner. | 08-23-2012 |
| 20120221755 | DEVICE AND METHOD FOR ADDRESSING A SLAVE UNIT - The invention relates to a dynamically addressable slave unit, comprising a bus interface, an enable circuit having a switch and two control ports which are connected via the enable circuit. The enable circuit only releases the slave unit for assigning an address by an address signal provided at the bus interface when a control signal is provided at one of the control ports and when the switch of the release signal is open. Otherwise, the enable circuit locks the slave unit for the assigning of an address. The switch locks depending on whether a switching signal is provided at the bust interface directed to the address assigned to the slave unit. The invention further relates to a master unit for use with one or more dynamically addressable slave units, to slave units according to the invention, and to a method for dynamically addressing slave units according to the invention. | 08-30-2012 |
| 20120226837 | Method and System of debugging Multicore Bus Transaction Problems - A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events. | 09-06-2012 |
| 20120226838 | Method and System for Handling Discarded and Merged Events When Monitoring a System Bus - A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. The bus is monitored for discarded speculative read and for merged write transactions in order to determine the true bus throughputs. Bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events. | 09-06-2012 |
| 20120226839 | Method and System for Monitoring and Debugging Access to a Bus Slave Using One or More Throughput Counters - A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Bus transactions to a selected slave are monitored to determine possible conflicts when multiple masters may be addressing the slave. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, by a selected address range or alternatively by external trigger events. | 09-06-2012 |
| 20120226840 | MULTIPLE COMMUNICATION CHANNELS ON MMC OR SD CMD LINE - The claimed subject matter can provide an architecture that interfaces a single slave device such as a UICC smartcard with multiple host controllers. For example, a secondary host can be interfaced between a primary host (e.g., a controller in a cellular phone, a PDA, an MP3 player . . . ) to manage all transactions with the slave device. The secondary host can operate transparently to the primary host and thus does not require any modifications to the primary host. This can be accomplished, e.g., by employing the CMD channel (which is relatively sparsely used by the primary host) to communicate both commands and data with the slave. | 09-06-2012 |
| 20120239841 | SERIAL INTERFACE - A method is provided. A communication is received by an input pin of an IC over a single-wire bus, where the communication includes a command byte. If the command byte is an initialization command byte, a self-addressing operation is performed to identify a bus address for the IC. Alternatively, if the command byte is a data movement command byte, a data movement operation is performed. When data movement operation is performed, the bus interface of the IC is set from the transparent mode to the operational mode if an operation address from the command byte matches the bus address so that a register identified in the command byte can be accessed and data movement with the register can be performed. | 09-20-2012 |
| 20120246367 | MEMORY SYSTEM, MEMORY CONTROLLER, AND SYNCHRONIZING APPARATUS - According to one embodiment, there is provided a memory system including a bus master, a bus slave, and a memory device. The bus slave includes a synchronizing unit, and a speed-enhancing unit. The synchronizing unit is connected to a bus. The synchronizing unit receives the data in synchronism with a third clock. The third clock is in synchronous relation with a second clock and is slower than a first clock. The speed-enhancing unit enhances a transfer speed from a speed corresponding to the third clock to a speed corresponding to the second clock, by transferring the data received in the synchronizing unit to the memory device in synchronism with the second clock. | 09-27-2012 |
| 20120246368 | SYSTEM ON CHIP IMPROVING DATA TRAFFIC AND OPERATING METHOD THEREOF - A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results. | 09-27-2012 |
| 20120246369 | BUS MONITOR CIRCUIT AND BUS MONITOR METHOD - A bus monitor circuit that produces a bus monitor output signal on a bus transmitting data between a master and a slave includes an access information/write data FIFO and a read data FIFO. When an attribute of the access information stored at a header of the access information/write data FIFO indicates a write access, it directly outputs a bus monitor output signal indicating access information accompanied with the corresponding write data which is transmitted in the same cycle. When an attribute of the access information stored at the header of the access information/write data FIFO indicates a read access, it waits for the read data FIFO storing the corresponding read data, and then outputs a bus monitor output signal indicating the access information paired with the read data in the same cycle. Thus, it is possible to guarantee the occurrence order of bus access according to a bus interface protocol enabling pipeline transaction, thus outputting a bus monitor output signal indicating a pair of access information and data information. | 09-27-2012 |
| 20120260013 | KVM switcher (Multi-computer switcher) with integrated parallel transmission,serial peripheral interface and universal serial bus - A KVM switcher (multi-computer switcher) with integrated parallel transmission, serial peripheral interface (SPI), and universal serial bus (USB), characterized in that signals are transmitted through a parallel transmission interface between a SPI master control unit and at least one USB host interface control unit. | 10-11-2012 |
| 20120284441 | ELECTRONIC MODULES WITH AUTOMATIC CONFIGURATION - A first slave electronic module and a second slave electronic module are adapted for communicating over the data bus. The first slave electronic module has a first resistor coupled in series with a main power line. The second electronic module has a second resistor coupled in series with the main power line. A master electronic module has a master current measurement circuit for determining an aggregate current level indicative of the total number of slave electronic modules on the main power line. A first current measurement circuits is capable of measuring a node current indicative of a number of other active slaves connected to the main power line and data bus. A master data processor in the master electronic module is arranged to assign a unique module identifier to a first slave electronic module based on the first node current and the aggregate current level, the unique module identifier indicating a respective position of the first slave electronic module on the data bus. | 11-08-2012 |
| 20120290752 | Transaction indentifier expansion circuitry and method of operation of such circuitry - Transaction identifier expansion circuitry is provided, along with a method of operating such circuitry. The transaction identifier expansion circuitry interfaces between a master device and interconnect circuitry used to couple the master device with a plurality of slave devices to enable transactions to be performed. Transaction analysis circuitry is responsive to each transaction in a sequence of transactions initiated by the master device, to compare at least one attribute of the transaction with predetermined attributes indicative of the target slave device for that transaction. Based on the comparison, an initial transaction identifier is then mapped to one of a plurality of revised transaction identifiers, such that the revised transaction identifier is dependent on the target slave device. Reordering circuitry is then arranged to buffer response transfers received from the interconnect circuitry destined for the master device, with each response transfer having the revised transaction identifier associated therewith. The reordering circuitry then re-orders the response transfers having regard to the original transaction order of those transactions within the sequence of transactions that had the same initial transaction identifier, prior to provision of each response transfer to the master device. By such an approach, the performance of a high performance master device can be maintained, by ensuring that for at least the transactions targeted to a particular subset of the slave devices, no intervention by deadlock avoidance circuitry within the interconnect is required when routing transactions to those slave devices, due to the use of different transaction identifiers when accessing those slave devices. | 11-15-2012 |
| 20120297101 | SAFETY MODULE FOR AN AUTOMATION DEVICE - Exemplary embodiments are directed to a safety module for connection to an automation device or automation system which is provided for control of safety critical and non-safety critical processes and/or plant components. The module includes a communication board that includes a processing unit which is connected via an input/output bus slave and an external input/output bus connected to a central processing unit, and one or more secure processing units arranged on one or more circuit boards having safety oriented input/output circuits for safety oriented functions. A serial communication master is connected via communication links to at least one of the circuit boards so that the at least one circuit board receives messages sent by the communication board, transmits safety oriented messages from and/or to the processing unit of the communication board via one of the secure processing units. | 11-22-2012 |
| 20120303848 | SYSTEM AND METHOD FOR ALLOCATING TRANSACTION ID IN A SYSTEM WITH A PLURALITY OF PROCESSING MODULES - A system and method for allocating transaction ID in a system with a plurality of processing modules is disclosed. In one embodiment, a method for assigning transaction ID to a processing module in a network on a chip system (NOCS) with a plurality of processing modules is disclosed. An address space is provided to each of the processing modules. A portion of the address space is selected. A subset of the selected portion of the address space for each of the processing module is selected as Valid Bits. The Valid Bits of the processing module is associated to a transaction ID. | 11-29-2012 |
| 20120303849 | ADVANCED EXTENSIBLE INTERFACE BUS AND CORRESPONDING DATA TRANSMISSION METHOD - An advanced extensible interface (AXI) bus is disclosed. 2×2 AXI crossbars are used as basic units; each including two slave interfaces and two master interfaces; an N | 11-29-2012 |
| 20120311209 | SYSTEM, CIRCUIT AND METHOD FOR IMPROVING SYSTEM-ON-CHIP BANDWIDTH PERFORMANCE FOR HIGH LATENCY PERIPHERAL READ ACCESSES - A system, circuit and method for improving system-on-chip (SoC) bandwidth performance for high latency peripheral read accesses using a bridge circuit are disclosed. In one embodiment, the SoC includes the bridge circuit, one or more bus masters, at least one high bandwidth bus slave and at least one low bandwidth bus slave that are communicatively coupled via a high bandwidth bus and a low bandwidth bus. Further, the bus masters access the at least one low bandwidth bus slave by issuing an early read transaction request in advance to a scheduled read transaction request. Furthermore, the bridge circuit receives the early read transaction request and fetches data associated with the early read transaction request. In addition, the bridge circuit receives the scheduled read transaction request. The fetched data is then sent to the bus masters upon receiving the scheduled read transaction request. | 12-06-2012 |
| 20120311210 | SYSTEM AND METHOD FOR OPTIMIZING SLAVE TRANSACTION ID WIDTH BASED ON SPARSE CONNECTION IN MULTILAYER MULTILEVEL INTERCONNECT SYSTEM-ON-CHIP ARCHITECTURE - A system and method for optimizing slave transaction ID width based on sparse connection between multiple masters and multiple slaves in a multilayer multilevel interconnect system-on-chip (SOC) architecture are disclosed. In one embodiment, slave transaction ID widths are computed for a first processing subsystem and a second processing subsystem including multiple masters and multiple slaves. Further, a slave transaction ID for each master to any slave in the first processing subsystem and in the second processing subsystem is generated based on the computed slave transaction ID width. Furthermore, sparse connection information between the multiple masters and multiple slaves is determined via a first bus matrix in the first processing subsystem. A first optimized slave transaction ID for each master to any slave in the first processing subsystem is then generated by removing don't care bits in each generated slave transaction ID based on the sparse connection information. | 12-06-2012 |
| 20120311211 | METHOD AND SYSTEM FOR CONTROLLING INTER-INTEGRATED CIRCUIT (I2C) BUS - The present invention discloses a method and a system for controlling an Inter-Integrated Circuit (I2C) bus. The method comprises: dividing a Serial Clock Line (SCL) signal collected from an I2C bus of a master device into a plurality of paths of signals and extending the signals to I2C buses of slave devices, by a Complex Programmable Logic Device (CPLD); judging a current state of data and determining a direction of a current Serial Data Line (SDA) signal, between the SDA signal collected from the I2C bus of the master device and the SDA signal collected from the I2C bus of the slave device. The system can reduce cost and design complexity of a single-board. | 12-06-2012 |
| 20120324132 | MASTER-SLAVE SYSTEM WITH REVERSIBLE CONTROL DIRECTION FUNCTION - A master-slave system includes a master and a slave. The master includes a first communication interface, a master controller, and a voltage meter. The voltage meter is connected to the first communication interface and the master controller. The slave includes a second communication interface, an input unit, a slave controller, and a control indicator unit. The control indicator unit is connected to the second communication interface and the slave controller. The salve controller controls voltage of a node between the control indicator unit and the second communication interface to change between a high logic level and a low logic level according to signals from the input unit. The voltage meter is connected to the control indicator unit to detect the voltage of the node. The master controller controls the master to execute a function according to change of the obtained voltage within a preset period. | 12-20-2012 |
| 20120324133 | SYSTEM AND METHOD FOR REMOTELY OPERATING A WIRELESS DEVICE USING A SERVER AND CLIENT ARCHITECTURE - The present disclosure relates to a system and method for remotely operating one or more peripheral devices of a wireless device using a server and client architecture. In one aspect, the system may comprise a wireless device that includes a processor, a memory, a peripheral device, and a server adapted to communicate with the peripheral device; and a removable media device that includes a memory, a processor, and a client adapted to communicate with the server of the wireless device. In another aspect, the method may comprise the steps of emulating a hardware interface on a removable media device; mapping a peripheral device of a wireless device to the interface; mapping a processor of the media device to the peripheral device; wrapping and sending hardware commands from a client of the media device to a server of the wireless device; and executing the commands on the peripheral device. | 12-20-2012 |
| 20120331194 | INTERFACE EXTENDER FOR PORTABLE ELECTRONIC DEVICES - The disclosed embodiments provide a system that facilitates communication between components in a portable electronic device. The system includes a first hub that couples a first set of interfaces to a high-speed link and a second hub that couples a second set of interfaces to the high-speed link. The first hub may receive a communication from a first component through a first interface in the first set of interfaces and transmit the communication through the high-speed link. The second hub may receive the communication from the high-speed link and transmit the communication to a second component through a second interface in the second set of interfaces. The first and second hubs may thus reduce the number of wires required to transmit communications between the first and second sets of interfaces. | 12-27-2012 |
| 20120331195 | Providing Multiple Communication Protocols For A Control System - A control system may be provided for a controlled system such as a drive or inverter system. To provide for control in such system, a master controller may be present to receive, via a second communication protocol from a cabinet controller coupled to the master controller, status information of a controlled device, generate control information based at least in part on the status information, and transmit the control information to the cabinet controller via the second communication protocol. In turn, the cabinet controller can generate and communicate a control packet to the controlled device via a first communication protocol. This packet can be interleaved within another message communicated from the cabinet controller to the device. | 12-27-2012 |
| 20120331196 | RESTORING STABILITY TO AN UNSTABLE BUS - A method for restoring stability to an unstable bus includes cycling a clock of the bus a number of times, transmitting a stop bit, cycling a clock line of the bus at least one time and transmitting a stop bit immediately after an acknowledgment bit has been received by a bus master. | 12-27-2012 |
| 20130007319 | METHOD AND SYSTEM FOR IMPLEMENTING REDUNDANT NETWORK INTERFACE MODULES IN A DISTRIBUTED I/O SYSTEM - A method and system is disclosed for implementing redundant master NIMs ( | 01-03-2013 |
| 20130007320 | SYSTEM AND METHOD FOR IMPROVING ECC ENABLED MEMORY TIMING - A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves. | 01-03-2013 |
| 20130007321 | REQUESTS AND DATA HANDLING IN A BUS ARCHITECTURE - Aspects relate to methods and systems for processing requests and sending data in a bus architecture. At least one master device is connected to at least two slave devices via a bus. An allocator allocates incoming requests from the master device to a target slave device. Incoming requests are buffered for the respective slave device. The master device sends a read request for a first slave device to the bus; the allocator generates a current-state indicator associated with the read request. The allocator generates a priority indicator associated with the read request. If the initial value of the current-state indicator equals the value of the priority indicator, the read request is processed; or if the initial value of the current-state indicator does not equal the value of priority indicator, the read request is deferred until a later time. | 01-03-2013 |
| 20130013830 | METHOD FOR MANAGING SUBNET IN COMPUTER SYSTEM, BUS ADAPTOR AND COMPUTER SYSTEM - A method for managing a subnet in a computer system, comprising: providing a bus adaptor which is engaged with a notch of a PCIE bus in a computer system, wherein the computer system comprises a plurality of subnet nodes, each subnet node comprises a node control chip and at least one Central Processing Unit (CPU), each subnet node is connected to the PCIE bus, the PCIE bus connects the respective subnet nodes through an IB switchboard to construct a subnet; providing, by the bus adaptor, a network address of each subnet node; and performing communications between the subnet nodes according to the network address of each subnet node provided by the bus adaptor. | 01-10-2013 |
| 20130013831 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit, including a first master circuit, a second master circuit, a first slave circuit assigned to the first master circuit, and determines that an access request signal is sent from the first master circuit when an identification information is a first value, a first bus coupled to the first master circuit, the second master circuit, and the first slave circuit, a bus controller is configured to transmit the access request signal to the first slave circuit via the first bus, a system controller directs the bus controller to substitute the first value for a second value on the identification information of the access request signal received from the second master circuit when the first master circuit is in the deactivated state. | 01-10-2013 |
| 20130019040 | FIELD COMMUNICATION SYSTEMAANM Sueki; MasanoriAACI TokyoAACO JPAAGP Sueki; Masanori Tokyo JPAANM Emori; ToshiyukiAACI TokyoAACO JPAAGP Emori; Toshiyuki Tokyo JPAANM Mizushima; FuyukiAACI TokyoAACO JPAAGP Mizushima; Fuyuki Tokyo JP - A field communication system includes a field device as a slave device, having a first slave communication port and a second slave communication port, a communication module as a master device, having first master communication port and a second master communication port, configured to execute communication with the field device, a first communication line configured to connect the first slave communication port with the first master communication port, and
| 01-17-2013 |
| 20130031286 | ACTIVE INFORMATION SHARING SYSTEM AND DEVICE THEREOF - An active information sharing system having a master device and a slave device is disclosed. When the master device is connected to a first host of an administrator, the master device automatically links to a server through a first network module of the first host, for sharing at least an information from the administrator. The master device correspondingly sets a first parameter to the slave device. When the slave device is connected to a second host of an invited client, the slave device automatically links to the server through a second network module of the second host according to the first parameter, for acquiring the information shared from the administrator. | 01-31-2013 |
| 20130036246 | MICROCONTROLLER SYSTEM BUS SCHEDULING FOR MULTIPORT SLAVE MODULES - A system includes master modules, at least one multiport slave module, and a scheduler connected by a system bus. The scheduler is configured to provide scheduling information to the multiport slave module. The scheduling information includes master categorization information and anticipated burst information. The anticipated burst information is based on a scheduler determination for an anticipated bus access by an anticipated master module. The master categorization information categorizes the anticipated master. | 02-07-2013 |
| 20130046909 | Method and Apparatus of Master-to-Master Transfer of Data on a Chip and System on Chip - A system on chip and associated method facilitates transfer of data between two or more master blocks through a bus on chip. The system creates a direct path for data transferring from a master port of a bus to another master port of the same bus. The bus includes a plurality of signals used to transfer data, address or control information between two or several blocks on chip. The behavior of bus connector block is controlled according to the destination of data coming from a master port. The system includes a master-connector-slave arrangement that enables the direct data communication between two or several master blocks, without taking any slave blocks as the data buffer. A bus connector block is configured to manage bus arbitrating and address decoding, and particularly to create the direct data path between master blocks. | 02-21-2013 |
| 20130054852 | Deadlock Avoidance in a Multi-Node System - Transaction requests in an interconnect fabric in a system with multiple nodes are managed in a manner that prevents deadlocks. One or more patterns of transaction requests from a master device to various slave devices within the multiple nodes that may cause a deadlock are determined. While the system is in operation, an occurrence of one of the patterns is detected by observing a sequence of transaction requests from the master device. A transaction request in the detected pattern is stalled to allow an earlier transaction request to complete in order to prevent a deadlock. | 02-28-2013 |
| 20130054853 | Method and Apparatus for Load-Based Prefetch Access - A load state of a slave memory is detected and provided to a master device. The master device communicates prefetch access requests to the slave memory based, at least in part, on the detected load state. Optionally, the master device communicates prefetch requests to the slave memory according to a schedule based, at least in part, on the detected load state. | 02-28-2013 |
| 20130054854 | Full Bus Transaction Level Modeling Approach for Fast and Accurate Contention Analysis - The present invention presents an effective Cycle-count Accurate Transaction level (CCA-TLM) full bus modeling and simulation technique. Using the two-phase arbiter and master-slave models, an FSM-based Composite Master-Slave-pair and Arbiter Transaction (CMSAT) model is proposed for efficient and accurate dynamic simulations. This approach is particularly effective for bus architecture exploration and contention analysis of complex Multi-Processor System-on-Chip (MPSoC) designs. | 02-28-2013 |
| 20130054855 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS - When a bus stop request control unit issues a module-specific bus stop request signal, a bus stop control unit coupled to a bus slave determines a module that serves as a bus master of the bus slave and on which the bus slave is dependent, for example, on the basis of information in a dependence setting register. The bus stop control unit then outputs a prior bus stop request signal to the module on which the bus slave is dependent, so as to stop use of a bus of the module. Upon receipt of a module-specific bus stop completion signal indicating that processing of stop of the bus of the module on which the bus slave is dependent is complete, the bus stop control unit outputs a module-specific bus stop request signal to the module which serves as a bus slave and whose bus is to be stopped. | 02-28-2013 |
| 20130067129 | COMMUNICATION SYSTEM AND SLAVE NODE - In a slave node, a signal processor stores therein wakeup information uniquely defined for the slave node. The signal processor includes a writing unit configured to write the wakeup information into the transceiver at a given timing. A transceiver includes a memory. The wakeup information is written into the memory to be held therein. The transceiver includes a wakeup determiner. The wakeup determiner compares information received via the communication bus with the wakeup information held in the memory if the slave node is operating in the sleep mode, and determines whether the slave node should shift to the wakeup mode according to a result of the comparison. | 03-14-2013 |
| 20130067130 | BUS CONTROL APPARATUS AND BUS CONTROL METHOD - An exemplary object is to make it possible to prompt notify a master-end control unit of failure information of a controlled device in a bus control apparatus that employs a structure in which a master-end circuit part is connected to a slave-end circuit part through a serial bus. A master circuit equipped with a control unit generates an access message for access to a control target equipped with a slave circuit, and transmits the access message to the slave circuit connected to the master circuit through a bus. The slave circuit collects information on the control target, generates a response message to the access message, generates an information message based on the information on the control target, and transmits the response message and the information message to the master circuit. If generation of the response message conflicts with generation of the information message, the slave circuit generates the information message, with a higher priority given to the generation of the information message. | 03-14-2013 |
| 20130073761 | NETWORK COMMUNICATIONS CIRCUIT, SYSTEM AND METHOD - Various exemplary aspects are directed to apparatuses and methods involving switches communicatively-coupled on a bus where one or more of the switches operate to block signals from passing through the switch in a first mode, and to pass signals through the switch in a second mode. A logic circuit is responsive to addressing information received in the first mode, by storing and configuring the apparatus with the address information. The logic circuit ignores address information received in the second mode (e.g., does not reconfigure the apparatus with address information received in the second mode). | 03-21-2013 |
| 20130073762 | SYSTEM ON CHIP, ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE SAME - A system-on-chip (SoC), an electronic system including the same, and a method of operating the same are provided. The method includes setting real-time information indicating whether a master block is a real-time block in a real-time information register of the master block. A weight is set in a weight register of the master block. Buffer information of the master block is checked. A quality-of-service (QoS) signal is generated using the buffer information and the weight. A priority of the master block to use the bus is determined based on the QoS signal. | 03-21-2013 |
| 20130080669 | Dynamically Determining A Primary Or Slave Assignment Based On An Order Of Cable Connection Between Two Devices - Methods, apparatuses, and computer program products for dynamically determining a primary or slave assignment based on an order of cable connection between two devices are provided. Embodiments include detecting, by a first device, insertion of one end of a cable into a port of the first device; determining, by the first device, whether a power signal is received from the cable at the port of the first device; if the power signal is received, performing, by the first device, a data transfer operation over the cable as a slave device to a second device that is coupled to the other end of the cable; and if the power signal is not received, performing, by the first device, a data transfer operation over the cable as a primary device to the second device that is coupled to the other end of the cable. | 03-28-2013 |
| 20130080670 | MODULAR SYSTEM HAVING CROSS PLATFORM MASTER DEVICE - A modular system of devices, in which a (master) device can be combined with one or more of the other (slave) devices in the system to form a functional electronic device (e.g., handheld cellular phone, tablet computing device), having different functionalities and features in different form factors across various platforms. The master device provides control and/or stored data to operate the slave devices, to reduce redundancy between devices of various form factors and/or platforms, in a manner that provides additional or different functions and features in an optimized and/or enhanced manner as the form factor and/or platform changes from one to another. The master device is not functional independent without attachment to a slave device. The master device requires at least a peripheral component (e.g., a display module) provided by the slave device to become an overall functional unit. | 03-28-2013 |
| 20130080671 | BUS CONTROLLER AND CONTROL UNIT THAT OUTPUTS INSTRUCTION TO THE BUS CONTROLLER - A bus controller is arranged on a plurality of network communication buses that connect together a plurality of bus masters, each sending out a packet, and at least one node, to which the packet is sent from each said bus master, in order to control the transmission route of a packet that is flowing through the plurality of communication buses. The bus controller includes: a route diagram manager configured to manage a plurality of transmission routes and their respective transmission statuses; a parameter generator configured to generate either a parameter that conforms to a predetermined probability distribution or a parameter that follows a predefined rule; a processor configured to select one of the plurality of transmission routes based on the respective transmission statuses of the transmission routes and the parameter; and a relay configured to perform relay processing on the packet that is flowing through the communication bus. | 03-28-2013 |
| 20130097348 | METHOD AND SYSTEM FOR COMMUNICATING WITH AND PROGRAMMING A SECURE ELEMENT - A method, device, and system are disclosed that enable the in-situ programming of an on-board secure element. A communication bus normally used to facilitate communications between the secure element and a microprocessor is borrowed to facilitate the in-situ programming with an off-board secure element. The microprocessor is disclosed to include the functionality to switch the configuration of the communication bus to enable the in-situ programming. | 04-18-2013 |
| 20130103868 | INTEGRATED CIRCUIT SYSTEM AND METHOD FOR OPERATING MEMORY SYSTEM - An integrated circuit system includes: a master chip; a slave chip configured to operate under a control of the master chip; and a data channel configured to transfer data between the master chip and the slave chip, wherein a data transfer rate from the master chip to the slave chip through the data channel is different from a data transfer rate from the slave chip to the master chip through the data channel. | 04-25-2013 |
| 20130103869 | BUS CONNECTION CIRCUIT, SEMICONDUCTOR DEVICE AND OPERATION METHOD OF BUS CONNECTION CIRCUIT - A bus connection circuit connects a bus master and a plurality of bus slaves. The bus connection circuit includes a mirror area access detecting circuit and a processing circuit. The mirror area access detecting circuit detects that the bus master accesses a mirror area of a first bus slave of the plurality of bus slaves, and output a detection signal based on a detection result. The processing circuit executes processing preset in correspondence to the detection result, to an area or data as an access object, based on the detection result. | 04-25-2013 |
| 20130111088 | TRAFFIC COMMUNICATION MODULE AND METHOD OF FORMING THE SAME | 05-02-2013 |
| 20130117483 | METHOD FOR OPERATING A BUS SYSTEM - A method for operating a bus system, which includes a master and k slaves as users, where a header of an interrogation frame, which includes k information fields, is transmitted by the master to the slaves; in each instance, an mth slave being assigned an mth information field; an information item regarding the amount of data that is to be sent by the mth slave to the master being written by the mth slave to the mth information field assigned to it; the interrogation frame being transmitted to the master; and a time schedule, by which the amount of data to be sent is taken into account, being prepared by the master for transmitting the data. | 05-09-2013 |
| 20130124763 | Methods for Discovery, Configuration, and Coordinating Data Communications Between Master and Slave Devices in a Communication System - Various embodiments of the present invention methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system. Exemplary embodiments are described with reference to a two-wire point-to-point bus system, although the method can be used in other communication systems. Provisions are included for controlling the sequential powering of the bus and slave devices. | 05-16-2013 |
| 20130124764 | METHOD OF TRANSACTION AND EVENT ORDERING WITHIN THE INTERCONNECT - The disclosure includes embodiments that apply to an interconnect architecture having multiple system masters and at least one shared resource. The disclosure provides a system and method for providing synchronization for transactions in a multi-master interconnect architecture that employs at least one shared resource, or slave component. | 05-16-2013 |
| 20130124765 | SIGNAL TRANSFER CIRCUIT - A signal transfer circuit comprising a control signal transfer unit configured to output an access request output signal and a memory address output signal to the arbiter after timings of the access request input signal of the access request and the memory address input signal input from the bus master have been adjusted, and output an access permission output signal, and a data signal transfer unit configured to output each data output signal to the corresponding bus master or the arbiter after a timing of each data input signal of the access request input from the arbiter or the bus master is adjusted, and output a data validity period output signal to the bus master after a timing of a data validity period input signal indicating a period in which each data is valid in the access request input from the arbiter is adjusted. | 05-16-2013 |
| 20130124766 | Method and Device for Operating a Slave - A method for operating a first slave which is connected to a master and to at least one further slave includes sending, with the master, in each case at least one forward telegram in a forward direction and at least one reverse telegram in a reverse direction via the bus line to the first slave and the at least one further slave. The method further includes deactivating a buffer memory of the first slave in order to stop a forwarding of forward telegrams and reverse telegrams up to a reactivation time when the forward telegram and the reverse telegram are received within a predetermined time window. The first slave is in an annularly closed bus line. | 05-16-2013 |
| 20130132626 | PIN SELECTABLE I2C SLAVE ADDRESSES - This document discusses, among other things, a multi-address Inter-Integrated Circuit (I | 05-23-2013 |
| 20130138847 | BUS APPARATUS WITH DEFAULT SPECULATIVE TRANSACTIONS AND NON-SPECULATIVE EXTENSION - A bus apparatus is provided, which includes a bus master and a bus slave coupled to the bus master through a bus interface. When the bus master sends a bus transaction to the bus slave, the bus slave executes the bus transaction. The bus transaction is speculative by default. The command of the bus transaction indicates whether the bus transaction is a write transaction or a read transaction. When the bus transaction is a write transaction, the bus slave stores the write data of the bus transaction at the address of the bus transaction. When the bus transaction is a read transaction, the bus slave responds the bus transaction with a read data stored at the address of the bus transaction. The bus slave informs the bus master that the bus slave will not recognize further bus transactions in a specific period of time by asserting a bus wait signal. | 05-30-2013 |
| 20130138848 | ASYNCHRONOUS BRIDGE - An asynchronous bridge includes a transmission unit and a receiving unit. The transmission unit receives a write valid signal and input data from a master circuit, outputs write addresses increment under control of the write valid signal, sequentially stores the input data in memory cells, as directed by write addresses, and then sequentially outputs the stored input data, as directed by read addresses. The receiving unit receives a read ready signal from a slave circuit, determines whether memory cells are valid, based on the write addresses and the read addresses, and then outputs a read valid signal and the input data, based on the determination. | 05-30-2013 |
| 20130145063 | Microcontroller resource sharing - A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus. | 06-06-2013 |
| 20130151741 | MEMORY APPARATUSES, COMPUTER SYSTEMS AND METHODS FOR ORDERING MEMORY RESPONSES - Memory apparatuses that may be used for receiving commands and ordering memory responses are provided. One such memory apparatus includes response logic that is coupled to a plurality of memory units by a plurality of channels and may be configured to receiving a plurality of memory responses from the plurality of memory units. Ordering logic may be coupled to the response logic and be configured to cause the plurality of memory responses in the response logic to be provided in an order based, at least in part, on a system protocol. For example, the ordering logic may enforce bus protocol rules on the plurality of memory responses stored in the response logic to ensure that responses are provided from the memory apparatus in a correct order. | 06-13-2013 |
| 20130151742 | SEMICONDUCTOR DEVICE AND CONTROLLING METHOD THEREOF - According to one embodiment, a semiconductor device includes a storing section that stores a setting state that is one of a first connecting state in which another end of a first outbound system bus is connected to an outbound output terminal and another end of a first inbound system bus is connected to an inbound output terminal, and a second connecting state in which another end of a second outbound system bus is connected to the outbound output terminal and another end of a second inbound system bus is connected to the inbound output terminal; and a control section that controls an outbound path switching section and an inbound path switching section based on the setting state so as to assume one of the first connecting state and the second connecting state. | 06-13-2013 |
| 20130166801 | BUS BRIDGE APPARATUS - Disclosed is a bus bridge apparatus may prevent a transfer performance from being lowered due to bus protocol performance mismatch between interconnections. The bus bridge apparatus is used to transfer data to a slave device of a network-based interconnection from a master device of a bus-based interconnection, data of the master device may be buffered by an internal buffer, and may then be transferred to the slave device. At this time, lowering of a transfer efficiency may be prevented by converting a transfer timing of addresses and data to be optimized to a transfer protocol of the network-based interconnection through a protocol converter. | 06-27-2013 |
| 20130166802 | TRANSPONDER, METHOD AND RECORDING MEDIUM CONTAINING INSTRUCTIONS FOR CONTROLLING THE SAME - A transponder connected to a master, a transmission module and a reception module, the transponder including: a memory which stores a table indicating whether or not a command from the master is executable, wherein the table including: type information indicating a type of the command; and first status information including at least one of: a transmission status indicating a communication status of the transmission module; and a reception status indicating a communication status of the reception module; an acquiring unit that acquires second status information including at least one of: a current transmission status indicating a current communication status of the transmission module; and a current reception status indicating a current communication status of the reception module; a judging unit that judges, in response to a received command received from the master, whether or not the received command is executable using the table and the second status information. | 06-27-2013 |
| 20130173832 | SWITCH FABRIC HAVING A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE - A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch. | 07-04-2013 |
| 20130185468 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a first module that issues a first transaction from a first interface unit to be a bus master, a second module that includes a second interface unit to be a bus slave and a third interface unit to be a bus master, and issues a second transaction in response to the first transaction, a third module that receives the second transaction by a fourth interface unit to be a bus slave, a bus master stop request control unit that asserts a bus master stop request and completes an assertion process in response to assertion of a bus master stop acknowledgement, and a code addition unit that adds to the first transaction a compulsory process request code for forcing issuance of the second transaction regardless of the bus master stop request. | 07-18-2013 |
| 20130191572 | TRANSACTION ORDERING TO AVOID BUS DEADLOCKS - Methods and apparatus for transaction ordering to avoid bus deadlocks are provided. In an exemplary method, custom routing rules for data transport are defined for data transport between a plurality of masters and a plurality of slaves via a plurality of interconnects, based on a network topology and traffic profile. In an example, the customized rule allows a request address to arbitrate in a first phase of arbitration at a first interconnect in the plurality of interconnects prior to receiving write data associated with the request address at a second interconnect in the plurality of interconnects, and does not allow the request address to arbitrate during a subsequent second phase of arbitration unless the request address beats other competing address requests. | 07-25-2013 |
| 20130198427 | SYSTEM AND METHOD FOR A BUS INTERFACE - In accordance with an embodiment, a method of operating a bus interface circuit includes detecting a start sequence on a plurality of input terminals, determining whether a first input terminal and a second input terminal is a data terminal and a clock terminal, respectively, or whether the first input terminal and the second terminal is a clock terminal and a data terminal, respectively. The method also includes routing the first input terminal to a data terminal and the second input terminal to a clock terminal if first input terminal and the second input terminal are determined to be a data terminal and a clock terminal, respectively, and routing the first input terminal to the clock terminal and the second input terminal to the data terminal if first input terminal and the second input terminal are determined to be a clock terminal and a data terminal, respectively. | 08-01-2013 |
| 20130198428 | Device for Transmitting Sensor Data - A device for transmitting sensor data, includes a slave interface connectable to a master interface of a control device, a master interface connectable to a slave interface of a measuring device, at least one sensor interface connectable to a sensor, and a circuit configuration including a manipulation unit and protocol unit. A master-data input signal of the master interface and a sensor-data output signal are supplied to the manipulation unit, which outputs a slave-data output signal to the slave interface. At least one protocol-relevant interface signal of the slave interface or the master interface, and a sensor-data signal of the sensor interface, are supplied to the protocol unit, which generates the sensor-data output signal and, based on manipulation rules and the at least one protocol-relevant interface signal, selects when the manipulation unit outputs the master-data input signal of the master interface or the sensor-data output signal as slave-data output signal. | 08-01-2013 |
| 20130212311 | INTER-COMPONENT COMMUNICATION INCLUDING SLAVE COMPONENT INITIATED TRANSACTION - Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed. A component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. Other embodiments may be disclosed or claimed. | 08-15-2013 |
| 20130238825 | INFORMATION PROCESSING APPARATUS, SERIAL COMMUNICATION SYSTEM, METHOD OF INITIALIZATION OF COMMUNICATION THEREFOR AND SERIAL COMMUNICATION APPARATUS - The disclosure provides a technique of enabling to appropriately confirm the state of a partner apparatus in high-speed serial communication. An information processing apparatus includes a master and a slave which is connected with the master by a plurality of signal lines. The master and the slave are configured to perform a handshake by changing a signal level of a respective data signal line for a period of time longer than a cycle of a clock each other. | 09-12-2013 |
| 20130246675 | MASTER-SLAVE INTERFACE - A bus interface couples a master device and one or more slave devices. Upon detecting a condition on the bus, one or more of the slave devices may force an extension of the bus condition for a predetermined time period. The forced extension may comprise forcing a voltage level, causing other devices on the bus to change modes. A master on the bus may detect an out-of-variance bus condition and, in response, take action to change the bus state to a stable condition. The bus interface may include power contacts and a single-wire bus for communicating between a host device and one or more battery packs. | 09-19-2013 |
| 20130246676 | CIRCUIT AND METHOD FOR SOFTWARE TRACING - A circuit for software tracing in a system on chip is described as including a plurality of components, each component having at least one local processor connected to a first communication bus; and each component being connected to a second communication bus. The circuit may further include a separate trace data bus being configured to transmit trace data generated by code running on the components. A method associated with software tracing on such a circuit is also disclosed. | 09-19-2013 |
| 20130254443 | Method For Determining The Topology Of A Serial Asynchronous Databus - A computer-implemented method for determining the topology of a serial asynchronous data bus, to which at least a first bus subscriber and a second bus subscriber are connected, which subscribers communicate via a prescribed bus access protocol. | 09-26-2013 |
| 20130254444 | IMAGE PROCESSING APPARATUS - An image processing apparatus capable of controlling data transmission between a plurality of bus masters and a memory, includes a bandwidth-limitation storing unit which calculates a memory bandwidth-limitation setting value for each of the bus masters corresponding to the combination of the operating statuses of the bus masters based on a bandwidth-limitation table which stores memory bandwidth-limitation setting values of the bus masters, respectively, for each of the combinations of the operating statuses of the bus masters; a bus adjustment unit connected between the plurality of bus masters and the memory, which limits the data transmission for a bus master whose memory bandwidth occupancy ratio obtained by monitoring the operating statuses of the bus masters, reaches a respective set memory bandwidth-limitation setting value; and a control unit which dynamically sets the calculated memory bandwidth-limitation setting value for each of the bus masters in the bus adjustment unit. | 09-26-2013 |
| 20130262724 | Method and Circuit Arrangement for Transmitting Data Between Processor Modules - The invention relates to a circuit arrangement for forming a digital interface comprising a digital data bus, which exchanges data when microprocessor systems are connected. The data exchange can be effected bidirectionally. On transmission of data the circuit arrangement generates as bus master a bus clock speed and operates on receipt of data as a bus slave in accordance with the received clock signal. The circuit arrangement comprises at least one FIFO memory for receiving data. | 10-03-2013 |
| 20130268705 | APPARATUS AND METHOD FOR PROVIDING A BIDIRECTIONAL COMMUNICATIONS LINK BETWEEN A MASTER DEVICE AND A SLAVE DEVICE - A bidirectional communications link between a master device and a slave device includes first endpoint circuitry coupled to the master device generating forward data packets, second endpoint circuitry coupled to the slave device for receiving reverse data packets, and bidirectional communication circuitry for transferring forward data packets from the first endpoint circuitry to the second endpoint circuitry and reverse data packets from the second endpoint circuitry to the first endpoint circuitry. In response to a power down condition requiring a power down of at least one of the first endpoint circuitry and the second endpoint circuitry, performance of said power down is deferred until both said outstanding forward credit signal and said outstanding reverse credit signal have been de-asserted. | 10-10-2013 |
| 20130268706 | SYSTEM ON CHIP FOR ENHANCING QUALITY OF SERVICE AND METHOD OF CONTROLLING THE SAME - A system on chip (SOC) include at least one slave device, a plurality of master devices, a plurality of service controllers and an interconnect device. The master devices generate requests to demand services from the slave device, respectively. The service controllers generate urgent information signals and priority information signals for each of the master devices. The interconnect device is coupled to the slave device and the master devices through respective channels. The interconnect device performs an arbitrating operation on the requests based on the priority information signals and controls request flows between the slave device and the master devices based on the urgent information signals. | 10-10-2013 |
| 20130275636 | ACCESSING PERIPHERAL DEVICES - A hardware system comprises a master device and a slave device that are coupled by a signal line. A frequency generator in the master device places a selected frequency signal on the signal line. A frequency detector/comparator in the slave device, which is coupled to the signal line, determines whether the selected frequency signal on the signal line matches a predetermined frequency for the slave device. If the selected frequency signal matches the predetermined frequency, then a chip select node on the slave device is enabled, in order to permit a data exchange session between the master device and the slave device. | 10-17-2013 |
| 20130282941 | NETWORK COMMUNICATIONS APPARATUS, SYSTEM, AND METHOD - In one embodiment, a communication circuit is configured for automated addressing in a network of series connected communication circuits. The communication circuit includes a voltage source and a switch connected in parallel between first and second data ports of the circuit. While operating in an addressing mode, a first voltage is sampled from a first data port while the switch is closed. The switch is opened to provide a voltage potential between the first and second data port and a second voltage is sampled from the second data port. An address of the communication circuit in the network is determined based on a difference of the first and second voltages. | 10-24-2013 |
| 20130290582 | Interconnect Congestion Reduction for Memory-Mapped Peripherals - A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device. | 10-31-2013 |
| 20130304954 | Dynamically Optimizing Bus Frequency Of An Inter-Integrated Circuit ('I2C') Bus - Optimizing an I | 11-14-2013 |
| 20130304955 | Methods and Apparatuses for Trace Multicast Across a Bus Structure, and Related Systems - Systems and methods for trace multicast across a bus structure are provided. Preferably, the bus structure is that of a System-on-a-Chip (SoC), where the SoC includes a number of master components and a number of slave components connected via the bus structure. The bus structure supports a trace multicast feature. In one embodiment, the bus structure receives a bus transaction from a master component and, in response, outputs the bus transaction to a corresponding slave port. In addition, the bus structure determines whether a trace multicast is desired for the bus transaction. If a trace multicast is desired, the bus structure generates an additional bus transaction having one or more transaction attributes that include a translated version of the bus transaction and outputs the additional bus transaction to a trace slave port of the bus structure. The trace multicast feature provides a non-invasive mechanism for driver-level trace. | 11-14-2013 |
| 20130311691 | System and Method to Address Devices Connected to a Bus System - A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is configured to detect a direction of a current to detect a location of the first component in the bus system. Each of the components can have a unique address. | 11-21-2013 |
| 20130318267 | APPARATUS AND METHOD FOR POLLING ADDRESSES OF ONE OR MORE SLAVE DEVICES IN A COMMUNICATIONS SYSTEM - An address polling method and system for communicating unique slave address values to a master device over a shared bus. The method includes receiving a request signal from the master device requesting that a slave address from each slave device coupled to the data line be sent to the master; causing, in a serial manner, the data line to be placed in logic states corresponding to bit values in a first slave address; and upon the data line being placed in a logic state that is different from a corresponding bit value of the first slave address, determining that another slave device is placing its slave address on the data line and temporarily entering an idle state until such other slave device has finished communicating its slave address to the master device. | 11-28-2013 |
| 20130326099 | METHOD FOR AUTOMATICALLY ALLOCATING ADDRESSES TO SIMILAR BUS USERS - In a method for allocating addresses in a CAN network having at least one master bus user and at least one slave bus user, the master bus user initiates the address allocation via a query message that is arranged for all bus users. Slave bus users which have already been assigned an address respond to this query message by transmitting a message at their assigned address. Slave bus users which have not yet been assigned an address take measures in response to this query message to be able to transmit on the bus without collisions, and transmit their serial number to the master bus user using these measures. At least the slave bus users which have not yet been assigned an address are assigned a suitable address by the master after receipt of the serial number, and use this address for further communication on the bus. | 12-05-2013 |
| 20130332636 | METHOD FOR CONFIGURATING CANOPEN NETWORK, METHOD FOR OPERATING SLAVE DEVICE OF CANOPEN NETWORK AND SYSTEM FOR CONTROLLING PLC DEVICE USING CANOPEN NETWORK - Disclosed are a method of configurating a CANopen network, a method of operating a slave device of the CANopen network, and a system for controlling a PC device using the CANopen network. The method of operating the slave device connected to the CANopen network includes creating a process data object for transmission, designating identifier information for the process data object, and transmitting the created process data object to a device corresponding to the designated identifier information. The identifier information includes a communication object identifier allowing another slave device or a master device connected to the CANopen network to receive the process data object. | 12-12-2013 |
| 20130332637 | MOTOR VEHICLE HAVING A FLEXRAY BUS - A motor vehicle has a FlexRay bus. Values for operating parameters are stipulated for the FlexRay bus. The value for at least one selected operating parameter is obtained from an optimization method in which, on the basis of prescribed messages to be transmitted via the FlexRay, a plurality of values for the at least one selected operating parameter have an Allocation—associated with these values—of slots to the prescribed messages provided for them according to a predetermined rule, and a predetermined sequence of the allocation is rated according to a predetermined criterion. | 12-12-2013 |
| 20130339559 | METHOD TO CONTROL OPTICAL TRANSCEIVER IMPLEMENTED WITH A PLURALITY OF INNER SERIAL BUSES - An optical transceiver implemented with a plurality of inner serial busses is disclosed. One of inner serial busses is the mother serial bus drawn out from the controller to the bus selector, while, the rest are daughter serial busses connecting the bus selector to respective circuit units. When some circuit units causes failures to hang the daughter serial bus connected thereto, the controller makes this daughter serial bus inactive by controlling the bus selector, and collects information and sets parameters to rest circuit units as activating other daughter serial busses. | 12-19-2013 |
| 20130346658 | Chip Select ('CS') Multiplication In A Serial Peripheral Interface ('SPI') System - Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output. | 12-26-2013 |
| 20130346659 | MASTER DEVICE THAT CHANGES DATA COMMUNICATION SPEED WHEN PREPARATION TO DRIVE MOTOR IS COMPLETED - A first communication speed setting unit sets a data communication speed of data transmitted and received between the master device and the slave device during the period from the time when the master device is activated to the time when the preparation to drive the motors is completed, to a first communication speed. A second communication speed setting unit sets a data communication speed of data transmitted and received between the master device and the slave device when the preparation to drive the motor is completed, to a second communication speed lower than the first communication speed. A change notification unit notifies the change of the data communication speed from the first communication speed to the second communication speed to the slave device. | 12-26-2013 |
| 20140025851 | DOUBLE DENSITY I2C SYSTEM - An I2C system comprises an inter-integrated circuit (I2C) master device coupled to an I2C multiplexer via a master I2C bus. A plurality of slave I2C busses emanating from the I2C multiplexer couple the I2C multiplexer to a plurality of I2C slave devices. Each of the slave I2C busses comprises a serial data (SDA) line and serial clock (SCL) line. Each of the slave I2C busses, which is coupled to two I2C slave devices, has a first channel and a second channel. The first channel puts bidirectional serial data on the SDA line and clock signals on the SCL line, and the second channel puts bidirectional serial data on the SCL line and clock signals on the SDA line. A channel selector, associated with the I2C multiplexer, selectively couples the I2C master device to one of the two I2C slave devices via the first channel or the second channel. | 01-23-2014 |
| 20140025852 | Configurable Response Generator for Varied Regions of System Address Space - A bus interconnect for interconnecting one or more master devices with one or more slave devices in a system includes at least one slave interface module adapted for communicating with a corresponding one of the master devices and at least one master interface module adapted for communicating with a corresponding one of the slave devices. The bus interconnect further includes a configurable response module coupled with the slave interface module. The configurable response module is operative to generate different configurable responses associated with access requests to corresponding portions of an address space of the system. | 01-23-2014 |
| 20140025853 | COMPUTER SYSTEM - The present invention provides a computer system including a CPU with an L2 cache, a bus master device and a bus slave device. They are connected via a system bus to communicate with each other. The computer system | 01-23-2014 |
| 20140025854 | Bus system having a master and a group of slaves and communication method for interchanging data in said bus system - The invention relates to a bus system having a master and a group of slaves connected thereto via a bus and to a communication method for interchanging data between the master and slaves in such a bus system. At least one communication frequency is associated with each slave in the group. The master places transmission data at different communication frequencies onto the bus in transmission phases. Each slave in the group reads in and processes those transmission data which have been placed onto the bus by the master at a frequency corresponding to the, or a, communication frequency associated with this slave and ignores and rejects those transmission data which have been placed onto the bus by the master at a frequency corresponding to a communication frequency associated with another slave in the group, with the result that each slave in the group can be individually addressed by the master by virtue of the fact that transmission data are transmitted from the master to each of the slaves in the group at that communication frequency which has been associated with said slave. | 01-23-2014 |
| 20140032802 | DATA ROUTING SYSTEM SUPPORTING DUAL MASTER APPARATUSES - A data routing system supporting dual master apparatuses is provided. The system includes a first master apparatus, a second master apparatus, at least one first-type interface apparatus, and at least one second-type interface apparatus, which are connected in a daisy chain manner. The first master apparatus provides data transmission of a first channel and a second channel. The second master apparatus transmits data with the first master apparatus through the first channel by using a peer-to-peer data transmission method and bypasses data of the second channel. The first-type interface apparatus transmits data with the first master apparatus through the second channel, and the second-type interface apparatus transmits data with the second master apparatus through the first channel. | 01-30-2014 |
| 20140040516 | BARRIER TRANSACTIONS IN INTERCONNECTS - Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained. | 02-06-2014 |
| 20140040517 | Dynamic Address Change Optimizations - A method of setting an address of a component that includes determining a characterization value associated with a consumable, calculating a number of address change operations based upon the characterization value, and setting a last address generated from the number of address change operations as the new address of the component, wherein the characterization value is determined based upon a usage of the consumable. | 02-06-2014 |
| 20140052881 | SYSTEMS AND METHODS FOR CONCATENATING MULTIPLE DEVICES - System and methods are provided. In one embodiment, a system includes serial peripheral interface (SPI) bus and a master device communicatively coupled to the serial peripheral interface (SPI) bus. The system further includes a first slave device communicatively coupled to the SPI bus. The system additionally includes a second slave device communicatively coupled to the SPI bus and to the first slave device; wherein the first and the second slave devices are communicatively coupled in parallel to the SPI bus and wherein the first and the second slave devices are communicatively coupled to each other by using a first chain line, and wherein the master device is configured to communicate with the first and with the second slave devices over the SPI bus. | 02-20-2014 |
| 20140059260 | BATTERY PACK MONITORING SYSTEM AND METHOD FOR ASSIGNING A BINARY ID TO A MICROPROCESSOR IN THE BATTERY PACK MONITORING SYSTEM - A battery pack monitoring system is provided. The system includes a master microprocessor and a first microprocessor. The master microprocessor outputs a first signal from an output port thereof to induce an input port of the first microprocessor to have a first low logic voltage. The master microprocessor sends a message having a first binary ID from the communication bus port thereof through a communication bus after outputting the first signal. The first microprocessor receives the first binary ID at the communication bus port thereof and stores the first binary ID in a non-volatile memory of the first microprocessor when the input port of the first microprocessor has the first low logic voltage. | 02-27-2014 |
| 20140068125 | MEMORY THROUGHPUT IMPROVEMENT USING ADDRESS INTERLEAVING - Aspects of the disclosure pertain to a system and method for promoting memory throughput improvement in a multi-processor system. The system and method implement address interleaving for promoting memory throughput improvement. The system and method cause memory access requests to be selectively routed from master devices to slave devices based upon a determined value of a selected bit of an address specified in the memory access request. | 03-06-2014 |
| 20140068126 | COMMUNICATION SYSTEM - A communication system having a plurality of communication nodes connected by a communication bus is provided. The system allows at least one non-periodical data message to have a higher priority order than a periodical data message that is transmitted in response to a periodically-transmitted reference message from a master node ECU. In such a manner, a transmission of an urgent non-periodical data message has a higher priority than a transmission of the periodical data message. As a result, a wait time before a start of a transmission of the non-periodical data message is reduced. | 03-06-2014 |
| 20140075072 | SYSTEMS AND METHODS FOR IMPROVED LINKING OF MASTER AND SLAVE DEVICES - System and methods are provided. In one embodiment, a system includes a master device comprising a first serial peripheral interface (SPI) port having only a first four wires. The system further includes a slave device comprising a second SPI port having only a second four wires. The system additionally includes a galvanic isolation barrier communicatively coupling the first four wires to the second four wires. The master device is configured to use the first four wires to transmit a plurality of signals representative of a reset and of a first communications mode. The first communications mode is used to transfer data between the master device and the slave device. | 03-13-2014 |
| 20140082238 | METHOD AND SYSTEM FOR IMPLEMENTING A CONTROL REGISTER ACCESS BUS - A communication system is described providing for access to registers over a control register access bus. The system includes one or more core units including one or more addressable core registers, wherein the units are coupled to the communication bus. The system also includes one or more core clusters (CCLUSTERs) coupled to the one or more core units through the communication bus. The CCLUSTERs provide one or more gateways for transactions to and from the one or more core units. The system also includes a request ordering and coherency (ROC) unit coupled to the CCLUSTERs through the communication bus that is configured for scheduling transactions relating to the registers onto the communication bus. The system also includes the one or more addressable registers that are located in the ROC unit, the CCLUSTERs, and the one or more core units. | 03-20-2014 |
| 20140089543 | Master Mode and Slave Mode of Computing Device - A computing device to couple with a second computing device. The computing device switches between a master mode and a slave mode based on whether the computing device is docked with the second computing device. | 03-27-2014 |
| 20140089544 | INFORMATION PROCESSING DEVICE AND DATA COMMUNICATION METHOD - An information processing device may include a master device and at least one slave device, which may be connected each other by using two types of signal lines comprising a serial clock line and a serial data line. A datum may be transmitted between the master device and the slave device according to a predetermined communication method by using the two types of signal lines. If either the master device resets the slave device, or a power supply to the master device and the slave device is turned on, the slave device may commence a starting operation. A notification of a starting condition may be provided to the master device by way of at least one of the serial clock line and the serial data line. | 03-27-2014 |
| 20140101351 | TWO-WIRE COMMUNICATION PROTOCOL ENGINE - In an example embodiment, a two-wire communication protocol engine manages control and data transmissions in a bi-directional, multi-node bus system where each node is connected over a twisted wire pair bus to another node. Some embodiments include a state machine that allows for synchronized updates of configuration data across the system, a distributed interrupt system, a synchronization pattern based on data coding used in the system, and data scrambling applied to a portion of the data transmitted over the twisted wire pair bus. The multi-node bus system comprises a master node and a plurality of slave nodes. The slave nodes can be powered over the twisted wire pair bus. | 04-10-2014 |
| 20140108687 | Gang Programming of Devices - Multiple devices may be simultaneously programmed using JTAG circuitry or a JTAG operation. The output of a master device's programming may be used to verify the programming of one or more slave devices. The comparison of the master device's programming output to a slave device's programming output may be handled by a logic circuit. The logic circuit may signal the result of the comparison by, for example, a LED. | 04-17-2014 |
| 20140115209 | Flow Control for a Serial Peripheral Interface Bus - Systems and methods for flow control within a Serial Peripheral Interface without additional signal lines are included herein. In one example, a method includes generating a flow control command. The method also includes sending the flow control command from a master device to a slave device with a Serial Peripheral Interface. In addition, the method includes sending a memory address from the master device to the slave device. Furthermore, the method includes detecting a ready indicator in the master device. The method also includes waiting to receive a ready indicator and communicating with the slave device in response to the ready indicator. | 04-24-2014 |
| 20140115210 | Multi Processor Multi Domain Conversion Bridge with Out of Order Return Buffering - An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the bus protocols used by each individual processor within the attached subsystem, and can perform the appropriate protocol conversion on each processor's transactions to adapt the transaction to/from the bus protocol used by the interconnect. | 04-24-2014 |
| 20140115211 | SYSTEM AND METHOD FOR CONTROLLING DEVICES - A method and system for communicating, comprising: at least one master device comprising at least one master driver with at least one intelligent vending controller application; at least one slave device comprising at least one slave driver; and at least one controller area network (CAN) bus facilitating communication between the at least one master device and the at least one slave device; the master device facilitating communication between at least one host application and the at least one master device and the at least one slave device such that the slave device does not require the at least one intelligent vending controller application in order to communicate with the host application; wherein the at least one master device and the at least one slave device are vendor devices. | 04-24-2014 |
| 20140115212 | SERIAL COMMUNICATION CIRCUIT, INTEGRATED CIRCUIT DEVICE, PHYSICAL QUANTITY MEASURING DEVICE, ELECTRONIC APPARATUS, MOVING OBJECT, AND SERIAL COMMUNICATION METHOD - A serial communication circuit includes a receiving unit configured to serially receive input data including a command and a synchronization identification code that is different from the command and a determining unit configured to receive the synchronization identification code from the receiving unit and when the synchronization identification code coincides with a slave selection value, to instruct a start of response processing based on the command. | 04-24-2014 |
| 20140122758 | METHOD AND DEVICE FOR PARAMETERIZING AN AS-I SLAVE - A method is disclosed for parameterizing an AS-i slave. In order to improve the parameterization of an AS-i slave, the following steps are carried out: determining the parameters of the AS-i slave to be parameterized via an engineering tool; transmitting the determined parameters to an AS-i master via a first telegram; receiving the first telegram, which contains the determined parameters of the AS-i slave to be parameterized, via a receiving unit of the AS-i master; automatically converting the received first telegram into an AS-i telegram by a processing unit of the AS-i master, such that the AS-i telegram contains the determined parameters of the AS-i slave to be parameterized; and transmitting the AS-i telegram, which contains the determined parameters of the AS-i slave to be parameterized, to the AS-i slave to be parameterized via a transmission unit of the AS-i master. | 05-01-2014 |
| 20140136741 | Bus Detection and Control Method and Bus Detection and Control Device and Mobile Industry Processor Interface System Thereof - A bus detection and control method for a mobile industry processor interface system is disclosed, wherein a host is coupled to a slave with a mobile industry processor interface bus. The bus detection and control method includes steps of detecting statuses of the mobile industry processor interface bus and the host, to output a control signal; and outputting one of a predefined signal corresponding to an initial state and a transmission signal outputted to the mobile industry processor interface bus by the host as a reception signal of the slave according to the control signal. | 05-15-2014 |
| 20140136742 | COMMUNICATION SYSTEM - A communication system includes: a master device; and slave devices communicating with the master device via a transmission line. The master device includes: an electric power supply unit for outputting an electric power supply signal having one specific frequency to the transmission line; a master communication unit for communicating with each slave device through a communication signal; and an electric power supply frequency setting unit for setting the one specific frequency. Each slave device includes: an electric power supply signal input and output unit for retrieving the electric power supply signal having a set frequency from the transmission line; a communication signal input and output unit for receiving and transmitting the communication signal to the transmission line; a slave communication unit for communicating with the master device through the communication signal; and a power source for energizing the slave communication unit according to the electric power supply signal. | 05-15-2014 |
| 20140143461 | SERIAL INTERFACE - A serial interface comprises a clock line, a request line, a ready line, a master-to-slave data line, and a slave-to-master data line. A master device transmits a clock signal to a slave device over the clock line. In a first transaction, the master device sends a master transmission request signal to the slave device over the request line; in response, the slave device sends a slave transmission accept signal over the ready line, which causes the master device to transmit binary data to the slave device over the master-to-slave data line. In a second transaction, the slave device sends a slave transmission request signal over the ready line; in response, the master device sends a master transmission accept signal over the request line, which causes the slave device to transmit binary data to the master device over the slave-to-master data line. In at least one of the transactions, the master and slave devices transmit binary data at the same time as each other. | 05-22-2014 |
| 20140143462 | REGISTER SLICING CIRCUIT AND SYSTEM ON CHIP INCLUDING THE SAME - A register slicing circuit includes first and second register circuits, a forward channel and a backward channel. The first and second register circuits sequentially store requests received from a plurality of master devices to output the stored requests toward a slave device. The forward channel is used for sending a first request from the first register circuit to the second register circuit, and the backward channel is used for sending back a second request from the second register circuit to the first register circuit. | 05-22-2014 |
| 20140143463 | SYSTEM ON CHIP AND CORRESPONDING MONITORING METHOD - The present invention relates to aSoC, which includes a master device, a slave device, a high-speed bus, and a monitoring apparatus. The master device is connected to a first port of the high-speed bus, and the slave device is connected to a second port of the high-speed bus, so that the master device is capable of accessing the slave device. The monitoring apparatus is arranged between the first port of the high-speed bus and the master device, and/or between the second port of the high-speed bus and the slave device, and configured to record, based on a high-speed bus communication protocol, state information of each command that passes through the first port and/or the second port, and when state information of a command indicates that an operation of the command is in a timeout state, report an interrupt to locate a faulty node on the high-speed bus. | 05-22-2014 |
| 20140149615 | CONNECTING MULTIPLE SLAVE DEVICES TO A SINGLE MASTER - A device comprising: a bus master, including a bi-directional data and clock lines, configured to produce a select signal output for enabling data transmission on the bi-directional data line to first/second different data busses supporting multiple slave devices configured to receive/transmit data over a respective data bus and to receive a clock signal from the bus master from the clock line; and a de-multiplexer including an input, first and second outputs and a control input, the input coupled to the bi-directional data line of the bus master, first/second outputs of the de-multiplexer coupled to first/second data busses, respectively, and the control input configured to receive the select signal from the bus master that is configured to communicate to a first slave device when the select signal is in a first state, and a second different slave device when the select signal is in a second different state. | 05-29-2014 |
| 20140149616 | I2C BUS STRUCTURE AND ADDRESS MANAGEMENT METHOD - An Inter-Integrated Circuit (I2C) bus structure includes a master device, a slave device, and an address setter connected to each other via I2C buses. The slave device has an original device address. The master device transmits an address set command to the address setter. The address setter changes the first device address of the slave device to a second device address in response to the address set command. An address management method is also provided. | 05-29-2014 |
| 20140149617 | I2C BUS STRUCTURE AND DEVICE AVAILABILITY QUERY METHOD - An Inter-Integrated Circuit (I2C) bus structure includes a master device and a slave device. The slave device is connected to the master device via an I2C bus and an interrupt line. When the master device receives an interrupt request from the slave device via the interrupt line, the master device determines that the slave device is available. When the master device has not received any interrupt request from the slave device via the interrupt line for a time period, the master device determines that the slave device is not available. A device availability query method is also provided. | 05-29-2014 |
| 20140149618 | CALIBRATION PROTOCOL FOR COMMAND AND ADDRESS BUS VOLTAGE REFERENCE IN LOW-SWING SINGLE-ENDED SIGNALING - A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode. | 05-29-2014 |
| 20140149619 | BUS SYSTEM INCLUDING AN INTERCONNECTOR, A MASTER DEVICE, A SLAVE DEVICE, AND AN OPERATING METHOD THEREOF - A system-on-chip bus system and an operating method of the same are provided. The bus system includes a master device, a slave device and an interconnector coupled between the master device and the slave device. The interconnector includes a synchronization/compaction block to control traffic provided from a master device to a slave device. When a write request traffic and a corresponding write data traffic are all provided from the master device, the synchronization/compaction block may transfer the two traffics to the slave device. | 05-29-2014 |
| 20140156891 | SYSTEMS AND METHODS FOR AUTOMATICALLY GENERATING MASTER-SLAVE LATCH STRUCTURES WITH FULLY REGISTERED FLOW CONTROL - A method for automatically generating master-slave latch structures is disclosed. A method includes, from another logic synthesis system that invokes a logic synthesis system for generating master-slave latch structures, accessing high level design descriptions of a master-slave latch structure that indicate a fully registered flow control structure design and based on the high level design descriptions, generating a master-slave latch structure design to include at least one master-slave latch pair. | 06-05-2014 |
| 20140156892 | METHOD, SYSTEM, AND APPARATUS FOR LINK LATENCY MANAGEMENT - A link latency management for a high-speed point-to-point network (pTp) is described The link latency management facilitates calculating latency of a serial interface by tracking a round trip delay of a header that contains latency information. Therefore, the link latency management facilitates testers, logic analyzers, or test devices to accurately measure link latency for a point-to-point architecture utilizing a serial interface. | 06-05-2014 |
| 20140164659 | REGULATING ACCESS TO SLAVE DEVICES - A method includes receiving a request from a master device to access a slave device of a plurality of slave devices that are associated with a slave port of bus switching fabric. The slave port is shared in common among the slave devices. The method includes, in response to the request, multiplexing use of the slave port among the slave devices. | 06-12-2014 |
| 20140173147 | TRIGGER ROUTING UNIT - Trigger routing in computational hardware such as a digital-signal processor involves routing a trigger signal from a first, master module to a second, slave module, thereby initiating an event at the slave module without involving a core processing unit. | 06-19-2014 |
| 20140189176 | PROCESSOR ARRANGEMENTS AND A METHOD FOR TRANSMITTING A DATA BIT SEQUENCE - A processor arrangement is provided. The processor arrangement includes: a first processor; a plurality of second processors, each second processor including a bit-mask generator configured to generate a processor-specific bit-mask sequence; wherein the first processor includes a bit-mask generator configured to generate the processor-specific bit-mask sequences of the second processors; wherein the first processor is configured to bit-mask a data bit sequence to be transmitted to one second processor of the plurality of second processors using a processor-specific bit-mask sequence specific to the one second processor, to thereby generate a processor-specific bit-masked data sequence to be transmitted to the one second processor. | 07-03-2014 |
| 20140189177 | HIGH SPEED OVERLAY OF IDLE I2C BUS BANDWIDTH - High-speed serial communications between programmable devices connected to an I | 07-03-2014 |
| 20140189178 | SINGLE WIRE SERIAL INTERFACE MASTER MODULE AND METHOD THEREOF FOR SAMPLING DATA INFORMATION - The present invention discloses a single wire serial interface (SSI) master module, including: a sample delay controlling unit, configured to send a delay instruction; the state machine unit, configured to wait, according to the delay instruction, for a delay period starting from a moment when an SSI master module completes sending the last bit of address information in a read operation frame, and then send a sample control signal to a selector unit; the selector unit, configured to enable a transmission channel with a sampling unit after receiving the sample control signal; and the sampling unit, configured to sample data information from an SSI slave module. In the present invention, the state machine unit delays sending the sample control signal, and the sampling unit is controlled to delay sampling the data information, which avoids a data reception error caused by slow discharging of an IO PAD. | 07-03-2014 |
| 20140189179 | SYSTEM ON CHIP AND METHOD FOR ACCESSING DEVICE ON BUS - The present invention discloses a system on a chip and a method for accessing a device on a bus, and belongs to the electronics field. The system includes: a primary device, configured to send an access request; an extension module, configured to receive the access request sent by the primary device, and extend the ID signal in the access request according to the number of primary devices; a parsing module, configured to parse the access request output by the extension module to obtain an access response instruction; and a secondary device, configured to respond to the extended access request according to the access response instruction. By using the foregoing technical solution, the present invention allows the primary device to flexibly access the secondary device, thereby reducing requirements on the primary and secondary devices. | 07-03-2014 |
| 20140195707 | EXECUTIVE DEVICE AND STACK METHOD AND STACK SYSTEM THEREOF - A stack method for executive devices includes the following steps: a present master-slave setting is detected of each execution device, such that the execution device is respectively set as a master device and a slave device. The master device generates coding information. It is detected if another execution device is connected successively to the current execution device, so as to process the coding information. If there is another execution device connected successively to the current execution device, the current execution device generates following coding information according to its coding information and writes the following coding information to the successive execution device as its coding information. If there is no execution device connected successively, the current execution device replies its coding information to the master device as end coding information. | 07-10-2014 |
| 20140201404 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A system can include at least one offload processor having a data cache, the offload processor including a slave interface configured to receive write data and provide read data over a memory bus; an offload processor module including context memory and a bus controller connected to the slave interface; and logic coupled to the offload processor and context memory and configured to detect predetermined write operations over the memory bus; wherein the offload processor is configured to execute operations on data received over the memory bus, and to output context data to the context memory, and read context data from the context memory. | 07-17-2014 |
| 20140201405 | INTERCONNECTION OF MULTIPLE CHIPS IN A PACKAGE UTILIZING ON-PACKAGE INPUT/OUTPUT INTERFACES - An interface. A first set of single-ended transmitter circuits reside on a first die having a master device. A first set of single-ended receiver circuits reside on a second die. The receiver circuits have no termination and no equalization. The second die has a slave device responsive to the master device of the first die. Conductive lines connect the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. | 07-17-2014 |
| 20140201406 | METHOD FOR CONTROLLING TRANSACTION EXCHANGES BETWEEN TWO INTEGRATED CIRCUITS - Transaction exchanges are controlled between two integrated circuits in a system having the integrated circuits (ICs), a power supply supplying power to a link between the ICs, thereby enabling transaction exchanges between both ICs and a controller controlling the ICs and the power supply. This involves receiving an order at the controller, wherein the order requires the link to be closed. An instruction is sent from the controller to each of the two ICs, wherein the instruction causes each of the ICs to stop initiating new transaction requests. For each one of the ICs, in response to detecting that the one of the two ICs has stopped initiating new transactions, it is detected when all pending transactions initiated by the one of the two ICs have been executed. The link is closed in response to detecting that all pending transactions of both of the two ICs have been executed. | 07-17-2014 |
| 20140201407 | INTERCONNECT, BUS SYSTEM WITH INTERCONNECT AND BUS SYSTEM OPERATING METHOD - Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master. | 07-17-2014 |
| 20140207986 | APPARATUS FOR MULTIPLE BUS MASTER ENGINES TO SHARE THE SAME REQUEST CHANNEL TO A PIPELINED BACKBONE - In accordance with embodiments disclosed herein are mechanisms for enabling multiple bus master engines to share the same request channel to a pipelined backbone including: receiving a plurality of unarbitrated grant requests at an agent bus interface from a plurality of masters, each requesting access to a backbone connected via a common request channel; determining which of the unarbitrated grant requests is to issue first as a final grant request; storing a master identifier code for the final grant request into a FIFO buffer, the master identifier code associating the final grant request with the issuing master among the plurality of masters; waiting for a backbone grant; and presenting the master identifier code for the final grant request to an agent bus interface, wherein the agent bus interface communicates a command and data for processing via a backbone responsive to the backbone grant to fulfill the final grant request. | 07-24-2014 |
| 20140215113 | HDMI-CEC DEVICE AND ADDRESS ALLOCATION METHOD OF HDMI-CEC DEVICE NETWORK - A method allocates physical addresses HDMI-CEC devices within an HDMI-CEC device network. The HDMI-CEC device network includes a plurality of HDMI-CEC devices consisting of at least two root devices, a plurality of parent devices, and a plurality of slave devices. Each of the root devices has a root ID. When a slave device is plug into an HDMI interface of a parent device, the parent device allocates a root ID and a physical address for the slave device. The slave device creates a route table according to the allocated root ID and physical address, to establish a serial communication with the parent device. | 07-31-2014 |
| 20140223051 | INFORMATION COLLECTION SYSTEM - An information collection system is provided. The information collection system includes an information collection unit, an information initiation unit, and an information relay unit. The information collection unit includes at least one slave port, and the information collection unit responds a transaction through the slave port. The information initiation unit includes at least one master port, and the information initiation unit initiates the transaction through the master port. The information relay unit includes at least one master port and at least one slave port, and the information relay unit relays the transaction through the master port and the slave port wherein the transaction includes a write transaction. Wherein, during an identification phase, the master port of the information initiation unit delivers a header, and the slave port of the information collection unit accepts the transaction according to the header. | 08-07-2014 |
| 20140223052 | SYSTEM AND METHOD FOR SLAVE-BASED MEMORY PROTECTION - A system includes a bus slave coupled to a plurality of bus masters via one or more interconnects. The system also includes a memory protection unit (MPU) associated with the bus slave, the MPU having a set of access permissions that grants access to the bus slave from a first bus master and denies access to the bus slave from a second bus master. The MPU generates an error response as result of a transaction generated by a task on the second bus master attempting to access the bus slave. | 08-07-2014 |
| 20140223053 | ACCESS CONTROLLER, ROUTER, ACCESS CONTROLLING METHOD, AND COMPUTER PROGRAM - The access controller conducts arbitration between first nodes, each of which is attempting to transmit data to any of second nodes as destinations through a network of buses. The access controller includes: a buffer which receives the data that have been provided by the first nodes with mutually different required qualities and destinations, classifies the data according to their destinations and required qualities, and stores the classified data separately; an inter-class arbitrator which sequentially selects one of the required qualities of the data after another in the order of their severity; an inter-destination arbitrator which selects the destinations of the data to be transmitted and gets the transmission quantities of the data distributed among the destinations; and a transmission controller which controls transmission of the data based on the required qualities selected by the inter-class arbitrator and the destinations selected by the inter-destination arbitrator. | 08-07-2014 |
| 20140223054 | MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS - A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures. | 08-07-2014 |
| 20140237148 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - A data processing device includes a first sub-arbiter configured to arbitrate an access by first and second masters that access data stored in a memory; a second sub-arbiter configured to arbitrate an access to the memory by a plurality of masters other than the first and the second masters; a main arbiter configured to prioritize the access to the memory by the first sub-arbiter over the access to the memory by the second sub-arbiter; and a limiting unit configured to limit an amount of the access to the memory by the second master within a preset range. | 08-21-2014 |
| 20140244873 | Methods And Systems For Interconnecting Host And Expansion Devices Within System-In-Package (SiP) Solutions - Methods and systems are disclosed for interconnecting die-to-die-port (DTDP) host devices and DTDP expansion devices for combined system-in-package (SiP) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device. Further, direct circuit interconnection blocks (e.g., using copper pillar (CuP) connectors) can be used to improve connectivity and performance. In addition, level shift circuitry can be utilized within expansion devices to allow for standardized interconnect signals and supply voltages to be provided by DTDP host devices to DTDP expansion devices. | 08-28-2014 |
| 20140244874 | RESTORING STABILITY TO AN UNSTABLE BUS - A logic module for restoring stability to an unstable bus. The logic module includes logic for detecting that a communications error has occurred on the bus. The logic module also includes logic for stabilizing a slave device operating in a read mode. The logic module further includes logic for stabilizing the slave device operating in a write mode. The stabilizing of the slave device operating in a write mode occurs after stabilizing the slave device operating in a read mode. | 08-28-2014 |
| 20140258573 | SYSTEMS AND METHODS FOR MASTER ARBITRATION - A power system is provided. The power system includes a communications bus and a plurality of modules communicatively coupled to the communications bus. Each of the plurality of modules is configured to continuously monitor the communications bus, transmit a modulated signal at a predetermined frequency when the module detects an incoherent signal on the communications bus, become a master module when the module detects a coherent signal at the predetermined frequency on the communications bus, and cease transmitting the modulated signal when the coherent signal is not detected after a period of time. | 09-11-2014 |
| 20140258574 | Two-Wire Serial Interface and Protocol - In a serial transmission method using a two-wire serial interface, a master device transmits a first synchronous serial signal via the two-wire serial interface to wake-up a slave device followed by an asynchronous data transmission on one of the two-wires of the two-wire serial interface. The asynchronous data signal directly controls a function of the slave device. | 09-11-2014 |
| 20140258575 | MASTER-SLAVE DETECTION METHOD AND MASTER-SLAVE DETECTION CIRCUIT - A master-slave detection method includes: every single time period, utilizing a random manner for determining whether a first device is used to transmit a specific pulse signal to a second device; every single time period, utilizing a random manner for determining whether the second device is used to transmit the specific pulse signal to the first device; when the first device receives at least one portion of the specific pulse signal earlier than the second device, setting the first device as a master device, stopping the master device from sending the specific pulse signal and utilizing the master device to start transmitting a specific sequence; and setting the second device as a slave device when the second device receives the specific sequence. The at least one portion of the specific pulse signal includes continuous single pulses. | 09-11-2014 |
| 20140258576 | COMMUNICATION DEVICE, COMMUNICATION METHOD, AND COMMUNICATION SYSTEM - A slave device ( | 09-11-2014 |
| 20140281077 | DUAL VOLTAGE COMMUNICATION BUS - A bidirectional bus system that includes a bus master having a first transmitter coupled to a bidirectional bus. The first transmitter transmits a signal in a first voltage range onto the bus. The bus master has a first receiver coupled to the bus. A bus slave having a second transmitter coupled to the bus is included. The second transmitter transmits a signal in a second voltage range onto the bus, where the bus slave having a second receiver is coupled to the bus. The first receiver is configured to interpret the signal in the first voltage range to indicate an idle state while the second receiver interprets the signal in the first voltage range as indicating data. The second receiver interprets the signal in the second voltage range as indicative of an idle state while the first receiver interprets the signal in the second voltage range as indicating data. | 09-18-2014 |
| 20140281078 | CONFIGURATION SWITCH FOR A BROADCAST BUS - A bidirectional bus system is provided. The bidirectional bus system includes a plurality of bus slaves configured to couple to a bidirectional bus. Each bus slave of the plurality of bus slaves has a switch operated by a switch control to selectably couple and decouple an upstream portion and a downstream portion of the bidirectional bus relative to the bus slave, with the switch control being powered by activity on the bidirectional bus. A method of operating a bus is also provided | 09-18-2014 |
| 20140281079 | FAULT-TOLERANT LOOP FOR A COMMUNICATION BUS - A communication bus system is provided. The communication bus system includes a communication bus having a plurality of isolatable segments and a bus master coupled to a first end of the communication bus. The bus master is configured to couple to a second end of the communication bus and to decouple from the second end of the communication bus based on a selection signal. A method for operating a communication bus is also disclosed. | 09-18-2014 |
| 20140281080 | ADDRESS TRANSLATION IN 12C DATA COMMUNICATIONS SYSTEM - A novel readdressing circuit is provided for supporting data communications over a data line and a clock line between at least one master device and multiple slave devices. For example, the master device and the multiple slave devices may be configured to communicate over an I2C bus including the data line and the clock line. The readdressing circuit has a data input node for receiving a data signal transferred over the data line and including an address word produced by the master device, and a data output node coupled to the multiple slave devices. The readdressing circuit also includes an address generator and an address transmit detections circuit. The address generator is configured for storing a multi-bit fixed offset value. The address generator is responsive to the address word at the data input node for generating multiple unique addresses for the multiple slave devices. The address transmit detection circuit is configured for enabling the address generator to generate the multiple unique addresses at the data output node when the address word is detected at the data input node, and for preventing an output signal of the address generator from being supplied to the data output node when no address word is detected at the data input node. | 09-18-2014 |
| 20140281081 | PROACTIVE QUALITY OF SERVICE IN MULTI-MATRIX SYSTEM BUS - A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path. | 09-18-2014 |
| 20140281082 | METHOD, APPARATUS, AND SYSTEM FOR IMPROVING INTER-CHIP AND SINGLE-WIRE COMMUNICATION FOR A SERIAL INTERFACE - A system and method consistent with the present disclosure includes a master device, bus interface link, and slave device. The master device includes a power supply and a detection unit to detect an impedance of the power supply. The inverter provides a first path to the power supply on a first stage of a clock signal and. Further, the inverter provides a second path to a first ground line on a second stage of a clock signal. The bus interface link couples the master device to a slave device. Additionally, a bi-directional communications line is coupled to the bus interface link. A gating component provides a second ground line to the power supply through the first path. Furthermore, a receiver determines bit values from a plurality of clock data signals transmitted from the master device. | 09-18-2014 |
| 20140297912 | STATUS SWITCHING METHOD - The present invention provides a status switching method applied to a slave device. The status switching method includes: receiving a command wrapper from a host device; receiving a status query command corresponding to the command wrapper from the host device; transmitting a status wrapper to the host device in response to the status query command; and refusing to enter a low-power status corresponding to a switch status request when the switch status request is received during a specific period, wherein the specific period starts when the command wrapper is received and ends when the status wrapper is transmitted. | 10-02-2014 |
| 20140297913 | SLAVE CONTROL DEVICE AND METHOD FOR PROGRAMMING A SLAVE CONTROL DEVICE - A slave control device for use in a master/slave bus system having at least two programs that are stored in the slave control device, wherein the programs are matched to different masters that differ in schedule tables, at least one distinguishing feature of the schedule tables is stored in the slave control device, the respectively connected master is detected as a function of the distinguishing feature and the associated program is loaded into a program memory or remains loaded. Also disclosed is a method for programming a slave control device. | 10-02-2014 |
| 20140304442 | SERIAL BUS BUFFER WITH NOISE REDUCTION - Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface. | 10-09-2014 |
| 20140304443 | SINGLE WIRE BUS SYSTEM - There is provided a single wire bus architecture comprising a single wire bus; a master device coupled to the single wire bus; at least one slave device coupled to the single wire bus; a communication protocol implemented over the single wire bus and employed by the master device and the at least one slave device; wherein when one of the at least one slave devices wishes to communicate with the master device, the one of the at least one slave devices discharges the clock signal during a tri-state stage of the clock signal; and wherein the single wire bus transmits a clock signal, power and data between the master device and the one of the at least one slave device in communication with the master device. | 10-09-2014 |
| 20140310436 | METHOD AND SYSTEM FOR SINGLE-LINE INTER-INTEGRATED CIRCUIT (I2C) BUS - Embodiments of a system and method are disclosed. One embodiment is an I2C compatible device. The I2C compatible device includes an SDA interface for connection to an SDA line and a single-line I2C module configured to transmit a sync word from the SDA interface over the SDA line and following the sync word, to transmit I2C data from the SDA interface over the SDA line such that digital data is communicated via a single line. In an embodiment, the sync word is a sync byte+NACK. | 10-16-2014 |
| 20140317322 | METHOD FOR OPERATING A COMMUNICATION SYSTEM - A method for transmitting frames containing data between users of a ring-shaped communication system which has a master and at least one slave as users. Each user has at least one interrupt register, and one field of the at least one interrupt register is associated with an interrupt request and includes a value for an interrupt bit. An interrupt request which includes the interrupt bit is transmitted to the master by a slave in a frame designed as an empty frame. In addition, the empty frame has a toggle bit for all slaves which indicates the state of an interrupt request. | 10-23-2014 |
| 20140325102 | METHOD FOR OPERATING A SLAVE NODE OF A DIGITAL BUS SYSTEM - A method for operating a slave node of a digital bus system is described. The slave node comprises two sending and receiving devices. In the bus system, an input data frame is sent to a master node in input direction. The slave node receives the input data frame by the first sending and receiving device. The slave node stores service data packets contained in the input data frame in a FIFO memory. The slave node attaches at least one process data packet of its own to a last process data packet in the input data frame. The slave node attaches the service data packets to the process data packet, which is now last, in the input data frame. The slave node sends the input data frame, which was changed in this manner, to the next node in input direction by the second sending and receiving device. | 10-30-2014 |
| 20140325103 | System and Method for a Bus Interface - In accordance with an embodiment, a method of operating a bus interface circuit includes detecting a start sequence on a plurality of input terminals, determining whether a first input terminal and a second input terminal is a data terminal and a clock terminal, respectively, or whether the first input terminal and the second terminal is a clock terminal and a data terminal, respectively. The method also includes routing the first input terminal to a data terminal and the second input terminal to a clock terminal if first input terminal and the second input terminal are determined to be a data terminal and a clock terminal, respectively, and routing the first input terminal to the clock terminal and the second input terminal to the data terminal if first input terminal and the second input terminal are determined to be a clock terminal and a data terminal, respectively. | 10-30-2014 |
| 20140325104 | COMMUNICATIONS ASSEMBLY HAVING LOGIC MULTICHANNEL COMMUNICATION VIA A PHYSICAL TRANSMISSION PATH FOR SERIAL INTERCHIP DATA TRANSMISSION - In a communications assembly having multiple users, one user is designated as a master and additional users are designated as peripheral modules, at least two of the peripheral modules as well as at least two interface modules are integrated into a shared physical implementation unit, and at least one interface module, which is designated as a slave, is unambiguously assigned to each of the at least two peripheral modules. | 10-30-2014 |
| 20140330997 | SYSTEM AND METHOD FOR MONITORING TWO-WIRE COMMUNICATION IN A NETWORK ENVIRONMENT - An example method is provided and includes receiving, from a host device, a first signal over a two-wire bus to an address on the two-wire bus corresponding to a small form factor (XFP) module, the host device being located outside the XFP module, the two-wire bus coupling the host device with a first controller inside the XFP module and a second controller inside the XFP module that share the address such that the first controller and the second controller receive the first signal, and blocking a second signal from the second controller to the host device using digital isolation buffers. A third signal from the first controller to the host device over the two-wire bus is not blocked. In specific embodiments, the first controller includes a XFP compliant controller and the second controller includes an optical controller. | 11-06-2014 |
| 20140337551 | APPARATUS FOR SETTING NETWORK OF PROCESS FIELD BUS DECENTRALIZED PERIPHERY - The present disclosure includes a master device, a plurality of slave devices performing a communication through Profibus and a configuration tool providing network configuration information of Profibus DP by generating the network configuration information, wherein the configuration tool includes an automatic configuration module configured to request the master device of information relative to the plurality of slave devices in response to an automatic configuration command inputted through a user communication module, to receive the information and provide profiles of relevant types by determining the types of the plurality of slave devices using the received information, and a network configuration information configured to generate the network configuration information in response to the types and profiles determined by the automatic configuration module and to provide the network configuration information to the master device. | 11-13-2014 |
| 20140337552 | SLAVE DEVICE BIT SEQUENCE ZERO DRIVER - A slave device to be connected to a master device by a data line comprises circuitry that, in response to receiving a command from the master device, drives a bit sequence comprising at least one zero. | 11-13-2014 |
| 20140351468 | Backplane Timing Distribution - A master and slave module are described that facilitate the distribution of timing, both frequency and phase over a backplane. The method is applicable over any pair of shared transmission medium. The signal transmitted from the master to the slave is suitable for delivering a frequency reference and an approximate phase. The precise phase at the slave is obtained by delaying the 1PPS by a programmable amount estimated by measuring the round-trip delay between the master and slave. | 11-27-2014 |
| 20140351469 | Dynamic Address Change Optimizations - A method of setting an address of a component that includes determining a characterization value associated with a consumable, calculating a number of address change operations based upon the characterization value, and setting a last address generated from the number of address change operations as the new address of the component, wherein the characterization value is determined based upon a usage of the consumable. | 11-27-2014 |
| 20140351470 | METHODS AND SYSTEMS FOR AN INTERPOSER BOARD - In accordance with at least some embodiments, a system includes an aggregator backplane coupled to a plurality of fans and power supplies and configured to consolidate control and monitoring for the plurality of fans and power supplies. The system also includes a plurality of compute nodes coupled to the aggregator backplane, wherein each compute node selectively communicates with the aggregator backplane via a corresponding interposer board. Each interposer board is configured to translate information passed between its corresponding compute node and the aggregator backplane. | 11-27-2014 |
| 20140365695 | ELECTRONIC DEVICE WITH MULTIFUNCTIONAL UNIVERSAL SERIAL BUS PORT - An electronic device with a multifunctional universal serial bus (USB) port is provided. The electronic device includes a USB port, a processing unit, a power module, a master-slave response module, and a power control module. The master-slaver response module is connected between the USB port and the processing unit, and is used to produce a corresponding trigger signal to the processing unit according to a type of an external device connected to the USB port. The power control module is connected between the power module and a voltage pin of the USB port. Therein, the processing unit disables the power control module when receiving a first trigger signal. The processing unit enables the power control module to output the power to the power pin of the USB port when receiving a second trigger signal, thus to power the external device. | 12-11-2014 |
| 20140372646 | RECEIVER BASED COMMUNICATION PERMISSION TOKEN ALLOCATION - A data processing apparatus is provided with a master device and a slave device which communicate via communication circuitry. The slave device is associated with a predetermined number of permission tokens that is equal to a maximum number of currently pending messages that can be accepted for processing from the communication circuitry by that slave device. The slave device transmits these permission tokens to the master device. The master device takes exclusive temporary possession of the permission tokens that it receives such that the permission tokens are then no longer available to any other master device. A master device initiates a message to a slave device when the master device has exclusive temporary possession of a permission token for that slave device. When the master device has initiated its message, then it relinquishes the exclusive temporary possession of the permission token such that it is then available for other devices. | 12-18-2014 |
| 20140372647 | NETWORK COMMUNICATION CONTROL APPARATUS, SYSTEM AND METHOD - Aspects of the present disclosure are directed to single-wire bus communications. In accordance with one or more embodiments, a pull-up current is delimited when a single-wire bus circuit is operated at a dominant level during the transmission of data on the single-wire bus circuit. This approach can be implemented to facilitate power savings, such as in applications involving a master control circuit that transmits signals by driving the single-wire bus circuit between dominant and recessive levels. | 12-18-2014 |
| 20140379949 | DATA COMMUNICATION SYSTEM, SLAVE, AND MASTER - A data communication system includes a master and a slave. The master transmits a first subject signal including a first subject data to the slave via a transmission line. The slave extracts a clock signal from the first subject signal by performing a clock data recovery process and determines the first subject data based on the first subject signal. The slave transmits a second subject signal including a second subject data to the master during an existing period of the first subject signal without interfering an extracting of the clock signal and a determination of the first subject data. The master receives the second subject signal and cancels a waveform component of the first subject signal from a waveform of the second subject signal, and then determines the second subject data based on the second subject signal. | 12-25-2014 |
| 20140379950 | MANAGEMENT OF COMPUTER SYSTEMS BY USING A HIERARCHY OF AUTONOMIC MANAGEMENT ELEMENTS - A method and system for managing a computing system by using a hierarchy of autonomic management elements are described. The autonomic management elements operate in a master-slave mode and negotiate a division of management responsibilities regarding various components of the computing system. | 12-25-2014 |
| 20150012678 | SENSOR SYSTEMS AND METHODS UTILIZING ADAPTIVELY SELECTED CARRIER FREQUENCIES - A sensor system utilizing adaptively selected carrier frequencies is disclosed. The system includes a system bus, a bus master, and a sensor. The system bus is configured to transfer power and data. The bus master is coupled to the system bus and is configured to provide power to the bus and receive data from the bus. The sensor is coupled to the system bus and is configured to transfer data on the bus using an adaptively selected carrier frequency. | 01-08-2015 |
| 20150012679 | IMPLEMENTING REMOTE TRANSACTION FUNCTIONALITIES BETWEEN DATA PROCESSING NODES OF A SWITCHED INTERCONNECT FABRIC - A method of implementing remote transactions between system on a chip (SoC) nodes of a node interconnect fabric includes determining that a bus transaction initiated at a first one of the SoC nodes specifies a target at a second one of the SoC nodes, providing a virtual on-chip bus between the first and second SoC nodes within the fabric, and providing the bus transaction to the second one of the SoC nodes over the virtual link on-chip bus. | 01-08-2015 |
| 20150019776 | SELECTIVE CHANGE OF PENDING TRANSACTION URGENCY - The present invention provides a transaction interface to be used between semiconductor intellectual property cores. The urgency attribute of pending transactions can be changed by a special type of transaction at the interface. The urgency can be incremented, raised to at least an indicated value, or changed to a value as specified. For an interface with multiple pending transactions, a mask can be used to indicate one or more IDs, the transactions of which should be changed. | 01-15-2015 |
| 20150019777 | CONFIGURATION VIA HIGH SPEED SERIAL LINK - Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided. | 01-15-2015 |
| 20150019778 | SWITCH FABRIC HAVING A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE - A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch. | 01-15-2015 |
| 20150026374 | MANAGING SLAVE DEVICES - A hardware system comprises a digital signal generator, which generates a digital electrical signal that describes a first physical state of a first device; an analog electrical signal generator, which generates an analog electrical signal that describes a second physical state of the first device; a hybrid digital state signal generator, which generates a hybrid digital state signal that comprises the analog electrical signal overlaid onto the initial digital electric signal; and a hybrid signal transmitter, which transmits the hybrid digital state signal from the first device to a second device, wherein the second device comprises a hybrid signal receiver/decoder that extracts the analog electrical signal from the hybrid digital state signal. | 01-22-2015 |
| 20150026375 | CONTROL APPARATUS, COMPUTER SYSTEM, CONTROL METHOD AND STORAGE MEDIUM - A control apparatus which controls an access to a memory acquires, for the access to the memory, a predetermined address corresponding to the order of addresses at which the memory is accessed, and determines whether the predetermined address is identical to the target address of the access. In a case where the predetermined address is identical to the target address, the control apparatus controls the access to the memory so as to perform page close after the end of the access to the target address. | 01-22-2015 |
| 20150032925 | System Management through Direct Communication between System Management Controllers - An information handling system includes a first managed system including a first processor and a first management controller and a second managed system including a second processor and a second management controller. The first management controller is coupled to directly communicate with the second management controller. In an embodiment, the first management controller is coupled to the second management controller via a first I2C interface. | 01-29-2015 |
| 20150032926 | STORAGE APPARATUS, AND SYSTEM AND METHOD FOR EXECUTING ACCESS OPERATIONS - Embodiments of the present invention provide a storage apparatus, and a system and a method for executing access operations. The apparatus includes an interleaved bus, N memory groups, and K direct-connect bus groups, where K is less than or equal to N; the interleaved bus includes M master interfaces and S slave interfaces, where M is less than or equal to S, and each master interface among the M master interfaces is configured to receive continuous-addresses access operations; each memory group among the N memory groups includes S memories respectively connected to the S slave interfaces, where the interleaved bus is configured to decode and send the continuous-addresses access operations to at least one memory group among the N memory groups in an interleaved manner; and a first direct-connect bus group among the K direct-connect bus groups receives and sends the discrete-addresses access operations to at least one memory group. | 01-29-2015 |
| 20150039795 | SYSTEM INTERCONNECTION, SYSTEM-ON-CHIP HAVING THE SAME, AND METHOD OF DRIVING THE SYSTEM-ON-CHIP - Provided is a method of driving a system-on-chip (SOC). The method includes adding a first transaction to a list, allocating the first transaction to a first slot, determining whether a second transaction is redundant, and adding the second transaction to the list and allocating the second transaction to the first slot when it is determined that the second transaction is redundant. Accordingly, the SOC can increase outstanding capability and enhance performance of a system interconnection. | 02-05-2015 |
| 20150046615 | MEMORY MODULE COMMUNICATION CONTROL - Methods and systems for memory module communication control are disclosed. A method includes receiving a message associated with a memory module in communication with a controller via a bus including a clock line. Further, the method includes determining whether the bus is idle. The method also includes communicating a signal via the clock line regarding the message associated with the memory module in response to determining that the bus is idle. | 02-12-2015 |
| 20150046616 | PERIPHERAL REGISTERS WITH FLEXIBLE DATA WIDTH - A flexible-width peripheral register mapping is disclosed for accessing peripheral registers on a peripheral bus. | 02-12-2015 |
| 20150052271 | METHOD OF OPTIMIZING THE WIDTH OF TRANSACTION ID FOR AN INTERCONNECTING BUS - The present invention discloses a method of to generate transaction ID(s) in a bus interconnection design. An encoding table for each slave can be derived by calculating all possible transactions from all the masters to the slave so as to determine the minimum width of the transaction ID received by the slave in the interconnecting bus design, thereby avoiding the routing congestion in the interconnecting bus. | 02-19-2015 |
| 20150058507 | METHOD TO MINIMIZE THE NUMBER OF IRQ LINES FROM PERIPHERALS TO ONE WIRE - A master device is provided which is coupled to a shared single line interrupt request (IRQ) bus and a control data bus. The master device group slave devices coupled to the shared single line IRQ bus into one or more groups, where each group is associated with a different IRQ signal. The master device then monitors the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device. The master device then identifies a group to with which the IRQ signal is associated. The slave devices for the identified group are then scanned or queried by the master device to ascertain which slave device asserted the IRQ signal on the IRQ bus. Each group uses a distinguishable IRQ signal to allow the master device to ascertain which group to query or scan. | 02-26-2015 |
| 20150067211 | Peripheral Equipment Control Device and Information Processing - Disclosed herein is a peripheral equipment control device controlling data flow via a peripheral equipment, the peripheral equipment control device including: a peripheral equipment control processor that can control an operation of one or more peripheral equipment; and a bus adapted to connect the peripheral equipment control processor, a main processor, and the one or more peripheral equipment, the main processor being provided outside the peripheral equipment control device to control the operation of the one or more peripheral equipment, in which the bus stores addresses that are referenced by the main processor and the peripheral equipment control processor to access the one or more peripheral equipment, and the bus prohibits access to the peripheral equipment by the peripheral equipment control processor while the main processor is active. | 03-05-2015 |
| 20150067212 | SYSTEMS AND METHODS FOR INITIALIZATION AND LINK MANAGEMENT OF NICS IN A MULTI-CORE ENVIRONMENT - The present application is directed towards systems and methods for coordination and management of a shared resource in a multi-core system. In a multi-core system, multiple cores may be utilizing a shared resource. However, internal resources common to the shared resource may need to be initialized by only one core, and independent and uncoordinated initialization by multiple cores may cause errors. The present invention provides systems and methods for coordinating such initialization and use through a handshaking protocol. | 03-05-2015 |
| 20150074304 | Apparatus and method for polling addresses of one or more slave devices in a communications system - An address polling method and system for communicating unique slave address values to a master device over a shared bus. The method includes receiving a request signal from the master device requesting that a slave address from each slave device coupled to the data line be sent to the master; causing, in a serial manner, the data line to be placed in logic states corresponding to bit values in a first slave address; and upon the data line being placed in a logic state that is different from a corresponding bit value of the first slave address, determining that another slave device is placing its slave address on the data line and temporarily entering an idle state until such other slave device has finished communicating its slave address to the master device. | 03-12-2015 |
| 20150074305 | METHOD AND APPARATUS TO ENABLE MULTIPLE MASTERS TO OPERATE IN A SINGLE MASTER BUS ARCHITECTURE - To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to trigger an IRQ signal over a shared, single line IRQ bus. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ signal. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device. | 03-12-2015 |
| 20150074306 | Single Wire Communications Interface and Protocol - In a single wire communications interface embodiment, a single wire is coupled between a master device and at least one slave device, the master device configured for transmitting data words as serial data to and for receiving data words as serial data from the at least one slave device, and the at least one slave device configured for transmitting data words as serial data to and receiving data words as serial data from the master device; wherein prior to transmission of any data word on the single wire by one of the master device and the slave device, a sync pulse is first transmitted on the single wire. Integrated circuit embodiments for implementing the single wire communications interface, and method embodiments incorporating the single wire communications interface are disclosed. Additional embodiments are disclosed. | 03-12-2015 |
| 20150081940 | Enhanced Serial Interface Systems and Methods Having a Higher Throughput - An enhanced serial interface system is disclosed. The system includes a master component and a slave component. The master component is configured to operate in a standard mode and an enhanced mode for communication. The master component includes standard terminals and hybrid terminals. Only the standard terminals are used for communicating in the standard mode. The hybrid terminals and the standard terminals are used for communicating in the enhanced mode. The slave component is configured to operate in the enhanced mode and communicate with the master component. | 03-19-2015 |
| 20150095536 | METHOD FOR AUTOMATICALLY SETTING ID IN UART RING COMMUNICATION - Disclosed is a method for automatically setting ID in UART ring communication in which a master and a plurality of slaves are formed in a ring-type network, the method including initializing the master to output a master ID (initializing step), receiving, by the plurality of slaves, the master ID, setting its own IDs by adding the master ID to a reference value and outputting the set ID (slave ID setting step), changing, by the plurality of slaves, its own IDs based on whether its own ID is same as the received ID, receiving, by the master, the IDs outputted by the plurality of slaves, and changing a currently highest value of slave IDs stored in the master in response to values of received slave IDs (changing step), and finishing the ID setting or re-setting the slave IDs, in response to the Current Max Slave ID (finish determining step). | 04-02-2015 |
| 20150095537 | CAMERA CONTROL INTERFACE SLEEP AND WAKE UP SIGNALING - A device is provided comprising a control data bus including at least a first line. A master device may be coupled to the control data bus and configured to control the control data bus. A plurality of slave devices may be coupled to the control data bus and share the first line. The master device may be configured to send a single global wake up signal on the control data bus that causes any sleeping slave devices to wake up. Alternatively, the master device may send a global wake up signal followed by a targeted sleep signal to non-targeted slave devices to implement a “targeted wake up” of specific slave devices. The master device may send the single global wake up signal by bringing the first line low for a predetermined period of time. | 04-02-2015 |
| 20150100712 | CAMERA CONTROL INTERFACE SLAVE DEVICE TO SLAVE DEVICE COMMUNICATION - In a shared bus where communications are managed by a master device, direct slave device to slave device (S2S) communications is implemented. A first slave device wanting to communicate with a second slave device may make a S2S communication request to the master device. The request may include a requested number of words that the first slave device wishes to send over the shared bus. The master device may have a current word limit which may vary based upon operating parameters. The master device may deny the request if the requested number of words is greater than the current word limit or if it does not support S2S communications. Denial of the request may also be for other reasons, like activity over the shared bus. If the master device grants the request, the slave device may send the requested number of words to another slave device over the shared bus. | 04-09-2015 |
| 20150100713 | COEXISTENCE OF I2C SLAVE DEVICES AND CAMERA CONTROL INTERFACE EXTENSION DEVICES ON A SHARED CONTROL DATA BUS - A plurality of slave devices is coupled to a control data bus along with at least one master device that is managing access of slave devices to the control data bus. At least one slave device operates in a sI2C protocol mode of operation and at least one other slave device operates in a CCIe mode of operation. At least the slave devices using sI2C protocol mode use the control data bus for interrupt requests. In order to maintain the integrity of CCIe communications, the slave devices using the sI2C protocol mode disables issuing IRQs when the control data bus operates according to the CCIe mode. | 04-09-2015 |
| 20150100714 | SLAVE IDENTIFIER SCANNING AND HOT-PLUG CAPABILITY OVER CCIe BUS - System, methods and apparatus are described that facilitate transmission of data, particularly between two or more devices within an electronic apparatus. Embodiments disclosed herein relate to scanning for slave identifiers (SIDs) on a CCIe bus. A disclosed method includes transmitting a first inquiry on a control data bus, where the first inquiry includes a first configuration of bits, determining presence of a slave device that has a slave identifier that includes a second configuration of bits that matches the first configuration of bits, and repetitively transmitting additional inquiries on the control data bus with different configurations of bits until all bits of the slave identifier are determined The slave device may assert a response to each inquiry that includes a configuration of bits that matches a corresponding configuration of bits in the slave identifier. | 04-09-2015 |
| 20150106541 | AUTO-CONFIGURATION OF DEVICES BASED UPON CONFIGURATION OF SERIAL INPUT PINS AND SUPPLY - A device includes a memory, at least two input/output (IO) pins, and slave identifier (ID) selection circuitry. The memory stores a slave ID, which identifies the device to other devices in a serial communication process. The slave ID selection circuitry changes the stored slave ID based on which one of the IO pins is coupled to a supply voltage. By changing the slave ID of the device based on which one of the IO pins is coupled to a supply voltage, a number of devices with otherwise identical slave IDs may change their slave IDs in order to participate in a serial communication process on the same bus. Further, the slave ID of the device may be changed without using an additional IO pin on the device. | 04-16-2015 |
| 20150113187 | Server System - A server system includes a baseboard management controller and calculation modules. Each calculation module includes a system on chip, slave devices and a switch. The switch is connected with the baseboard management controller, the system on chip and the slave devices. The switch issues an address selection signal to select one of the slave devices to be connected with the switch. The switch switches the baseboard management controller and the system on chip to be connected with one of the slave devices by a control signal. | 04-23-2015 |
| 20150113188 | DATA STORAGE EXPANDING APPARATUS - A data storage expanding apparatus is electrically coupled to a terminal equipment and multiple data storage groups. Each data storage group includes a plurality of data storage devices. The data storage expanding apparatus configured to transmit an operating data between the terminal equipment and to a particular data storage device. The data storage expanding apparatus includes a data storage expanding module and multiple signal expanding modules. The data storage expanding module is electrically coupled to the terminal equipment. The signal expanding modules are electrically coupled in series, and to the data storage groups, respectively. One of the signal expanding modules is electrically coupled to the data storage expanding module. The operating data signal is transmitted to the signal expanding module via the data storage expanding module electrically connected to the signal expanding module, and then transmitted to particular data storage device via the signal expanding module. | 04-23-2015 |
| 20150120974 | ELECTRONIC CONTROLLER TO BE CONNECTED TO PROGRAM TOOL - A first external tool ( | 04-30-2015 |
| 20150120975 | CAMERA CONTROL SLAVE DEVICES WITH MULTIPLE SLAVE DEVICE IDENTIFIERS - System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. An address list may associate each of a plurality of slave devices coupled to a control data bus with a plurality of slave device identifiers. Access to the control data bus may be controlled based on the address list such that, in a first mode of operation information may be broadcast to multiple slave devices using a first group slave device identifier and, in a second mode of operation, information may be exchanged with a single slave device using an individualized slave device identifier. | 04-30-2015 |
| 20150120976 | METHOD AND APPARATUS FOR PERFORMING A BUS LOCK AND TRANSLATION LOOKASIDE BUFFER INVALIDATION - A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor. | 04-30-2015 |
| 20150120977 | INTER-COMPONENT COMMUNICATION INCLUDING SLAVE COMPONENT INITIATED TRANSACTION - Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed. | 04-30-2015 |
| 20150127861 | Dynamic Data Collection Communication Between Adapter Functions - An approach is provided that collects data from a multi-function adapter that is used by multiple functions. In the approach, a master function is dynamically selected from the group of functions. The approach further allows the master function to perform a disruptive adapter data collection while inhibiting performance of disruptive adapter data collection processes by the other (non-master) functions. | 05-07-2015 |
| 20150127862 | Intelligent Connector and Bus Controller - An intelligent connector is disclosed having a signal processing unit, a first port, and a second port. The signal processing unit communicates signals between a bus and a slave module. The first port is coupled between the bus and the signal processing unit, and is connected to a power supply line. The second port is coupled between the signal processing unit and the slave module, and is positioned to provide a power supply to the slave module. | 05-07-2015 |
| 20150143007 | CONTROL CIRCUITRY MODULE GROUP, ELECTRIC DEVICE AND MODEM DEVICE - The present invention relates to a control circuitry module group, an electrical device, and a modem device. The control circuitry module group is configured for communication and/or power supply between a master control module and at least one slave modules in an electrical device. The control circuitry module group comprises: a bus; a bus control module coupled to the master control module and the bus, configured to receive a control signal from the master control module, add a target address in the control signal, and send to the bus the control signal with the target address; and at least one slave control modules each coupled to a corresponding slave module and the bus, respectively, and configured to receive the control signal with the target address via the bus, and controlling power supply to the slave module in response to the control signal. | 05-21-2015 |
| 20150143008 | FIELD BUS SYSTEM - A field bus system includes at least one bus module designed as a master module with at least one connecting device for connection to a network and with at least one port for connecting a parameterizable IO link device. The field bus system uses a data storage device which is designed as an IO link device and which can be connected to the at least one port for connecting an IO link device and in which all parameters of the IO link devices connected to the master module are stored and can be read by the master module. | 05-21-2015 |
| 20150143009 | USE OF AN IO LINK FOR LINKING FIELD DEVICES - The invention relates to the use of an IO link for linking a field device to a master assembly. | 05-21-2015 |
| 20150149673 | FENCE MANAGEMENT OVER MULTIPLE BUSSES - Embodiments of a bridge unit and system are disclosed that may allow for processing fence commands send to multiple bridge units. Each bridge unit may process a respective portion of a plurality of transactions generated by a master unit. The master unit may be configured to send a fence command to each bridge unit, which may stall the processing of the command. Each bridge unit may be configured to determine if all transactions included in its respective portion of the plurality of transactions has completed. Once each bridge unit has determined that all other bridge units have received the fence command and that all other bridge units have completed their respective portions of the plurality of transactions that were received prior to receiving the fence command, all bridge units may execute the fence command. | 05-28-2015 |
| 20150149674 | EMBEDDED STORAGE DEVICE - An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. The microprocessor provides a clock signal and creates data transmission link to the computer device. The master storage unit has a master clock pin, at least a master data pin, and a master control pin. The master control pin receives a command signal from the microprocessor. The slave storage unit has a slave clock pin and at least a slave data pin. The relay bus is coupled to the master storage unit and the slave storage unit to enable communication between the master storage unit and the slave storage unit, such that the command signal from the microprocessor is sent from the master storage unit to the slave storage unit via the relay bus. | 05-28-2015 |
| 20150301968 | METHODS FOR DISCOVERY, CONFIGURATION, AND COORDINATING DATA COMMUNICATIONS BETWEEN MASTER AND SLAVE DEVICES IN A COMMUNICATION SYSTEM - Various embodiments of the present invention methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system. Exemplary embodiments are described with reference to a two-wire point-to-point bus system, although the method can be used in other communication systems. Provisions are included for controlling the sequential powering of the bus and slave devices. | 10-22-2015 |
| 20150309950 | System and Method to Address Devices Connected to a Bus System - A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is configured to detect a direction of a current to detect a location of the first component in the bus system. Each of the components can have a unique address. | 10-29-2015 |
| 20150316974 | METHOD AND APPARATUS FOR GENERATING SLAVE DEVICE IDENTIFIER - A slave controller including an impedance element, and a processor configured to generate an identifier of the slave controller based on an electrical value of electric energy entering the impedance element. | 11-05-2015 |
| 20150317271 | GRAPHICS PROCESSING MICROPROCESSOR SYSTEM HAVING A MASTER DEVICE COMMUNICATE WITH A SLAVE DEVICE - A slave device communicates with a host system via a host communications bus. The host system includes one processor that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processor and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the “internal” physical addresses of the slave's resources and forwards the accesses to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request. | 11-05-2015 |
| 20150324310 | BUS CONNECTION CIRCUIT, SEMICONDUCTOR DEVICE AND OPERATION METHOD OF BUS CONNECTION CIRCUIT FOR MAKING PROCEDURE FOR SWITCHING BETWEEN A 1-CYCLE TRANSFER AND A 2-CYCLE TRANSFER UNNECESSARY - A bus connection circuit connects a bus master and a plurality of bus slaves. The bus connection circuit includes a minor area access detecting circuit and a processing circuit. The minor area access detecting circuit detects that the bus master accesses a minor area of a first bus slave of the plurality of bus slaves, and output a detection signal based on a detection result. The processing circuit executes processing preset in correspondence to the detection result, to an area or data as an access object, based on the detection result. | 11-12-2015 |
| 20150331776 | SWITCH MONITORING SYSTEM - A switch monitoring system is provides information on sensor readings and contact closures over a one-wire network or a loop | 11-19-2015 |
| 20150331819 | SLAVE COMMUNICATION DEVICE AND BUS COMMUNICATION SYSTEM - A slave communication device is connected to a master communication device through a single bus, and transmits a data signal according to a synchronization signal transmitted from the master communication device. The slave communication device includes a current reduction unit that reduces a current flowing into the bus from the slave communication device at least in a period where the synchronization signal is transmitted from the master communication device. | 11-19-2015 |
| 20150339248 | METHOD AND APPARATUS FOR PROCESSING DATA - A data processing method and a data processing apparatus are disclosed. The data processing method may include determining whether a device address included in a signal received from a master device is a registered group device address, and processing data by accessing one or more slave devices mapped to the registered group device address when the device address is the registered group device address. | 11-26-2015 |
| 20150339253 | ELECTRONIC DEVICE WITH ENHANCED MANAGEMENT DATA INPUT/OUTPUT CONTROL - An electronic device has a management data input/output (MDIO) bus, a control unit, and an MDIO master. The control circuit receives a host command from a host device, and outputs a plurality of MDIO commands in response to the host command. The MDIO master receives the MDIO commands from the control circuit, and transmits the MDIO commands to the MDIO bus. | 11-26-2015 |
| 20150339257 | SYSTEM AND METHOD FOR MASTER-SLAVE DATA TRANSMISSION BASED ON A FLEXIBLE SERIAL BUS FOR USE IN HEARING DEVICES - A data transmission system for use in hearing devices includes a master unit with a first local bit clock and a slave unit with a second local bit clock. The master unit and the slave unit are connected to each other via a bus line, and are configured to communicate over the bus line according to a communication protocol based on a frame-wise serial transmission of bits. Each frame includes a clock reference, a master signalling interval, a slave signalling interval and a data payload. The slave unit further includes a clock recovery device for synchronising the second local bit clock with the first local bit clock based on the clock reference transmitted once per frame by the master unit. A corresponding method for data transmission is also provided. Moreover, hearing devices including such a data transmission system as well as uses of such a method for data transmission are proposed. | 11-26-2015 |
| 20150347344 | CONNECTING MULTIPLE SLAVE DEVICES TO SINGLE MASTER CONTROLLER IN BUS SYSTEM - A device comprising: a bus master, including a bi-directional data and clock lines, configured to produce a select signal output for enabling data transmission on the bi-directional data line to first/second different data busses supporting multiple slave devices configured to receive/transmit data over a respective data bus and to receive a clock signal from the bus master from the clock line; and a de-multiplexer including an input, first and second outputs and a control input, the input coupled to the bi-directional data line of the bus master, first/second outputs of the de-multiplexer coupled to first/second data busses, respectively, and the control input configured to receive the select signal from the bus master that is configured to communicate to a first slave device when the select signal is in a first state, and a second different slave device when the select signal is in a second different state. | 12-03-2015 |
| 20150347347 | Dynamic Data Collection Communication Between Adapter Functions - An approach is provided that collects data from a multi-function adapter that is used by multiple functions. In the approach, a master function is dynamically selected from the group of functions. The approach further allows the master function to perform a disruptive adapter data collection while inhibiting performance of disruptive adapter data collection processes by the other (non-master) functions. | 12-03-2015 |
| 20150356043 | MASTER BUS DEVICE FOR A VEHICLE COMMUNICATION BUS OF A MOTOR VEHICLE - A master bus device for a motor vehicle exchanges messages with slave bus devices via a vehicle communication bus of the motor vehicle. It is specified in the master bus device by an operating schedule which is stored in a memory of the master bus device which messages the master bus device exchanges with the slave bus devices. To utilize the vehicle communication bus more efficiently, the master bus device has a switch-over device which is designed to receive a control signal from a device-external transmitting device and, in dependence on the control signal, to switch from the memory with the operating schedule to a further memory with a maintenance schedule which differs from the operating schedule, so that the maintenance schedule is used after switching over, for exchanging messages. | 12-10-2015 |
| 20150356046 | SYSTEM AND METHOD FOR VIRTUAL HARDWARE MEMORY PROTECTION - A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented. | 12-10-2015 |
| 20150356049 | ASSIGNING PROCESSORS TO MEMORY MAPPED CONFIGURATION - Embodiments herein relate to assigning processors to a memory mapped configuration. The processors having access to different buses of a Peripheral Component Interconnect (PCI) segment are quiesced. The quiesced processors are assigned a memory mapped configuration. | 12-10-2015 |
| 20150356052 | Seamless addition of high bandwidth lanes - Seamless addition of high bandwidth lanes, including the steps of: sending, by a master, an idle sequence using 7b/10b code words over new high bandwidth lanes in parallel to sending and receiving 8b/10b data with a fixed delay over master-to-slave (m2s) and slave-to-master (s2m) active high bandwidth lanes; sending in parallel a synchronization sequence and a known non-idle sequence during an inter packet gap; utilizing, by the slave, the known non-idle sequence for deskewing the new high bandwidth lanes; and sending, by the master, a transition sequence over both the m2s active high bandwidth lane and the new high bandwidth lanes, and immediately thereafter the master is ready to transmit high bandwidth data using 8b/10b code words over both the m2s active high bandwidth lane and the new high bandwidth lanes. | 12-10-2015 |
| 20150363353 | COMMUNICATION SYSTEM AND ELECTRONIC CIRCUIT - A communication system includes an I2C device, an SPI device, a selection circuit and an electronic circuit. The selection circuit selects the first data signal when the CS signal is not received, and generates a signal corresponding to the CS signal and transmit the CS signal to the SCL terminal as the stop signal and at the same time. The selection circuit selects the second data signal when the CS signal is received. The electronic circuit functions as a slave of the SPI communication in a case where the CLK signal has made a transition. The electronic circuit further functions as a slave of the I2C communication in a case where the CLK signal does not make a transition and signals indicating a condition under which the I2C communication is started are transmitted to the CS/SCL terminal and the data terminal. | 12-17-2015 |
| 20150370735 | DYNAMICALLY ADJUSTABLE MULTI-LINE BUS SHARED BY MULTI-PROTOCOL DEVICES - A device is provided that has a bus including a first line and a second line. A first set of devices are coupled to the bus and, in a first mode of operation, configured to use the first line for data transmissions and use the second line for a first clock signal. One or more additional lines are connected between two or more of the devices in the first set of devices for transmitting signaling between the two or more devices. A second set of devices are configured to use the bus and at least one of the additional lines for data transmissions in a second mode of operation, where in the second mode of operation symbols are encoded across the first line, the second line, and the at least one of the additional lines. | 12-24-2015 |
| 20150378949 | Method of Transaction and Event Ordering within the Interconnect - The disclosure includes embodiments that apply to an interconnect architecture having multiple system masters and at least one shared resource. The disclosure provides a system and method for providing synchronization for transactions in a multi-master interconnect architecture that employs at least one shared resource, or slave component. | 12-31-2015 |
| 20150378955 | GENERATING COMBINED BUS CLOCK SIGNALS USING ASYNCHRONOUS MASTER DEVICE REFERENCE CLOCKS IN SHARED BUS SYSTEMS, AND RELATED METHODS, DEVICES, AND COMPUTER-READABLE MEDIA - Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device. | 12-31-2015 |
| 20160004647 | METHOD AND CIRCUIT ARRANGEMENT FOR ACCESSING SLAVE UNITS IN A SYSTEM ON CHIP IN A CONTROLLED MANNER - A circuit arrangement and method for accessing slave units in a system on chip in a controlled manner, wherein an access of a master unit of the system on chip to one of the slave units is performed via a network-on-chip bus system using an access address, where a memory protection unit is integrated between the at least one master unit and the network-on-chip bus system, and access authorization of the master unit to a slave unit is checked by the memory protection unit by comparing the access address with specified address sections, and when an unauthorized access of the master unit to a slave unit is identified, the access address is modified by the memory protection unit such that the unauthorized access is terminated in the network-on-chip bus system. | 01-07-2016 |
| 20160004656 | BRIDGING INTER-BUS COMMUNICATIONS - Approaches for bridging communication between first and second buses are disclosed. Address translation information and associated security indicators are stored in a memory. Each access request from the first bus includes a first requester security indicator and a requested address. Each access request from the first bus and directed to the second bus is either rejected, or translated and communicated to the second bus, based on the requester security indicator and the security indicator associated with the address translation information for the requested address. Each access request from the second bus to the first bus includes the requested address, and the access request is translated and communicated to the first bus along with the security indicator that is associated with the address translation information for the requested address. | 01-07-2016 |
| 20160011639 | NETWORK POWER MANAGEMENT SYSTEM | 01-14-2016 |
| 20160019173 | BANDWIDTH CONTROL METHOD FOR AN ON-CHIP SYSTEM - The invention concerns a bandwidth control method in an on-chip system comprising at least one main master module, at least one secondary master module, at least one slave module and a bus connected to each module on a communication link, the bus comprising interconnection means to make at least one common slave module communicate with at least one main master module and with at least one secondary master module via at least one common path portion, the method comprising the following steps carried out for each common slave module: first detection of a first request to access the common slave module, issued by a main master module, definition of a blocking time Dj associated with the common slave module, blocking, during blocking time Dj, of any data transfer on the at least one common path portion between a secondary master module and the common slave module. | 01-21-2016 |
| 20160019175 | METHOD FOR MONITORING COMMUNICATIONS FOR AN ON-CHIP SYSTEM - The invention concerns a method for monitoring transactions in an on-chip system comprising at least one main master module, at least one secondary master module, at least one slave module and a bus connected to each module, the bus comprising interconnection means to make at least one common slave module communicate with at least one main master module and with at least one secondary master module, the method comprising the following steps implemented during each transaction between a secondary master module and a common slave module: starting a counter upon initial detection of a transaction start signal, waiting for a final detection of a transaction end signal within a predefined time T, closing the transaction if the time tc that has elapsed since starting the counter is greater than predefined time Tmax, and reinitialising the counter. | 01-21-2016 |
| 20160019180 | METHOD AND DEVICE FOR FILTERING TRANSACTIONS FOR AN ON-CHIP SYSTEM - The invention in particular concerns a method for filtering access to an on-chip system comprising at least one master module, at least one slave module and a bus, the bus comprising at least one slave port, at least one master port and means for interconnection between at least one of the slave ports and at least one of the master ports, the method being characterised in that it comprises the following steps implemented when an access request is routed from a master module connected to a slave port to a slave module connected to a master port: intercepting an item of source information on the link between the master port and the slave module before the slave module receives the request, searching for the item of source information in at least one access control list controlling access to the slave module, blocking the request such that the slave module is unaware of the requested access if the item of source information is not found in the at least one access control list. | 01-21-2016 |
| 20160026593 | DETECTING THE DRIFT OF THE DATA VALID WINDOW IN A TRANSACTION - Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for detecting the drift of the data valid window in a transaction. An embodiment operates by configuring a data capture range comprising data capture points, measuring values of a signal at the data capture points, and detecting the drift of the data valid window based on the values at the data capture points. | 01-28-2016 |
| 20160034409 | SYSTEM-ON-CHIP AND DRIVING METHOD THEREOF - A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO. | 02-04-2016 |
| 20160034417 | DISTRIBUTED AUDIO COORDINATION OVER A TWO-WIRE COMMUNICATION BUS - Disclosed herein are systems and technique for distributed audio coordination over a two-wire communication bus. For example, in some embodiments, a first slave device may include circuitry to receive, over a two-wire bus a synchronization control frame, audio data, and a dynamics processor (DP) parameter for a second audio device coupled to a second slave device. The first slave device may include circuitry to derive timing information from the synchronization control frame, and circuitry to provide the audio data and a DP parameter (based on the DP parameter for the second audio device) to a first audio device coupled to the first slave device. | 02-04-2016 |
| 20160048470 | MASTER-SLAVE SYSTEM WITH TRIGGERED REMOTE FUNCTION CALLS - Triggered remote function calls can be used in master-slave systems to trigger slave-side software functions pre-loaded by a master into slave MCU memory, with associated parameters pre-loaded into a slave function interface memory. A master issues trigger-function signals (such as rising/falling edges or signal levels) over a trigger-function signal line. The slave includes a trigger conditioning block that in response issues a trigger-function request to the slave MCU, which calls/executes the associated software function, including accessing the associated trigger-function parameters from function interface memory. A slave can include a hardware function block with functionality configurable by a pre-loaded software configuration function (with associated parameters). A master can include a hardware function block configured to issue trigger-function signals. The slave (trigger conditioning block) can be configured to service trigger-function signals as an IRQ (interrupt request) to the MCU, which executes an ISR (interrupt service routine) as a triggered function call. | 02-18-2016 |
| 20160054777 | 1-WIRE BUS PD DETECTION AND CLASSIFICATION SCHEME FOR ETHERNET PoDL - A PoDL system includes a PSE supplying DC power and Ethernet data over a single twisted wire pair to a PD. Prior to coupling the DC voltage source to the wire pair, the PD needs to receive sufficient power to perform a detection and classification routine with the PSE to determine whether the PD is PoDL-compatible. The PSE has a low current, pull-up current source coupled to a first wire in the wire pair via a first inductor. This pull-up current charges a capacitor in the PD to a desired operating voltage, and the operating voltage is used to power a PD logic circuit. The PD logic circuit and a PSE logic circuit then control pull-down transistors to communicate detection and classification data via the first wire. After the handshaking phase, the PSE then applies the DC voltage source across the wire pair to power the PD for normal operation. | 02-25-2016 |
| 20160055114 | HIGH-SPEED SERIAL RING - Methods and systems for transferring a high-speed data signal between more than two electronic devices within a system comprising a master device and a plurality of slave devices are presented. The master device and the plurality of slave devices are connected through high-speed links between high-speed interfaces, thereby forming a closed ring. The high-speed interfaces are comprised by the master device and each of the plurality of slave devices, respectively. A common low frequency clock signal is provided by the master device to each of the slave devices, and a high-speed interface communication method for communication between the master device and the plurality of slave devices through the high-speed links is used. | 02-25-2016 |
| 20160062929 | MASTER DEVICE, SLAVE DEVICE AND COMPUTING METHODS THEREOF FOR A CLUSTER COMPUTING SYSTEM - A master device, a slave device and computing methods thereof for a cluster computing system are provided. The master device is configured to receive device information of the slave device, select a resource feature model for the slave device according to the device information and a job, estimate a container configuration parameter of the slave device according to the resource feature model, transmit the container configuration parameter to the slave device, and assign the job to the slave device. The slave device is configured to transmit the device information to the master device, receive the job assigned by the master device with the container configuration parameter from the master device, generate at least one container to compute the job according to the container configuration parameter, and generate the resource feature model according to job information corresponding to the job and a metric file. | 03-03-2016 |
| 20160062930 | BUS MASTER, BUS SYSTEM, AND BUS CONTROL METHOD - There is provided: an access generation unit ( | 03-03-2016 |
| 20160062931 | HARDWARE DATA STRUCTURE FOR TRACKING PARTIALLY ORDERED AND REORDERED TRANSACTIONS - Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design comprising one or more slaves configured to receive transaction requests from a plurality of masters. The data structure includes one or more counters for keeping track of the number of in-flight transactions; a table that keeps track of the age of each of the in-flight transactions for each master using the one or more counters; and control logic that verifies that a transaction response for an in-flight transaction for a particular master has been issued by the slave in a predetermined order based on the tracked age for the in-flight transaction in the table. | 03-03-2016 |
| 20160070324 | Advanced Power Strip - An advanced power strip includes a housing having at least one control outlet, at least one switched outlet, and at least one auxiliary input port; and at least one auxiliary device coupled to the at least one auxiliary input port. The advanced power strip can be configured to a) allow for master/slave control sensing the current produced by a control device coupled to the at least one control outlet, and, if current is detected, allowing current to be drawn by any device coupled to the at least one switched outlet; and b) allow for manual control of the switched outlets via the at least one auxiliary device coupled to the at least one auxiliary input port. | 03-10-2016 |
| 20160070666 | METHOD OF CONTROLLING DIRECT MEMORY ACCESS OF A PERIPHERAL MEMORY OF A PERIPHERAL BY A MASTER, AN ASSOCIATED CIRCUITRY, AN ASSOCIATED DEVICE AND AN ASSOCIATED COMPUTER PROGRAM PRODUCT - A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. Also, an associated device and an associated computer program product are described. | 03-10-2016 |
| 20160070672 | SLAVE DEVICE FOR A SERIAL SYNCHRONOUS FULL DUPLEX BUS SYSTEM - A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device. | 03-10-2016 |
| 20160072492 | DELAY CIRCUITS AND RELATED SYSTEMS AND METHODS - Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner. | 03-10-2016 |
| 20160092375 | DATA ACCESS PROTECTION FOR COMPUTER SYSTEMS - A protection circuit can be used with a computer system having a master device and at least one slave device that are connected by an inter-integrated circuit (I2C) bus. A first access request is received that includes an address that identifies a first slave device. In response to a permissible mode, the first access request is communicated to the first slave device using the I2C bus. A sticky protection bit can be set. In response to the sticky protection bit being set, the protection circuit can be placed in a protected mode. A second access request is received. The second access request can be determined to be a protected access to the first slave device. In response to the determining and the protected mode, the second access request to the first slave device can be denied. | 03-31-2016 |
| 20160092385 | Single-Wire Communication with Adaptive Start-Bit Condition - The present disclosure pertains to a wired network which includes a master device and a plurality of slave devices coupled to the master device by a wired connection. The master device includes control logic to determine whether information is to be sent to a slave device. In addition, the master device includes a transmitter to drive a logic level for a predetermined amount of time to address the slave device in response to the control logic to determine whether information is to be sent to a slave device. | 03-31-2016 |
| 20160092387 | DATA ACCESS PROTECTION FOR COMPUTER SYSTEMS - A protection circuit can be used with a computer system having a master device and at least one slave device that are connected by an inter-integrated circuit (I2C) bus. A first access request is received that includes an address that identifies a first slave device. In response to a permissible mode, the first access request is communicated to the first slave device using the I2C bus. A sticky protection bit can be set. In response to the sticky protection bit being set, the protection circuit can be placed in a protected mode. A second access request is received. The second access request can be determined to be a protected access to the first slave device. In response to the determining and the protected mode, the second access request to the first slave device can be denied. | 03-31-2016 |
| 20160092388 | MODULE AUTO ADDRESSING IN PLATFORM BUS - A system and approach for addressing modules on a platform bus that may incorporate a master module and one or more slave modules. The platform bus may run through sub-base connectors that interlock modules together on a rail. Addressing of the modules may occur automatically and dynamically in that the master module may have a first address by default, and a first slave module adjoining the master module may be assigned a second address. A second slave module adjoining the first slave module, if there is one, may be assigned a third address. Each of the other slave modules, adjoining a preceding slave module assigned an address, may be assigned a next address after an address assigned to a preceding slave module. Addresses may be assigned in a numerical order to each module based on a physical position of the respective module on a rail. | 03-31-2016 |
| 20160098371 | SERIAL PERIPHERAL INTERFACE DAISY CHAIN COMMUNICATION WITH AN IN-FRAME RESPONSE - In one example, a master device connected in a serial-peripheral interface (SPI) daisy chain configuration with a plurality of servant devices, wherein the master device is configured to output a master data output to a first servant data input of a first servant device of a plurality of servant devices, wherein the plurality of servant devices are connected in a serial-peripheral interface (SPI) daisy chain configuration with the master device. The master device further configured to receive a master data input from a last servant device of the plurality of servant devices, wherein the master data input comprises an in-frame response of the plurality of servant devices, and wherein the in-frame response is received by the master device in a single SPI communication frame. | 04-07-2016 |
| 20160103773 | DYNAMICALLY ADDRESSABLE MASTER-SLAVE SYSTEM AND METHOD FOR DYNAMICALLY ADDRESSING SLAVE UNITS - A master-slave system includes a master unit having a digital output for providing a signal or a serial signal sequence of signals, and at least two slave units. Each of the slave units includes at least one digital serial memory having a size of one bit, and each slave unit includes an input and an output. The slave units are serially connected to one another via the inputs and the outputs via a signal line ( | 04-14-2016 |
| 20160103776 | TRANSACTION RESPONSE MODIFICATION WITHIN INTERCONNECT CIRCUITRY - Interconnect circuitry | 04-14-2016 |
| 20160117275 | APPARATUS AND METHODS FOR SERIAL INTERFACES - Apparatus and methods for serial interfaces are provided. In one embodiment, an integrated circuit operable to communicate over a serial interface is provided. The integrated circuit includes analog circuitry, registers for controlling the operation of the analog circuitry, and a distributed slave device including a primary block and a secondary block. The registers are accessible over the serial interface using a shared register address space. Additionally, the primary block is electrically connected to the serial interface and to a first portion of the registers and the secondary block is electrically connected to the primary block and to a second portion of the registers. | 04-28-2016 |
| 20160117282 | TWO MODES OF A CONFIGURATION INTERFACE OF A NETWORK ASIC - Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module. | 04-28-2016 |
| 20160124881 | CHIP SYNCHRONIZATION BY A MASTER-SLAVE CIRCUIT - A master-slave circuit is disclosed that maintains synchronization between two integrated circuit chips, using minimal chip resources. In one embodiment, a single, bidirectional communication path is shared by the two chips. Meanwhile, only one I/O port on each chip is used to send and receive signals via the bidirectional communication path. The first chip to detect a signal event is designated the master and controls the bidirectional communication path. The master can communicate the status to the other chip by controlling the logic state of the I/O ports. When the second chip detects that the I/O port is controlled by the first chip, the second chip will logically deduce that it is now the slave. If both chips detect the signal event at substantially the same time, one of the two chips is pre-programmed to assume control of the I/O port as the master. | 05-05-2016 |
| 20160124883 | Multicore Bus Architecture With Non-Blocking High Performance Transaction Credit System - This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process. | 05-05-2016 |
| 20160124892 | PREDEFINED STATIC ENUMERATION FOR DYNAMIC ENUMERATION BUSES - Predefined static enumeration systems and processes for dynamic enumeration buses are disclosed. In one aspect, the dynamic enumeration bus may be a SOUNDWIRE™ bus. Slave devices are provided predefined device numbers which are provided to a master. The master uses the provided predefined device number to populate an address table. By providing the predefined device numbers, an iterative enumeration process may be reduced or eliminated, saving time and/or power. | 05-05-2016 |
| 20160124896 | SIMULTANEOUS EDGE TOGGLING IMMUNITY CIRCUIT FOR MULTI-MODE BUS - A device is provided comprising a shared bus including a first and a second line, a first subset of devices and a second subset of devices coupled to the shared bus. The first subset of devices may be configured to operate according to a first protocol mode. The second subset of devices may be configured to operate according to a second protocol mode, wherein the second protocol mode is distinct from the first protocol mode. A first device within the first subset of devices may include a receiver circuit adapted to adjust a signal transition occurring on the first line while the second line is in a first logical state so that the signal transition instead occurs when the second line is in a second logical state. The signal transition is adjusted only if it occurs within a threshold amount of time from a second transition on the second line. | 05-05-2016 |
| 20160132441 | HETEROGENEOUS MULTIPROCESSOR PLATFORM TARGETING PROGRAMMABLE INTEGRATED CIRCUITS - An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller. | 05-12-2016 |
| 20160132451 | SYSTEM ON CHIP HAVING SEMAPHORE FUNCTION AND METHOD FOR IMPLEMENTING SEMAPHORE FUNCTION - A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result. | 05-12-2016 |
| 20160140065 | Register Access Control Among Multiple Devices - A circuit manages and controls access requests to a register, such as a control and status register (CSR) among a number of devices. In particular, the circuit selectively forwards or suspends off-chip access requests and forwards on-chip access requests independent of the status of off-chip requests. The circuit receives access requests at a plurality of buses, one or more of which can be dedicated to exclusively on-chip requests and/or exclusively off-chip requests. Based on the completion status of previous off-chip access requests, further off-chip access requests are selectively forwarded or suspended, while on-chip access request are sent independently of off-chip request status. | 05-19-2016 |
| 20160140066 | DISTRIBUTED TIMER SUBSYSTEM - A silicon device configured to distribute a global timer value over a single serial bus to a plurality of processing elements that are disposed on the silicon device and that are coupled to the serial bus. Each of the processing elements comprises a slave timer. Upon receipt of the global timer value, the processing elements synchronize their respective slave timers with the global timer value. After the timers are synchronized, the global timer sends periodic increment signals to each of the processing elements. Upon receipt of the increment signals, the processing elements update their respective slave timers. | 05-19-2016 |
| 20160140067 | SLAVE SIDE BUS ARBITRATION - A method includes, in response to a master port requesting bus access for a bus transfer with a slave port, selecting the master port to allow a master device that is coupled to the master port to perform a bus transfer with a slave device that is coupled to the slave port. The bus transfer is associated with at least one bus cycle. The method includes, in response to an end of the bus transfer, maintaining selection of the master port for at least one additional bus cycle. | 05-19-2016 |
| 20160140078 | Control device for I2C slave device - A method for controlling an I | 05-19-2016 |
| 20160147686 | SYNCHRONIZATION OF ELECTRONIC DEVICE WITH ANOTHER ELECTRONIC DEVICE ON BUS USING SYNCHRONIZATION FIELD - Various embodiments are described herein related to techniques for synchronizing a slave device to a master device that communicates using a unified bus communication protocol or some aspect thereof. In one example, the method may comprise assuming a first mode of operation for the unified bus communication protocol; searching for a synchronization pattern at one or more locations in transmitted data according to the first mode of operation; obtaining synchronization when the located synchronization pattern is verified according to at least one synchronization rule for the mode of operation; and if synchronization is not obtained based on the assumed first mode of operation, a second mode of operation for the unified bus communication protocol is assumed and the searching and obtaining acts are carried out on the transmitted data according to the second mode of operation. | 05-26-2016 |
| 20160147707 | BUS SERIALIZATION FOR DEVICES WITHOUT MULTI-DEVICE SUPPORT - A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support. | 05-26-2016 |
| 20160147708 | BUS SERIALIZATION FOR DEVICES WITHOUT MULTI-DEVICE SUPPORT - A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support. | 05-26-2016 |
| 20160154752 | DYNAMIC THREAD STATUS RETRIEVAL USING INTER-THREAD COMMUNICATION | 06-02-2016 |
| 20160170927 | ACCESS AND PROTECTION OF I2C INTERFACES | 06-16-2016 |
| 20160170930 | Low cost low overhead serial interface for power management and other ICs | 06-16-2016 |
| 20160170934 | DATA COMMUNICATION DEVICE AND METHOD FOR DATA COMMUNICATION | 06-16-2016 |
| 20160179726 | PROGRAMMING HARDWARE REGISTERS USING A PIPELINED REGISTER BUS, AND RELATED METHODS, SYSTEMS, AND APPARATUSES | 06-23-2016 |
| 20160188507 | ELECTRONIC DEVICE GROUP-COUPLING SYSTEM AND METHOD - An electronic device coupling system includes a master electronic device and a plurality of slave electronic devices which are each independently connected to the master. The master electronic device includes connecting module and identity module, the slave electronic device includes coupling module and identify module. The identity module stores identity information of each slave device and sends out serially all the identity information. The identify module confirms correspondence of the identity information to a selected slave device. The connecting module has a plurality of matching codes corresponding to each connecting port and each group address code. The master device can couple to a slave device when the identity information corresponds to a selected slave device. The coupling module is couplable to the connecting module according to the matching codes. An electronic device coupling method is further provided. | 06-30-2016 |
| 20160188509 | METHOD FOR AUTOMATICALLY MATCHING ELECTRONIC DEVICES - A method for group matching electronic devices includes entering a system for group matching, activating an automatic group matching mode of a master electronic device and generating a master automatic matching identification code, activating a group matching mode of a slave electronic device and generating a function software automatic matching code and a slave automatic matching identification code, sending out the master automatic matching identification code to the slave electronic device, writing the interface code of the master automatic matching identification code into the wireless module of the slave electronic device, setting up a function software of the master electronic device having the function software automatic matching code as the function software for controlling an operation of the slave electronic device, and completing the automatic matching between the wireless modules of the master and slave electronic devices. | 06-30-2016 |
| 20160188511 | COMPUTER SYSTEM AND COUPLING CONFIGURATION CONTROL METHOD - A computer system includes a switch having a plurality of ports, a plurality of devices coupled to the plurality of ports, and a management system coupled to at least one of the plurality of devices and the switch. The coupling between the plurality of devices and the switch is a communication interface in which the number of master devices capable of existing in the same space is defined. The management system collects device coupling data of each of the plurality of devices coupled to the switch. Each of the device coupling data includes an ID of a port to which the device is coupled and information representing an attribute indicating whether the device is a master or a slave. The management system determines a coupling configuration on the basis of the plurality of the collected device coupling data and a communication interface protocol and, configures, to the switch, coupling information that is information in accordance with the determined coupling configuration. | 06-30-2016 |
| 20160188512 | ELECTRONIC DEVICE COUPLING SYSTEM AND METHOD - An electronic device coupling system includes a master electronic device and a plurality of slave electronic devices. The master electronic device includes a connecting module. Each slave electronic device includes a coupling module. The connecting module includes a plurality of connecting ports. Each connecting port assembly has a plurality of group address codes corresponding to the slave devices and a plurality of matching codes corresponding to each connecting port and each group address code. The master device can be coupled to each slave device according to a group address code. The coupling ports are configured to couple to the connecting ports according to the matching codes. An electronic device coupling method is further provided. | 06-30-2016 |
| 20160196227 | SYSTEM ON CHIP (SoC), MOBILE ELECTRONIC DEVICE INCLUDING THE SAME, AND METHOD OF OPERATING THE SoC | 07-07-2016 |
| 20160196232 | Commissioning Method, Master Control Board, and Service Board | 07-07-2016 |
| 20160203092 | Method and Circuit Arrangement for Temporally Limiting and Separately Access in a System on a Chip | 07-14-2016 |
| 20160203093 | INTERCONNECT AND METHOD OF OPERATION OF AN INTERCONNECT | 07-14-2016 |
| 20160253279 | SYSTEM INCLUDING INTERFACE CIRCUIT FOR HIGH SPEED COMMUNICATION | 09-01-2016 |
| 20160254925 | BUS NODE AND BUS SYSTEM AND METHOD FOR IDENTIFYING THE BUS NODES OF THE BUS SYSTEM | 09-01-2016 |
| 20160378512 | CIRCUIT, METHOD, AND DEVICE FOR WAKING UP MASTER MCU - The present disclosure relates to a circuit that includes: a master microcontroller unit (MCU) having a clock line connected with a master clock signal; a peripheral interface chip; and a peripheral processing chip connected to the master MCU via the peripheral interface chip, wherein each of a clock line of the peripheral processing chip and a clock line of the peripheral interface chip is connected with a slave clock signal; wherein the peripheral processing chip is configured to remain working normally after the master MCU enters a deep sleep mode; and wherein the peripheral interface chip is configured to: remain working normally after the master MCU enters the deep sleep mode; monitor an amount of data sent by the peripheral processing chip to the peripheral interface chip; and send a wake-up signal to the master MCU when the amount of the data exceeds a threshold. | 12-29-2016 |
| 20170235688 | ACCESS CONTROL METHOD, BUS SYSTEM, AND SEMICONDUCTOR DEVICE | 08-17-2017 |
| 20170235697 | SYSTEM AND METHOD FOR ABSTRACTING SATA AND/OR SAS STORAGE MEDIA DEVICES VIA A FULL DUPLEX QUEUED COMMAND INTERFACE TO INCREASE PERFORMANCE, LOWER HOST OVERHEAD, AND SIMPLIFY SCALING STORAGE MEDIA DEVICES AND SYSTEMS | 08-17-2017 |
| 20170235699 | ARCHITECTURES AND METHODS FOR PROCESSING DATA IN PARALLEL USING OFFLOAD PROCESSING MODULES INSERTABLE INTO SERVERS | 08-17-2017 |
| 20190146939 | COMMUNICATION DEVICE, COMMUNICATION METHOD, PROGRAM, AND COMMUNICATION SYSTEM | 05-16-2019 |
