Class / Patent application number | Description | Number of patent applications / Date published |
710109000 | Bus polling | 15 |
20080270653 | Intelligent resource management in multiprocessor computer systems - In one embodiment, a computer system comprises at least a first processor core, at least one memory module coupled to the first processor core and the second processor core, the memory module comprising at least one application for execution by at least one of the first processor core, at least one resource manager to configure at least one component of the computer system according to at least one configuration parameter collected during a previous execution of the software application on the computer system. | 10-30-2008 |
20090089468 | COHERENT INPUT OUTPUT DEVICE - According to some embodiments, data to be exchanged via a system input output interface may be determined at a processor. It may then be arranged to exchange the data via a coherent input output device coupled to a coherent system interconnect. Other embodiments are described. | 04-02-2009 |
20090248931 | COMPUTER SYSTEM - A computer system is provided that can realize polling without increasing the processing burden on the processor. Data is read by a polling unit during a prescribed period from a prescribed address in the address space. Then, if the read data satisfies a prescribed condition, an interrupt signal is generated in the polling unit. Since processor can receive the interrupt from hardware instead of performing polling with firmware, the processing burden on processor | 10-01-2009 |
20090313409 | METHOD AND APPARATUS FOR MULTI-PHY COMMUNICATION WITHOUT AN ATM BUS MASTER - A communication system includes a bus, first and second devices coupled to the bus, and a handshaking unit. The bus includes at least one data line and control lines. The data line is coupled between the first and second devices. The handshaking unit is coupled to the control lines of the bus and is adapted to determine if the first and second devices are capable of completing a data transfer and enable the first and second devices to facilitate the data transfer. A method for interfacing first and second devices coupled to a bus is provided. The bus has at least one data line coupled to the first and second devices and control lines. The method includes determining if the first and second devices are capable of completing a data transfer based on the control lines; providing handshaking signals on the control lines to enable the first and second devices; and transferring the data over the data line in response to the handshaking signals. | 12-17-2009 |
20100088440 | DETECTING AND PREVENTING THE SPLIT-BRAIN CONDITION IN REDUNDANT PROCESSING UNITS - In an example embodiment the occurrence of the split-brain condition in a High-Availability system, having active and standby processing units, is detected, its cause is diagnosed, and the cause is treated to prevent interruption of service. Diagnosis and treatment procedures are performed at the active processing unit prior to being performed at the standby processing unit. | 04-08-2010 |
20110022755 | COMMUNICATION DEVICE, COMMUNICATION SCHEME DETERMINATION METHOD, AND PROGRAM - Provided is a communication device including a first communication unit that is capable of sending a polling-signal in a specific polling cycle and receiving a response-signal sent from a counterpart device in response to the polling-signal, based on a first scheme, a second communication unit that is capable of sending a polling-signal in a longer polling cycle than the first communication unit and receiving a response-signal sent from the counterpart device in response to the polling-signal, based on a second scheme, and a scheme determination unit that waits for reception of the response-signal by the second or the first communication unit for a specific period of time longer than the polling cycle of the second communication unit with a time of the response-signal being received by the first or the second communication unit as a reference, and determines a scheme usable by the counterpart device based on the reception result. | 01-27-2011 |
20120005384 | ACCESS CONTROL APPARATUS, ACCESS CONTROL METHOD AND STORAGE SYSTEM - An access control apparatus which establishes a connection based on connection establishment requests from connected devices and controls accesses to a connection target device. The access control apparatus includes a connection information managing unit which manages connect wait conditions to the connection target device of the connected devices based on criterion information in a connection request transmitted from the connected devices and determination for selecting one connected device from the connected devices. The access control apparatus includes a selecting unit which selects one of the connected devices which has a delay tendency related to connection based on adjustment information which is set in accordance with the connect wait conditions of the connected devices and increases a delay tendency in connection of the connected device, and a determining unit which determines the connected device selected by the selecting unit as one to be connected to the connection target device. | 01-05-2012 |
20130117482 | METHOD AND A SYSTEM FOR POLLING AND PROCESSING DATA - The embodiments herein provide a method and system for polling and processing data. The method comprises computing a maximum time from a source after a last update time, waiting for a preset time to ensure that all transactions with respect to a change in a data is completed, querying for a plurality of changes after an elapse of the preset waiting time since the last update time and up to the maximum time, generating a time window, collecting a list of changes occurred within the generated time window, sending the collected list of changes for processing; and updating the processed data at the destination. The time window comprises a time interval between the last update time and the maximum time. | 05-09-2013 |
20150120973 | METHOD FOR DETECTING RECEIVE END, DETECTION CIRCUIT, OPTICAL MODULE, AND SYSTEM - A method for detecting a receive end, a detection circuit, an optical module, and a system are provided, and relate to the field of optical communications. The method includes: transmitting a first detection code pattern to a PCI-E receive end through optical transmission, so that after receiving the first detection code pattern, the PCI-E receive end feeds back a second detection code pattern through the optical transmission; detecting whether the second detection code pattern fed back by the PCI-E receive end through the optical transmission is received; and determining that the PCI-E receive end is in position if a detection result is that the second detection code pattern fed back by the PCI-E receive end through the optical transmission is received. | 04-30-2015 |
20150293864 | SERIAL MEMORY DEVICE ALERT OF AN EXTERNAL HOST TO COMPLETION OF AN INTERNALLY SELF-TIMED OPERATION - In one embodiment, a method of performing an active polling operation can include: (i) detecting a self-timed operation that is to be executed on a serial memory device; (ii) determining if an active polling mode has been enabled; (iii) determining when the self-timed operation has completed execution on the serial memory device; and (iv) providing a completion indication external to the serial memory device when the self-timed operation has completed execution and the active polling mode is enabled. | 10-15-2015 |
20150331815 | NETWORK INTERFACE CARD RATE LIMITING - Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network appliance through a bus system. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are transmitted from the NIC to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing transmission of the received data packets from the NIC to the host CPU for processing. | 11-19-2015 |
20150370740 | Computing System With Unified Storage, Processing, And Network Switch Fabrics And Method For Making And Using The Same - A system and method for making and using a computing system with unified storage, processing, and network switch fabrics are provided. Processing nodes, either physical or virtual, are associated with intra-module ports, inter-module ports, and local storage spaces. A plurality of processing nodes are linked through intra-module ports to form processing modules. A plurality of the processing modules are further connected through inter-module ports to form the computing system. Several inter-module connection schemes are described, each of which can be adapted to use with existing network packet routing algorithms. Each processing node need only to keep track of the states of its directly connected neighbors, obviating the need for a high-speed connection to the rest processing nodes within the system. As a result, dedicated network switching equipment is not needed and network capacity grows naturally as processing nodes are added. | 12-24-2015 |
20160041933 | SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER IN A COMPUTER SYSTEM - A method of implementing a multi-threaded device driver for a computer system is disclosed. According to one embodiment, a polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted state, and changes the first state of the device to the scouted state. The driver thread further determines that the second device state of the device is in the inactive state and changes the second device state of the device to the active state. The driver thread executes an operation on the device during a pre-determined time slot configured for the driver thread. | 02-11-2016 |
20160179729 | INPUT/OUTPUT SWTICHING MODULE INTERFACE IDENTIFICATION IN A MULTI-SERVER CHASSIS | 06-23-2016 |
20180024963 | STAGED POWER ON/OFF SEQUENCE AT THE I/O PHY LEVEL IN AN INTERCHIP INTERFACE | 01-25-2018 |