| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710108000 | Bus locking | 15 |
| 20080228975 | DEVICE ADDRESS LOCKING TO FACILITATE OPTIMUM USAGE OF THE INDUSTRY STANDARD IIC BUS - A mechanism is provided for locking an end device for the period of time that the device is needed, thus disabling access by any other application or process. Having the device locked, rather than the bus, allows other applications to use the bus to access other devices at the same time. This is achieved by providing a virtual bus arbitration, which arbitrates applications' use of the physical bus. The virtual bus arbitration algorithms allow bus operations from different applications to overlap on the physical bus as long as their target devices and associated bus locks are on different end devices. | 09-18-2008 |
| 20080235419 | Integrated Circuit and Method of Securing Access to an On-Chip Memory - The integrated circuit comprises: —an on-chip access right manager ( | 09-25-2008 |
| 20080244130 | FLOW LOOKAHEAD IN AN ORDERED SEMAPHORE MANAGEMENT SUBSYSTEM - In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order. | 10-02-2008 |
| 20080270652 | System and method of tamper-resistant control - A method of tamper-resistant configuration control for a system, the method comprising reading a flag from a memory of an electronic device, the flag indicating an enable/disable state of at least one component device of the electronic device, setting a register in memory to a disable state for the at least one component device in response to the flag indicating a disabled state for the at least one component device, and locking the register. | 10-30-2008 |
| 20080276022 | Method to Resolve Deadlock in a Bus Architecture Comprising Two Single-Envelope Buses Coupled Via a Bus Bridge and Running Asynchronously - A method to resolve a deadlock in a bus architecture comprising a first and a second single-envelope bus with at least one master and one slave each, where the first and second single-envelope buses are arranged on different sides of an asynchronous boundary and are coupled via a bus bridge, said method comprising the steps of:
| 11-06-2008 |
| 20090164679 | DATA TRANSMISSION METHOD AND CORRESPONDING DEVICE - A method for transmitting data in packets between a first circuit element and a second circuit element includes sending the data by the first circuit element followed by a reception and a storage of the data by the second circuit element. A data transmission flow control operation detects an event signaling an imminent state of congestion of the data stored by the second circuit element. In response thereto, the control operation stops the sending of the data from the first circuit element to the second circuit element until a delay period expires and the event is no longer detected. | 06-25-2009 |
| 20090259784 | PERIPHERAL DEVICE LOCKING MECHANISM - A computing system having a host device and at least one client device having a lock used to prevent modification of data in the client device. A lock clear signal from the host device causes the client device to clear a lock used to prevent modification of data stored in at least a protected portion of the client device where the client device remains fully operational. | 10-15-2009 |
| 20100138574 | ELECTRONIC APPARATUS AND SIGNAL DISCONNECTION/CONNECTION METHOD - An electronic apparatus includes a first board that includes a first processor, a second board that is connected to the first board with a bus and that includes a second processor, and a disconnecting/connecting unit that, when the first board is in a first state in which power of the first processor is turned off and the second board is in a second state in which power of the second processor is turned on, disconnects a signal supplied via the bus between the first board and the second board. | 06-03-2010 |
| 20100299468 | Signal Termination Scheme for High Speed Memory Modules - A memory device is coupled to a subset of lines of a data input/output (I/O) bus. The memory device includes an on-die active termination circuit for terminating the subset of lines of the data I/O bus with a selected impedance being one of a plurality of selectable impedances; a termination value register being coupled to the on-die active termination circuit for storing a value representing the selected impedance; and a termination value setting circuit being coupled to the termination value register, for setting the value representing the selected impedance in the termination value register. | 11-25-2010 |
| 20110173356 | EXCLUSIVE ACCESS DURING A CRITICAL SUB-OPERATION TO ENABLE SIMULTANEOUS OPERATIONS - A method, apparatus, and system of exclusive access during a critical sub-operation to enable simultaneous operations are disclosed. In one embodiment, a method of a host device includes identifying a critical sub-operation of an operation associated with a storage system, applying a lock associated with the critical sub-operation based on a type of the sub-operation, providing exclusive access of the critical sub-operation to a first instance requiring the critical sub-operation, denying other instances access to the critical sub-operation during an interval comprising a period when the first instance executes the critical sub-operation, and releasing the lock when the critical sub-operation is no longer required by the first instance. The first instance and the other instances may originate on different host devices. | 07-14-2011 |
| 20120221754 | SYSTEM ON CHIP BUS SYSTEM AND A METHOD OF OPERATING THE BUS SYSTEM - A bus system of a system on chip (SoC) includes a first and a second masters, a first slave, and a first and a second control modules. The control modules generates a first and a second access control state signals in response to a first locking access preparation request signal from a corresponding master. The access control signals are broadcasted between the first and the second control modules through a communication channel. | 08-30-2012 |
| 20120311208 | METHOD AND SYSTEM FOR PROCESSING COMMANDS ON AN INFINIBAND HOST CHANNEL ADAPTOR - A method for processing commands on a host channel adapter includes a host channel adapter receiving data from a host connected to the host channel adapter. The command includes an instruction, identification of packet data, and a length field. The host channel adapter extracts a length of the command from the length field, generates a scoreboard mask based on the length, where the scoreboard mask includes unused bits in the scoreboard preset, and sets, with each portion of the data received, a corresponding bit in a scoreboard. The host channel adapter further determines that the size of the data received for the command matches the length using the scoreboard, issues a kick on the host channel adapter when a size of the data received for the command matches the length, executes, in response to the kick, the instruction on a pipeline, and sends the packet data on a network. | 12-06-2012 |
| 20150046614 | CENTRALIZED PERIPHERAL ACCESS PROTECTION - Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error. | 02-12-2015 |
| 20150331829 | SERVICE AND SYSTEM SUPPORTING COHERENT DATA ACCESS ON MULTICORE CONTROLLER - A system and method for accessing coherent data on a controller. The system and method include a first buffer and a second buffer that each may be read from or written to and an indicator that indicates which of the first or the second buffer is read from while the other of the first or second buffers is written to. The system and method also include a read synchronization protocol that allows the coherent data to be read from the buffer that the indicator indicates is the read buffer and a write synchronization protocol that allows the coherent data to be written to the buffer that the indicator indicates is the write buffer. | 11-19-2015 |
| 20160125205 | SESSION-LEVEL-RESTRICTION FOR UNIVERSAL SERIAL BUS STORAGE DEVICES - A system and method of implementing SLR for a USB device of an information handling system is disclosed herein. An OS may load a disk driver stack and a volume driver stack for the USB device, where the USB device is being enumerated by a first driver. The OS may load a second driver on the disk driver stack. The OS may also load second driver on the volume driver stack. The OS may restrict an access to the USB device at the second driver as loaded on the disk driver stack. Furthermore, the OS may restrict an access to a volume of the USB device at the second driver as loaded on the volume driver stack. | 05-05-2016 |
