| Entries |
| Document | Title | Date |
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| 20080209090 | System, method and apparatus for multiple-protocol-accessible OSD storage subsystem - An apparatus, system, and method enable access to a storage system by distinguishing SCSI Object-Based Storage Device Commands (OSD) commands from block-based SCSI commands on the same port and storage subsystem. The storage subsystem has the capability of identifying the storage protocol from a corresponding command, and processes the command accordingly for a storage device formatted for use with the respective storage protocol. This way, a storage subsystem can consolidate data from several dedicated command ports to a single physical port, while also enabling a single storage system to store and provide access to data in multiple different storage protocol formats. | 08-28-2008 |
| 20080228972 | Systems and methods for multiple mode voice and data communications using intelligenty bridged TDM and packet buses - Systems and methods by which voice/data communications may occur in multiple modes/protocols are disclosed. In particular, systems and methods are provided for multiple native mode/protocol voice and data transmissions and receptions with a computing system having a multi-bus structure, including, for example, a TDM bus and a packet bus, and multi-protocol framing engines. Such systems preferably include subsystem functions such as PBX, voice mail and other telephony functions, LAN hub and data router. In preferred embodiments, a TDM bus and a packet bus are intelligently bridged and managed, thereby enabling such multiple mode/protocol voice and data transmissions to be intelligently managed and controlled with a single, integrated system. A computer or other processor includes a local area network controller, which provides routing and hub(s) for one or more packet networks. The computer also is coupled to a buffer/framer, which serves to frame/deframe data to/from the computer from TDM bus. The buffer/framer includes a plurality of framer/deframer engines, supporting, for example, ATM and HDLC framing/deframing. The buffer/framer is coupled to the TDM bus by way of a switch/multiplexer, which includes the capability to intelligently map data traffic between the buffer/framer and the TDM bus to various slots of the TDM frames. Preferably, a DSP pool is coupled to buffer/framer in a manner to provide various signal processing and telecommunications support, such as dial tone generation, DTMF detection and the like. The TDM bus is coupled to a various line/station cards, serving to interface the TDM bus with telephone, facsimiles and other telecommunication devices, and also with a various digital and/or analog WAN network services. | 09-18-2008 |
| 20080228973 | MEMORY CARD HAVING PLURALITY OF INTERFACE PORTS, MEMORY CARD SYSTEM, AND DATA COMMUNICATION METHOD FOR THE MEMORY CARD - A memory card is disclosed including first and second host interfaces facilitating the communication of data between the memory card and a host using, respectively, first and second protocols, wherein the first protocol defines low-speed operations and the second protocol defines high-speed operations for the memory card. The second host interface is only enabled in response to an indication by the host device of a high-speed memory card operation. | 09-18-2008 |
| 20080235415 | Method and System for Modeling a Bus for a System Design Incorporating One or More Programmable Processors - Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload. | 09-25-2008 |
| 20080244127 | COMPUTER INTERFACE CONTROLLER FOR PORTABLE PLUG-AND-PLAY PERIPHERALS - The computer interface controller for portable plug-and-play peripherals of this invention comprises:
| 10-02-2008 |
| 20080244128 | Dynamic Run-Time Configuration Information Provision and Retrieval - A system employing a storage device and a host for configuration information exchange between the host and the storage device. In operation, the host manages host configuration information in a data management layer of a communication model, and communicates the host configuration information to the storage device by one or more data communication layers of the communication model. Likewise, the storage device manages storage device configuration information in the data management layer of the communication model, and communicates the storage device configuration information to the host by one or more data communication layers of the communication model. | 10-02-2008 |
| 20080250176 | ENHANCING PERFORMANCE OF SATA DISK DRIVES IN SAS DOMAINS - Methods and apparatus to enhance performance of Serial Advanced Technology Attachment (SATA) disk drives in Serial-Attached Small Computer System Interface (SAS) domains are described. In one embodiment, a data packets and/or commands communicated in accordance with SAS protocol may be converted into SATA protocol. Other embodiments are also described. | 10-09-2008 |
| 20080250177 | MEMORY DEVICE INCLUDING CONNECTOR FOR INDEPENDENTLY INTERFACING HOST AND MEMORY DEVICES - A memory device including a connector for independently interfacing a host and memory devices using a multimedia card (MMC) protocol is provided. The memory device includes an internal bus and a connector. The internal bus is configured to receive a command or data from the host via a plurality of input/output pins. The connector is electrically connected with the internal bus and connected with another memory device, which interfaces with the host through the internal bus using the MMC protocol. | 10-09-2008 |
| 20080270650 | SERIALIZATION OF DATA FOR MULTI-CHIP BUS IMPLEMENTATION - Bus communication for components of a system on a chip. In one aspect of the invention, a system includes a matrix operative to select destinations for information on buses connected to the matrix. A first serializer provided on a first device serializes information received from the matrix and sends the serialized information over a communication bus. A second serializer provided on a second device receives the serialized information and deserializes the serialized information, where the deserialized information is provided to a peripheral provided on the second device. | 10-30-2008 |
| 20080276019 | Data transport architecture - The present invention is a novel device, system, and method for data transport and bus architecture. According to an exemplary embodiment of the present invention, the bus architecture may comprise of a continuous serial bus that may be incorporated into a process control sample system to provide an intrinsically safe and efficient system. An alternative exemplary embodiment, in an intrinsically safe control sampling system, a data transport device may be used to couple sampling controls and analyzers. An exemplary embodiment of the present invention may contain an access controller providing a protocol bridge for an intrinsically safe control sampling system to couple sampling controls and analyzers. | 11-06-2008 |
| 20080282005 | METHOD AND PROCESSING UNIT FOR INTER-CHIP COMMUNICATION - The invention relates to an inter-chip communication protocol, based on a standard interface protocol, which is adapted to incorporate control, configuration and/or recovery information for computer chips, and the data encoded within communication packets of a communication layer above the physical layer of the interface protocol. | 11-13-2008 |
| 20080288683 | Method and system for managing a plurality of I/O interfaces with an array of multicore processor resources in a semiconductor chip - The present invention relates to a method and system for managing I/O interfaces with an array of multicore processor resources in a semiconductor chip. The I/O interfaces are connected to the processor resources through an I/O shim. An I/O interface sends a dataframe to the I/O shim. The I/O interface packetizes data to form the dataframe, based on an I/O protocol. The dataframe includes a header and the data. The I/O shim identifies a command corresponding to the dataframe by using one or more of the processor resources. The command includes a set of tasks. Subsequently, the set of tasks is executed on the data. | 11-20-2008 |
| 20080294819 | Simplify server replacement - There is provided techniques for automating attachment of a server to a storage area network (SAN). In accordance with one embodiment, a method is provided which includes storing identifiers in a memory associated with an enclosure adapted to house one or more servers. The identifiers are correlated to a particular location of the enclosure. Additionally, the method includes providing the identifiers from the memory to host bus adapters (HBAs) associated with a particular location when a server is placed in the particular location. | 11-27-2008 |
| 20080294820 | Latency dependent data bus transmission - In a system | 11-27-2008 |
| 20080301342 | Device Directed Memory Barriers - Efficient techniques for controlling synchronization of bus transactions to improve performance and reduce power requirements in a shared memory system are described. Interconnect arrangements in complex processing systems are also described that provide efficient data transfers between bus masters and shared memory devices to improve performance and reduce power use. In one example, a method for controlling synchronization of bus transactions to remote devices is addressed. A device directed memory barrier command is received. The device directed memory barrier command is decoded to determine one or more destination devices. A memory barrier command is selectively routed to the one or more destination devices in response to the decoding. The described techniques combine high speed device directed memory barrier capability, improved bus bandwidth functionality, and power saving features. | 12-04-2008 |
| 20080307131 | Method for Assigning Addresses to Nodes of a Bus System, and Installation - A method for assigning addresses to nodes of a bus system, and installation, bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery address via the bus system, (ii) the information includes a first address, (iii) an action is performed whose effect is detected by a first bus node, (iv) the first bus node accepts the first address, (v) the first bus node sends a response to the assigning entity, and (vi) steps (i) through (v) are repeated, each time with a further address for a further bus node. | 12-11-2008 |
| 20080313372 | Method of Receiving a Message Processable by a Component on One of Plurality of Processing Threads - There is disclosed a method, apparatus and computer program product for receiving a message, the message being processable by a component on one of a plurality of processing threads. A message is received from a first component on a current thread. The communication style that was used by the first component is determined. Responsive to receipt of the message, the communication style that is desired to be used by a second component is determined. Responsive to determining that the two components are asynchronous, communication takes place with the second component using the current thread. | 12-18-2008 |
| 20080320189 | Simple Serial Interface - method of communication and information exchange, and electronic devices based on this method. - A new simple serial interface method and device based on this method, which reduces the complexity of the existing universal serial bus (USB) interface, and allows fast and efficient data exchange, and quick development of hardware and software for this device. | 12-25-2008 |
| 20090013110 | CONNECTOR INTERFACE SYSTEM FOR ENABLING DATA COMMUNICATION WITH A MULTI-COMMUNICATION DEVICE - A connector interface system for a communication device is disclosed. The interface includes a docking connector. The docking connector includes first make/last break contacts that minimize internal damage to the internal electronics. The docking connector also includes specific keying arrangement to prevent noncompliant connectors from being plugged in, and thereby minimizes potential damage to the multi-communication device. The connector interface system also includes a remote connector which provides for the ability to output audio, input audio, provides I/O serial protocol, and to provide an output video. Embodiments of the present invention allow for a standard headphone cable to be plugged in but also for special remote control cables, microphone cables, video cables could be utilized in such a system. The connector interface system also includes a serial protocol to control device features. These controls help a user sort and search for data more efficiently within the device. | 01-08-2009 |
| 20090024774 | NETWORK BRIDGE DEVICE AND BUS RESET CONTROL METHOD THEREOF - A network bridge device for controlling IEEE 1394 bus reset includes an interface for receiving information relating to devices belonging to a foreign cluster, from the foreign cluster; and a controller for determining whether to reset a bus of a local cluster by comparing the received information with pre-stored information. Accordingly, the bus reset storming between the clusters can be prevented by selectively executing the bus reset of the cluster. | 01-22-2009 |
| 20090031063 | Data Processing System And Method - Embodiments of the present invention relate a data processing method comprising executing a first application on a first processor of a multiprocessor system and implementing, on the first processor, a first protocol stack supporting a first communication channel, bearing first communication data, associated with the first application; and executing a second application on a second processor of the multiprocessor system and implementing, on the second processor, a second protocol stack supporting a second communication channel, bearing second communication data, associated with the second application. | 01-29-2009 |
| 20090031064 | Information processing apparatus including transfer device for transferring requests - According to an aspect of an embodiment, an apparatus has a pair of first system boards, each of the first system boards including a processor and being adapted for sending duplicate requests, in parallel, respectively, a second system board including a processor and being adapted for sending requests, a first transfer device for transferring requests, having a first arbiter for selecting and outputting one of the duplicate requests sent from each of the first system boards, and a second arbiter for selecting and outputting one of the requests sent from the second system board and a second transfer device for transferring requests, having a third arbiter for selecting one of the duplicate requests sent from each of the first system boards and outputting the selected request in synchronization with the selected request outputted by the first arbiter, the second transfer device having a forth arbiter. | 01-29-2009 |
| 20090037627 | Flash memory with millimeter wave host interface and method for use therewith - A host interface module includes a millimeter wave transceiver that is coupled to wirelessly communicate read commands, write commands, read data and write data between a flash memory device and a host device over a millimeter wave communication path in accordance with a host interface protocol. A protocol conversion module is coupled to convert the read commands, the write commands and the write data from the host interface protocol and to convert the read data to the host interface protocol. A host module is coupled to decode the read commands and the write commands from the host device, to process the read commands to retrieve the read data from the flash memory and to process the write commands to write the write data to the flash memory. | 02-05-2009 |
| 20090055562 | SEMICONDUCTOR DEVICE WITH COPYRIGHT PROTECTION FUNCTION - A semiconductor device includes a serial communication interface connector, a non-volatile semiconductor memory, a memory controller, and a memory reader/writer. The serial communication interface connector is capable of being connected to a serial communication interface terminal of electronic equipment. The memory controller includes a memory interface connected to the non-volatile semiconductor memory and a copyright protection function and controls the non-volatile semiconductor memory. The memory reader/writer includes a controller interface connected to the memory controller and a serial communication interface connected to the serial communication interface connector. | 02-26-2009 |
| 20090055563 | Method for Providing Low-Level Hardware Access to In-Band and Out-of-Band Firmware - In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware. | 02-26-2009 |
| 20090063738 | Systems and Methods for Overriding Hardwired Responses in an HDA Codec - Systems and methods for overriding hardwired responses of a codec to High Definition Audio (HDA) verbs that are received from an HDA controller. In one embodiment, an HDA codec is configured to store one or more overriding responses, each of which is associated with a corresponding HDA verb. When an HDA verb is received by the codec, the codec determines whether the verb is associated with one of the overriding responses. If the verb is associated with one of the overriding responses, the overriding response is returned to the HDA controller. If the first HDA verb is not associated with one of the stored overriding responses, provide a hardwired response associated with the first HDA verb to the HDA bus. Overriding responses can be returned for unsupported verbs only, or for any verbs that prompt responses. | 03-05-2009 |
| 20090070504 | Multi-Protocol Bus Device - In one general aspect, methods and devices for use with multiple communications protocols automatically determine which communications protocol to use when connected to a system bus. Signals transmitted on the system bus are monitored to determine what communications protocol the system bus is using. After determining which communications protocol the system is using, a compatible communications protocol is selected from one of several communications protocols stored in a device's memory. As a result, a user may connect a device to the system bus without having to determine which communications protocol is used by the system bus. Furthermore, suppliers may stock a single type of device that is compatible with multiple communications protocols reducing overhead associated with stocking devices. In addition, a device may be switched between systems without regard to the communications protocol of the device or system. | 03-12-2009 |
| 20090083462 | METHOD FOR PROCESSING INFORMATION OF AN OBJECT FOR PRESENTATION OF MULTIPLE SOURCES - In case that a main component and an auxiliary component to be presented in synchronization with the main one have to be presented through data transmission between both devices, the present invention issues an action for setting access location information (e.g., URL) of at least one auxiliary component to a media renderer, wherein the action is different from an action for setting access location information of a main component. As a different way, the present invention sets access location information of at least one auxiliary component to a media renderer through an action including access location information of an auxiliary component as well as access location information of a main component. | 03-26-2009 |
| 20090083463 | Method for Transmitting Data From and to a Control Device - A method for transmitting data from and to a control device, in particular an engine control device for a motor vehicle that has a first communication interface and a second communication interface, the method having the following steps: connecting the first communication interface to a development tool, and connecting the second communication interface to one or more function units during the development phase of the control device, transmitting data from the control device to the development tool via the first communication interface using a first communication protocol, transmitting data from the development tool to the control device via the first communication interface using the first communication protocol, breaking the connection between the first communication interface and the development tool, connecting the first communication interface to one or more additional 20 function units, and transmitting data between the control device and the other function unit or function units via the first communication interface using a second communication protocol. | 03-26-2009 |
| 20090144470 | Method of transmitting ieee 1394 data over a wireless link and apparatus implementing the method - The invention relates to a method of transmitting data over a wireless link, comprising the insertion of the data into packets according to a format corresponding to at least certain layers of a first protocol for data transmission over a wireless network, as well as the use of these packets to form a frame in accordance with a second protocol for data transmission over a wireless network, different from the first protocol, and the transmission over the wireless network according to the second protocol. The invention also relates to the apparatus implementing the method. | 06-04-2009 |
| 20090157925 | Method for integrating device-objects into an object-based management system for field devices in automation technology - The invention relates to a method for integration of device-objects (DTM | 06-18-2009 |
| 20090157926 | COMPUTER SYSTEM, CONTROL APPARATUS, STORAGE SYSTEM AND COMPUTER DEVICE - A computer system which enables more efficient use of a storage system shared by plural host computers and optimizes the performance of the whole system including the host computers and storages. A computer device has a first control block which logically partitions computing resources of the computer device and makes resulting partitions run as independent virtual computers. The storage system has a second control block which logically partitions storage resources of the storage system and makes resulting partitions run as independent virtual storage systems. The system also has a management unit incorporating: a first control table which controls computing resources of the computer device; a second control table which controls storage resources of the storage system; and a third control table which controls the relations between the virtual computers and the virtual storage systems. The first control block logically partitions the computing resources according to the first control table; and the second control block logically partitions the storage resources according to the second control table. | 06-18-2009 |
| 20090177819 | INTEGRATED CIRCUIT CARDS INCLUDING MULTIPLE COMMUNICATION INTERFACES AND RELATED METHODS OF OPERATION - A multi-interface integrated circuit (IC) card includes a first communication interface configured to communicate with a host device in a first protocol mode, a second communication interface configured to communicate with the host device in a second protocol mode different than the first protocol mode, and a controller configured to detect a voltage supplied by the host device and a counter value associated therewith. The controller is configured to enable either the first interface or the second interface according to the detected voltage and the counter value. Related methods of operation are also discussed. | 07-09-2009 |
| 20090187690 | FEMTOCELL DEVICE - There is provided a femtocell device for communicating with one or more user devices in a communication network, the network having a plurality of subchannels available for transmissions, wherein the femtocell device is adapted to use a first subset of the plurality of subchannels for communicating with user devices that are in a closed subscriber group of the femtocell device and within a first area, and a second subset of the plurality of subchannels for communicating with other user devices. | 07-23-2009 |
| 20090193163 | System for connecting UPnP devices in a UPnP network - A system for connecting Universal Plug and Play UPnP devices in a UPnP network includes a generic UPnP control point for UPnP devices and, externalized to such UPnP control point, control logic of the devices. | 07-30-2009 |
| 20090204737 | Wireless universal serial bus system and driving method thereof - Disclosed is a wireless universal serial bus system that includes a device; a first host communicating with the device according to a wireless universal serial bus protocol; and a second host communicating with the device according to a wireless universal serial bus protocol, wherein when the first host receives a beacon from the second host, the first host provides new host information read out from the beacon to the device. | 08-13-2009 |
| 20090204738 | COMMUNICATION BETWEEN AN ACCESSORY AND A MEDIA PLAYER WITH MULTIPLE PROTOCOL VERSIONS - An interface and protocol allow a media player to communicate with external accessories over a transport link. The protocol includes a core protocol functionality and a number of accessory lingoes. Examples of accessory lingoes include a microphone lingo, a simple remote lingo, a display remote lingo, an RF transmitter lingo, and an extended interface lingo. | 08-13-2009 |
| 20090210592 | Network On Chip With A Low Latency, High Bandwidth Application Messaging Interconnect - A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus ( | 08-20-2009 |
| 20090210593 | SYSTEM AND METHOD FOR COMMUNICATION OVER A BUS - Systems and methods for communicating data over a communication bus are disclosed. In some aspects, the data is digital information communicated over a multiple-line bus connecting two or more electronic devices such as integrated circuits. The disclosure presents useful formats for arranging data into data cells communicated over the bus, and include some exemplary features as shared clock signals, Ready bit information, and vertical parity checking. | 08-20-2009 |
| 20090234996 | SYSTEM AND METHOD FOR DYNAMIC BANDWIDTH DETERMINATIONS - A system and method of determining bandwidth thresholds dynamically. Frames per second are measured at an interface. An effective throughput is measured at the interface. An average packet size is determined for a plurality of frames received at the interface. The average packet size being determined in response to the measured frames per second and the measured effective throughput. A threshold is determined for the effective throughput in response to the determined average packet size. A determination is made whether the effective throughput at the interface exceeds the threshold for the interface. A throughput rate communicated to the interface is adjusted in response to determining the effective throughput at the interface exceeds the threshold. | 09-17-2009 |
| 20090240855 | METHOD AND APPARATUS FOR CONTROL IN RECONFIGURABLE ARCHITECTURE - An apparatus and method for control in a reconfigurable architecture is shown and described. In one example, an integrated circuit configured to implement a plurality of communications standards includes a plurality of upper level controllers and a plurality of lower level controllers. The upper level controller are configured to operate according to a portion of a communications standard and implement upper level control functions for the associated standard. The low level controllers are capable of communicating with each of the upper level controllers and can be assigned to each of the upper level controls to implement low level functions of each of the plurality of communications standards. | 09-24-2009 |
| 20090240856 | VIRTUAL HOST ISOLATION AND DETECTION OF EMBEDDED OPERATIONAL FLIGHT PROGRAM (OFP) CAPABILITIES - The present invention relates to an object oriented architecture that includes a plurality of host aircraft interface objects that enable a plurality of different host aircraft or variants to be attached or interfaced to an associated store, such as a targeting pod or a weapon system. The union of all aircraft hosts and variants are packaged and maintained as one executable capable of adapting to the predetermined suite of identified hosts and host variants. At least one or more interface objects provide a virtual translation layer which is dynamically determined and allocated during instantiation. Auto detection of the host aircraft/host aircraft variant provides the specific interface protocol by which the store can process and provide status via a predetermined signal format. | 09-24-2009 |
| 20090248927 | INTERCONNECT BANDWIDTH THROTTLER - An interconnect bandwidth throttler is disclosed. The interconnect bandwidth throttler turns off the interconnect, based on whether a maximum number of transactions has take place within a predetermined throttle window. Both the maximum number of transactions and the throttle window are adjustable. | 10-01-2009 |
| 20090248928 | Integrating non-peripheral component interconnect (PCI) resources into a personal computer system - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 10-01-2009 |
| 20090259783 | LOW-POWER RECONFIGURABLE ARCHITECTURE FOR SIMULTANEOUS IMPLEMENTATION OF DISTINCT COMMUNICATION STANDARDS - A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols. | 10-15-2009 |
| 20090271547 | Target Discovery and Virtual Device Access Control based on Username - This invention is for discovery of a target such as iSCSI and virtual device access control based on a username and its synonyms. Since the same username can be entered from any initiator, the target discovery and virtual device access control will work from any initiator. In other words, this new method will be user-specific instead of being initiator-specific. | 10-29-2009 |
| 20090287864 | ELECTRONIC MODULE FOR PROGRAMMING CHIP CARDS COMPRISING CONTACTS - The invention relates to an electronic module for reading data on and/or writing data to at least one card-type carrier, in particular an electronic module of this type comprising a control unit for controlling at least one interface that can be connected to the card-type data carrier for receiving and/or sending the data. In one aspect, the electronic module according to the invention comprises at least one first interface which can be connected to the card-type data carrier for receiving and/or sending the data, and a control unit for controlling the first interface. The control unit is formed by an embedded PC which communicates with the first interface via a data bus. | 11-19-2009 |
| 20090300244 | MONITORING A CONNECTION IN A COMPUTER SYSTEM - Some embodiments of the present invention provide a system that monitors a connection in a computer system between a connector and a component coupled to the connector. During operation, a first motion parameter of the connector, and a second motion parameter of the component are measured. Then, the connection is monitored by comparing information related to the first motion parameter and information related to the second motion parameter. | 12-03-2009 |
| 20090300245 | Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 12-03-2009 |
| 20090313407 | DATA COMMUNICATION SYSTEM AND METHOD - A data communication system includes one or more data processing units and includes a central control unit. The decentralized data processing units are connected to the central control unit by data connection. The central control unit includes a synchronisation unit for outputting via the data connection an electric synchronisation signal to the data processing unit. The data processing unit includes a data generator for generating data and transmitting, after the electric synchronisation signal, data to the central control unit. The central control unit further includes a discharge signal generator for outputting a discharge signal via the data connection to the data processing unit. | 12-17-2009 |
| 20090313408 | BUS CONTROL DEVICE - A bus control device includes a multiplexer which connects a ROM controller to a common bus when a ROM mode is set and which connects a PCI controller to the common bus when a PCI mode is set. The bus control unit further includes a bus switch which disconnects a PCI bus from the common bus when the ROM mode is set and which connects the PCI bus to the common bus when the PCI mode is set. | 12-17-2009 |
| 20090327542 | Arrangement of Components - An arrangement for transferring message based communications between separate disjunctive components. The arrangement includes at least two components. At least a first component is arranged to provide services to at least one second component and/or to an operator of the loosely coupled system. At least one message bus is arranged to perform real-time transfers of communications from/to the at least one first component to/from the at least one second component. The at least one message bus is connected to or integrated in an internal communication backbone arranged with a communication member for establishing outgoing communication links. A predetermined message based interface is arranged relative to each of the components and the at least one message bus such that all communications between the at least one first component and the at least one second component are defined in the same single standardized message language. A method for providing components in the arrangement and a platform including the arrangement. | 12-31-2009 |
| 20090327543 | Protocol Method Apparatus and System for the Interconnection of Electronic Systems - Disclosed are methods, apparatus, and systems for the interconnection of electronic system apparatus having one or more different communication protocols. A preferred embodiment is disclosed in which a single physical interface and a single protocol are used for providing an efficient and scalable interconnection between a host and operably coupled subsystem apparatus connected to the MMC. In a disclosed method, a bus is provided for coupling a system host to a plurality of system components and a Multi-Management Protocol (MMP) is employed. The Multi-Management Protocol includes a plurality of subclasses, each further including component identity information and function data. The subclasses are grouped by functionality into at least two groups comprising a standard group and an extension group. In a multi-component electronic system according to the invention, an electronic protocol packet structure includes a starting frame delimiter, a length field, a target address field, a subclass identifier, an operation identifier, a data field, and a frame check field. Disclosed preferred embodiments also include protocol conversion apparatus having a Multi-Management Controller (MMC) using a host bus for transmitting and receiving data between a host and the MMC based on a Multi-Management Protocol (MMP). | 12-31-2009 |
| 20090327544 | DISPATCH CAPABILITY USING A SINGLE PHYSICAL INTERFACE - An apparatus, system and method for performing dispatch operations using a signal physical interface are disclosed. In one embodiment, the apparatus is for use in a wireless communication system for communicating with a wireless network and comprises a host processor, a transceiver, a physical interface coupling the host processor and the transceiver, and a memory accessible by the host processor and the transceiver to exchange information between the host processor and the transceiver. The transceiver is operable to store data in the memory for the host processor to send data to the host processor using the memory and asserts a control signal to the host processor to notify the host processor that the memory contains data for the host processor, and the host processor is operable to access the memory to obtain the data thereafter. The data is associated with a remote device in the wireless network and is stored as one or more packets at a first storage location in the memory with a first identifier identifying the remote device. | 12-31-2009 |
| 20090327545 | METHOD FOR TRANSMITTING A DATUM FROM A TIME-DEPENDENT DATA STORAGE MEANS - A method of transmitting a datum from a time-dependent data storage means, the datum being that most recently acquired before the occurrence of an allocated transmission slot; the method comprising the steps of: writing a first acquired datum to a first side of the data storage means; transferring the first datum to a second side of the data storage means; and writing a next datum, acquired before the occurrence of the next allocated transmission slot, to the first side of the data storage means; wherein the method further comprises the step of: replacing the first acquired datum in the second side of the data storage means with the next acquired datum; and transmitting the next acquired datum from the data storage means at the next allocated transmission slot. | 12-31-2009 |
| 20100005205 | Device For Processing A Stream Of Data Words - State of the art processor systems, esp. in embedded systems, are not able to process data under real-time conditions especially with throughput rates near 10 Gbps. So, when using interfaces like PCI Express (PCIe) or Infiniband or 10G-Ethernet for 10 Gbps data throughput, special data-paths have to process the high throughput rate data. But tasks like connection management or time uncritical control messaging are better manageable by a processor. According to the invention it is proposed a kind of multiplexer architecture that is needed to split between control and data-path access for a PCI Express based architecture. | 01-07-2010 |
| 20100011137 | Method and apparatus for universal serial bus (USB) command queuing - A method and apparatus for improving performance of mass storage class devices accessible via a Universal Serial Bus (USB) is presented. Performance is improved by providing support in a USB host to allow command queuing and First-Party DMA (FPDMA) to be supported in the mass storage class devices. | 01-14-2010 |
| 20100017550 | METHOD AND SYSTEM FOR DATA TRANSMISSION BETWEEN DUAL PROCESSORS - A method and system for data transmission between dual processors are provided. The dual processors include a first processor and a second processor with a controller and a point-to-point protocol (PPP) module. The method includes sending a connection instruction from the first processor to the PPP module, transmitting network configurations from the PPP module to the first processor, and a protocol stack shared by the first processor and the second processor for establishing a connection between the first processor and the PPP module, the protocol stack comprising a new PPP (NPPP) layer, and transmitting data to the PPP module through the connection between the first processor and the second processor. | 01-21-2010 |
| 20100030935 | Modbus Register Data Reformatting - A Modbus data protocol register formatting system and method are disclosed. The system and method provide for the Modbus communications protocol request and recall of data stored in a register in the data base native format, and the conversion of the data into a different requested format. The system and method similarly provide for the writing of data into a device register from a known variable format into the data base native format. The ability to convert the data by a format converter after recalling the data, or before storing the data, obviates the need to store or write data in different or multiple formats. The inventive method uses a modified register mapping that comprises defined mapping elements identifying the data address location, the requested data format, along with the data variable. The register mapping is fully variable to provide for a wide range of data formats and data address formats. The inventive system uses, in addition to the Modbus master and slave devices, a format converter that converts the data recalled into the requested data format, or converts the data to be written into the slave device native data format. | 02-04-2010 |
| 20100064080 | MANAGING PCI-EXPRESS MAX PAYLOAD SIZE FOR LEGACY OPERATING SYSTEMS - The present disclosure is directed to a method for balancing latency versus bandwidth trade-offs in packet transmission utilizing PCI-Express. The method may comprise identifying at least one system element along a path of a packet to be transmitted; determining and storing an optimum payload size for each one of the at least one system element; configuring a Max Payload Size parameter for each one of the at least one system element, wherein the Max Payload Size parameter is configured based on the optimum payload size for each one of the at least one system element. | 03-11-2010 |
| 20100082860 | SYSTEM AND METHOD FOR UPDATING THE STATUS OF AN ASYNCHRONOUS, IDEMPOTENT MESSAGE CHANNEL - The present invention provides systems and methods for an abstraction layer for an asynchronous, idempotent message channel useful for performing status updates between communicating processes via a protocol that reduces overhead. The system comprises a sink endpoint that is operative to send a status message, a data path that is operative to transmit the status message over a message channel, a source endpoint that is operative to receive the status message sent by the sink endpoint over the data path, and an abstraction layer that is operative to provide an interface between the sink endpoint and the source endpoint over the message channel, relaying the status message from the sink endpoint to the source endpoint according to an optimized algorithm. | 04-01-2010 |
| 20100088439 | INTELLIGENT CASE FOR HANDHELD COMPUTER - An intelligent case for a handheld computer, the case including a compartment for removably housing the handheld computer; a microcontroller; a first communication device to enable communication between the handheld computer and the microcontroller; one or more recesses for housing one or more data-capture modules; and a second communication device to enable communication between the data-capture modules and the microcontroller; wherein the microcontroller includes: a module manager adapted to handle activation of the data-capture modules, collection of data from the data-capture modules, and communication of the collected data to the hand-held computer; and a first set of applications for controlling, in a first mode, at least some operations of the module manager independently of the handheld computer. | 04-08-2010 |
| 20100095034 | BUS-CONNECTED DEVICE WITH PLATFORM-NEUTRAL LAYERS - A bus-connected device includes a data storage element, a physical layer and a controller. The data storage element stores user data and multiple adaptations for multiple platform protocols. The physical layer uses at least a portion of a selected one of the multiple platform protocols to access the user data. The controller controls and communicates with the data storage element using a controller communication protocol that is neutral relative to the multiple platform protocols. | 04-15-2010 |
| 20100115165 | Data Communications Among Electronic Devices Within A Computer - Data communications among electronic devices within a computer, including transmitting, from a transmitting device to a first translation device, data communications encoded according to an unreliable wireline data communications protocol; translating, by the first translation device, the data communications from the encoding of the unreliable wireline data communications protocol to an encoding of a reliable wireless data communications protocol; transmitting, by the first translation device to a second translation device, the data communications according to the reliable wireless data communications protocol; translating, by the second translation device, the data communications from the encoding of the reliable wireless data communications protocol to the encoding of the unreliable wireline data communications protocol; and transmitting, by the second translation device to a receiving device, the data communications according to the unreliable wireline data communications protocol. | 05-06-2010 |
| 20100121999 | Generating of a Device Description for a Measuring Device - A method for generating a device description for a measuring apparatus in a target field bus protocol is described. The method comprises the reception of a first device description of the apparatus. The first device description of the apparatus comprises at least one variable. The at least one variable is related to a storage cell of the apparatus. The target field bus protocol is selected from a plurality of field bus protocols, and at least one block is formed from the at least one variable. The at least one block has a maximum block size that corresponds to the smallest maximum block size of at least two field bus protocols of the plurality of field bus protocols. The maximum block size can be transmitted via a field bus with a single request when the respective field bus protocol is used. Subsequently, the at least one block is provided as device description for the apparatus in the target field bus protocol. | 05-13-2010 |
| 20100131686 | Method and System for Secure Transmission of Process Data to be Transmitted Cyclically - The invention relates to a method and system for secure transmission of process data to be transmitted cyclically in a cyclical data transmission to be performed protocol-specifically via a transmission channel between a user functioning as a master and at least one user functioning as a slave that are connected to the transmission channel. Within a transmission protocol frame, a time slot that can always accommodate the same number of bits independently of the data to be transmitted is assigned to each slave during a data transmission cycle. For safety-relevant process data that is to be transmitted during a data transmission cycle from a slave to at least one additional user, or that is to be transmitted during a data transmission cycle from a user to at least one slave, additional first protection data for recognizing error-free transmission of this safety-relevant process data is generated and transmitted in each case. | 05-27-2010 |
| 20100146169 | Bus-handling - A processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive and a communication port adapted to receive signals from external units over a bus, which is configured to be not fully operative when the processor is in the sleep state. The processor additionally includes a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission started while it was in the sleep state. | 06-10-2010 |
| 20100146170 | Differentiating Traffic Types in a Multi-Root PCI Express Environment - Mechanisms for differentiating traffic types in a multi-root PCI Express environment are provided. The mechanisms generate a first mapping data structure that, for each single-root virtual hierarchy in the multi-root data processing system, associates a plurality of traffic classes with a plurality of priority groups and maps each traffic class in the plurality of traffic classes to a corresponding virtual channel in a plurality of virtual channels. Moreover, a second mapping data structure is generated that maps each virtual channel in the plurality of virtual channels to corresponding virtual link in a plurality of virtual links of the multi-root data processing system. Traffic of a particular priority group is routed from a single-root virtual hierarchy to a particular virtual link in the plurality of the virtual links based on the first mapping data structure and second mapping data structure. | 06-10-2010 |
| 20100161859 | System and method for separating information and signal communications - A communication system is disclosed for communicating data among a plurality of electronic modules. The communication system may include a data type classifier configured to separate the data into information-type data and signal-type data. The communication system may further include a first communication stack configured to communicate the information-type data among the plurality of electronic modules. The communication system may also include a second communication stack configured to communicate the signal-type data among the plurality of electronic modules. The first communication stack and the second communication stack may share a physical data link. | 06-24-2010 |
| 20100169524 | DEVICE CONTROL METHOD AND PROGRAM RECORDED MEDIUM ON WHICH THE METHOD IS RECORDED - Detecting an input source of a signal of a device connected to a bus and determining whether the signal is converted, extracted, multiplexed, or processed. Efficiently controlling the connection of each unit connected on the bus. Issuing a command for detecting the output plug or source plug as the signal source. The unit or subunit receiving this command shows the signal source. Obtaining information showing whether a subunit is present in the unit or not. | 07-01-2010 |
| 20100185799 | System and Method for Security Configuration - A system and method for accessing and identifying the security parameters of a device in an information handling system is disclosed. A device in a computer system may operate according to a defined security protocol, and multiple security protocols may exist across the devices of the system. In operation, a configuration capability is defined within the PCI Express communications protocol. This capability includes a capabilities data structure through which parameters concerning the security parameters of the device may be identified and passed to a processor. | 07-22-2010 |
| 20100191882 | COMMUNICATION SYSTEM AND PROTOCOL - A communication system and protocol that permits a first device to communicate a plurality of messages in a predetermined order to a user of the first device, where the plurality of messages, their content, and their predetermined order need not be known to the first device until the messages are provided to the first device by a second device. The user of the first device is permitted to move backward or forward through the messages in the predetermined order while utilizing a minimal amount of resources of the first device, such as processor power and memory. | 07-29-2010 |
| 20100199004 | COMMUNICATION METHOD IN A MRI SYSTEM - In a method of communication on a multidrop bus of a magnetic resonance system, an adaptive protocol script for telegrams on the multidrop bus is used, that implements adaptive protocol matching using telegram start characters, addresses and frame-type binding. For this purpose, a telegram frame is divided into a link layer and a service layer, the link layer being device-based and being responsible for differentiating addresses and frame types, and enabling devices that use different communication protocols to be simultaneously present on the bus. The service layer represents the load of the link layer, and its service script is operation-based, and the service layer provides, for the exterior, interfaces that are independent of the communication protocols used by the devices. | 08-05-2010 |
| 20100205337 | DIGITAL DEVICE INTERCONNECT SYSTEM - A simple clock source synchronous DDR data transfer mechanism may be combined with static bus state signaling to replace a complex bus (e.g. USB) with an easy to implement digital serial interconnect bus. This may eliminate various pull-up/pull-down resistors required in USB, and enable the interconnect bus to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The interconnect bus may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The digital serial interconnect bus may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features. | 08-12-2010 |
| 20100228899 | CHANNEL ACTIVATING METHOD AND PERIPHERAL DEVICE PERFORMING THE SAME - A channel activating method and a peripheral device are provided for activating a serial transmission channel to retrieve at least one firmware instruction from a host. The peripheral device includes a serial transmission port coupled to the host, a microprocessor coupled to the serial transmission port for performing functions of the peripheral device according to the firmware instruction, a memory for holding the firmware instruction, a trigger generator for generating a trigger signal by monitoring a control signal received from the host via the serial transmission port, and a signal generator, coupled to the trigger generator, for generating an indication signal to the host via the serial transmission port according to the trigger signal to activate the serial transmission channel. | 09-09-2010 |
| 20100262733 | PROTOCOL-BASED BUS TERMINATION FOR MULTI-CORE PROCESSORS - A multi-core bus termination apparatus includes a protocol analyzer and a plurality of drivers. The protocol analyzer is disposed within a processor core and configured to receive one or more protocol signals, and is configured to indicate whether or not the processor core owns the bus. The plurality of drivers is coupled to the protocol analyzer. Each of the plurality of drivers has one of a corresponding plurality of nodes, and each is configured to control how the one of the corresponding plurality of nodes is driven responsive whether or not the processor core owns the bus. Each of the plurality of drivers has protocol-based multi-core logic. The protocol-based multi-core logic is configured to enable pull-up logic if the processor core owns the bus, and is configured to disable the pull-up logic if the processor core does not own the bus. | 10-14-2010 |
| 20100268860 | Methods for Generating Display Signals in an Information Handling System - An information handling system (IHS) is provide for generating display signals associated with an alternative display protocol. The system may include a display protocol receptacle operable to receive a display protocol plug and a display bus switch in communication with the display protocol receptacle. The system may also include a display converter in communication with the IHS. The display converter may include a first end having a display connector associated with an alternative display protocol and a second end having a display protocol plug. Moreover, upon receipt of the display protocol plug by the display protocol receptacle, the display bus switch may output display signals associated with the alternative display protocol. | 10-21-2010 |
| 20100281195 | Virtualization of a host computer's native I/O system architecture via internet and LANS - A hardware/software system and method that collectively enables virtualization of the host computer's native I/O system architecture via the Internet and LANs. The invention includes a solution to the problems of the relatively narrow focus of iSCSI, the direct connect limitation of PCI Express, and the inaccessibility of PCI Express for expansion in blade architectures. | 11-04-2010 |
| 20100281196 | MANAGEMENT DEVICE OF HARDWARE RESOURCES - A management device for managing states of components. The management device includes a reading unit to read management information from each of plural components; a determining unit to refer to license information associated with management information of each component stored in a license storage unit, and to determine, based on the referred license information, whether each component is usable or not; and an operation control unit to make a component determined to be usable operate but to inhibit an operation of a component determined to be unusable. | 11-04-2010 |
| 20100293310 | DATA PROCESSING UNIT, CONTROL METHOD THEREFOR AND PROGRAM - A data processing unit to that reliably avoids a deadlock condition regardless of status of a ring bus occupied with normal data packets. The data processing unit comprises ring bus, a plurality of data processing units connected to the ring bus, for mutually performing data exchange using a packet circulated on the ring bus and a injection unit for injecting a special packet distinguished from the packet on the ring bus so as to circulate the special packet on the ring bus, wherein the plurality of data processing units respectively comprise for confirming whether or not a transmission destination data processing unit of the data is capable of receiving data by using the special packet, and a transmission unit for transmitting the data to the transmission destination data processing unit using the special packet. | 11-18-2010 |
| 20100299466 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Power supply of ECUs connected to a communication network is optimally controlled so that power consumption is reduced. A transceiver/receiver converts a message of a differential signal received via a CAN bus into a digital signal. A select circuit determines whether the converted message is in a CAN format or a UART format. If it is in the UART format, the select circuit outputs a message to the UART circuit. A UART circuit determines whether the message matches a UART format. If matched, an ID determination circuit determines whether the input message is specifying a CAN ID of its own ECU. If it is the CAN ID of the ECU, the ID determination circuit outputs an enable signal to turn on a regulator and supply power to an MCU and an actuator. | 11-25-2010 |
| 20100299467 | STORAGE DEVICES WITH SECURE DEBUGGING CAPABILITY AND METHODS OF OPERATING THE SAME - A device includes a first bus, a second bus, a processor configured to communicate with a storage circuit through the first bus and to communicate with a debug host through the second bus and a control circuit configured to inhibit transfer of data from the second bus to the debug host while receiving authentication information from the debug host and to enable transfer of data from the second bus to the debug host responsive to authentication of the received authentication information. The control circuit may be configured to inhibit data transfer from the second bus to the debug host by causing dummy data to be transmitted to the debug host over a transmit channel between the device and the debug host. | 11-25-2010 |
| 20100306429 | System and Method of Signal Processing Engines With Programmable Logic Fabric - A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits. | 12-02-2010 |
| 20100318702 | Automated system and control device for identifying a connecting element - The invention relates to an automated system ( | 12-16-2010 |
| 20100318703 | DELEGATING NETWORK PROCESSOR OPERATIONS TO STAR TOPOLOGY SERIAL BUS INTERFACES - An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner. | 12-16-2010 |
| 20100318704 | UNIVERSAL SERIAL BUS (USB) TO DIGITAL VIDEO - This document discusses, among other things, a system and method for switching serialized video information (e.g., non-packet-based video information) and Universal Serial Bus (USB) information (e.g., packet-based information) to a common output (e.g., to a physical USB interface). | 12-16-2010 |
| 20100332704 | SEMICONDUCTOR DEVICE AND SERIAL INTERFACE CIRCUIT - The serial interface circuit can adapt to various frame formats readily and reduces the load on CPU owing to serial interface. The interface circuit includes a rewritable control register used for programmably specifying a field structure to be targeted for processing out of structures of fields before a data field of a frame defined by a communication protocol. The inter face circuit analyzes the field structure before the data field according to a setting of the control register. Only when a destination of a received frame is judged to match an expected value, the inter face circuit issues a request for having CPU process the data field information. After a setting is made on the control register, the serial interface circuit can readily adapt to various formats of frames defined by a communication protocol according to the information held there, and can even analyze a destination. | 12-30-2010 |
| 20100332705 | GROUP MASTER COMMUNICATION SYSTEM AND METHOD FOR SERIALLY TRANSMITTING DATA IN AUTOMATION SYSTEMS - A communication system and method are disclosed for serially transmitting data in automation systems. In at least one embodiment, the system includes a base module as the system master, a plurality of extension modules as the slaves and a bidirectional communication connection that serially connects the base module to the extension modules. A status as group master for the serially subsequent extension module is allocated to at least two of the extension modules, the base module communicating with the extension modules depending on said allocation. | 12-30-2010 |
| 20110010475 | METHOD AND DEVICE FOR LOGGING PROCESS VARIABLES OF A DIGITAL FIELD DEVICE - A method and an electronic device are provided for logging process variables of a bus-controlled automation system in which process variables which are relevant to evaluation are buffered in at least one digital field device and are subsequently read, for the purpose of evaluation, by a central computer unit which is connected to the field device via a data bus. Process variable values which are relevant to evaluation are buffered in the field device in the form of a message, a plurality of equidistantly successive process variable values are recorded as messages, where the first process variable value is assigned a time stamp recorded for each message, and further process variable values are stored in further identical messages. | 01-13-2011 |
| 20110022752 | METHOD FOR TRANSMITTING DATA IN A CYCLE-BASED COMMUNICATION SYSTEM - In a method for transmitting data from a transmitting user of a cycle-based communication system to a receiving user of the communication system, the data are transmitted via a communication medium in messages that repeat in communication cycles and that respectively include a plurality of data blocks. The receiving user identifies the end of the data blocks in the received messages and subsequently extracts the transmitted data from the identified data blocks. | 01-27-2011 |
| 20110035520 | MOTHERBOARD FOR SELECTING ONE OF SUB-SYSTEMS IMMEDIATELY - A motherboard for selecting one of sub-systems immediately includes a plurality of sub-systems, a shared/control unit, and an input/output unit. The plurality of sub-systems individually has a corresponding kernel unit, a corresponding interface control unit and a corresponding power circuit. According to an external selecting signal, the shared/control unit selects a corresponding sub-system to be the target sub-system, so that the target sub-system can control all the shared peripherals. | 02-10-2011 |
| 20110066774 | PROCESSING SYSTEM WITH RF DATA BUS AND METHOD FOR USE THEREWITH - A processing system includes a plurality of first circuit modules. A plurality of second circuit modules are coupled to an RF data bus via a 60 GHz communications. The RF data bus receives first data from at least one of the plurality of first circuit modules, and transmits the first data via 60 GHz communications to at least one of the plurality of second circuit modules. | 03-17-2011 |
| 20110066775 | Communication Between a Media Player and an Accessory with an Extended Interface Mode - An interface and protocol allow a media player to communicate with external accessories over a transport link. The protocol includes a core protocol functionality and a number of accessory lingoes. Examples of accessory lingoes include a microphone lingo, a simple remote lingo, a display remote lingo, an RF transmitter lingo, and an extended interface lingo. | 03-17-2011 |
| 20110066776 | Communication Between a Media Player and an Accessory with an Extended Interface Mode - An interface and protocol allow a media player to communicate with external accessories over a transport link. The protocol includes a core protocol functionality and a number of accessory lingoes. Examples of accessory lingoes include a microphone lingo, a simple remote lingo, a display remote lingo, an RF transmitter lingo, and an extended interface lingo. | 03-17-2011 |
| 20110078349 | BUS-PROTOCOL CONVERTING DEVICE AND BUS-PROTOCOL CONVERTING METHOD - A bus-protocol converting device includes: a command detecting unit that detects a command sent from an external-memory control device, connected to a primary bus, to a primary bus interface controller; a command converting unit that converts the detected command into a command to be sent from a secondary bus interface controller to an external memory device through a secondary bus; a status detecting unit that detects a status sent from the external memory device; a status converting unit that converts the detected status into a status to be sent from the primary-bus interface controller to the external-memory control device through the primary bus; and a data transfer controller that is provided between the primary bus interface controller and the secondary bus interface controller to perform data transfer between the external-memory control device and the external memory device through a DMA bus. | 03-31-2011 |
| 20110087812 | MULTI-MASTER BI-DIRECTIONAL I2C BUS BUFFER - Systems and methods are disclosed that promote communication in an I2C Bus. These systems and methods can include at least two groups, wherein each of the two groups comprise at least one I2C communication units, and wherein each of the I2C communication units within a group are coupled together. These systems and methods can also comprises a connector that creates a connection between at least two groups of units and controls the flow of data by altering at least one signal that is transmitted between the at least two groups. | 04-14-2011 |
| 20110087813 | SYSTEM AND METHOD OF SENDING AND RECEIVING DATA AND COMMANDS USING THE TCK AND TMS OF IEEE 1149.1 - A system and method that use the TCK and TMS to transmit address and data. IEEE 1149.1 based tools can use the system and method without modification to make IEEE 1149.1 TAPs appear and disappear, add compliance-enable circuits without pins and broadcast commands to IEEE P1687 instruments. The system and method use Test-Logic-Reset sequences with Run-Test-Idle to enable an on/off switch of various DFT capabilities. IEEE 1149.1 compliant TAP interfaces disappear to pass-through wires using the system and method. The sequences communicate an “address” which enables one or more of the TAP interfaces and a “command”. The system and method has benefits for IEEE P1687 instrument chains and on-chip routing of the P1687 network. | 04-14-2011 |
| 20110093632 | METHOD FOR TRANSMITTING DATA FROM AND TO A CONTROL DEVICE - A method for transmitting data from and to a control device, in particular an engine control device for a motor vehicle that has a first communication interface and a second communication interface, the method having the following steps: connecting the first communication interface to a development tool, and connecting the second communication interface to one or more function units during the development phase of the control device, transmitting data from the control device to the development tool via the first communication interface using a first communication protocol, transmitting data from the development tool to the control device via the first communication interface using the first communication protocol, breaking the connection between the first communication interface and the development tool, connecting the first communication interface to one or more additional 20 function units, and transmitting data between the control device and the other function unit or function units via the first communication interface using a second communication protocol. | 04-21-2011 |
| 20110093633 | ASYMMETRICAL SERIAL COMMUNICATIONS - In some embodiments a Universal Serial Bus cable includes a first differential pair to transmit bus signals, and a second differential pair to transmit bus signals in a same direction as the bus signals transmitted by the first differential pair. In this manner, a bandwidth of the Universal Serial Bus cable is doubled in that same direction. Other embodiments are described and claimed. | 04-21-2011 |
| 20110099309 | POWER SUPPLY CIRCUIT FOR CPU - A power supply circuit includes a PWM controller capable of providing pulse signals to a CPU, and an I/O controller electrically coupled to the PWM controller and the CPU respectively. The I/O controller is capable of receiving voltage selection signals from the CPU and outputting a control signal to the PWM controller. The PWM controller is capable of adjusting pulse signals provided to the CPU according to the control signal. | 04-28-2011 |
| 20110125940 | COMMUNICATION SYSTEM HAVING A CAN BUS AND A METHOD FOR OPERATING SUCH A COMMUNICATION SYSTEM - A communication system and a method for operating a communication system, the communication system having a CAN bus and at least two devices connected with the aid of the CAN bus. Such a device has a CAN control unit, an asynchronous, serial communication (ASC) interface unit, and a switch. The CAN control unit is suitable for transmitting, in a first transmission mode, CAN data frames over the CAN bus with the aid of a first physical protocol. The asynchronous, serial communication interface unit or ASC interface unit is suitable for transmitting, in a second transmission mode, ASC data frames over the CAN bus with the aid of a second physical protocol. The switch is designed for switching over between the first transmission mode and the second transmission mode as a function of at least one agreement effective between the device and at least one other device. | 05-26-2011 |
| 20110125941 | METHOD AND INTEGRATED CIRCUIT FOR PROVIDING ENCLOSURE MANAGEMENT SERVICES UTILIZING MULTIPLE INTERFACES AND PROTOCOLS - A method and integrated circuit for providing enclosure management services compatible with a multitude of physical interfaces and protocols for exchanging enclosure management data between an HBA and an enclosure management backplane is provided. According to one method, two or more interfaces utilized for exchanging enclosure management data may be monitored to determine whether one of the interfaces is actively being utilized by an HBA to transmit enclosure management data. If one of the interfaces is identified as being active, a determination is then made as to which of a plurality of protocols for transferring enclosure management data is being utilized on the active interface. In particular, a determination may be made as to whether a protocol defined by one HBA manufacturer is being utilized or whether another protocol defined by another HBA manufacturer is being utilized. Alternatively, a determination may be made as to whether one of a multitude of different protocols defined by the same manufacturer is being utilized. Once the interface and protocol have been identified, enclosure management data received on the active interface is decoded utilizing the identified protocol. | 05-26-2011 |
| 20110131356 | METHOD AND SYSTEM FOR HIGH-SPEED DETECTION HANDSHAKE IN UNIVERSAL SERIAL BUS BASED DATA COMMUNICATION SYSTEM - A USB system includes a USB hub, a USB device, and a USB bus interconnecting the USB hub and the USB device. The USB hub asserts a reset signaling on the USB bus to initiate a high-speed detection handshake. The USB hub and the USB device activate corresponding dual-mode squelch detectors in a first (handshake) mode of operation. The USB device transmits a device chirp signal to the USB hub. The USB hub responds with a sequence of hub chirp signals. The USB device detects the hub chirp signals and then the USB hub and the USB device establish a communication link in a high-speed mode of communication in accordance with USB 2.0. The dual-mode squelch detectors in the USB hub and the USB device can also be activated in a second (normal) mode of operation. | 06-02-2011 |
| 20110161536 | METHOD FOR HIGH SPEED DATA TRANSFER - A method for transferring data between a data source and a data sink which are controlled by a common clock provides a handshake-based streaming data protocol for intra-circuitry data transfer between and through functional units of a system built in an integrated circuit. | 06-30-2011 |
| 20110167182 | TRANSPORT PRIORITIZATION BASED ON MESSAGE TYPE - A system for controlling message transmission in an apparatus. Messages pending for transmission in an apparatus may be analyzed in order to determine a type for each message. The type determined for each message may then be utilized to select a transport set comprising one or more transports. The apparatus may select a transport from the transport set and may then transmit the pending messages using the selected transport. | 07-07-2011 |
| 20110185090 | Apparatus for Translating and Expanding Inputs for a Point Of Sale Device - An apparatus includes a PS2 input for receiving first input logic signals from a first device. A USB input receives second input logic signals from a second device. A RS232 input receives third input logic signals from a third device. A TTL input receives fourth input logic signals from a fourth device. A programmed logic circuit translates the first input logic signals, the second input logic signals, the third input logic signals and the fourth input logic signals to first output logic signals having a RS232 output. The programmed logic circuit further translates the first input logic signals, the second input logic signals, the third input logic signals and the fourth input logic signals to second output logic signals having a TTL output. A RS232 output transmits the first output logic signals to a POS device and a TTL output transmits the second output logic signals to a POS device. Input Ports for logic signals may be distinct in cases where a signal translation function is sought. Input Ports for logic signals may also be repeated for the same input logic where an expansion function is sought. | 07-28-2011 |
| 20110208884 | COMMUNICATION APPARATUS, RELAY APPARATUS, COMMUNICATION SYSTEM AND COMMUNICATION METHOD - It is expected to provide a communication apparatus, relay apparatus, communication system and communication method for effectively performing a communication timing adjustment when a collision has occurred on a communication line, efficiently reducing the communication collision with reducing processing loads on each apparatus, for making each apparatus effectively perform the transmission timing adjustment, and for improving the communication efficiency. ECUs are connected to communication lines with a bus topology. A relay apparatus is connected to the communication lines, obtains a time distribution based on a number of messages transmitted to the communication lines. When the bias occurs in the transmission timings, the relay apparatus transmits an instruction message that instructs to perform the timing adjustment for messages transmitted between the ECUs. In addition, it is determined whether a message to be relayed is held. When it is determined that such a message is held, the instruction message is transmitted. | 08-25-2011 |
| 20110219154 | ABSTRACT PROTOCOL INDEPENDENT DATA BUS - An abstraction layer (e.g., transport) between consumer logic (e.g., presentation) and provider logic (e.g., business) that makes composition of, for example, many presentation technologies to many business logic data providers possible without imposing strict interface boundaries to each. The abstraction layer can be an abstract transport data model bus that provides serialization, transformation, and transport services. A core concept of the data access library implementation is a transmittable data object based on a flexible property bag data structure and abstract type system. Pluggable data providers declare the associated data model, and pluggable consumer clients declare the data model consumed (a many-to-many implementation). In other words, declarative (codeless) combinations of front ends and back ends are employed. Moreover, the abstraction layer is hidden from the developer. | 09-08-2011 |
| 20110219155 | PROCESSING SYSTEM AND METHOD FOR TRANSMITTING DATA - A method for exchanging data between first and second functional units includes the following steps. In a first handshake procedure, data is exchanged corresponding to a communication thread selected by the first functional unit, while independently in a second handshake procedure, information relating to a status of at least one communication thread is exchanged from the second to the first functional unit. The information enables the first functional unit to anticipate the possibility of exchanging data for the at least one communication thread. | 09-08-2011 |
| 20110252168 | Handling Atomic Operations For A Non-Coherent Device - In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed. | 10-13-2011 |
| 20110252169 | Method for Data Exchange - Method for data exchange via a bus system (BS), | 10-13-2011 |
| 20110271021 | Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 11-03-2011 |
| 20110276734 | USB Dedicated Charger Identification Circuit - In an embodiment, set forth by way of example and not limitation, a USB dedicated charger identification circuit includes a USB D+ port, a USB D− port, a first circuit conforming to a first identification protocol, a second circuit conforming to a second identification protocol, and logic selectively coupling one of the first circuit and the second circuit to the USB D+ port and the USB D− port. In an alternate embodiment set forth by way of example and not limitation, a method to provide USB charger identification includes providing a first USB charger identification at a USB D+ port and a D− port. Next, it is detected if the first USB charger identification was inappropriate. Then, if the first USB charger identification was inappropriate, a second USB charger identification is provided at the USB D+ port and the D− port. | 11-10-2011 |
| 20110283027 | Automation Appliance and Method for Accelerated Processing of Selected Process Data - An automation appliance ( | 11-17-2011 |
| 20110302342 | SMART CARD SET PROTOCOL OPTIMIZATION - A method of facilitating communications between a computer device and a smart card reader having an associated smart card, the computer device including a smart card resource manager and a smart card reader service, the smart card reader service acting as a relay for commands between the smart card resource manager and the smart card reader, the method comprising: receiving from the smart card resource manager a first command for setting a protocol for communications with the smart card; and responding, prior to receiving a reply from the smart card to the first command, to the smart card resource manager with a message indicating that the smart card has successfully received the first command. | 12-08-2011 |
| 20110314195 | MAGNETIC RESONANCE APPARATUS WITH A DATA TRANSFER UNIT TO TRANSFER DATA BETWEEN A MEASUREMENT SYSTEM AND AN EVALUATION SYSTEM, AND A TRANSFER METHOD THEREFOR - A magnetic resonance apparatus has at least one basic magnet that generates a basic magnetic field, a measurement system that is arranged within a region permeated by the basic magnetic field, an evaluation system that is arranged outside of the region permeated by the basic magnetic field, and a data transfer unit to transfer data between the measurement system and the evaluation system. The data transfer unit has at least one USB standard unit along a transmission path of the data transfer between the measurement system and the evaluation system. | 12-22-2011 |
| 20110320655 | Adapter for physically interfacing between an accessory and a device - Circuits, methods, and apparatus that provide compatibility among incompatible accessories and portable media players. One example provides an adapter having a connector receptacle to mate with an accessory's connector insert and a connector insert to mate with a portable media player's connector receptacle. Another example provides an adapter having a direct connection between pins on the connector insert and pins on the connector receptacle that are used for compatible signals. Another example provides an adapter including a DC-to-DC converter that receives a first power supply from an accessory and provides a second power supply to a portable media player. Another translates signals using different signaling technologies. Authentication and identification circuitry may also be included. Other examples may employ wireless technologies instead of either or both the connector insert and connector receptacle. | 12-29-2011 |
| 20120005382 | Register Access Protocol - A system and a method are disclosed for allowing a host device to communicate with an accessory device using a lightweight communications protocol. A communications link is first established between the connected accessory and host device. The host device sends a request for a register map file (RMF) to the accessory device. A RMF identifies registers for elements of the accessory device. The accessory device sends the RMF to host device, responsive to the request and the host device maps the RMF to interface with a higher level language such as C++ or JavaScript, allowing the host to act on the register mapping. Such interaction can be handled at the driver layer of an operating system, the application framework layer or the application layer. This permits both a layered service model and a fine-grant access at the application layer of the host device. | 01-05-2012 |
| 20120005383 | SYSTEM AND A METHOD FOR CONSTRUCTING AND DECONSTRUCTING DATA PACKETS - A packet processing data path is attached to the processor bus as a slave via a bus interface. The packet processing data path comprises a number of blocks. Respective blocks comprise configuration registers operable to provide information on what operation the blocks should perform for the current packet field being processed. The bus interface comprises a first register operable to control a bus of Update Enable signals, which bus is also connected to the blocks. The bus interface also comprises a second register operable to control a Mode signal, which is also connected to the blocks. An Update Mode signal is connected to the bus interface and to the blocks. A write to the second register causes the Update Mode signal to be pulsed active, triggering the enabled configuration registers to update their values. | 01-05-2012 |
| 20120036295 | CONTROLLED DEVICE - The controlled device includes: an external terminal; a memory; a processor for controlling the memory according to a control signal received via the external terminal; a plurality of buses forming a first transmission path connecting the external terminal and the memory via the processor, and a second transmission path connecting the external terminal and the memory directly by bypassing the processor; and a switching unit for switching a transmission state to either a first transmission state in which one or more of the buses forming the first transmission path are caused to transmit the control signal from the external terminal to the processor according to a first protocol, or a second transmission state in which one or more of the buses forming the second transmission path are caused to transmit data directly between the external terminal and the memory according to a second protocol capable of transmitting data at a higher rate than the first protocol. | 02-09-2012 |
| 20120036296 | INTERCONNECT THAT ELIMINATES ROUTING CONGESTION AND MANAGES SIMULTANEOUS TRANSACTIONS - A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect. The flow control logic for the interconnect applies a flow control splitting protocol to permit transactions from each initiator thread and/or each initiator tag stream to be outstanding to multiple channels in a single aggregate target at once, and therefore to multiple individual targets within an aggregate target at once. The combined flow control logic and flow control protocol allows the interconnect to manage simultaneous requests to multiple channels in an aggregate target from the same thread or tag at the same time. | 02-09-2012 |
| 20120066422 | METHOD AND SYSTEM FOR TRANSFERRING HIGH-SPEED DATA WITHIN A PORTABLE DEVICE - A system for high-speed data transfer within a portable device, such as, cell phone or a set-top box, which includes a memory medium and a processor. The system includes a first port for coupling to the processor, and a second port for coupling to the memory medium. Further, the system includes an embedded Universal Serial Bus (USB) host configured for receiving data transfer commands from the processor, and transferring data at high speed between a USB device on the processor and the memory medium. Moreover, a data path is provided between the embedded USB host and the first port. | 03-15-2012 |
| 20120079145 | ROOT HUB VIRTUAL TRANSACTION TRANSLATOR - Systems and methods of operating root hub host controllers provide for determining, at a protocol engine having a dedicated port, a speed of a device in response to a coupling of the device to the dedicated port. Data transfer can occur at a second speed between software interface logic of the host controller and the protocol engine, and at the first speed between the protocol engine and the device via the dedicated port, wherein the second speed is greater than the first speed. In addition, data may be transferred in unicast transactions in which no split tokens are exchanged. | 03-29-2012 |
| 20120079146 | METHOD AND ARRANGEMENT FOR STREAMING DATA PROFILING - A circuit arrangement includes a plurality of functional units each of which comprises a plurality of data processing modules and a local controller. The plurality of data processing modules run a common system clock and are connected by a streaming data bus running a handshake-type streaming data transfer protocol. A profiling module of the circuit arrangement assesses control signals tapped at predefined interfaces of the streaming data bus during real time operation, for determining link performance and communication patterns for profiling and debugging purposes, and hence constitutes a simple and low cost approach for assessing intra-component and inter-component link performance and communication patterns on large SoCs. A method for profiling data flow for use in such a circuit arrangement is also provided. | 03-29-2012 |
| 20120084473 | METHOD AND BUS SYSTEM FOR EQUALIZING DATA INFORMATION TRAFFIC AND DECODER - In the field of integrated circuit (IC) design, a method and a bus system for equalizing data information traffic and a decoder are provided. The method includes: receiving data information sent by a device, and allocating at least two transmission interfaces for the data information according to a decoding result of decoding a designated bit in the data information, where the data information carries a device ID, and the designated bit position occupied at least one bit in the device ID; judging whether the data information traffic of the at least two transmission interfaces is balanced; and when the data information traffic of the at least two transmission interfaces is not balanced, switching the designated bit position, and decoding the designated bit after switching, so as to balance the traffic of the at least two transmission interfaces. The bus system includes an interface allocation module, a traffic judging module and a bit position switching module. The decoder includes a decoding module and a designated bit position switching module. | 04-05-2012 |
| 20120096199 | BUS SYSTEM INCLUDING ID CONVERTER AND CONVERTING METHOD THEREOF - A bus system includes a plurality of master devices each of which issues a transaction request having a first transaction identifier with a first bit width and a slave device responding to the transaction request having a second transaction identifier with a second bit width and supplying a transaction response having the second transaction identifier to the plurality of master devices. The embodiment further comprises a bus configured to connect one of the plurality of master devices and the slave device; and an ID converter configured to connect the bus and the slave device and to map the first transaction identifier to the second transaction identifier for providing the second transaction identifier to the slave device and map the second transaction identifier to the first transaction identifier for providing the first transaction identifier to the one of the plurality of master devices. | 04-19-2012 |
| 20120110229 | SELECTIVE SWITCHING OF A MEMORY BUS - A memory bus with a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch between the first bus segment and the second bus segment. The control logic outputs control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in the length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to increase the length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate. | 05-03-2012 |
| 20120117284 | CONFIGURABLE 2-WIRE/3-WIRE SERIAL COMMUNICATIONS INTERFACE - A configurable 2-wire/3-wire serial communications interface (C23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. In response to detecting the SOS, the SOS detection circuitry provides an SOS detection signal to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal. The received sequence is associated with one of multiple serial communications protocols. | 05-10-2012 |
| 20120124256 | METHOD FOR DETERMINISTIC SAS DISCOVERY AND CONFIGURATION - The present invention is directed to a method for deterministic Serial Attached Small Computer System Interface (SAS) discovery and configuration. The method includes transmitting a Serial Management Protocol (SMP) DISCOVER Request from a node of a SAS domain to each expander of the SAS domain. The method further includes receiving SMP DISCOVER Responses at the node from each expander of the SAS domain. The method further includes comparing BROADCAST (CHANGE) RECEIVED (BCR) counts provided in each of the received SMP DISCOVER Responses to stored BCR counts, said stored BCR counts having been recorded and stored by the node prior to said transmitting of said SMP DISCOVER Request. The method further includes updating the stored BCR counts based upon said received BCR counts. The method further includes selectively transmitting a second SMP DISCOVER Request from the node to at least one, but not all of the expanders of the SAS domain. | 05-17-2012 |
| 20120131244 | Encoding Data Using Combined Data Mask and Data Bus Inversion - A data encoding scheme for transmission of data from one circuit to another circuit combines DBI encoding and non-DBI encoding and uses a data mask signal to indicate the type of encoding used. The data mask signal in a first state indicates that the data transmitted from one circuit to said another circuit is to be ignored, and the data mask signal in a second state indicates that the data transmitted from one circuit to said another circuit is not to be ignored. If the data mask signal is in the second state, a first subset of the data is encoded with data bus inversion and a second subset of the data is encoded differently from data bus inversion. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data is transmitted from one circuit to another circuit. | 05-24-2012 |
| 20120137031 | COMMUNICATION BUS WITH SHARED PIN SET - Bus communications are effected. In accordance with one or more example embodiments, a bus circuit is configured for communicating data in accordance with a main protocol (e.g., as a default), and for communicating with an alternate protocol when signals corresponding to the main protocol are not present. In some implementations, a sense circuit is used with input pins to sense a type of signal for bus communications, and to control communications on the bus with a protocol appropriate for the sensed signals, and for a main protocol when main protocol signals are sensed (e.g., for a default bus operation, or for test operation). | 05-31-2012 |
| 20120144078 | SINGLE WIRE BUS SYSTEM - There is provided a single wire bus architecture comprising a single wire bus; a master device coupled to the single wire bus; at least one slave device coupled to the single wire bus; a communication protocol implemented over the single wire bus and employed by the master device and the at least one slave device; wherein when one of the at least one slave devices wishes to communicate with the master device, the one of the at least one slave devices discharges the clock signal during a tri-state stage of the clock signal; and wherein the single wire bus transmits a clock signal, power and data between the master device and the one of the at least one slave device in communication with the master device. | 06-07-2012 |
| 20120166691 | In band dynamic switching between two bus standards - In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed. | 06-28-2012 |
| 20120166692 | COMMON PROTOCOL ENGINE INTERFACE FOR A CONTROLLER INTERFACE - A signal transmission system includes a controller interface, a protocol engine to convert data based on at least one protocol, and a common protocol interface coupled between the controller interface and the protocol engine. The controller interface includes or is coupled to a common dispatcher, and the data is to be transmitted between the controller interface and protocol engine through the common protocol interface and common dispatcher. The same protocol engine may convert data into different protocols, with all of the converted data be transmitted to or received from the controller interface through the common dispatcher and common protocol interface. | 06-28-2012 |
| 20120166693 | Intelligent Asset Management System - A system and method of associating the identification of a server with its physical location thorough the use of an asset management strip and asset management tags. The asset management strip is extendable by means of slave asset management strips. The asset tags are attached to data center components, such as servers, in racks. They are removably attached to the asset strip and provide identification information to the asset strip. The asset strip can correlate the identification information with the location where the tag attaches to the strip. The strip provides the rack identity to management software over a network, which includes an indication of a vertical location on the rack of the component and the component identification data. | 06-28-2012 |
| 20120185626 | METHOD AND APPARATUS FOR DIVIDING A SINGLE SERIAL ENCLOSURE MANAGEMENT BIT STREAM INTO MULTIPLE ENCLOSURE MANAGEMENT BIT STREAMS AND FOR PROVIDING THE RESPECTIVE BIT STREAMS TO RESPECTIVE MIDPLANES - A controller is provided that receives a single enclosure management (EM) serial bit stream from an expander or other device and divides the EM serial bit stream into multiple EM serial bit streams for delivery to multiple respective midplanes or backplanes. In this way, a separate EM serial bit stream is provided to each midplane or backplane without having to increase the number of ports that are available on the expander or other device that interfaces with the backplane or midplane. | 07-19-2012 |
| 20120203943 | RADIO COMMUNICATION DEVICE AND METHOD FOR CONTROLLING RF-BB STATE IN THE SAME - A radio communication device enabling a serial interface to restart transmission in a short time when interface setting is changed, as well as a method for controlling RF-BB state in the device, are provided. According to the radio communication device in which a radio frequency section (20) and a baseband section (10) are connected through a serial interface, exclusive signals (Act, Act_Ack) for triggering an interface state change and for acknowledging it are provided between the radio frequency section and the baseband section, respectively. Interface state change control is performed by transmitting and receiving the interface state change trigger exclusive signal and its acknowledgement exclusive signal between the radio frequency section and the baseband section. | 08-09-2012 |
| 20120226835 | PCI Express to PCI Express based low latency interconnect scheme for clustering systems - PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between external systems, such that the scalability can be applied to enable data transport between connected systems to form a cluster of systems is proposed. These connected systems can be any computing or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture. | 09-06-2012 |
| 20120233366 | Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 09-13-2012 |
| 20120239838 | Safety Arrangement - A monitoring system including a first and a second portion. The first portion includes a controller for providing a set of codes. The first portion is configured to connect the system to a common data bus. The first portion is configured to provide a synchronisation signal to the second portion when the two portions are in a predetermined position. The second portion includes a controller for replaying a code sequence to the first portion and the first portion being further configured to output said code sequence from the second portion for verification by a verification entity. | 09-20-2012 |
| 20120239839 | Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 09-20-2012 |
| 20120271975 | DEFINITION OF WAKEUP BUS MESSAGES FOR PARTIAL NETWORKING - A method of encoding a digital bus message information, in particular a wake-up bus message information or configuring data, on a bus system, the method comprising: encoding a predetermined part of digital bus message information bits by means of sub-patterns in a stream of line symbols on at least one bus line, wherein sub-patterns consist of successive dominant and recessive phases, comprised of recessive and dominant line symbols, wherein a recessive phase is comprised of at least two recessive line symbols in order to establish a ratio of successive dominant and recessive phases that corresponds to a value of the predetermined part. A respective digital bus message, particularly for use on a bus system, is to be encoded in accordance with the method. | 10-25-2012 |
| 20120278520 | SYSTEM AND METHOD OF TRANSMITTING DATA BETWEEN DEVICES CONNECTED VIA A BUS DEFINING A TIME SLOT DURING TRANSMISSION FOR RESPONSIVE OUTPUT INFORMATION FROM BUS DEVICES - A device and method are provided in which the data to be transmitted is transmitted in units together with information concerning the transmission and/or the use of the data. At least some of the units include at least one region which defines a time slot within which freely selectable devices can output onto the bus data representing freely selectable information at freely selectable points in time. | 11-01-2012 |
| 20120297100 | STORAGE SYSTEM AND DATA TRANSMISSION METHOD - A storage system and a data transmission method are disclosed in embodiments of the present invention. According to embodiments of the present invention, a storage system contains a master node, and auxiliary nodes at different physical positions, for example, a short-distance auxiliary node and a long-distance auxiliary node, and for auxiliary nodes at different physical positions, different protocols are adopted for data transmission, for example, data is transmitted between the master node and the short-distance auxiliary node by using a SAS protocol through a SAS cable, while data is transmitted between the master node and the long-distance auxiliary node by using a protocol that supports serial long-distance transmission through an optical fiber or a serial cable, thereby minimizing the cost when long-distance data transmission can be implemented. | 11-22-2012 |
| 20120311205 | MESSAGE FLOW REROUTING FOR SELF-DISRUPTING NETWORK ELEMENT - A method, apparatus, and machine readable storage medium is disclosed for establishing a test protocol processor which intercepts success path protocol messages at a network element port buffer and substitutes a failure path message to simulate the introduction of unexpected protocol messages into the protocol message flow from an external source to the network element under test. The disclosed self disrupting network element is particularly useful for providing a means to perform in situ field testing of a network element. | 12-06-2012 |
| 20120311206 | FACILITATING PROCESSING IN A COMMUNICATIONS ENVIRONMENT USING STOP SIGNALING - Processing, such as debug and/or recovery processing, within a communications environment is facilitated. Responsive to detecting an event, a stop signal is propagated through a communications network of the communications environment, and each network element that receives the stop signal, transmits the signal to its neighbors (if any), and then performs an action depending on its specific programming. The action can be to take no action, perform a debugging action or perform a recovery action. The elements that receive the signal and perform the same action as other elements form a coordinated network providing a coordinated result. | 12-06-2012 |
| 20120331192 | MANAGEMENT DATA TRANSFER BETWEEN PROCESSORS - A method for transferring management data between processors over an Input/Output (I/O) bus system ( | 12-27-2012 |
| 20130019037 | BATTERY MANAGEMENT SYSTEMS WITH VERTICAL BUS CIRCUITSAANM Flippin; AllanAACI BrentwoodAAST CAAACO USAAGP Flippin; Allan Brentwood CA USAANM Densham; WilliamAACI Los GatosAAST CAAACO USAAGP Densham; William Los Gatos CA USAANM Goh; Jiun HengAACI SunnyvaleAAST CAAACO USAAGP Goh; Jiun Heng Sunnyvale CA USAANM Bucur; ConstantinAACI SunnyvaleAAST CAAACO USAAGP Bucur; Constantin Sunnyvale CA USAANM Lupu; FlaviusAACI San JoseAAST CAAACO USAAGP Lupu; Flavius San Jose CA USAANM Maireanu; StefanAACI SunnyvaleAAST CAAACO USAAGP Maireanu; Stefan Sunnyvale CA US - A battery management chip may include a battery management unit and a vertical bus circuit. The battery management unit can monitor a cell status of multiple cells in a battery module coupled to the battery management chip in response to an instruction from a host processor. The vertical bus circuit may transfer the instruction from the host processor to the battery management unit. The vertical bus circuit may include a first receiver, a command processor and a first transmitter. The first receiver can receive a first pair of differential input data signals. The command processor can process the first pair of differential input data signals. The first transmitter can output a first pair of differential output data signals. | 01-17-2013 |
| 20130019038 | MULTIPLE SLIMBUS CONTROLLERS FOR SLIMBUS COMPONENTS - Methods, systems, apparatuses, and computer-readable media for controlling components connected to and/or otherwise associated with a data bus are presented. According to one or more aspects of the disclosure, a plurality of processing devices having data bus management capability and at least one data bus associated with the plurality of processing devices may be identified. Subsequently, an inter-processor communication (IPC) layer for communication between the plurality of processing devices and the at least one data bus may be established over a messaging layer utilized by the at least one data bus. At least one component associated with the at least one data bus may then be controlled via the IPC layer using at least one of the plurality of processing devices. | 01-17-2013 |
| 20130019039 | SYSTEM AND METHOD FOR OPERATING A ONE-WIRE PROTOCOL SLAVE IN A TWO-WIRE PROTOCOL BUS ENVIRONMENT - A method for transmitting data on a data line of a two-wire bus wherein the bus includes a data line and a clock line includes the step of pulling the data line of the two-wire bus low to define a start condition. Next, a first group of fixed data bits enabling a slave device to determine a clock signal for an address portion of a transmission of data are transmitted between a master device and the slave device. An address of the slave device is transmitted from the master device in a second group of data bits. A third group of fixed data bits enabling the slave device to determine the clock signal for a data portion of the transmission of data between the master device and the slave device are transmitted from the master device to the slave device. | 01-17-2013 |
| 20130031284 | BUS SYSTEM IN SOC AND METHOD OF GATING ROOT CLOCKS THEREFOR - A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal. | 01-31-2013 |
| 20130054850 | DATA MODIFICATION FOR DEVICE COMMUNICATION CHANNEL PACKETS - Techniques are disclosed relating to modifying packet data to be sent across a communication link and/or bus. Data may be modified in accordance with one or more data processing algorithms, and according to the capabilities of a destination device to receive such modified data. Lossless compression algorithms may be used on data in order to achieve a higher effective bandwidth over a particular bus or link. Encryption algorithms may be used, as well as data format conversion algorithms. One or more processing elements of a communication channel controller or other structure within a computing device may be used to modify packet data, which may be in PCI-Express format in some embodiments. A packet prefix or header may be used to store an indication of what algorithm(s) has been used to modify packet data so that a destination device can process packets accordingly. | 02-28-2013 |
| 20130054851 | METHOD AND DEVICE FOR DISABLING A HIGHER VERSION OF A COMPUTER BUS AND INTERCONNECTION PROTOCOL FOR INTEROPERABILITY WITH A DEVICE COMPLIANT TO A LOWER VERSION OF THE COMPUTER BUS AND INTERCONNECTION PROTOCOL - A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol. | 02-28-2013 |
| 20130060980 | VARIABLE READ LATENCY ON A SERIAL MEMORY BUS - Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer. | 03-07-2013 |
| 20130073755 | DEVICE PROTOCOL TRANSLATOR FOR CONNECTION OF EXTERNAL DEVICES TO A PROCESSING UNIT PACKAGE - A processing unit package includes a processing unit disposed on an interposer and a device protocol translator disposed on the interposer. Through-silicon vias (TSVs) may be used to provide connections from the device protocol translator through the interposer to an external device. The device protocol translator uses a controller to control a plurality of buffers that store information received from respective information buses coupled to the processing unit, such that the processing unit information is translated according to a protocol of the external device. | 03-21-2013 |
| 20130073756 | PROCESSOR AND SYSTEM FOR PROCESSING STREAM DATA AT HIGH SPEED - A processor for processing stream data at a high speed is provided. The processor may include a functional unit to perform an operation on the stream data, an input interface module to perform relaying between the functional unit and an external data producer module that is used to input the stream data to the processor, and an output interface module to perform relaying between the functional unit and an external data consumer module that is used to receive an input of result data regarding a result of the operation performed by the functional unit. | 03-21-2013 |
| 20130080667 | Handling Atomic Operations For A Non-Coherent Device - In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed. | 03-28-2013 |
| 20130086287 | Protocol Neutral Fabric - An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modem PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein. | 04-04-2013 |
| 20130097346 | STORAGE DEVICE AND CONNECTING SEAT FOR CONNECTING THE SAME TO HOST - Provided herein are a storage device and a connecting seat for connecting the storage device to a host. More particularly, the storage device and the connecting seat may be used to transmit at least one SATA protocol data. The storage device comprises a PATA interface connector. The connecting seat is a PATA interface connecting seat that can be installed on a circuit board. A plurality of pins of the connector/connecting seat are defined to be in the true IDE mode and a plurality of pins of the connector/connecting seat are defined to be in the non-true IDE mode. The storage device and the circuit board with the connecting seat thereon communicate through the pins of the connector/connecting seat in the non-true IDE mode. Thereby, the manufacturing cost of the storage device or the host is lowered and the convenience is enhanced. | 04-18-2013 |
| 20130111085 | APPARATUS INSTALLING DEVICES CONTROLLED BY MDIO OR SPI PROTOCOL AND METHOD TO CONTROL THE SAME | 05-02-2013 |
| 20130111086 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS | 05-02-2013 |
| 20130117481 | FIBRE CHANNEL N-PORT ID VIRTUALIZATION PROTOCOL - Disclosed is a computer implemented method, data processing system and computer program product to discover an SCSI target. The method comprises a client adapter transmitting an N_port ID virtualization (NPIV) login to a virtual I/O server (VIOS). The client adapter receives a successful login acknowledgement from the VIOS and issues a discover-targets command to the fabric. Upon determining that the SCSI target information is received, wherein the SCSI target information includes at least one SCSI identifier. Responsive a determination that SCSI target information is received the client adapter issues a port login to a target port, wherein the target port is associated with the at least one SCSI target. The client adapter makes a process login to form an initiator/target nexus between a client and at least one SCSI target. The client adapter queries the SCSI target by using a world wide port name associated with the target port. | 05-09-2013 |
| 20130132622 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
| 20130159573 | CONTROL METHOD FOR A DOOR DRIVE AND DOOR DRIVE - The invention relates to a method of controlling a door drive having a plurality of components which are communicatively connected to one another via a digital bus system, wherein at least one component is a safety component which reports the occurrence of a safety-relevant event over the data bus, and wherein the bus protocol reserves a cyclic safety phase for reporting a safety-relevant event and at least one component recognizes an undefined data transmission during the safety phase as a report of a safety-relevant event. | 06-20-2013 |
| 20130166798 | MULTI-PROTOCOL TUNNELING OVER AN I/O INTERCONNECT - Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for multi-protocol tunneling may include establishing a first communication path between ports of a switching fabric of a multi-protocol interconnect of a computer apparatus in response to a peripheral device being connected to the computer apparatus, establishing a second communication path between the switching fabric and a protocol-specific controller, and routing, by the multi-protocol interconnect, packets of a protocol of the peripheral device from the peripheral device to the protocol-specific controller over the first and second communication paths. Other embodiments may be described and claimed. | 06-27-2013 |
| 20130191567 | Wireless Bus for Intra-Chip and Inter-Chip Communication, Including Data Center/Server Embodiments - Embodiments of the present invention are directed to a wire-free data center/server. The data center/server is wire-free in the sense that communication within a data unit of the data center/server (i.e., intra-data unit), between data units of the data center/server (inter-data unit), and between the data units and the backplane of the data center/server is performed wirelessly. | 07-25-2013 |
| 20130205053 | PCI EXPRESS TUNNELING OVER A MULTI-PROTOCOL I/O INTERCONNECT - Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed. | 08-08-2013 |
| 20130205054 | Intelligent serial interface - An intelligent serial interface circuit in accordance with one embodiment of the invention can include a first communication interface circuit for enabling a first communication protocol. The intelligent serial interface circuit can also include a second communication interface circuit for enabling a second communication protocol. Furthermore, the intelligent serial interface circuit can include a detector circuit coupled to the first communication interface circuit and the second communication interface circuit. The detector circuit can be for automatically detecting a factor that indicates automatically enabling the first communication interface circuit and automatically disabling the second communication interface circuit. The detector circuit can be for detecting a coupling of a pin of the first communication interface circuit that is not used by the second communication interface circuit. | 08-08-2013 |
| 20130246674 | ASYMMETRICAL UNIVERSAL SERIAL BUS COMMUNICATIONS - In some embodiments a Universal Serial Bus cable includes a first differential pair to transmit bus signals, and a second differential pair to transmit bus signals in a same direction as the bus signals transmitted by the first differential pair. In this manner, a bandwidth of the Universal Serial Bus cable is doubled in that same direction. Other embodiments are described and claimed. | 09-19-2013 |
| 20130275635 | ELECTRONIC SYSTEMS, HOST ELECTRONIC DEVICES, ELECTRONIC DEVICES AND COMMUNICATION METHODS - An electronic system is provided, including a host electronic device and a first electronic device. The host electronic device is coupled to a mini display port (mDP) bus composed of a first lane and a second lane, in which the host electronic device turns off the second lane according to a disable signal in a first communication protocol mode. The first electronic device is coupled to the mDP bus and outputs a detection signal to the host electronic device, in which, when the first electronic device is coupled to the host electronic device, the host electronic device communicates with the first electronic device through the first lane in the first communication protocol mode and communicates with the first electronic device through the second lane in a second communication protocol mode, according to an enable signal. | 10-17-2013 |
| 20130290577 | METHOD THE CONFIGURE SERIAL COMMUNICATIONS AND DEVICE THEREOF - In response to a reset condition, the state of a steady-state signal at an I/O pin of the serial communication port of an integrated circuit die is determined. The serial communication port is configured to support one of the plurality of serial communication protocols based upon the detected steady-state condition. | 10-31-2013 |
| 20130290578 | DEADLOCK RESOLUTION IN END-TO-END CREDIT PROTOCOL - A system for deadlock resolution in end-to-end credit protocol includes a plurality of source controllers configured to receive data frames on an incoming link, wherein each source controller includes a plurality of credit counters. The system also includes a plurality of end controllers configured to receive data frames from the plurality of source controllers, wherein each end controller includes a buffer credit counter, a plurality of request counters, and an output buffer. Each of the plurality of credit counters corresponds to one of the plurality of end controllers and stores a number of credits received from that end controller. The buffer credit counter of each end controller stores a number of available credits of the end controllers. Each of the request counters corresponds to one of the plurality of source controllers and stores a number of credit requests received from that source controller. | 10-31-2013 |
| 20130290579 | PCI-BASED INTERFACING DEVICE WITH MAPPABLE PORT ADDRESSES TO LEGACY I/O PORT ADDRESSES - A PCI-based interfacing device with mappable port addresses to legacy I/O port addresses has an addressing circuit, a PCI controller connected to the addressing circuit and a PCI port, and an equipment controller connected to the PCI controller and an equipment port. The addressing circuit sets up a legacy I/O port address. The PCI controller transmit and receive data packets having data and one of the set of legacy I/O port addresses encapsulated therein to be processed to and from the PCI port, and output the received data packets to the equipment controller. The equipment controller converts the data packets into equipment data corresponding to the equipment port, and transmits the equipment data to the equipment port. Accordingly, the PCI-based interfacing device can perform data communication with legacy I/O port addresses. | 10-31-2013 |
| 20130290580 | METHOD AND DEVICE FOR SERIAL DATA TRANSMISSION AT A SWITCHABLE DATA RATE - In a method for enabling transmission of larger data quantities relatively rapidly in a data network, the sent data frames have a logical structure according to CAN Specification ISO 11898-1, the bit length in time within a data frame being able to assume at least two different values; for a first specifiable range within the data frame, the bit length in time being greater than, or equal to a specified minimum value of approximately one microsecond and in at least one second specifiable range within the data frame the bit length in time compared to the first range is at least halved, preferably less than halved; the change of the bit length in time being implemented by using at least two different scaling factors for setting the bus time unit relative to a shortest time unit or the oscillator clock pulse during running operation. | 10-31-2013 |
| 20130290581 | HYBRID INTERFACE FOR SERIAL AND PARALLEL COMMUNICATION - Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins. | 10-31-2013 |
| 20130297841 | PROTOCOLS FOR REPORTING POWER STATUS OVER MULTIPLE BUSES - An automated power reporting system is provided in one aspect. The system includes one or more devices that can report or transmit power status information over a bus or network. A protocol component utilizes a generalized protocol to process or convert the power status information over the network in order to facilitate power management operations for a plurality of devices. In this manner, devices that send power information can interact and exploit personal computing resources in order to better help users manage limited power resources for their respective devices. | 11-07-2013 |
| 20130297842 | METHODS AND APPARATUS TO IDENTIFY A COMMUNICATION PROTOCOL BEING USED IN A PROCESS CONTROL SYSTEM - Methods and apparatus to identify a communication protocol being used in a process control system are disclosed. An example method includes determining a message structure of a process control message received via a port, determining that the message structure corresponds to a first one of a plurality of process control message protocols, and processing the process control message according to the first process control message protocol. | 11-07-2013 |
| 20130297843 | Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Computer System - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 11-07-2013 |
| 20130304953 | CIRCUITRY TO GENERATE AND/OR USE AT LEAST ONE TRANSMISSION TIME IN AT LEAST ONE DESCRIPTOR - An embodiment may include circuitry that may generate and/or use, at least in part, at least one descriptor to be associated with at least one packet. The at least one descriptor may specify at least one transmission time at which the at least one packet is to be transmitted. The at least one transmission time may be specified in the at least one descriptor in such a manner as to permit the at least one transmission time to be explicitly identified based at least in part upon the at least one descriptor. Many alternatives, modifications, and variations are possible without departing from this embodiment. | 11-14-2013 |
| 20130318263 | System and Method to Transmit Data over a Bus System - A system includes a bus system to connect a number of components in a chain-like structure. A first control device (e.g., microcontroller or microprocessor) is configured to control the components in a first mode of the system. A second control device (e.g., microcontroller or microprocessor) is configured to control a first subset of the components in a second mode of the system. | 11-28-2013 |
| 20130318264 | Optimized Link Training And Management Mechanism - In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed. | 11-28-2013 |
| 20130326098 | METHOD FOR MANIPULATING THE BUS COMMUNICATION OF A CONTROL DEVICE - A method for manipulating the bus communication of an electronic control device is provided, wherein the bus communication includes a bus hardware-independent first communication layer and a bus hardware-dependent second communication layer. The first communication layer encodes at least one piece of information in a first protocol data unit and transmits it to the second communication layer and/or the first communication layer receives the first protocol data unit from the second communication layer and decodes the first information from the first protocol data unit. The second communication layer generates bus hardware-dependent bus information from the first protocol data unit or from an additional protocol data unit derived from the first protocol data unit for transmission via the bus and/or the second communication layer generates the first protocol data unit or an additional protocol data unit, from which the first protocol data unit can be derived. | 12-05-2013 |
| 20130332635 | PROTOCOL TRANSLATING ADAPTER - An adapter facilitates communications between an accessory and a media source. When the adapter is connected to the accessory, the adapter can receive a connection request from the media source. Based on the connection request, the adapter can determine whether the media source supports an accessory protocol. The adapter can receive streamed media from the media source. When a control message is received by the adapter from the accessory, if the adapter determined that the media source supports the accessory protocol, the adapter transmits the control message to the media source using the accessory protocol. If the adapter determined that the media source does not support the accessory protocol, the adapter translates the control message and transmits the translated message to the media source. | 12-12-2013 |
| 20130339558 | Delegating Network Processor Operations to Star Topology Serial Bus Interfaces - An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner. | 12-19-2013 |
| 20130346654 | Platform Neutral Device Protocols - Platform neutral device protocol techniques are described in which functionality to customize device interactions through communication busses is made accessible through platform independent script-based infrastructure. Functionality provided by an operating system to manipulate standard protocols of a communication bus used to interact with a connected device is exposed as script-based objects. Script-based protocol definition files associated with connected device may be employed to customize device protocols for the communications using the functionality exposed through the script-based objects. A computing device may acquire a protocol definition file for a particular device in various ways and host the protocol definition file via a suitable run-time platform. Requests for interaction with the particular device may then be handled using the custom protocols defined by the hosted protocol definition file. | 12-26-2013 |
| 20130346655 | BUS AGENT CAPABLE OF SUPPORTING EXTENDED ATOMIC OPERATIONS AND METHOD THEREFOR - A bus protocol compatible requester includes a bus protocol port for transmitting bus protocol compatible requests to a bus protocol link, and an extended atomic operation generation system, coupled to the bus protocol port, for generating an extended atomic operation by using at least one bit in a field of a standard bus protocol request other than an opcode field, and providing the extended atomic operation to the bus protocol port for transmission to a completer. A bus protocol compatible completer includes a bus protocol port for receiving bus protocol compatible requests from a bus protocol link, and an extended atomic operation execution system, coupled to the bus protocol port, for decoding an extended atomic operation according to at least one bit in a field of a standard bus protocol request other than an opcode field, and executing the extended atomic operation according to the at least one bit. | 12-26-2013 |
| 20140006661 | Method and Apparatus For Bus Lock Assistance | 01-02-2014 |
| 20140006662 | EXPLICIT CONTROL MESSAGE SIGNALING | 01-02-2014 |
| 20140013017 | I2C TO MULTI-PROTOCOL COMMUNICATION - A method, device and computer program product for providing multi-protocol communication on an inter-integrated circuit (I2C) bus. The method for providing multi-protocol communication on an inter-integrated circuit (I2C) bus can include issuing a start command by a bus management device onto the I2C bus. Thereafter, the bus management device can send an embedded differential protocol to a non-I2C device. Once communication with the non-I2C device is completed, the bus management device can issue a stop command to release the I2C bus. In one aspect of this embodiment, the method can include receiving a response from the non-I2C device. | 01-09-2014 |
| 20140032800 | VEHICLE MESSAGE FILTER - A message filtering system for a communications system in a vehicle enabling communication between various systems and subsystems via a vehicle bus. Electronic devices may be coupled to the bus. Electronic control units (ECUs) may be located therebetween. The ECU may regulate or control the flow of messages between the bus and the electronic devices. Message filters may apply a filter policy to incoming and outgoing messages. In addition, the message filtering system may have an alert policy for violations of the filter policy. In one embodiment, the source identity of outgoing messages may be overwritten by a message filter dedicated to outgoing messages; this message filter may be an application specific integrated circuit. | 01-30-2014 |
| 20140047145 | EXPANSION MODULE - An expansion module including a first expansion device and at least one second expansion device is provided. The first expansion device includes a first expansion bus interface, a second expansion bus interface and at least one first peripheral device. The first expansion device is coupled to a mobile electronic device via the first expansion bus interface. The first expansion bus interface provides the first peripheral device to the mobile electronic device for use. Each of the second expansion devices includes a third expansion bus interface and at least one second peripheral device. The second peripheral device is coupled to the third expansion bus interface and coupled to the second expansion bus interface in a daisy chain via the third expansion bus interface. The first expansion bus interface and the second expansion bus interface provide the second peripheral device to the mobile electronic device via the third expansion bus interface. | 02-13-2014 |
| 20140047146 | COMMUNICATION LOAD DETERMINING APPARATUS - A communication load determining apparatus is used for a communication system which includes a plurality of communication devices performing communication via a common bus. The communication system operates in accordance with a communication protocol that defines which a priority order is set to each of the frames transmitted from the communication devices and which a frame having a lower priority has a longer transmission latency before being transmitted to the bus. In the communication load determining apparatus, a low-priority frame having a lower priority than other frames to the bus is transmitted, and a transmission latency of the low-priority frame is measured. The communication load determining apparatus determines whether or not abnormality has occurred in a communication load in the bus on the basis of the measured transmission latency to produce a determination result. The produced determination result is stored. | 02-13-2014 |
| 20140075067 | DATA STRUCTURES FOR FACILITATING COMMUNICATION BETWEEN A HOST DEVICE AND AN ACCESSORY - Computer readable storage mediums, electronic devices, and accessories having stored thereon data structures. A data structure includes a pin selection field operable to identify a connector pin and cause a host device to select one of a plurality of communication protocols for communicating with an accessory over the identified connector pin. The data structure also includes an accessory capability field defining an accessory identifier that uniquely identifies the accessory. | 03-13-2014 |
| 20140089541 | BUS PROTOCOL COMPATIBLE DEVICE AND METHOD THEREFOR - A bus protocol compatible device, includes a transmitter having a first mode for providing a reference clock signal to an output, and a second mode for providing a training sequence to the output, and a power state controller for placing the transmitter in the first mode for a first period of time in response to a change in a link state, and in the second mode after an expiration of the first period of time. | 03-27-2014 |
| 20140089542 | CHAINED INFORMATION EXCHANGE SYSTEM COMPRISING A PLURALITY OF MODULES CONNECTED TOGETHER BY HARDENED DIGITAL BUSES - A chained information exchange system ( | 03-27-2014 |
| 20140095750 | Method for Managing the Operation of a Circuit Connected to a Two-Wire Bus - A method is provided for managing the operation of a circuit operating in a slave mode. The circuit is connected to a bus having at least two of wires and a priority logic level. The slave circuit imposes the priority logic level on a first wire of the bus. While imposing, the slave circuit detects a possible conflict on the first wire resulting from a forcing, external to the slave circuit, of the first wire to another logic level. Upon detecting a conflict, the slave circuit is placed in a state stopping the sending by the circuit of any data over the bus while leaving the circuit listening to the bus. | 04-03-2014 |
| 20140108684 | INTERCONNECT BANDWIDTH THROTTLER - An interconnect bandwidth throttler is disclosed. The interconnect bandwidth throttler turns off the interconnect, based on whether a maximum number of transactions has taken place within a predetermined throttle window. Both the maximum number of transactions and the throttle window are adjustable. Characteristics such as performance, thermal considerations, and average power are adjustable using the interconnect bandwidth throttler. | 04-17-2014 |
| 20140108685 | METHOD FOR TRANSMITTING A PROCESS MAP VIA A GATEWAY DEVICE - Exemplary methods and systems are directed to transmitting a process map of a control or automation system via a gateway device. The gateway device includes at least one first functional unit connected to a higher-ranking control unit via a first communications link based on a primary field bus protocol, and at least one second functional unit connected to at least one field device via a second communications link based on a secondary field bus protocol. Binary signals are stored in corresponding registers and analog signals, which are in an integer format, are transmitted to the first functional unit such that the number of binary signals is reduced by packing the binary signals into data bytes. The data bytes are translated into corresponding telegrams that can be processed by the primary field bus protocol and with the analog signals are transmitted to the higher-ranking control unit. | 04-17-2014 |
| 20140115206 | METHODS AND SYSTEMS FOR RUNNING NETWORK PROTOCOLS OVER PERIPHERAL COMPONENT INTERCONNECT EXPRESS - Methods and devices for running network protocols over Peripheral Component Interconnect Express are disclosed. The methods and devices may receive an electronic signal comprising data. The methods and devices may also determine the data corresponds to a protocol selected from a set comprising a PCIe protocol and a network protocol. In addition, the methods and devices may also configure a CPU based on the determined protocol. The methods and devices may also receive a second electronic signal comprising second data at a pin or land of the CPU, wherein the pin or land is connected to a PCIe lane and wherein the second data is formatted in accordance with determined protocol. In addition, the methods and devices may process the second data in accordance with the determined protocol. | 04-24-2014 |
| 20140115207 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link. | 04-24-2014 |
| 20140115208 | CONTROL MESSAGING IN MULTISLOT LINK LAYER FLIT - A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements. | 04-24-2014 |
| 20140129747 | GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL - A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link. | 05-08-2014 |
| 20140136739 | METHODS AND APPARATUS FOR FAST CONTEXT SWITCHING OF SERIAL ADVANCED TECHNOLOGY ATTACHMENT IN ENHANCED SERIAL ATTACHED SCSI EXPANDERS - Methods and apparatus for enabling Fast Context Switching (FCS) operation of an enhanced Serial Attached SCSI (SAS) expander and initiator for switching between one or more concurrently established connections including at least one Serial Advanced Technology Attachment (SATA) target device connection. Features and aspects hereof provide for enhanced logic within a SAS expander and/or initiator to detect the completion of an exchange over a first connection between an initiator device and a SATA target device and to allow switching to another (a second) connection without closing the first connection. | 05-15-2014 |
| 20140149614 | SATA Data Appliance for Providing SATA Hosts with Access to a Configurable Number of SATA Drives Residing in a SAS Topology - A method and apparatus for providing a SATA host with access to multiple SATA drives is disclosed. The apparatus may include: an emulated port multiplier for presenting at least one logical drive to the SATA host; a mapping module for maintaining a mapping between the at least one logical drive and a plurality of physical SATA drives, wherein the plurality of physical SATA drives reside in a SAS topology; and a SATA/STP bridge for providing an interface between the SATA host and the SAS topology, the SATA/STP bridge configured to function as a SATA target to communicate with the SATA host and to function as a STP initiator to communicate with the plurality of physical SATA drives in the SAS topology. | 05-29-2014 |
| 20140156887 | METHOD AND DEVICE FOR SERIAL DATA TRANSMISSION WHICH IS ADAPTED TO MEMORY SIZES - A method is described for serial data transmission in a bus system having at least two participating data processing units, the data processing units exchanging messages via the bus, the sent messages having a logical structure in accordance with CAN standard ISO 11898-1. When a first changeover condition is present, then, deviating from CAN, the data field of the messages can include more than eight bytes, the values of the data length code being interpreted, given the presence of the first changeover condition to determine the size of the data field. For forwarding data between the data field and the application software, at least one buffer memory is provided, and, if the size of the data field differs from the size of the buffer memory used, the forwarded quantity of data is adapted at least corresponding to the difference in size between the data field and the buffer memory. | 06-05-2014 |
| 20140164658 | Wireless Protocol Communication Bridge And System Comprising Bridge - A bridge for linking a first and a second wireless communication device and translating between differing wireless protocols is described and taught. The bridge system comprises at least one wireless device and a bridge apparatus. The bridge apparatus takes the form of a universal serial bus that contains components that allows it to function without a host system. Additionally, the bridge apparatus enables the translation between different wireless protocols. This, in turn, enables older or outdated wireless technology to function seamlessly with the most current wireless protocols. | 06-12-2014 |
| 20140189172 | DISCOVERY MECHANISMS FOR UNIVERSAL SERIAL BUS (USB) PROTOCOL ADAPTATION LAYER - A WiFi serial bus (WSB) attribute for use in Wi-Fi Alliance defined point-to-point (P2P) discovery mechanism includes a plurality of fields disposed in the frame. The WiFi serial bus attribute is arranged to provide information in the plurality of fields to support connectivity decisions for a USB device in a point-to-point network using a WSB protocol. The WSB attribute includes WSB architectural element information and information associated with a USB device behind a USB protocol adaptation layer (PAL). | 07-03-2014 |
| 20140195704 | CHASSIS MANAGEMENT IMPLEMENTATION BY MANAGEMENT INSTANCE ON BASEBOARD MANAGEMENT CONTROLLER MANAGING MULTIPLE COMPUTER NODES - Certain aspects of the present disclosure are directed to a baseboard management controller (BMC). The BMC includes a processor and a memory having firmware. The firmware includes a master management instance and a plurality of assisting management instances. When the firmware is executed at the processor, the master management instance is configured to manage a chassis of a computer system, and each of the assisting management instances is configured to manage at least one health or performance related aspect a respective different computer node of a plurality of computer nodes of the computer system. | 07-10-2014 |
| 20140207983 | TIME-DIVISION MULTIPLEXED DATA BUS INTERFACE - An audio system bus has a bus data line and a bus clock line. Audio producers are coupled to the bus to form a time-division multiplexed multi drop bus interface arrangement having protocol slots 0,1, . . . N where N is an integer greater than two. A bus device is coupled to the bus that produces a) a frame marker on the bus data line in slot 0, and b) a data bit on the bus data line in slot 1. The audio producers are to produce their respective audio data bits in their assigned slots other than slots 0 and 1. Other embodiments are also described and claimed. | 07-24-2014 |
| 20140207984 | SIGNAL CONITIONER - A signal conditioner can include a state machine configured to detect a predetermined protocol level mode of a data signal on a bi-directional serial bus. The signal conditioner can also include a re-driver configured to inject current into at least one of a rising edge and a falling edge of the data signal on the bi-directional serial bus in response to the detection of the predetermined protocol level mode. | 07-24-2014 |
| 20140215108 | REDUCING WRITE I/O LATENCY USING ASYNCHRONOUS FIBRE CHANNEL EXCHANGE - A FCP initiator sends a FCP write command to a FCP target within a second FC Exchange, and the target sends one or more FC write control IUs to the initiator within a first FC Exchange to request a transfer of data associated with the write command. The first and second FC exchanges are distinct from one another. A payload of each write control IU includes an OX_ID value with which the initiator originated the second Exchange and a RX_ID value assigned by the FCP target for the second exchange. The two Exchanges yield a full-duplex communication environment between the initiator and target that enables the reduction or elimination of latencies incurred in a conventional FCP write I/O operation due to the half-duplex nature of a single FC Exchange. The write control IU may be an enhanced FCP_XFER_RDY IU or a new FC IU previously undefined by the FCP standard. | 07-31-2014 |
| 20140215109 | Compatible Network Node, in Particular, For Can Bus Systems - A network node is provided, including a device, in particular, an error detection logic, which is deactivated if it is detected that a signal according to a first protocol or a first version of a first protocol is received, and which is not deactivated if it is detected that a signal according to a second, different protocol or a second, different version of the first protocol is received. | 07-31-2014 |
| 20140215110 | DRIVING INTEGRATED CIRCUIT AND UPATE METHOD THEREOF - A driving IC is being controlled by a host IC to update a driving program stored in a storage with a SPI interface. The driving IC includes a IIC interface, an identifying module, and a calculating module. The IIC interface receives an instruction from the host IC in the IIC protocol format. The identifying module determines whether the received instruction is an update instruction, and generates a converting instruction when the received instruction is the update instruction. The calculating module converts the received instruction into a SPI format according to a predetermined converting rule. The SPI interface transmits the converted instruction in the SPI format to the storage. | 07-31-2014 |
| 20140215111 | VARIABLE READ LATENCY ON A SERIAL MEMORY BUS - Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer. | 07-31-2014 |
| 20140281070 | Method and System for Platform Management Messages Across Peripheral Component Interconnect Express (PCIE) Segments - A method is disclosed to manage platform management messages through multiple peripheral component interconnect express (PCIe) segments implemented on a root complex of a computing system. | 09-18-2014 |
| 20140281071 | OPTICAL MEMORY EXTENSION ARCHITECTURE - An optical memory extension architecture. A first electrical logic circuit on a first die communicates data according to a packetized, point-to-point interconnect protocol at a full data rate. A first gasket circuit is coupled to receive the data from the first electrical logic circuit. The first gasket circuit causes the data to be converted to an optical format to be transmitted at a rate that is at least double the full data rate. A second gasket circuit is coupled to receive the data in the optical format from the first gasket circuit. The second gasket circuit causes the data to be converted to an electrical format conforming to the packetized, point-to-point interconnect protocol. A second electrical logic circuit on a second die is coupled to receive the data from the first electrical logic circuit through the first gasket circuit and the second gasket circuit. | 09-18-2014 |
| 20140289434 | Leveraging an Enumeration and/or Configuration Mechanism of One Interconnect Protocol for a Different Interconnect Protocol - An interconnect architecture device of an aspect includes a processor to generate a transaction that is of a different interconnect protocol than LLI. The interconnect architecture device also includes conversion logic coupled with the processor. The conversion logic is to convert the transaction, which is of the different interconnect protocol than LLI, to an LLI packet. The interconnect architecture device also includes an LLI controller coupled with the conversion logic. The LLI controller is to couple the interconnect architecture device with an LLI link. The LLI controller is to transmit the LLI packet on the LLI link. | 09-25-2014 |
| 20140304441 | PROTOCOL CONVERSION INVOLVING MULTIPLE VIRTUAL CHANNELS - Embodiments of a bridge circuit and system are disclosed that may allow converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The second bus may include a plurality of virtual channels. The bridge circuit may be configured to receive transactions over the first bus, and convert the transactions to the second communication protocol, and to assign the converted transaction to one of the plurality of virtual channels. The bridge circuit may be further configured store the converted transaction. A plurality of limited throughput signals may be generated by the bridge circuit dependent upon a number of available credits for the plurality of virtual channels. | 10-09-2014 |
| 20140330994 | SYNCHRONOUS DATA-LINK THROUGHPUT ENHANCEMENT TECHNIQUE BASED ON DATA SIGNAL DUTY-CYCLE AND PHASE MODULATION/DEMODULATION - A synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation demodulation is disclosed. A method includes receiving multiple bits to be transmitted, encoding the multiple bits to generate a multi-bit signal that represents the multiple bits, and transmitting, via a synchronous interface, the multi-bit signal during a time period that corresponds to one-half of a cycle of a synchronization signal. | 11-06-2014 |
| 20140330995 | DATA STORAGE SYSTEM - In an embodiment, a storage device may include a tangible non-transitory physical storage for storing information. The storage device may also include an interface. The interface may be used to receive a signal that may be associated with one of a plurality of different protocols. The signal may be received serially. The storage device may include circuitry which may be used to identify a protocol associated with the received signal. The protocol may be identified based on an attribute associated with the received signal. Alternatively or in addition to, the protocol may be identified based on information encoded in the received signal. The information encoded in the received signal may include, for example, a data header that may be associated with the protocol. | 11-06-2014 |
| 20140351465 | Limited Functionality Link State Protocol Node - In one embodiment a limited functionality link state protocol node has one or two interfaces configured to send and receive link state protocol packets. In response to receiving, by the partially-participating link state protocol node on a first interface, a particular link state protocol data unit (LSP): sending the particular LSP from a second interface of the partially-participating link state protocol node without updating the local link state database when the second interface is currently participating in the link state protocol distribution; and sending an acknowledgment of the particular LSP from the first interface when the second interface is not currently participating in the link state protocol distribution. | 11-27-2014 |
| 20140365693 | CAN AND FLEXIBLE DATA RATE CAN NODE APPARATUS AND METHODS FOR MIXED BUS CAN FD COMMUNICATIONS - Controller area network (CAN) communications apparatus and methods are presented for CAN flexible data rate (CAN FD) communications in a mixed CAN network with CAN FD nodes and one or more non-FD CAN nodes in which a CAN FD node wishing to transmit CAN FD frames sends a first predefined message requesting the non-FD CAN nodes to disable their transmitters before transmitting the CAN FD frames, and thereafter sends a second predefined message or a predefined signal to return the non-FD CAN nodes to normal operation. | 12-11-2014 |
| 20140372642 | CAMERA CONTROL INTERFACE EXTENSION BUS - System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols. | 12-18-2014 |
| 20140372643 | CAMERA CONTROL INTERFACE EXTENSION BUS - System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols. | 12-18-2014 |
| 20150019771 | DAISY CHAIN COMMUNICATION BUS AND PROTOCOL - A battery pack has first and second battery terminals, plural battery cells each with a battery element, a cell supervisor electrically connected to the battery element, and a communication section to communicate with the cell supervisor. The battery elements are connected serially between the first and second battery terminals. Bus interfaces are arranged in alternating fashion with the battery cells to define a daisy chain bus, each such bus interface being configured for signal communication, the interfaces respectively connecting the communication sections of two adjacent battery cells. A battery manager communicates with the battery cells via the daisy chain bus. The battery manager sends a command message to the battery cells using a through mode protocol, and each battery cell sends at least one of a confirmation message and a service request to the battery manager using a shift mode protocol. | 01-15-2015 |
| 20150026372 | Device, method and system for communicating with a control unit of a motor vehicle - A control unit for controlling or regulating a component, including a processing arrangement for controlling or regulating the component for connecting the control unit to a bus for communicating with a further control unit; an application tool port for connecting the control unit to an application tool for communicating with the control unit; and a connecting arrangement for connecting the application tool port and the bus port so that the application tool is able to communicate via the bus port, and a bus, a motor vehicle, a method, an application tool, and computer program products. | 01-22-2015 |
| 20150026373 | Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 01-22-2015 |
| 20150039793 | NETWORK INTERFACE CARD FOR A COMPUTING NODE OF A PARALLEL COMPUTER ACCELERATED BY GENERAL PURPOSE GRAPHICS PROCESSING UNITS, AND RELATED INTER-NODE COMMUNICATION METHOD - A Network Interface Card (NIC) for a cluster node for parallel calculation on multi-core GPU is described. The NIC has a cluster network including a host and a host memory, a graphics processing unit (GPU) with a GPU memory, a bus and the NIC. The NIC has a transmission network connection block and a reception network connection block. The NIC further includes the following blocks: a transmission block, a reception block, and a GPU memory management block for a direct exchange between the GPU memory and the network through the NIC. An inter-nodal communication method of a nodes cluster, which uses the NIC is also described. | 02-05-2015 |
| 20150046612 | MEMORY DEVICE FORMED WITH A SEMICONDUCTOR INTERPOSER - A packaged memory device includes a semiconductor interposer, a first memory stack, a second memory stack, and a buffer chip that are all coupled to the semiconductor interposer. The first memory stack and the second memory stack each include multiple memory chips that are configured as a single stack. The buffer chip is electrically coupled to the first memory stack via a first data bus, electrically coupled to the second memory stack via a second data bus, and electrically coupled to a processor data bus that is configured for transmitting signals between the buffer chip and a processor chip. Such a memory device can have high data capacity and still operate at a high data transfer rate in an energy efficient manner. | 02-12-2015 |
| 20150046613 | NETWORKING APPARATUS AND A METHOD FOR NETWORKING - This specification discloses a protocol agnostic networking apparatus and method of networking. The networking apparatus receives physical layer signal through a plurality of communications ports that interface with external computing systems. A dynamic routing module interconnects the communications ports with discrete reconfigurable data conduits. Each of the data conduits defines a transmission pathway between predetermined communications ports. A management module maintains the data conduits based on routing commands received from an external computing system. The management module interfaces with the dynamic routing module to make and/or break data conduits responsive to received routing commands. | 02-12-2015 |
| 20150067206 | MULTI-PROTOCOL SERIAL COMMUNICATION INTERFACE - Systems and methods for multi-protocol serial communication interfaces are described. One example system includes an interface module including a buffer for storing a protocol selection. The system includes a protocol module coupled to the interface module and configured for providing one or more serial communication protocols. Based on the protocol selection, one of the serial communication protocols is selected. The system also includes a serial engine module coupled to the interface module and the protocol module. The serial engine module is configured for transmitting and receiving data or commands based on the selected serial communication protocol. | 03-05-2015 |
| 20150067207 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics. | 03-05-2015 |
| 20150067208 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link. | 03-05-2015 |
| 20150081936 | IIC BUS START-STOP DETECTION CIRCUIT - A start/stop condition detection circuit is coupled to receive the SDA and SCL signals from an IIC Bus. The circuit generates a first signal in response to an edge of the SDA signal and generates an inversion of the first signal as a second signal in response to an opposite edge of the SCL signal. The first and second signals are logically combined to generate an output signal. The particular directions of the edges of the SDA and SCL signals that the circuit is response to determines whether the output signal is indicative of a start condition detection or a stop condition detection. | 03-19-2015 |
| 20150089099 | MILITARY STANDARD (MIL-STD-1760) INTERFACE BRIDGE - A military standard-1760 (MIL-STD-1760) interface bridge can include a housing, a translator device, and an energy storage device. The housing can include a MIL-STD-1760 connector on a first end and a weapon side connector on a second end. The translator device can translate a MIL-STD-1553B remote terminal (RT) protocol to a weapon side signaling protocol and translate the weapon side signaling protocol to the MIL-STD-1553B RT protocol. The energy storage device can be coupled to the operating power of the MIL-STD-1760 connector and can be configured to provide power to the translator device for a duration after the power from the MIL-STD-1760 connector is disconnected. | 03-26-2015 |
| 20150095531 | LANE DIVISION MULTIPLEXING OF AN I/O LINK - A system can include a host device and a remote terminal. The host device can include a host terminal, the host terminal including a host configuration manager to allocate a data lane to an I/O protocol and a protocol multiplexer to carry out allocation of the data lane based on the allocation of the configuration manager. The remote terminal can include a remote configuration manager. The remote configuration manager is to communicate with the remote configuration manager via a control bus to detect connection of an I/O device to an I/O port and to allocate the data lane to the I/O protocol. | 04-02-2015 |
| 20150095532 | CONTROLLER AREA NETWORK (CAN) DEVICE AND METHOD FOR CONTROLLING CAN TRAFFIC - Embodiments of a device and method are disclosed. In an embodiment, a CAN device is disclosed. The CAN device includes a TXD input interface, a TXD output interface, an RXD input interface, an RXD output interface, and a traffic control system connected between the TXD input and output interfaces and between the RXD input and output interfaces. The traffic control system is configured to detect the presence of CAN Flexible Data-rate (FD) traffic on the RXD input interface and if the traffic control system detects the presence of CAN FD traffic on the RXD input interface, disconnect the RXD input interface from the RXD output interface and disconnect the TXD input interface from the TXD output interface. | 04-02-2015 |
| 20150106539 | COMMUNICATION CONTROL PINS IN A DUAL ROW CONNECTOR - Methods and apparatus, including computer program products, are provided for communications control in a dual row connector. In one aspect there is provided a method. The method may include coupling a first data connector including a pair of communication control pins and another pair of communication control pins, wherein the pair further comprises a first communication control pin located at a first row of the first data connector and a second communication control pin located at a second row of the data connector, wherein the other pair further comprises a third communication control pin located at the first row of the first data connector and a fourth communication control pin located at the second row of the first data connector. Related apparatus, systems, methods, and articles are also described. | 04-16-2015 |
| 20150120970 | METHOD AND APPARATUS FOR PROVIDING PERFORMANCE DATA OVER A DEBUG BUS - A device and method for providing performance information about a processing device. A stream of performance data is generated by one or more devices whose performance is reflected in the performance data. This performance data stream is then provided to a parallel port for outputting thereof. | 04-30-2015 |
| 20150134862 | SYSTEM AND METHOD OF SENDING DATA VIA ADDITIONAL SECONDARY DATA LINES ON A BUS - A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line. | 05-14-2015 |
| 20150143004 | COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD - Provided is a communication system that can aim to prevent unauthorized communications, i.e., to improve the reliability of communicated messages. A communication system comprises a plurality of ECUs connected to a communication line such that the plurality of ECUs can communicate communication messages. Each of the plurality of ECUs has a unique ID and also has a plurality of dummy IDs defined, as substitute candidates, from the unique ID. The ECU further has a defined pattern in which to cause one of the plurality of dummy IDs to be selected as a dummy ID that is a substitution object to be converted to the unique ID. Among the plurality of ECUs, the selection conditions of the substitution objects based on the pattern are synchronized, and the unique ID, which has been added to a communication message, is converted to a dummy ID on the basis of the pattern. Further, among the plurality of ECUs, the communication message, to which the dummy ID after the conversion has been added, is transmitted, and the dummy ID, which is acquired from the received communication message, is reconverted to the unique ID on the basis of the pattern. Finally, among the plurality of ECUs, the received communication message is identified on the basis of the unique ID after the reconversion. | 05-21-2015 |
| 20150301970 | VERIFYING RUNTIME SWITCH-OVER BETWEEN MULTIPLE I/O PROTOCOLS ON SHARED I/O CONNECTION - A verification environment enables verification of runtime switch-over—i.e., a switch-over without restarting the device under test—between multiple I/O protocols that share a same physical interface. The device under test can be a switch unit having multiple logical protocol processing units and a logical protocol multiplexor. The verification environment includes a switch-over detector which monitors the state of the device under test, and a switch-over controller that controls the switch-over sequence by pausing and re-starting traffic on all or specific protocol drivers of the verification environment. | 10-22-2015 |
| 20150301975 | MULTI-CORE PROCESSOR FOR MANAGING DATA PACKETS IN COMMUNICATION NETWORK - A system for managing data packets has multiple cores, a data buffer, a hardware accelerator, and an interrupt controller. The interrupt controller transmits a first interrupt signal to a first one of the cores based on a first hardware signal received from the hardware accelerator. The first core creates a copy of buffer descriptors (BD) of a buffer descriptor ring that correspond to the data packets in the data buffer in a first virtual queue and indicates to the hardware accelerator that the data packets are processed. If there are additional data packets, the interrupt controller transmits a second interrupt signal to a second core, which performs the same steps as performed by the first core. The first and the second cores simultaneously process the data packets associated with the BDs in the first and second virtual queues, respectively. | 10-22-2015 |
| 20150301980 | SYNCHRONIZATION METHOD FOR MULTI-SYMBOL WORDS - System, methods and apparatus are described that offer improved performance of a camera control interface (CCIe) bus. A method of data communications includes transmitting a first synchronization code on a serial bus, establishing synchronization with a first device coupled to the serial bus in response to the first synchronization code, communicating with the first device over the serial bus in accordance with a first protocol, after establishing synchronization with the first device, transmitting a first unsynchronization code on the serial bus, where the unsynchronization code is configured to cause a loss of synchronization with the first device, transmitting a second synchronization code on the serial bus, establishing synchronization with a second device coupled to the serial bus in response to the second synchronization code, and communicating with the second device over the serial bus in accordance with a second protocol, after establishing synchronization with the second device. | 10-22-2015 |
| 20150317275 | IMPLEMENTING COHERENT ACCELERATOR FUNCTION ISOLATION FOR VIRTUALIZATION - A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy. | 11-05-2015 |
| 20150317276 | RECONFIGURABLE HIGH SPEED MEMORY CHIP MODULE AND ELECTRONIC DEVICE WITH A RECONFIGURABLE HIGH SPEED MEMORY CHIP MODULE - A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus. | 11-05-2015 |
| 20150324315 | PARALLEL OPERATION OF A BUS SYSTEM AND A CAN BUS SYSTEM HAVING A DEVICE FOR COMPENSATING FOR INTERFERENCES - A user station is provided for connecting to a bus line and a method for compensating for an interference due to a CAN bus system in a received signal. A signal of a CAN bus system is transmitted via the bus line in coexistence with a signal of a further bus system. The user station includes a receiving unit for receiving an overall signal and for compensating for an interference in the received overall signal which occurs due to a changing output impedance of a user station of the CAN bus system which is connected to the bus line. | 11-12-2015 |
| 20150346762 | DWELL TIMERS FOR SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE DEVICES - Methods and structure for dwell timers in Serial Attached Small Computer System Interface (SAS) devices. An exemplary system includes a SAS end device. The SAS end device includes a physical link (PHY) operable to receive an OPEN Address Frame (OAF) from a coupled SAS device. The SAS end device also includes a controller. The controller is able to determine that the end device is presently unable to service a connection, and to wait a period of time for a dwell timer to expire. The controller is also able to service the connection by sending an OPEN_ACCEPT response if the end device becomes able to service the connection before the dwell timer expires, and to send an OPEN_REJECT (RETRY) response if the end device does not become able to service the connection before the dwell timer expires. | 12-03-2015 |
| 20150347343 | INTERCOMPONENT DATA COMMUNICATION - A request to send a first message from a first component to a second component is received at an arbiter. The first component is located in a first time zone and the second component is located in a second time zone. The arbiter determines that the second component is located in the second time zone. It is determined that the second time zone can be communicated with via one or more communications channels in a first direction. It is determined whether bandwidth is available on the one or more communications channels in the first direction. If bandwidth is available on the one or more communications channels in the first direction, a data path between the first component and the one or more communications channels in the first direction is created and the request is granted. Otherwise, the grant of the request is delayed. | 12-03-2015 |
| 20150363351 | DATA TRANSFER DEVICE AND DATA TRANSFER METHOD - A data transfer device performing data transfer at a high speed if a descriptor chain cannot be entirely transferred by a single activation. In a DMA control device, when a transfer activation signal is asserted, a descriptor information control part sequentially reads descriptor information from a descriptor information storage part. When the count of pieces of descriptor information that have been read becomes equal to a transferable frame count, a backward skip control part outputs a backward skip instruction. When the backward skip instruction is outputted, a descriptor information control part skips reading remaining descriptor information. | 12-17-2015 |
| 20150370745 | SYSTEM AND METHOD FOR COMMUNICATION PORT BASED ASSET MANAGEMENT - An identifier of an asset is retrieved using a first communication protocol and is converted to a form compatible with a second communication protocol. Translation circuitry can convert the identifier and can transmit the converted identifier to a communication bus that uses the second communication protocol. An identifier from a USB device can be converted to a Dallas Semiconductor/Maxim Integrated 1-Wire protocol format in an example, and an RFID identifier can be converted to 1-Wire protocol format in another example. | 12-24-2015 |
| 20150370746 | BIDIRECTIONAL DATA TRANSMISSION SYSTEM - A system for bidirectional signal transmission may comprise a forward data transmission circuit to unidirectionally transmit a first input signal and a backward data transmission circuit to unidirectionally transmit a second input signal. The backward data transmission circuit may comprises a logic circuit to detect a voltage difference over a resistance element in the forward data transmission circuit. When the voltage difference is lower than a threshold value, the logic circuit outputs a first voltage level. When the voltage difference is greater than or equal to a threshold value, the logic circuit outputs a second voltage level different from the first voltage level. | 12-24-2015 |
| 20150370752 | TRANSLATION OF UNIVERSAL ARMAMENT INTERFACE (UAI) TO MILITARY STANDARD (MIL-STD-1760) MESSAGING INTERFACE - A Universal Armament Interface (UAI) translator for a legacy military standard-1760 (MIL-STD-1760) messaging interface can include a legacy interface, a UAI, and a processor. The legacy interface can transmit a legacy receive message (‘R’ message) and receive a legacy transmit message (‘T’ message). The legacy interface can include a MIL-STD-1760 remote terminal (RT) messaging interface. The UAI can receive a UAI ‘R’ message and transmit a UAI ‘T’ message. The processor can translate the legacy ‘R’ message to the UAI ‘R’ message, and translate the UAI ‘T’ message to the legacy ‘T’ message. | 12-24-2015 |
| 20150370753 | Architected Protocol For Changing Link Operating Mode - In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed. | 12-24-2015 |
| 20150378952 | METHOD AND APPARATUS OF USB 3.1 RETIMER PRESENCE DETECT AND INDEX - An apparatus for retimer presence detection is described herein. The apparatus includes at least one retimer, wherein an algorithm is to enable the at least one retimer to announce its presence by asserting a bit of a presence message during link initialization. The at least one retimer can declare an index and is accessible via the index. | 12-31-2015 |
| 20150378958 | ARBITRATING USAGE OF SERIAL PORT IN NODE CARD OF SCALABLE AND MODULAR SERVERS - A system and method for provisioning of modular compute resources within a system design are provided. In one embodiment, a node card or a system board may be used. | 12-31-2015 |
| 20160019182 | GENERATING A PARALLEL DATA SIGNAL BY CONVERTING SERIAL DATA OF A SERIAL DATA SIGNAL TO PARALLEL DATA - Methods and deserializer circuits are provided for generating a parallel data signal by converting serial data of a serial data signal to parallel data. In a particular embodiment, the deserializer circuit includes a logic divider configured to generate based on a half rate clock, a quarter rate clock, a mode rate clock, and a selection control signal. The deserializer circuit includes a first set of latches for sampling and aligning the serial data from the serial data signal into the deserializer circuit based on the half rate clock. The deserializer circuit also includes a shift register including a second set of latches configured to latch the output of the first set of latches based on the quarter rate clock generated by the logic divider. In the particular embodiment, the deserializer circuit also includes multiplexer logic configured to output the parallel data signal including latching data from the shift register. | 01-21-2016 |
| 20160026597 | MODE SELECTIVE BALANCED ENCODED INTERCONNECT - An apparatus is described herein. The apparatus includes a plurality of conductors, wherein at least one conductor is a common-mode conductor. The apparatus also includes an encoder to encode data to be transmitted on the plurality of conductors, wherein a data speed of the common-mode conductor is limited and a data speed of other conductors is maximized according to an encoding matrix. | 01-28-2016 |
| 20160034413 | OPERATING METHOD OF CONTROLLER FOR SETTING LINK BETWEEN INTERFACES OF ELECTRONIC DEVICES, AND STORAGE DEVICE INCLUDING CONTROLLER - An operating method includes sensing a connection of the first electronic device to an interface circuit of the second electronic device; receiving an identification code from the first electronic device; and setting a state of the interface circuit as an express linkup state corresponding to the received identification code. The identification code has a value different from values defined and reserved in an interface protocol which defines an operating procedure of the interface circuit. The value of the identification code varies with an attribute of the first electronic device. | 02-04-2016 |
| 20160055116 | DYNAMIC VEHICLE BUS SUBSCRIPTION - A method of controlling access at a vehicle to information communicated over a vehicle bus includes: storing one or more electronic control unit (ECU) identities in a central gateway module (CGM) that is communicatively linked with a vehicle bus; associating one or more message permissions for receiving messages via the vehicle bus with one of the ECU identities in the CGM that represents an ECU communicatively linked with the vehicle bus; wirelessly receiving a computer-readable instruction at the vehicle directing the CGM to change one or more message permissions associated with the ECU identity; and storing the changed message permissions in the CGM. | 02-25-2016 |
| 20160062360 | MEDIA MOBILITY UNIT (MMU) AND METHODS OF USE THEREOF - In one embodiment, a media mobility unit includes a media cartridge holding portion configured to simultaneously store multiple media cartridges, a sensing mechanism for sensing at least an approximate location of the holding portion in relation to other objects, a drive mechanism for moving the holding portion from a source media library to a destination media library, and a power source electrically coupled to at least one of the sensing mechanism and the drive mechanism for providing current to the at least one of the drive mechanism and the sensing mechanism. In another embodiment, a method for transporting a media cartridge includes receiving one or more media cartridges from a source media library, storing the one or more media cartridges in a holding portion of a media mobility unit, sensing at least an approximate location of the media mobility unit, and transporting the one or more media cartridges to a destination library. | 03-03-2016 |
| 20160110301 | Inline PCI-IOV Adapter - A system for enabling input/out virtualization for a device is disclosed. In one embodiment the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device. | 04-21-2016 |
| 20160124894 | METHOD, APPARATUS AND SYSTEM FOR MEASURING LATENCY IN A PHYSICAL UNIT OF A CIRCUIT - In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed. | 05-05-2016 |
| 20160126964 | REFERENCE FREQUENCY CALIBRATION MODULE AND APPARATUS USING THE SAME - A reference frequency calibration module is provided. The reference frequency calibration module includes an oscillator, a frequency divider, a phase-locked loop (PLL) and a frequency-offset calibration unit. The frequency divider couples to the oscillator. The phase-locked loop couples to the frequency divider. The frequency-offset calibration unit couples to the frequency divider and the phase-locked loop. The oscillator is configured for operatively generating an oscillating signal having an oscillating frequency. The frequency divider divides the oscillating signal having the oscillating frequency by a first division parameter to generate a first clock signal having a first reference frequency. The phase-locked loop generates a second clock signal having a second reference frequency according to the first clock signal. The frequency-offset calibration unit is configured for operatively generating the first division parameter according to the second clock signal. | 05-05-2016 |
| 20160132452 | PCI EXPRESS FABRIC ROUTING FOR A FULLY-CONNECTED MESH TOPOLOGY - A PCIe Fabric that includes an IO tier switch, hub tier switches, and a target device connected to one of the hub tier switches. The IO tier switch is configured to receive a TLP from a client, make a determination that an address in the TLP is not associated with any multicast address range in the first IO tier switch and is not associated with any downstream port in the first IO tier switch, and, based on the determinations, route the TLP to the first hub tier switch via a upstream port on the IO tier switch. The hub tier switch is configured to make a determination that the TLP is associated with a multicast group, and, based on the determination, generate a rewritten TLP and route the rewritten TLP to a target device via a downstream port on the hub tier switch. | 05-12-2016 |
| 20160132455 | CONTROL METHOD APPLIED TO OPERATING-MODE FINITE-STATE-MACHINE AND COMPUTER READABLE MEDIA - A control method applied to an Operating-Mode Finite-State-Machine (OPFSM) arranged for deciding a behavior of a first port of an apparatus includes: controlling the OPFSM to enter a second local state from a first local state and controlling the first port to send a signal with a wakeup pattern to a link partner of the first port when the state of the OPFSM is the first local state, and a wakeup request bit is a first local value. | 05-12-2016 |
| 20160140073 | PROGRAMMABLE VALIDATION OF TRANSACTION REQUESTS - A data processor includes an input/output bridge that provides enforcement of a security status on transactions between devices across the bridge. The bridge includes circuitry to parse a received request to obtain one or more identifiers, and compare the identifiers against one or more programmable lookup tables. Based on this comparison, the bridge can determine the security status of the transaction, as well as selectively forward the transaction based on the security status. | 05-19-2016 |
| 20160140077 | SERIAL COMMUNICATION SYSTEM, COMMUNICATION CONTROL UNIT, AND ELECTRONIC DEVICE - To provide a serial communication system that can flexibly or easily change a system configuration. For example, when coupled to first and second serial buses, a motor module transmits a first signal to the second serial bus. Subsequently, the motor module transmits a first command containing a candidate address to the first serial bus; meanwhile, the motor module searches for an address where an acknowledgement is not received in response to the first command. The motor module transmits the search result address to the second serial bus. A control unit at the reception of the first signal changes to a sleep state that stops communications with the first serial bus and receives an address as a search result from the second serial bus. | 05-19-2016 |
| 20160147676 | PERIPHERAL COMPONENT INTERCONNECT (PCI) DEVICE AND SYSTEM INCLUDING THE PCI - A peripheral component interconnect (PCI) device includes a PCI register including a base address register (BAR) configured to determine a first memory area accessed by a PCI host, an offset register configured to store an offset transmitted from the PCI host, an address translation unit (ATU) configured to detect an operation of the PCI host writing the offset to the offset register and to change an accessed area by the PCI host to a second memory area based on the offset stored in the offset register, and a device memory including the first memory area and the second memory area, the device memory configured to store data transmitted from the PCI host and to transmit data stored therein to the PCI host. | 05-26-2016 |
| 20160147684 | IN-BAND INTERRUPT TIME STAMP - System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A method performed by a slave device coupled to a serial bus includes detecting an event related to a function of the slave device, initiating a first counter in the slave device, asserting an in-band interrupt request by driving at least one signal on the serial bus, and transmitting content of the first counter to a bus master coupled to the serial bus during an interrupt handling procedure. The first counter may count cycles of a clock used by the slave device or occurrences of a signaling state or condition on the serial bus. The content of the first counter may be used to determine a time stamp for the event. | 05-26-2016 |
| 20160147702 | COMMUNICATION CONTROL DEVICE, METHOD OF COMMUNICATING A FRAME, AND STORAGE MEDIUM - A communication control device includes a plurality of ports, a memory, and a processor. The memory stores one or more pieces of identification information correlated with each of one or more of the plurality of ports to which a communication device has been coupled, the one or more pieces of identification information being included in a frame for transmission of the frame by one or more communication devices each coupled to the one or more ports. The processor outputs, to the plurality of ports, a frame in which has been set second identification information regarding which determination will be made at the one or more communication devices that the frame is to be discarded, instead of the first identification information, when first identification information in a frame received at a first port of the one or more ports is not stored in the memory correlated with the first port. | 05-26-2016 |
| 20160179730 | HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS | 06-23-2016 |
| 20160179736 | CHIP PROCESSING DEVICE AND METHOD FOR CHIP PROCESSING USING THE SAME | 06-23-2016 |
| 20160179746 | COORDINATING MULTIPLE REAL-TIME FUNCTIONS OF A PERIPHERAL OVER A SYNCHRONOUS SERIAL BUS | 06-23-2016 |
| 20160188510 | METHOD FETCHING/PROCESSING NVMe COMMANDS IN MULTI-PORT, SR-IOV OR MR-IOV SUPPORTED PCIe BASED STORAGE DEVICES - A method of fetching I/O commands received from a host in a Peripheral Component Interconnect Express (PCIe) device includes; assigning priority to PCIe functions in the host, fetching a PCIe function from among the PCIe functions based on an assigned priority, selecting a host command queue associated with the selected PCIe function, and indicating the selected host command queue, as well as a number of commands to be fetched from the selected command queue. | 06-30-2016 |
| 20160188519 | METHOD, APPARATUS, SYSTEM FOR EMBEDDED STREAM LANES IN A HIGH-PERFORMANCE INTERCONNECT - In an example, a high-performance interconnect (HPI) is provisioned without a separate stream lane. To provide equivalent functionality, stream lane data are provided within data lines during idle periods. Because one stream lane may be provided per 20 data lanes, elimination of the stream lane saves approximately 5% of area. In a pre-data time, the 20 data lanes may be brought high from midrail to represent one species of data (for example, Intel® in-die interconnect (IDI)), and brought low to represent a second species of data (for example, Intel® on-chip system fabric (IOSF)). To represent additional species of data, such as link control packets (LCPs) for example, lanes can be divided into two or more groups, and a single bit can be encoded into each group. LCP can also be encoded into a post-data time, for example by ceasing flit traffic and manipulating a “VALID” lane from midrail to 0 or 1. | 06-30-2016 |
| 20160188520 | ELECTRONIC DEVICE AND DATA TRANSMISSION SYSTEM - The present disclosure relates to an electronic device and a data transmission system. A first electronic device includes a micro universal serial bus (USB) interface, a central processing unit (CPU) and a diode, wherein a pull-circuit for an identity (ID) pin of the CPU is coupled to a line between the ID pin of the CPU and an ID pin of the micro USB interface; the diode is coupled between the ID pin of the CPU and the ID pin of the micro USB interface, and is coupled between the pull-up circuit and the ID pin of the micro USB interface; the diode has a conducting direction from the ID pin of the CPU to the ID of the micro USB interface. With the present disclosure, the electronic device may be prevented from being damaged. | 06-30-2016 |
| 20160188523 | LOWER-POWER SCRAMBLING WITH IMPROVED SIGNAL INTEGRITY - An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal. | 06-30-2016 |
| 20160203091 | MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME | 07-14-2016 |
| 20160203099 | SYSTEM ON CHIP FOR PACKETIZING MULTIPLE BYTES AND DATA PROCESSING SYSTEM INCLUDING THE SAME | 07-14-2016 |
| 20180024959 | MOBILE COMPUTING DEVICE RECONFIGURATION IS RESPONSE TO ENVIRONMENTAL FACTORS INCLUDING DOWNLOADING HARDWARE AND SOFTWARE ASSOCIATED WITH MULTIPLE USERS OF THE MOBILE DEVICE | 01-25-2018 |
| 20190146934 | DEVICE PROGRAMMING SYSTEM WITH PROTOCOL EMULATION | 05-16-2019 |
| 20190146943 | Method and Apparatus for Host Adaptation to a Change of Persona of a Configurable Integrated Circuit Die | 05-16-2019 |
| 20220138141 | USB MODULE - A USB module includes a first USB port configured to connect a first USB-compatible device with a first USB cable and a USB plug, and a second port configured to connect a second USB-compatible device with a second USB cable. The USB cables are multi-core and respectively comprise first and second configuration lines. An interface is arranged between the first USB port and the second port in a housing interior of a housing of the USB module. The interface makes at least the first configuration line connectable to the second configuration line. The interface comprises a semiconductor module configured to reference to a ground potential of the USB module at least one output signal at the USB module on a configuration connection between the first and second configuration lines. | 05-05-2022 |
