| Entries |
| Document | Title | Date |
|---|
| 20080201507 | Bus system and methods of operation thereof - A bus system and methods for initialization and communication in a bus system are presented. | 08-21-2008 |
| 20080215778 | APPARATUS AND METHOD FOR IDENTIFYING DEVICE TYPE OF SERIALLY INTERCONNECTED DEVICES - A memory controller is unaware of device types of a plurality of memory devices in a serial interconnection configuration. Possible device types include, e.g., random access memories (DRAM, SRAM, MRAM) and NAND-, NOR- and AND-type Flash memories. Each device has device type information on its device type. Each device is capable of performing a “+1” to an input search number. First, the memory controller sends a specific device type (“don't care”) and an initial search number. Each device performs the “+1” calculation. The last device provides the memory controller with an Nד+1” search number from which the memory controller can recognize the total number of devices in the serial interconnection configuration. Thereafter, the memory controller sends a pre-determined device number for device type matching. Each device performs device type match determination of “previous match”, “present match” and “don't care match” and based on the match determination, the input search number is or is not modified and propagated through the devices. From the propagated search number, the memory controller can identify the device type of each device. | 09-04-2008 |
| 20080228970 | EMBEDDED SYSTEM DESIGN THROUGH SIMPLIFIED ADD-ON CARD CONFIGURATION - Methods for configuring an embedded system are described. One method includes connecting a plurality of add-on cards to a circuit board having a programmable processor. The programmable processor is configured to communicate with the plurality of add-on cards. At least one add-on card connects to a circuit board utilizing two or more connectors. The method also includes determining an identifier of each of the plurality of add-on cards, where the identifier of each of the plurality of add-on cards is used to generate a configuration image. Further included is configuring the programmable processor to communicate with the plurality of add-on cards by obtaining the configuration image. In some examples, the programmable processor is an FPGA. | 09-18-2008 |
| 20080228971 | Device modeling in a multi-core environment - A method and apparatus for modeling devices in a multi-core environment is herein described. A hardware offload engine or add-in device is modeled by offload engine code or device model code stored in memory. An event agent in a hypervisor traps accesses to the offload engine or add-in device and routes them to at least one core of a multi-core processor to be serviced. The core of the multi-core processor executes the offload engine code or device model code to emulate the physical hardware offload engine or add-in device to service the access. Therefore, virtual devices may be provided by providing virtual device code, allowing upgrade of a computer system without adding physical hardware. | 09-18-2008 |
| 20080244125 | Method and Apparatus for Non-Disruptively Unassigning an Active Address in a Fabric - A non-disruptive unassignment of an address from a fabric responsive to a request from a channel adapter. A logout command requests the fabric to unassign an address. The status of the address is thereby changed from active to unassigned and an acknowledgment sent back to the channel adapter. | 10-02-2008 |
| 20080244126 | METHOD AND APPARATUS FOR CHAINING MULTIPLE INDEPENDENT HARDWARE ACCELERATION OPERATIONS - Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple independent hardware acceleration operations within a circuit card assembly. Multiple independent hardware accelerators can be configured on a single circuit card assembly that is coupled to a computing device. The computing device can generate a playlist of hardware acceleration operations identifying hardware accelerators and associated accelerator options. A task management unit on the circuit card assembly receives the playlist and schedules the hardware acceleration operations such that multiple acceleration operations may be successively chained together without intervening data exchanges with the computing device. | 10-02-2008 |
| 20080288681 | Devices with multiple functions, and methods for switching functions thereof - Devices with multiple functions and methods for switching functions thereof are provided. The device comprises a plurality of hardware components, a plurality of functional modules, an input device, and a processing module. Each functional module corresponds to one of the functional connecting configurations for the hardware components. The processing module executes one of the functional modules and drives the hardware components according to the functional connecting configuration corresponding to the executed functional module. The processing module determines whether to generate a switch command according to an input command received by the input device. When the switch command is generated, the processing module directly terminates the functional module being currently executed and adjusts to execute another functional module, and drives the hardware components according to the functional connecting configuration corresponding to the functional module to be executed. | 11-20-2008 |
| 20080288682 | Database Contention and Deadlock Detection and Reduction Within Application Servers - A method in a data processing system for detecting and reducing database contention and deadlock caused from within an application server. A determination is made as to whether a set of parameters in a statistical model indicates contention. If the set of parameters in the statistical model indicates contention, an application server administrator is notified of the contention and the number of threads in an application server pool is reduced. If the set of parameters in the statistical model indicates contention is reduced, the number of threads in the application server pool is increased. | 11-20-2008 |
| 20080320188 | Method And Apparatus For Backing Up TCP Connection - A method for backing up a TCP connection includes a data transmission process and a data receiving process. The data transmission process includes obtaining, by an AMB of a transmitting end, boundary information of data; and backing up the data and the boundary information of the data to a SMB of the transmitting end. The data receiving process includes backing up, by the SMB, data received from a peer side of the TCP connection and the boundary information of the data received by the peer side to the AMB; and deleting the data received by the peer side from the data backed up by the SMB during the transmission process according to the boundary information of the data received by the peer side. The disclosure also provides an apparatus for backing up a TCP connection. | 12-25-2008 |
| 20090006683 | STATIC POWER REDUCTION FOR MIDPOINT-TERMINATED BUSSES - A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well. | 01-01-2009 |
| 20090006684 | Backplane - There is described a backplane with connections for connecting functional units. The backplane has hardware resources to handle software tasks, wherein the hardware resources are redundantly implemented or comprise essentially identical hardware modules, and wherein the hardware resources are organized in such that the software tasks are dynamically assigned to the hardware resources. | 01-01-2009 |
| 20090006685 | Computer Server System and Computer Server for a Computer Server System - A computer server system comprises multiple computer server units, each computer server comprising a server processing system. Each computer server comprises a local subsystem access module which is standardized for the multiple computer servers and which provides virtual control function for a single instantiation of a hardware resource of the computer server system, wherein the hardware resource is shared between each of the computer servers. | 01-01-2009 |
| 20090043931 | AUTOMATIC CONFIGURATION OF A COMMUNICATION PORT AS TRANSMITTER OR RECEIVER DEPENDING ON THE SENSED TRANSFER DIRECTION OF A CONNECTED DEVICE - A communications port is implemented for configuration in direction and arrangement. According to an example embodiment of the present invention, a communications link, such as a PCI Express type link, is configurable for communicating with devices having different directional and/or polarity configurations. The communications link is configured to match a communications port condition (e.g., a directional and/or polarity condition) of a device coupled to the communications link. In one instance, the communications link is directionally configurable for reassigning input lanes to output lanes and output lanes to input lanes. With this approach, the communications link can be used to communicate with a variety of devices having varied communication characteristics. | 02-12-2009 |
| 20090049213 | Computers having USB buses, methods of operation thereof and programs and information for use therewith - A computer has a USB bus with at least two USB connectors for removable USB devices. When a removable USB device is connected to at least one of the connectors, conventional standard actions are auto-launched. However, when a removable USB device is connected to at least one special USB connector, no action is auto-launched, or some non-standard action is auto-launched. The special USB connector is designated as such by a configuration file stored by the computer, because neither the USB address and port number of the hub for the special connector, nor the USB address allocated to the removable USB device can simply be used for this purpose. | 02-19-2009 |
| 20090049214 | GRAPHICS CARD TEST METHOD - A method for testing graphics cards is provided. The method utilizes a principle that when an operating system operates under a kernel layer, a CPU of the computer has privileges to execute any instructions, thus, able to perform privileged functions of a graphics card, thereby testing hardware acceleration functions of the graphics card. Utilizing the above method can test self-owned brand graphics cards before the GPU manufactured provides a formal graphics card driver of the graphics cards, and avoids abnormal situations resulting in bad communication between a graphics card test program and an informal graphics card driver of the graphics cards. | 02-19-2009 |
| 20090063737 | Portable amplified stethoscope with recording capability - The present invention relates to an improved design for a stethoscope. The invention is a stethoscope with a built-in amplifier and a memory stick to digitally record sounds as well as patient information. The present invention will be able to digitally record the sounds from the stethoscope through the use of an electronic amplification system and a built in memory stick. This system will also have a USB Port that allows the invention to communicate with a computer system. The medical practitioner will also be able to digitally hear the patient sounds with a set of head-phones or through the use of a Bluetooth system. | 03-05-2009 |
| 20090083460 | Re-configurable bus fabric for integrated circuits - The present invention relates to a flexible and reconfigurable bus fabric for microelectronic processing units, which can offer efficient memory data management, together with efficient data transfer and relieving data transfer congestion in an integrated circuit. In an embodiment, the present reconfigurable bus fabric comprises a multistate intersection between two data buses. Preferably, the multistate intersection comprises at least two states, a connecting state connecting the two data buses, and a disconnecting state disconnecting the two data buses. The multistate intersection provides a reconfigurable bus fabric, allowing different connection configuration for the data buses. This reconfigurable bus fabric offers soft-configurability and soft-reconfigurability, using software programming to arrange the circuits' interconnections. Other configurations are also disclosed in exemplary embodiments. | 03-26-2009 |
| 20090083461 | Soft-reconfigurable massively parallel architecture and programming system - The present disclosure provides a methodology for reducing congestion of a processing unit, preferably by configuring a plurality of functional blocks to run in parallel or in series without the influence or input from the processing unit. In an embodiment, the present method chains a plurality of functional blocks together by software so that one functional block starts after the completion of another functional block. The configuration of the chain can be series, parallel, and any combination thereof, arranged to meet the circuit's objective. The chaining can be configured and re-configured, preferably by software input. The chaining can also be performed at design time or at run time. The chaining can also be modified, preferably at design time, but can also be modified at run time. | 03-26-2009 |
| 20090094396 | MODULE FOR REPRODUCING A TRANSMITTER SIGNAL - The invention relates to a module for reproducing a transmitter signal (x | 04-09-2009 |
| 20090113095 | COMPUTER WITH COMPOUND AUDIO INTERFACE - An exemplary computer with compound audio interface includes a chassis, a USB interface arranged in the chassis, an audio interface arranged in the chassis, and a switch arranged in the chassis. The USB interface includes two signal terminals and a ground terminal. The audio interface includes two audio signal terminals and a ground terminal, wherein the audio signal terminals and the ground terminal of the audio interface are connected to the signal terminals and the ground terminal of the USB interface via the switch respectively. The audio signals received by the USB interface can be transmitted to an audio system in the chassis via the audio interface. | 04-30-2009 |
| 20090125655 | ENABLING SAS EXPANDER LOOPS FOR INCREASED FAIRNESS AND PERFORMANCE - The use of loops in SAS networks is enabled by designating ports connected to loop connections as table loop ports (TLPs). Under normal operating conditions, each TLP is blocked from receiving BCNs, appears to the expander to have nothing connected to it, and is made invisible to initiators. The loop connection and TLPs may be enabled and used to access devices when a problem is detected. In particular, the TLP will now appear in a list of destination ports within the expander to which a BCN should be propagated. In addition, during a subsequent self-configuration, the TLP is allowed to populate its route table with devices accessible through it, and the existence of the TLP is also reported back to initiators. After re-discovery is complete, communications between the initiator and a target can resume, with traffic re-routed through the TLPs as needed, bypassing the failure point. | 05-14-2009 |
| 20090125656 | Method and Arrangement for the Automatic Configuration of a Master-Slave Field Bus System - A field bus system ( | 05-14-2009 |
| 20090132741 | COMMUNICATION CHANNEL CALIBRATION USING FEEDBACK - A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component. | 05-21-2009 |
| 20090150583 | Video data processing module furnished with a configurable video processing unit with a single input bus - According to the invention, the video data to be processed and the configuration data are transferred to the module via one and the same data bus. These modules are advantageously chained in series on a common bus which transfers to each module both the configuration data and the video data to be processed. Preferably, dead time or “blanking” periods between two picture frames transmitted on this bus are used in order to insert the configuration data. | 06-11-2009 |
| 20090157923 | Method and System for Managing Performance Data - The present invention is directed to a method and system for managing performance data. In accordance with a particular embodiment of the present invention, cache metrics are received. At least one of the cache metrics may be compared with a threshold value. A determination may be made as to whether one or more parameter adjustments are required based upon the comparison. | 06-18-2009 |
| 20090157924 | METHOD AND APPARATUS FOR CONFIGURING ELECTRONIC DEVICES TO PERFORM SELECTABLE PREDEFINED FUNCTIONS USING DEVICE DRIVERS - A multifunctional mobile telephone handset is connected to a PC using a Universal Serial Bus. During bus enumeration, a device class descriptor is returned by the handset to the PC. The PC's operating system receives information relating to one of the functions of the handset and assigns an appropriate device driver. | 06-18-2009 |
| 20090164677 | TIMING ADJUSTMENT IN A RECONFIGURABLE SYSTEM - This disclosure provides a method for adjusting system timing in a reconfigurable memory system. In a Dynamic Point-to-Point (“DPP”) system, for example, manufacturer-supplied system timing parameters such as access latency and maximum clock speed typically reflect a worst-case configuration scenario. By in-situ detecting actual configuration (e.g., whether expansion boards have been inserted), and correspondingly configuring the system to operate in a mode geared to the specific configuration, worst-case or near worst-case scenarios may be ruled out and system timing parameters may be redefined for faster-than-conventionally-rated performance; this is especially the case in a DPP system where signal pathways typically become more direct as additional modules are added. Contrary to convention wisdom therefore, which might dictate that component expansion should slow down timing, clock speed can actually be increased in such a system, if supported by the configuration, for better performance. | 06-25-2009 |
| 20090172223 | Method and Apparatus for Distributing Configuration Files in a Distributed Control System - The invention described herein provides a system and method for distributing and applying a configuration file from a master device ( | 07-02-2009 |
| 20090182915 | Performing a Configuration Virtual Topology Change and Instruction Therefore - In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU. | 07-16-2009 |
| 20090182916 | SERVER, AND METHOD OF RECOVERY FROM LINK FAILURE IN SERVER - In a server composed of a server module having a processor in it, an I/O module having an I/O extension slot for accommodating an I/O extension adapter to expand the server's I/O capability, and a management module managing the entire server, the server module and the I/O extension slot (and through it, ultimately the I/O extension adapter) are interconnected using a PCI Express interface and the I/O module and the management module are interconnected using a special interface carrying detection information indicating whether an I/O extension adapter is actually mounted on the I/O extension slot. In the event of a link failure on the PCI Express interface, link recovery is attempted by grasping the status of the link based on the detection information obtained through the special interface. | 07-16-2009 |
| 20090193162 | COORDINATED ACTIONS OF KERNEL AND USERSPACE COMPONENTS - A system for and method of coordinating actions of components between userspace and kernel are described. The system comprises a processor; zero or more hardware components coupled with the processor; and a memory coupled with the processor and comprising a set of processor-executable instructions. The instructions comprise a component handling state machine responsive to at least one of a kernel component or a userspace component; and at least one component interface thread in communication with the component handling state machine and configured to interact with at least one of the zero of more hardware components responsive to a signal from the component handling state machine. | 07-30-2009 |
| 20090204736 | COMPUTING DEVICE WITH FLEXIBLY CONFIGURABLE EXPANSION SLOTS, AND METHOD OF OPERATION - A computing device that allows for a flexible allocation of bandwidth among peripheral devices using a peripheral bus is disclosed. The computing device includes a peripheral bus and at least two slots. The computing device may be used with a single peripheral card or multiple peripheral cards. In a multi-card configuration the invention allows the bandwidth on the peripheral bus to be shared by all the cards. In a single-card configuration, the computing device allows available bandwidth on the peripheral bus to be used by a single card. The device is particularly useful with PCI express compliant expansion cards, such as graphics adapters. | 08-13-2009 |
| 20090216924 | Interconnection system - An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing. | 08-27-2009 |
| 20090234995 | MOTHERBOARD DETECTION OF COMPUTER CHASSIS TYPE - A computer motherboard detects the form factor type of the chassis in which it is installed to permit tailoring functionality accordingly. | 09-17-2009 |
| 20090240853 | Method and apparatus for configuring a bus network in an asset management system - A method and system for managing assets includes a controller area network bus having a first end and a second end. One or more sensor systems are connected to the network bus. The sensor systems are connected to one or more assets to obtain at least one of operational data and condition data for the one or more assets. A self-healing bridge is connected to the first end and the second end of the network bus and is adapted to minimize a loss of connectivity in the network bus. | 09-24-2009 |
| 20090240854 | Multiple Removable Non-Volatile Memory Cards Serially Communicating With a Host - Two or more very small encapsulated electronic circuit cards to which data are read and written are removably inserted into two or more sockets of a host system that is wired to the sockets. According to one aspect of the disclosure, command and response signals are normally communicated between the host and the cards by a single circuit commonly connected between the host and all of the sockets but during initialization of the system a unique relative card address is confirmed to have been written into each card inserted into the sockets by connecting the command and status circuit to each socket one at a time in sequence. This is a fast and relatively simple way of setting card addresses upon initialization of such a system. According to a second aspect of the disclosure, the host adapts to transferring data between it and different cards of the system over at least two different number of the data lines commonly connected between the host and all of one or more sockets, each card permanently storing a host readable indication of the number of parallel data lines the card is capable of using. This allows increasing the rate of data transfer when the need justifies an increased card circuit complexity. According to a third aspect of the disclosure, a serial stream of data is sent over a number of data lines from one to many by alternately connecting bits of the stream to a particular number of individual lines. | 09-24-2009 |
| 20090248926 | System for automating storage device swaps and/or replacements - A storage device manipulation system for implementing communications between a set of storage devices and a midplane is described. The storage device manipulation system may comprise a receiver and a communication system. The receiver may be configured to receive a command and generate a stimulus corresponding to the command. The communication system may be communicatively connected to the receiver and may be communicatively connectable to the set of storage devices and the midplane. The communication system may be configured to implement communication between the set of storage devices and the midplane based upon the stimulus by selectively providing power to the storage devices in the set of storage devices, selectively providing power to the ports on the midplane, and selectively establishing communication between the storage devices and the ports. | 10-01-2009 |
| 20090259782 | APPARATUS AND METHOD FOR AUTOMATICALLY PERFORMING SYSTEM CONFIGURATION - An apparatus and a method for automatically performing system configuration are provided. The apparatus includes a motherboard and a peripheral backplane. The motherboard includes a data transmission interface and has a plurality of predetermined messages, and the peripheral backplane includes a sensor. The motherboard is coupled to the peripheral backplane through the data transmission interface. The sensor disposed on the peripheral backplane identifies the type of a system in which the apparatus is applied and generates an identification code corresponding to the system type. The motherboard then selects one of the predetermined messages as a configuration message according to the identification code and automatically performs system configuration to peripheral devices by using the configuration message. | 10-15-2009 |
| 20090276552 | MOTHERBOARD AND POWER MANAGING METHOD FOR GRAPHIC CARD INSTALLED THEREON - A motherboard and a power managing method for a graphic card installed thereon are provided. When the motherboard is switched to a second performance mode from a first performance mode, a microcontroller in the motherboard outputs a regulation signal to the graphic card through an exclusive connection interface, so as to correspondingly adjust an operation parameter of the graphic card, thus achieving better overall power saving and performance improving the effects of a computer. | 11-05-2009 |
| 20090282176 | COMPUTER SYSTEM AND METHOD FOR PROCESSING DATA SIGNAL OF MEMORY INTERFACE THEREOF - A computer system and a method for processing a data signal of a memory interface thereof are provided. The computer system includes a memory module, a memory controller, and a digital signal processor. The memory controller accesses data temporarily stored in the memory module through a data bus. The digital signal processor processes varied data on the bus according to a select code to recover the data. | 11-12-2009 |
| 20090307398 | Method for Manufacturing Memory Modules - In a method for manufacturing memory modules MM, first a support board SB is populated with memory components MC. After the populating process, individual memory components MC are programmed via a bus system BS provided on the support board. After programming, the support board SB is separated into individual memory modules MM. | 12-10-2009 |
| 20090327539 | Multiple Die System Status Communication System - Suitably arranged circuits located on a die surface are operatively connected via a shared link which is configured for carrying data information content between the suitably arranged circuits. A suitably arranged and configured system status signal is transferred between a first of the suitably arranged circuits and a second of the suitably arranged circuits via the shared link for mirroring a system status of the first of the suitably arranged circuits in the second of the suitably arranged circuits. | 12-31-2009 |
| 20090327540 | System and Method for Determining a Bus Address for a Controller Within a Network - A system and a method for determining a bus address for a controller within a network are provided. The method includes coupling a first set of pins of a wire harness connector to a second set of pins of a PCB connector of the controller. The method further includes sampling voltages of a portion of the first set of pins of the PCB connector to determine a wire harness ID utilizing a microprocessor. The method further includes accessing a look-up table from a memory device to select the bus address for the controller using the wire harness ID utilizing the microprocessor. The look-up table includes a plurality of bus addresses correspondingly associated with a plurality of wire harness IDs. The method further includes storing the selected bus address in the memory device utilizing the microprocessor. | 12-31-2009 |
| 20090327541 | ADAPTABLE DATAPATH FOR A DIGITAL PROCESSING SYSTEM - The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided. | 12-31-2009 |
| 20100005204 | Power optimized dynamic port association - A method, device, system, and computer readable medium are disclosed. In one embodiment the method includes dynamically associating a newly active port in a computer system with a first host controller. The first association happens when a total number of currently active ports in the computer system is less than a maximum capacity number of ports for the first host controller. The method also includes dynamically associating the newly active port in the computer system with a second host controller. The second association happens when the total number of currently active ports in the computer system is greater than or equal to the maximum capacity number of ports for the first host controller. In this method, each port, the first host controller, and second host controller all utilize the same protocol. | 01-07-2010 |
| 20100017549 | MECHANISM TO FLEXIBLY SUPPORT MULTIPLE DEVICE NUMBERS ON POINT-TO-POINT INTERCONNECT UPSTREAM PORTS - A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed. | 01-21-2010 |
| 20100030934 | Bus Termination System and Method - A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus. | 02-04-2010 |
| 20100036983 | PROCESSING MODULE, INTERFACE, AND INFORMATION HANDLING SYSTEM - A processing module, interface, and information handling system are disclosed. According to an aspect, a processing module can include a plurality of components coupled to a circuit card operable to be coupled to a host processing system. The processing module can also include a processing module interface configured to be coupled to a host interface of the host processing system. According to an aspect, the processing module interface can include a plurality of contacts operable to couple a plurality of signals configured to be coupled between the host processing and the circuit card to enable or disable use of resources of the circuit card during a reduced operating state of the host processor. | 02-11-2010 |
| 20100042765 | Dynamically Migrating Channels - In one embodiment, the present invention includes a method of determining a relative priority between a first agent and a second agent, and assigning the first agent to a first channel and the second agent to a second channel according to the relative priority. Depending on the currently programmed status of the channels, information stored in at least one of the channels may be dynamically migrated to another channel based on the assignments. Other embodiments are described and claimed. | 02-18-2010 |
| 20100057957 | RECONFIGURABLE FADEC FOR GAS TURBINE ENGINE - A reconfigurable FADEC includes a reconfigurable CPU configured for performing digital computing functions. A reconfigurable MSPD communicates with the CPU and is configured for performing analog I/O functions. A data bus is coupled to the CPU and the MSPD. The data bus is configured for connecting the CPU and the MSPD to an external connector. | 03-04-2010 |
| 20100095033 | PERFORMING A CONFIGURATION VIRTUAL TOPOLOGY CHANGE AND INSTRUCTION THEREFORE - In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU. | 04-15-2010 |
| 20100131684 | SHARING RESOURCES IN MULTI-DICE STACKS - Apparatus, systems, and methods for configuring a plurality of stacked semiconductor dice with unique identifiers and identifying a die in the stack using the unique identifier are provided. Additional apparatus and methods are disclosed. | 05-27-2010 |
| 20100131685 | HARDWARE CONFIGURATION INFORMATION SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT - A method for determining configuration information to be reported comprises accessing a table corresponding to a configuration resource associated with the configuration information, wherein the table comprises an entry for each hardware configuration definition to be built for the configuration resource, identifying a seed value in the table corresponding to the configuration resource, and modifying the seed value based on a result of processing each entry indicated by the table. | 05-27-2010 |
| 20100146168 | System and method of inter-connection between components using software bus - A method for inter-connection between components using a software bus, which may analyze whether a port in which at least one component is connected with each other is a data transmission port or a function interface calling port in accordance with an application of the port, determine an execution attribute of the port based on an analyzed result, and control the port in accordance with the execution attribute of the port. The function interface calling port may be divided into any one of a thread generation-connection port for each request using an attribute of an on-demand function calling port, or a recursive server connection port using an attribute of an on load function calling port in accordance with a type of the called port. | 06-10-2010 |
| 20100161858 | ADDRESS CONVERSION SYSTEM AND METHOD - An address conversion system is applied for a numerical control device and connected between a software inner address unit and a hardware contact point address unit. The address conversion system includes an address editing unit and an address conversion unit. The address editing unit includes an address display module and an address editing module. The address display module is configured for displaying hardware device startup addresses stored in the software inner address unit via an address display interface. The address editing module is configured for displaying contact point addresses stored in the hardware contact point address unit via an address editing interface. The contact point addresses are capable of being amended in the address editing interface. The address conversion unit is configured for matching the hardware device startup addresses with the corresponding contact point address. | 06-24-2010 |
| 20100169523 | Scalable method and apparatus to configure a link - Disclosed herein are reconfigurable ports and methods for doing the same. | 07-01-2010 |
| 20100185798 | Method and communications system for the configuration of a communications module containing a logic component - The invention relates to a method according to which a cycle-oriented control program generated for a programmable logic controller ( | 07-22-2010 |
| 20100191881 | System and Method for Reserving and Provisioning IT Resources - A method for reserving and provisioning IT resources comprises receiving, from a user, a request to reserve a desired configuration of IT resources. The desired configuration comprises one or more desired technical specifications and a desired reservation time having a start time and an end time. The method further comprises accessing an IT resource database to determine one or more of a plurality of resource pools that the user has access to. The one or more resource pools are consulted to determine if one or more IT resources matching the desired configuration are available. If the one or more IT resources matching the desired configuration are available, the one or more IT resources are reserved for the user and provided to the user at the start time. | 07-29-2010 |
| 20100223408 | APPARATUS FOR NON-DISRUPTIVELY DISCONNECTING A PERIPHERAL DEVICE - An electronic device includes a communication bus having a physical layer for interacting with a peripheral device. The physical layer is configured to be adjacent to a link layer on the peripheral device. The electronic device further includes a connector at a junction of the physical layer and the link layer. Communication through the communication bus is maintained through the physical layer when the link layer of the peripheral device is disconnected from the physical layer at the connector. | 09-02-2010 |
| 20100235554 | RECONFIGURABLE POINT-TO-POINT MEMORY INTERFACE - Embodiments of an apparatus are described. An interface circuit in this apparatus receives or transmits digital signals on a bus and is configured to alternatively operate as either a data-bus interface circuit or a control-bus interface circuit in dependence upon a mode setting stored in a register. For example, the interface circuit may be pre-configured to interpret a line of an external bus as either a data line or a control line in accordance with the stored mode setting. Moreover, the stored mode setting may be dynamically configured (e.g., reprogrammed) during operation of the interface circuit so that subsequent digital signals are subsequently handled in accordance with a new mode setting. | 09-16-2010 |
| 20100268859 | Server - A server includes a motherboard, a central processing unit (CPU) and a riser card. The CPU is mounted on the motherboard. The riser card is inserted in the motherboard. The riser card includes a first circuit board extending parallel to the CPU, such that the CPU positioned between the motherboard and the first circuit board. At least one memory is inserted in the first circuit board. | 10-21-2010 |
| 20100299465 | SCALING ENERGY USE IN A VIRTUALIZED ENVIRONMENT - A method, system, and computer usable program product for scaling energy use in a virtualized data processing environment are provided in the illustrative embodiments. A set of PIOAs is configured such that each PIOAs in the set of PIOAs is a functional equivalent of another PIOAs in the set of PIOAs. A utilization of each PIOA in the set of PIOAs is measured. A number of PIOAs needed to service a workload is determined. A first subset of PIOAs from the set of PIOAs is powered down if the number of PIOAs needed to service the workload is smaller than a number of operational PIOAs. The I/O operations associated with the first subset of PIOAs are transferred to a second subset of PIOAs remaining operational in the set of PIOAs. | 11-25-2010 |
| 20100318701 | LOCATION ENABLED BOOKMARK AND PROFILE - Location based profiles are used to modify the configuration of a computing device based on a detected location. The location based profiles allow features such as cameras to be enabled and disabled. Physical and logical data storage partitions can also be mounted and unmounted, and the home screen displayed by a device can be modified. Location bookmarks can be used to further customize the appearance and function of a computing device. | 12-16-2010 |
| 20100332703 | COMPUTER UNIT, COMPUTER PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT - Improves ease of operation by making it easier for the operator to view and select storage media devices connected to a computer unit. Provides a computer unit with a USB root hub and running an operating system that has the function of managing a storage media device connected to the root hub directly or indirectly via a hub. The unit includes a topology configuration portion that, when the hub is connected to a port of the root hub and the storage media device is connected to the hub, configures the hub as a virtual drive and sets up a connection whereby a folder corresponding to the storage media device is placed in the virtual drive; and a display controller that displays on a display device a directory list DP of the connections that were configured by the topology configuration portion. | 12-30-2010 |
| 20110022751 | METHODS AND APPARATUS FOR AN IMPROVED MOTOR CONTROL CENTER - Methods, apparatus, and systems are provided for operating a motor control center. The invention includes determining a hardware configuration of functional modules within a motor control center; downloading the hardware configuration to a programmable logic controller; configuring a program to run on the programmable logic controller based on the hardware configuration; and executing the program. Numerous additional aspects are disclosed. | 01-27-2011 |
| 20110047307 | DATA TRANSFER METHOD AND DATA TRANSFER APPARATUS - A data transfer method for transferring data between a source device and a sink device includes receiving a query about a channel number included in connection plug information from the sink device and notifying the sink device of information of an unused connection plug when a channel corresponding to the channel number is unused. | 02-24-2011 |
| 20110060854 | FUNCTIONAL CONFIGURATION WIZARD - Described herein are methods and systems for configuration of complex applications. The configuration is performed by invoking from a repository of an executable checklist. The repository includes executable checklists to be used for different configuration scenarios. An executable checklist consists of all the necessary activities for a particular configuration setting. | 03-10-2011 |
| 20110093631 | ADAPTERS FOR EVENT PROCESSING SYSTEMS - Methods, systems, and computer-readable media are disclosed for implementing adapters for event processing systems. A particular system includes an input adapter configured to store event objects received from a source at an input queue. The system also includes a query engine configured to remove event objects from the input queue, to perform a query with respect to the removed event objects to generate result objects, and to insert result objects into an output queue. The system also includes an output adapter configured to remove result objects from the output queue and to transmit the result objects to a sink. | 04-21-2011 |
| 20110125939 | Function expansion apparatus, information processing apparatus, and control method - A disclosed function expansion apparatus for expanding a function of an information processing apparatus by connecting the information processing apparatus to an external storage apparatus via a first interface includes a first storage unit that stores first setup information used for connecting the information processing apparatus to the external storage apparatus, a connection module unit that is operated based on the first setup information and connects the information processing apparatus to the external storage apparatus via the first interface, a control unit that is connected to the first storage unit, and the connection module unit or a second storage unit, and stores second setup information stored in the second storage unit into the first storage unit, wherein the second storage unit is exchangeable with the connection module unit and stores the second setup information in connecting to the connection module unit. | 05-26-2011 |
| 20110161534 | Control Architectures for RF Transceivers - Described herein are devices and methods for implementing a transceiver with independently controlled components. The components may include a programmable digital portion, a dedicated digital portion, and an analog portion. Each independently controlled component includes a programmable controller that resides in the programmable digital portion of the component that controls components in the dedicated digital or analog portions using state transition information. The programmable controller is configured to accommodate a broad spectrum of state transition information and is capable of emulating a plurality of hardwired finite state machines | 06-30-2011 |
| 20110161535 | ADAPTABLE DATAPATH FOR A DIGITAL PROCESSING SYSTEM - The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided. | 06-30-2011 |
| 20110246691 | METHOD AND APPARATUS FOR COHERENT DEVICE INITIALIZATION AND ACCESS - A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base address of a memory space and a second set of IPIs is sent to indicate a size of the memory space. Furthermore, similar methods and apparatus' are herein described for dynamic reconfiguration of an accelerator device in a processor socket. | 10-06-2011 |
| 20110252167 | PHYSICAL TO HIERARCHICAL BUS TRANSLATION - In an embodiment, a translation of a physical bus number to a hierarchical bus number is written to a south chip. The south chip receives a configuration write command that comprises a physical bus number. The south chip sends the configuration write command to a device via the bus identified by the physical bus number, and the device stores the physical bus number in the device. In response to a received message from a device that comprises the physical bus number, the south chip replaces the physical bus number in the message with the hierarchical bus number. The south chip sends the message to a north chip via a point-to-point serial link. Both the physical bus number and the hierarchical bus number identify a bus with which the device connects to a bridge in the south chip. | 10-13-2011 |
| 20110264834 | RE-CONFIGURABLE MULTIPURPOSE DIGITAL INTERFACE - Systems and apparatus are provided for a reconfigurable, multi-purpose input/output (I/O) interface. The system comprises a comparator coupled to a means for signal generation. The system further comprises a switch fabric configured to reconfigure the I/O circuit in real time to perform a variety of signal processing, signal generation and built-in-test functions. | 10-27-2011 |
| 20110271020 | Node Differentiation in Multi-Node Electronic Systems - A technique for differentiating nodes in a multi-node electronic system includes establishing an intended configuration for the system, the configuration including a number of nodes to be installed and a specification of intended node locations. A node ID for each of multiple nodes to be installed in the system is established, and the multiple nodes are installed. Using the node ID established for each of the multiple nodes, a determination is made whether the multiple nodes as installed comply, with the intended configuration. | 11-03-2011 |
| 20110289245 | Memory Controller and Method Utilizing Equalization Co-Efficient Setting - A chip includes a transmitter circuit and a register provided to store a value representative of an equalization co-efficient setting. The transmitter circuit includes an output driver configured to adjust an output data signal based at least in part on the equalization co-efficient setting. | 11-24-2011 |
| 20110314194 | METHOD AND APPARATUS FOR USING A SINGLE MULTI-FUNCTION ADAPTER WITH DIFFERENT OPERATING SYSTEMS - A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface. | 12-22-2011 |
| 20120030386 | Configurable Interface Controller - A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization. | 02-02-2012 |
| 20120030387 | MECHANISM TO FLEXIBLY SUPPORT MULTIPLE DEVICE NUMBERS ON POINT-TO-POINT INTERCONNECT UPSTREAM PORTS - A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed. | 02-02-2012 |
| 20120059959 | Method for Assigning Addresses to Nodes of a Bus System, and Installation - A method for assigning addresses to nodes of a bus system, and installation, | 03-08-2012 |
| 20120072626 | Automatic Addressing Protocol for a Shared Bus - An automatic addressing protocol for a shared bus is described. In an embodiment, devices connected in a chain by a shared bus are also connected by an independent electrical connection between each pair of neighboring devices. A protocol is used over the independent electrical connections which is independent of that used on the shared bus. Devices in the chain receive at least one device ID from an upstream neighbor via the independent electrical connection and either use this received ID as their ID or use the received ID to compute their ID. Where the device has a downstream neighbor, a device then transmits at least one device ID to the downstream neighbor via the independent electrical connection and this transmitted ID may be their ID or an ID generated based on their ID, for example, by incrementing the ID by one. The process is repeated by devices along the chain. | 03-22-2012 |
| 20120072627 | DYNAMIC CREATION AND DESTRUCTION OF IO RESOURCES BASED ON ACTUAL LOAD AND RESOURCE AVAILABILITY - A method for binding input/output (I/O) objects to nodes. The method includes binding an I/O object group to a NUMA node of a plurality of NUMA nodes on a system, obtaining an I/O object group size of the I/O object group, and determining an I/O object group target size based on an I/O object group aggregate load of the I/O object group. The method further includes comparing, by the NUMA I/O Framework, the I/O object group target size and the I/O object group aggregate load, determining, by the NUMA I/O Framework, that a difference between the I/O object group target size and the I/O object group aggregate load exceeds a threshold, and instructing, by the NUMA I/O Framework, an I/O Subsystem associated with the I/O object group to change the I/O object group size, wherein the I/O Subsystem changes, in response to the instruction, the I/O object group size. | 03-22-2012 |
| 20120084471 | USB TRANSACTION TRANSLATOR AND A MICRO-FRAME SYNCHRONIZATION METHOD - The present invention is directed to a universal serial bus (USB) transaction translator and a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, wherein the counting value of the SOF counter is compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves the predefined value or is greater than the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host. | 04-05-2012 |
| 20120084472 | PROGRAMMABLE MULTIMEDIA CONTROLLER WITH FLEXIBLE USER ACCESS AND SHARED DEVICE CONFIGURATIONS - A system which includes a programmable multimedia controller is provided in which flexible user access is provided through a combination of user profiles and usernames/pas swords. A configuration for a given device which may form part of the system or may interoperate with the system may be shared by multiple similar devices. A sharable device configuration is stored by a master device and can be shared by other devices of the same type as the master device. | 04-05-2012 |
| 20120124255 | Priority Logic Module - In a nuclear process control system, a priority logic module (PLM) is provided. The priority logic module comprises a plurality of input ports, each input port associated with one of a plurality of priorities, a plurality of output ports, and a test mode select port associated with a test mode select signal. The test mode select signal selects one of a normal mode or test mode, each mode being associated with matching signals received by the input ports to signals sent by the output ports. The priority logic module further comprises a configurable priority logic circuit, wherein the priority logic circuit maps one of the input ports to one of the output ports. | 05-17-2012 |
| 20120159022 | INTEGRATION OF FIELD DEVICES IN A DISTRIBUTED SYSTEM - Exemplary embodiments are directed to a system and method for integrating field devices in an automation system having a plurality of field devices connectable via at least one bus system. A respective field device is connected to the bus system of the automation system, and is automatically addressed by a superordinate controller using a predefined default address. The device addressed using the default address then registers in the system with its device address, and a fixed address which is provided from a multiplicity of unassigned addresses from an address memory is automatically allocated to the device registered in the system. An individually assigned identification (TAG) provided from the predetermined configuration of the automation system is allocated to the allocated fixed address, and, after the automatically allocated fixed address has been transmitted to the field device, the field device is changed to a suitable state for communication with the superordinate controller. | 06-21-2012 |
| 20120159023 | Method and System for Inter-PCB Communications with Wireline Control - Aspects of a method and system for inter-PCB communications with wireline control may include setting up a microwave communication link between a first PCB and a second PCB via a wireline communication bus. The initialization may comprise adjusting beamforming parameters of a first antenna array communicatively coupled to the first PCB, and of a second antenna array communicatively coupled to the second PCB. The first PCB and the second PCB may communicate data via the microwave communication link. The microwave communication link may be routed via one or more relay PCBs, when the first PCB and the second PCB cannot directly communicate satisfactorily. Control data may be transferred between the first PCB, the second PCB, and/or the one or more relay PCBs, which may comprise one or more antennas. The relay PCBs may be dedicated relay PCBs or multi-purpose transmitter/receivers. | 06-21-2012 |
| 20120166690 | MULTI-ROOT SHARING OF SINGLE-ROOT INPUT/OUTPUT VIRTUALIZATION - In a first embodiment of the present invention, a method for multi-root sharing of a plurality of single root input/output virtualization (SR-IOV) endpoints is provided, the method comprising: CSR redirection to a management processor which either acts as a proxy to execute the CSR request on behalf of the host or filters it and performs an alternate action, downstream routing of memory mapped I/O request packets through the switch in the host's address space and address translation with VF BAR granularity, upstream routing of requests originated by I/O devices by table lookup indexed by Requester ID, and requester ID translation using a fixed local-global RID offset. | 06-28-2012 |
| 20120185624 | Automated Cabling Process for a Complex Environment - A method is provided for cabling a plurality of hardware components. A chassis controller establishes a wireless connection to a wireless device. The chassis controller, via a wireless interface, transmits a chassis map to the wireless device over the wireless connection. The chassis controller, via the wireless interface, transmits to the wireless device, an indication of a first port to be cabled over the wireless connection, the first port. The first port is of a first hardware component of the plurality of hardware components. The chassis controller tests the first port to determine whether cabling of the first port has been performed correctly. | 07-19-2012 |
| 20120185625 | Method for operating a fieldbus interface - A method for operating a fieldbus interface (FI) connected to a fieldbus of process automation technology. The method includes the following: tapping data traffic on the fieldbus by the fieldbus interface; and registering tapped configuration information relative to cyclic data traffic on the fieldbus by the fieldbus interface. | 07-19-2012 |
| 20120191885 | METHOD FOR CONFIGURING CHARGING PORTS AND CONTROLLER APPLYING THE SAME - A method for configuring charging ports and a controller applying the same are disclosed. The method includes recording a maximum permission value and a permitted value, and comparing the maximum permission value and the permitted value to determine whether the interface port can be used as a charging port when a device is connected to an interface port. | 07-26-2012 |
| 20120198110 | MAIN BOARD AND METHOD FOR DYNAMICALLY CONFIGURING PCIE PORTS THEREOF - A main board and a method for dynamically configuring PCIE ports thereof. The main board comprises a PCIE slot, a detecting circuit, an ROM, a chipset and a modifying circuit. The chipset comprises a Management Engine controller and several PCIE ports. The chipset has a Management Engine function or a similar function. The detecting circuit detects the PCIE slot to generate a current state parameter. The ROM stores a default configuration data. The modifying circuit coupled between the chipset and the ROM determines whether the default configuration data needs to be modified according to the current state parameter. When the default configuration data needs to be modified, the modifying circuit modifies the default configuration data according to the current state parameter, so that the Management Engine controller initially configures the PCIE ports according to the modified default configuration data. Thus, the dynamical configuration of the chipset PCIE ports is realized. | 08-02-2012 |
| 20120215954 | Resetting A Hypertransport Link In A Blade Server - Methods, apparatus, and computer program products are described for resetting a HyperTransport link in a blade server, including reassigning, by a blade management module, a gate signal from enabling a transceiver to signaling a HyperTransport link reset; sending, by the blade management module to a reset sync module on an out-of-band bus, the gate signal; and in response to the gate signal, sending, by the reset sync module to the blade processor, HyperTransport reset signals. The HyperTransport link includes a bidirectional, serial/parallel, high-bandwidth, low-latency, point to point data communications link. The blade server includes the blade processor, the reset sync module, and the baseboard management controller. The blade server is installed in the blade center. The blade center includes the blade management module. The blade management module is coupled to the baseboard management controller by the blade communication bus. | 08-23-2012 |
| 20120239837 | RELATIONAL ADMINISTRATION OF SAS DOMAIN MANAGEMENT DATA - Disclosed is a process that is performed by a management application for automatically mapping the topology of one domain to another domain. In addition, if a device in a domain fails, the domain application can automatically associate replacement devices with predecessor management objects. | 09-20-2012 |
| 20120254489 | BUS CONTROL FOR A DOMESTIC APPLIANCE - A domestic appliance ( | 10-04-2012 |
| 20120278518 | NON-PORTED GENERIC DEVICE (SOFTWARE MANAGED GENERIC DEVICE) - Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed. | 11-01-2012 |
| 20120278519 | UPDATING INTERFACE SETTINGS FOR AN INTERFACE - A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria. | 11-01-2012 |
| 20120284437 | PCI EXPRESS SR-IOV/MR-IOV VIRTUAL FUNCTION CLUSTERS - An apparatus, including a first multiple of virtual function clusters positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, each of the clusters comprising at least one virtual function, and a second multiple of physical functions positioned on the PCIe configuration space. The apparatus also includes an extended virtual function shell positioned on the PCIe configuration space and configured to select one of the physical functions, to select one of the available virtual function clusters and to associate the selected virtual function cluster with the selected the physical function. | 11-08-2012 |
| 20120284438 | COMPUTING SYSTEM WITH DATA AND CONTROL PLANES AND METHOD OF OPERATION THEREOF - A method of operation of an computing system includes: providing a microkernel; controlling a reconfigurable hardware device by the microkernel; configuring an event scoreboard module for monitoring the reconfigurable hardware device; and implementing an application configured in the reconfigurable hardware device including receiving a machine identifier for the reconfigurable hardware device. | 11-08-2012 |
| 20120284439 | COMPUTING SYSTEM WITH HARDWARE BUS MANAGEMENT AND METHOD OF OPERATION THEREOF - A method of operation of a computing system includes: providing reconfigurable hardware devices having a first application fragment and a second application fragment; configuring a virtual bus module having a virtual bus for coupling the reconfigurable hardware devices; allocating a physical port in the virtual bus, based on availability, for communicatively coupling the first application fragment and the second application fragment through the virtual bus; and implementing an application through the virtual bus including transferring application data between the first application fragment and the second application fragment. | 11-08-2012 |
| 20120297099 | CONTROL OVER LOADING OF DEVICE DRIVERS FOR AN INDIVIDUAL INSTANCE OF A PCI DEVICE - A method identifies a plurality of PCI devices in a computer system by an associated PCI device handle, wherein each of the PCI devices is also associated with a default EFI device driver. The method further identifies a target PCI device to be disabled from within the plurality of PCI devices, provides a dummy driver that enables fewer functions for the target PCI device than would the default EFI device driver, and binds the dummy driver to the target PCI device instead of binding the default EFI device driver associated with the target PCI device. The dummy driver may be used to effectively disable the target PCI device so that the POST does not hang up or completes faster without loading the default EFI device driver. | 11-22-2012 |
| 20120303847 | SENSOR INTERFACE ENGINEERING - A method for communication between function modules in drive engineering is described, wherein a first function module has a first sensor interface, wherein a second function module has a second sensor interface, wherein the first sensor interface is functionally assigned to the second sensor interface, wherein the first function module is assigned to a first automation component, wherein the second function module is assigned to a second automation component, wherein an address, in particular a logical address, for the transfer of sensor data is automatically specified. | 11-29-2012 |
| 20130013829 | MECHANISM TO FLEXIBLY SUPPORT MULTIPLE DEVICE NUMBERS ON POINT-TO-POINT INTERCONNECT UPSTREAM PORTS - A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed. | 01-10-2013 |
| 20130019036 | Expanded Electronic Bus Communication Capacity - In an embodiment, an apparatus comprises a bus network having a set of lines, and a number of communication system devices associated with a number of electronics equipment connected to the bus in which each communication system device configures the electronics equipment to send and receive a plurality of signals on a line of the set of lines in a noise region of the set of lines. | 01-17-2013 |
| 20130024586 | VERIFICATION OF HARDWARE CONFIGURATION - A method for verifying an input/output (I/O) hardware configuration is provided. Data from an input/output data set (IOCDS) is extracted for building a verification command. The IOCDS contains hardware requirements that define at least software devices associated with a logical control unit (LCU). The verification command is processed. The verification command includes a software device address range associated with a logical control unit (LCU) of the I/O hardware. The LCU utilizes a first logical path. The software device address range utilizing the first logical path is compared with an existing software device address range utilizing at least one additional logical path. The verification command is accepted if the software device address range and the existing software device address range match. | 01-24-2013 |
| 20130046908 | SCALABLE METHOD AND APPARATUS TO CONFIGURE A LINK - Disclosed herein axe reconfigurable ports and methods for doing the same. | 02-21-2013 |
| 20130060978 | INTEGRATED LINK CALIBRATION AND MULTI-PROCESSOR TOPOLOGY DISCOVERY - Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated. | 03-07-2013 |
| 20130060979 | MULTIPLEXED SERIAL MEDIA INDEPENDENT INTERFACE - Systems, methods, and devices are provided for a multiplexed serial media independent interface ( | 03-07-2013 |
| 20130067127 | METHOD AND APPARATUS FOR INTERLEAVING BURSTS OF HIGH-SPEED SERIAL INTERCONNECT LINK TRAINING WITH BUS DATA TRANSACTIONS - In an apparatus according to one embodiment of the present disclosure, a communications link comprises a first device and a second device communicating with each other via the communications link at a plurality of different speeds. However, prior to communicating via the communications link for the first time at a second speed, the first device and second device complete a first training cycle at the second speed. Further, during this first training cycle for the second speed, the first training cycle for the second speed will pause before the first training cycle at the second speed completes, and the first device and second device communicate at a first speed for a period of time before returning to the paused first training cycle at the second speed. When the paused first training cycle for the second speed continues, the first training cycle for the second speed will continue where it had paused. | 03-14-2013 |
| 20130073754 | APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES - A method or apparatus operates a multitude of devices in a serial interconnection configuration to establish a device identifier (ID) for each device. An input signal is transmitted through a serial interconnection to a first device using inputs that are also used by the first device to input other information thereto (e.g., data, commands, control signals). A generating circuit generates a device ID in response to the input signal. A transfer circuit then transfers an output signal associated with the device ID to a second device through a serial output of the first device. The serial output is also used by the first device to output other information (e.g., signals, data) to another device in the serial interconnection configuration. | 03-21-2013 |
| 20130097345 | ADDRESS LEARNING AND AGING FOR NETWORK BRIDGING IN A NETWORK PROCESSOR - Described embodiments process data packets received that include a source address and at least one destination address. If the destination address is stored in a memory of an I/O adapter, the received data packet is processed in accordance with bridging rules associated with each destination address stored in the I/O adapter memory. If the destination address is not stored in the I/O adapter memory, the I/O adapter sends a task message to a processor to determine whether the destination address is stored in an address table stored in a shared memory of the network processor. The I/O adapter memory has lower access latency than the address table. If the destination address is stored in the address table, the received data packet is processed in accordance with bridging rules stored in the address table and the bridging rules stored in the I/O adapter memory are updated. | 04-18-2013 |
| 20130117480 | METHOD FOR CONFIGURING STORAGE SYSTEM CONNECTION, DEVICE AND STORAGE SYSTEM - A method for configuring a connection in a storage system is provided. A configuring device determines that the configuring device cannot communicate with a first control board; searches a route information table for route information related to the first control board, wherein the route information is route information between an adapter card and the first control board, wherein the adapter card is connected to a north bridge of the first control board through a PCIe bus; modifies the searched out route information by changing an address of the first control board in the route information to an address of a second control board, and stores the modified route information in the route information table. | 05-09-2013 |
| 20130138845 | INTEGRATED CIRCUIT NETWORK NODE CONFIGURATION - An electronic device for transmitting and/or receiving data through an electronic networking bus-system having a network topology includes an analog input connector for receiving an analog input signal representative for a network location in a network topology, and a processing unit for handling network data traffic transmitted through an electronic networking bus-system having said network topology, wherein the processing unit is further adapted for determining at least one network configuration parameter for the handling of network data traffic taking into account said input signal or digitized version thereof. | 05-30-2013 |
| 20130138846 | ENHANCED DATA STORAGE DEVICE - A data storage device includes one or more data paths through electrical contacts of the data storage device. The data paths are operably connected to allow bits to be transferred into and out of the data storage device. The data storage device stores an indication of a number of the one or more data paths in a configuration register. A method includes performing, while the data storage device is operatively coupled to a host device, receiving a command of the host device to read the configuration register and providing the indication via at least one of the one or more data paths. Providing the indication enables indicating to the host device the number of the one or more data paths. | 05-30-2013 |
| 20130145062 | UNIVERSAL SERIAL BUS PRE-DETERMINING CIRCUIT - A universal serial bus pre-determining circuit for determining whether a universal serial bus is connected to a host or a device includes an input unit, a detection unit, a processing unit, and a switch unit. The input unit is connected to the host or the device. Once the input unit is connected to the host, the detection unit will enable the host, allowing the host to generate and send a synchronous signal to the input unit. Once the input unit is connected to the device, no synchronous signal will be generated. The processing unit determines accurately whether the universal serial bus is connected to the host or the device by judging the synchronous signal. | 06-06-2013 |
| 20130159572 | MANAGING CONFIGURATION AND SYSTEM OPERATIONS OF A NON-SHARED VIRTUALIZED INPUT/OUTPUT ADAPTER AS VIRTUAL PERIPHERAL COMPONENT INTERCONNECT ROOT TO MULTI-FUNCTION HIERARCHIES - A computer system includes an adapter, a processor, and a memory storing program code, the program code executable by the processor to determine the adapter is single root input/output virtualization (SR-IOV) capable, to determine that an operating system is capable of using the adapter in SR-IOV mode, to configure the adapter in SR-IOV mode by generating an SR-IOV function associated with the adapter, and to assign control of the SR-IOV function to the operating system. | 06-20-2013 |
| 20130191566 | Overcoming Limited Common-Mode Range for USB Systems - An intelligent level shifter may be added to adjust the voltage level on the data lines (D+ and D−) used for communications in USB systems, to address the issue of missing negative common-mode range as defined by the USB specification. The level shifter may be part of a port power controller that allows adaptive shifting of the signal level in accordance with the current levels drawn on the supply line by a device, for example during charging. The port power controller may be operated in systems enabled for battery charging, and may combine overcurrent sensing (current meter for VBus) and the routing of the D+ and D− lines (used for the battery charging protocol) into a single package. By varying the voltage levels on the D+ and D− data lines according to the drawn current levels, the performance of USB Hosts ports and USB Hub ports may be greatly increased. | 07-25-2013 |
| 20130212308 | MEMORY MAPPED INPUT/OUTPUT BUS ADDRESS RANGE TRANSLATION - In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge. | 08-15-2013 |
| 20130219091 | Island-Based Network Flow Processor Integrated Circuit - A reconfigurable, scalable and flexible island-based network flow processor integrated circuit architecture includes a plurality of rectangular islands of identical shape and size. The islands are disposed in rows, and a configurable mesh command/push/pull data bus extends through all the islands. The integrated circuit includes first SerDes I/O blocks, an ingress MAC island that converts incoming symbols into packets, an ingress NBI island that analyzes packets and generates ingress packet descriptors, a microengine (ME) island that receives ingress packet descriptors and headers from the ingress NBI and analyzes the headers, a memory unit (MU) island that receives payloads from the ingress NBI and performs lookup operations and stores payloads, an egress NBI island that receives the header portions and the payload portions and egress descriptors and performs egress scheduling, and an egress MAC island that outputs packets to second SerDes I/O blocks. | 08-22-2013 |
| 20130219092 | Global Event Chain In An Island-Based Network Flow Processor - An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form one or more local event rings and a global event chain. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. Each local event ring involves event ring circuits and event ring segments. In one example, an event packet being communicated along a local event ring reaches an event ring circuit. The event ring circuit examines the event packet and determines whether it meets a programmable criterion. If the event packet meets the criterion, then the event packet is inserted into the global event chain. The global event chain communicates the event packet to a global event manager that logs events and maintains statistics and other information. | 08-22-2013 |
| 20130219093 | Electrically Configurable Option Board Interface - A Main Logic Board having an electrically configurable option board interface (ECOBI) to facilitate connection of option boards into apparatus for providing optional functions. Once connected to the host, an Option board provides identification (ID) data to the main logic board host processor. The host processor determines the interface configuration necessary to enable communication between the host and the option board based on the option board ID, then configures electrically configurable interface circuitry for operational compatibility. The option board may provide an interface driver directly to the host for configuration of the interface. The interface may comprise a standard interface protocol such as PCI or USB that the host configures through the same connection to the option board. | 08-22-2013 |
| 20130227182 | Adaptable Datapath for a Digital Processing System - The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided. | 08-29-2013 |
| 20130227183 | MEMORY ACCESS DURING MEMORY CALIBRATION - A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus. | 08-29-2013 |
| 20130246673 | AUTOMATED DATA CENTER NETWORK PATCHING SYSTEM - In one embodiment, a computer implemented method is provided for generating a network patch plan. The method can include selecting at least two devices to be interconnected. The method can include selecting a role for each of the at least two devices. The method can include identifying a patching template. The method can include determining a priority order of available logical ports associated with each of the at least two devices. The method can include generating a patch plan based on the priority order. | 09-19-2013 |
| 20130282937 | PORTABLE COMMUNICATION DEVICES WITH ACCESSORY FUNCTIONS AND RELATED METHODS - Portable communication devices and related methods for use in supporting voice and/or data communication are provided. One example portable communication device includes a housing, a display device disposed at said housing, a processor disposed at least partially within said housing, the processor coupled to said display device, and an interface connector disposed at said housing and coupled to said processor. The interface connector is configured to couple to a module. The processor is configured to communicate, through said interface connector, via a plurality of communication protocols. The processor is configured to select at least one of the plurality of communication protocols based on the module coupled to the interface connector. | 10-24-2013 |
| 20130304952 | METHODS AND STRUCTURE FOR CONFIGURING A SERIAL ATTACHED SCSI DOMAIN VIA A UNIVERSAL SERIAL BUS INTERFACE OF A SERIAL ATTACHED SCSI EXPANDER - Methods and structure are provided for managing a Serial Attached SCSI (SAS) domain via Universal Serial Bus (USB) communications. The system comprises a SAS expander. The SAS expander comprises a plurality of physical links, a USB interface, and a control unit. The control unit is operable to receive USB packets via the USB interface, to determine SAS management information based upon the received USB packets, and to alter a configuration of the SAS domain based upon the SAS management information determined from the USB packets. | 11-14-2013 |
| 20130326097 | SEMICONDUCTOR DEVICE - A semiconductor device capable of implementing system configurations corresponding to various PCIe topologies is provided. A RAM stores one or more configuration registers that define function information of a PCIe device. A Link control unit decodes a request received from a PCIe host and outputs a decoded result to a CPU. The CPU reads a corresponding configuration register from the RAM based on the decoded result received from the Link control unit, and generates a response to the request and causes the Link control unit to transmit the response. Thus, system configurations corresponding to various PCIe topologies can be implemented. | 12-05-2013 |
| 20130332634 | TUNNEL SUITABLE FOR MULTI-SEGMENT COMMUNICATION LINKS AND METHOD THEREFOR - A tunnel for a communication system includes first and second bridges. The first bridge has a first port adapted to couple to a first link and a second port, and has a first programmable bus number and a first programmable function number. The second bridge has a first port coupled to the second port of the first bridge, and a second port, and has a second programmable bus number and a second programmable function number. In a hoist enabled mode, the first bridge forwards a packet on the first link to the second bridge if the second programmable bus number is equal to the first programmable bus number, a bus number of the packet is equal to the first programmable bus number, and a function number of the packet is equal to the second programmable function number. | 12-12-2013 |
| 20130346653 | VERSATILE LANE CONFIGURATION USING A PCIE PIE-8 INTERFACE - Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration. | 12-26-2013 |
| 20140006660 | METHOD AND APPARATUS FOR MONITORING AND PROCESSING SENSOR DATA IN AN INTERFACING-DEVICE NETWORK | 01-02-2014 |
| 20140032799 | Efficient Calibration of a Low Power Parallel Data Communications Channel - A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed. | 01-30-2014 |
| 20140059259 | METHOD FOR CONFIGURING AND OPERATING A MEDICAL APPARATUS WITH ELECTRONICALLY READABLE COMPONENT DESCRIPTIONS - In a method to operate a magnetic resonance tomography apparatus that includes a number of electronically controlled sub-components, the components and/or the apparatus are controlled by a control unit via sensors and actuators. All relevant configuration data and operating data are stored in respective electronic objects that are stored in an apparatus memory. An electronic object is respectively associated with each component. | 02-27-2014 |
| 20140075066 | LOW-POWER MODES OF MICROCONTROLLER OPERATION WITH ACCESS TO CONFIGURABLE INPUT/OUTPUT CONNECTORS - A microcontroller includes I/O pins whose respective functions are configurable by an I/O controller in accordance with user-programmable input. The availability of such configurable I/O pins is extended to low-power or power savings modes of operation during which the I/O controller is powered off or deactivated. | 03-13-2014 |
| 20140082237 | RUN-TIME FABRIC RECONFIGURATION - Methods, apparatus and systems for implementing run-time fabric reconfiguration are described herein. In accordance with one aspect, techniques are disclosed for implementing run-time fabric reconfiguration on a System on a Chip (SoC) via use of multiple endpoint fabric interfaces having routing logic that is dynamically reconfigured at run-time by a fabric control unit in response to system-state changes. The endpoint fabric interfaces may be coupled to or integrated in IP blocks that are coupled to a switch fabric, or may be implemented in the switch fabric itself. The run-time fabric reconfiguration techniques may be implemented to for various purposes and/or to address various events, such as node failures, security events, IP or design bugs, feature prototyping, and virtualization. | 03-20-2014 |
| 20140095748 | RECONFIGURABLE HARDWARE STRUCTURES FOR FUNCTIONAL PIPELINING OF ON-CHIP SPECIAL PURPOSE FUNCTIONS - A method and apparatus for reconfiguring hardware structures to pipeline the execution of multiple special purpose hardware implemented functions, without saving intermediate results to memory, is provided. Pipelining functions in a program is typically performed by a first function saving its results (the “intermediate results”) to memory, and a second function subsequently accessing the memory to use the intermediate results as input. Saving and accessing intermediate results stored in memory incurs a heavy performance penalty, requires more power, consumes more memory bandwidth, and increases the memory footprint. Due to the ability to redirect the input and output of the hardware structures, intermediate results are passed directly from one special purpose hardware implemented function to another without storing the intermediate results in memory. Consequently, a program that utilizes the method or apparatus, reduces power consumption, consumes less memory bandwidth, and reduces the program's memory footprint. | 04-03-2014 |
| 20140095749 | METHOD FOR ADDRESSING THE PARTICIPANTS OF A BUS SYSTEM - A robust method for addressing each of the participants of a bus system comprising a control unit, and a bus and a plurality of addressable participants connected to the bus, comprising the steps of a) pre-selecting a first number of participants, b) selecting from the pre-selected participants a second number of participants, and c) assigning one or more addresses to them, and repeating the steps a) to c). The selection and pre-selection is based on current sources, specific threshold values, and measurement error. The bus system and addressable device (are also claimed. | 04-03-2014 |
| 20140101349 | CONFIGURABLE SERIAL INTERFACE - Method and system for configuring a serial interface. The system includes one or more input nodes each coupled to a corresponding serial bus. One or more output nodes are coupled to a respective serial bus, each output node having a respective driver. A voltage detection circuit determines the voltage at a configuration node. Mode of serial bus operation is based on the voltage level detected at the configuration node. In at least one mode of serial bus operation, the configuration node is used as a mode select input and power source for at least one output driver. | 04-10-2014 |
| 20140101350 | METHOD FOR FINDING STARTING BIT OF REFERENCE FRAMES FOR AN ALTERNATING-PARITY REFERENCE CHANNEL - The present invention discloses a method for locating the reference frames of the reference lane on the transmitting data bus. The present invention addresses this object by disclosing a method whereby the relationship between the size of the reference frame transmitted over the reference lane and the width of the data bus is such that the reference frame is bit-shifted automatically until it is aligned with the data bus. | 04-10-2014 |
| 20140122754 | METHOD FOR CONFIGURING A COMMUNICATION INTERFACE MODULE IN A CONTROL OR AUTOMATION SYSTEM - A method and system for configuring at least one communication interface module in a control or automation system includes a communication interface module for coupling at least two field bus systems. At least one first functional unit integrated in the communication interface module implements a connection to a configured superordinate controller via a first communication link on the basis of a first field bus protocol. At least one second functional unit integrated in the communication interface module implements a connection for field devices via a second communication link on the basis of a second field bus protocol. At least one further, third functional unit integrated in the communication interface module is configured to connect further field devices via input and/or output functionalities integrated in the communication interface module, and at least one serial interface integrated in the communication interface module can be used to configure the communication interface module. | 05-01-2014 |
| 20140136738 | EMULATED LEGACY BUS OPERATION OVER A BIT-SERIAL BUS - Legacy bus operations, such as x86 I/O instructions having an address space separate from memory address space, are supported in a system in which I/O devices are coupled to a microcontroller connected via an SPI bus or other bit-serial bus. Each legacy bus operation is recognized and trapped by an interface controller, such as a south-bridge controller, which maps the trapped legacy bus operation into a corresponding bit-serial bus transaction, and transacts this corresponding bit-serial bus transaction on the bit-serial bus. Existing software infrastructure using x86 I/O instructions can remain intact, with I/O transactions bound for the SPI bus. | 05-15-2014 |
| 20140156886 | DATA MIGRATION METHOD AND APPARATUS - The present invention provides a data migration method and apparatus, where the method includes: after a second control board is inserted into a second control board slot, receiving, by a first control board, type information from the second control board, and determining whether the type information of the second control board and type information of the first control board are the same; and when determining that the type information of the second control board and the type information of the first control board are different, sending, by the first control board, configuration data stored by the first control board itself to the second control board, so that the second control board utilizes the configuration data to perform a configuration. | 06-05-2014 |
| 20140164657 | MAPPING VIRTUAL DEVICES TO COMPUTING NODES - A method for providing virtualization of information handling resources includes accessing a information handling system and a information handling resource, accessing a first virtual function configured to cause virtualized access to the information handling resource through the interface, accessing a second virtual function configured to cause virtualized access to the information handling resource through the interface, and selectively mapping the first virtual function and the second virtual function to information handling systems of the system. The selective mapping includes preventing the first virtual function and the second virtual function from both being mapped to the same information handling system. | 06-12-2014 |
| 20140201401 | INFORMATION PROCESSING APPARATUS, DEVICE CONNECTION METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM FOR CONNECTING DEVICE - An information processing apparatus includes: a connection port configured to be capable of attaching a device thereto; an acquisition unit configured to acquire, from a storage unit included in the device, bus-configuration information indicating a bus configuration of the device; and a setting unit configured to set a bus configuration of the connection port based on the bus-configuration information. | 07-17-2014 |
| 20140223047 | SYSTEM AND METHOD FOR PER-TASK MEMORY PROTECTION FOR A NON-PROGRAMMABLE BUS MASTER - A system includes a non-programmable bus master. The non-programmable bus master includes a memory protection unit (MPU) to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions, and hardware logic. The hardware logic executes a first task and a second task. The tasks generate transactions and the hardware logic switches between executing the first and second tasks. The hardware logic also causes the MPU to operate in the first configuration when the hardware logic executes the first task and causes the MPU to operate in the second configuration when the hardware logic executes the second task. | 08-07-2014 |
| 20140244868 | INTEGRATED CIRCUIT DEVICES, SYSTEMS AND METHODS HAVING AUTOMATIC CONFIGURABLE MAPPING OF INPUT AND/OR OUTPUT DATA CONNECTIONS - Integrated circuit devices are disclosed with receive ports having mapping circuits automatically configurable to change a logical mapping of data received on receive-data connections. Automatic configuration can be based on a data value included within a received data set. Corresponding systems and methods are also described. | 08-28-2014 |
| 20140258570 | IMPLEMENTING CONFIGURATION PRESERVING RELOCATION OF SRIOV ADAPTER - A method, system and computer program product are provided for implementing configuration preserving relocation of a Single Root Input/Output Virtualization (SRIOV) adapter in a computer system. At system power on an SRIOV adapter having been relocated to a different slot while the system was powered off is automatically detected, and the configuration data associated with the adapter automatically updated so that it remains associated with the adapter in the adapter's new location. | 09-11-2014 |
| 20140281067 | Apparatus, system, and method for performing link training and equalization - A system and method comprising, in response to a first component and a second component undergoing a link training and equalization procedure, a second component is to communicate a first set of data to the first component via a first transmission logic along at least one channel of a communications link. The first component and the second component are link partners. The first set of data further includes a full swing value and a low frequency value which are stored in a first storage unit of the first component. The first component is to store a first computed set of coefficients from the full swing value and the low frequency value. The second component is to apply the first computed set of coefficients to the first transmission logic of the second component. | 09-18-2014 |
| 20140281068 | APPARATUS, SYSTEM, AND METHOD FOR IMPROVING EQUALIZATION WITH A HARDWARE DRIVEN ALGORITHM - A system and method comprising, in response to a first component and a link partner of the first component, undergoing equalization, the first component is to communicate a first set of data to the link partner component. The first component may comprise at least one receiver to receive a first set of equalization data. The first component may further comprise coefficient storage coupled to the receiver to store the equalization data. In addition, coefficient logic coupled to the coefficient storage to generate a first set of coefficients based on the first set of equalization data. The first component is to send the first set of coefficients to the link partner component. | 09-18-2014 |
| 20140281069 | MULTI ROOT SHARED PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) END POINT - A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table. | 09-18-2014 |
| 20140297910 | SAS EXPANDER - A SAS expander that includes a storage management module to cause the SAS expander to configure zoning of targets coupled to the SAS expander based on zone configuration rules. The storage management to cause, in response to receipt of a command to enter an expander reduced functionality mode of operation, the SAS expander to prevent initiators access to the targets coupled to the SAS expander and to allow update of expander functionality module for controlling operation of the SAS expander. The storage management module to cause, upon completion of the expander reduced functionality mode of operation, the SAS expander to reconfigure the zoning of the targets coupled to the SAS expander based on the zone configuration rules and to allow initiators access to the targets coupled to the SAS expander. | 10-02-2014 |
| 20140359177 | DELAYED PHYSICAL LINK ACTIVATION IN SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE DEVICES THAT UTILIZE SMART CABLING - Methods and structure for delayed physical link activation in systems that utilize smart cabling are provided. The system includes a Serial Attached Small Computer System Interface (SAS) device comprising a physical link and a controller. The controller is able to disable the physical link to prevent discovery from occurring along the physical link, to detect a cable attached to a physical link, to acquire cable parameters from a memory of the cable, and to configure the physical link based on the acquired cable parameters to enable communications along the cable. The controller is also able to enable the configured physical link to trigger discovery for the physical link. | 12-04-2014 |
| 20140372641 | Selectively Transparent Bridge for Peripheral Component Interconnect Express Bus Systems - A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers. | 12-18-2014 |
| 20150012676 | Configurable data processing system based on a hybrid data and control driven processing architecture - A data processing system comprising a plurality of data inputs and of data outputs for processing input data and providing processed data to a data output. The system comprises a plurality of data processing hardware units, each being configured to process data within a predetermined latency and according to a data processing task of a predetermined type. The system further comprises a memory for storing a predetermined latency for each of the data processing hardware units and a controller configured to determine a type of a data processing task to be executed as a function of a source of data to be processed or of a destination of processed data and further configured to select one data processing hardware unit as a function of the determined type of the task to be executed and of latency constraints associated with the task to be executed. | 01-08-2015 |
| 20150019770 | DYNAMICALLY CALIBRATING THE OFFSET OF A RECEIVER WITH A DECISION FEEDBACK EQUALIZER (DFE) WHILE PERFORMING DATA TRANSPORT OPERATIONS - Dynamically calibrating an offset of a receiver with a DFE while performing data transport operations, the DFE comprising a plurality of independent data transport banks, at least one data transport bank operating a data transport mode and at least one data transport bank operating in a calibration mode, including: iteratively, while carrying out data transport operations: utilizing the data transport bank operating in the data transport mode to perform data transport operations; calibrating the data transport bank operating in the calibration mode; and upon completing calibration of the data transport bank operating in the calibration mode, switching the mode of each data transport bank. | 01-15-2015 |
| 20150032923 | COUPLING DEVICE AND METHOD FOR DYNAMICALLY ALLOCATING USB ENDPOINTS OF A USB INTERFACE, AND EXCHANGE TRADING SYSTEM TERMINAL WITH COUPLING DEVICE - The invention relates to a method and a coupling device ( | 01-29-2015 |
| 20150046611 | DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT - Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system. | 02-12-2015 |
| 20150058506 | SERVER SYSTEM AND METHOD FOR TRANSFERRING AT LEAST ONE CHASSIS-SPECIFIC CONFIGURATION VALUE - A server system includes a chassis having a plurality of insertion slots that receive a plurality of server plug-in modules; at least one printed circuit board including at least one first microcontroller and arranged in the chassis to contact server plug-in modules received in the insertion slots; and a first server plug-in module including a first system management controller and arranged in a first insertion slot and coupled to the at least one printed circuit board, wherein the first microcontroller and the first system management controller are coupled together via at least one first signal line, and the first microcontroller is arranged to provide the first system management controller with at least one chassis-specific configuration value. | 02-26-2015 |
| 20150074300 | MOBILE COMPUTING DEVICE AND METHOD OF TRANSMITTING DATA THEREFROM - A mobile computing device is provided. The device includes a first port having a pinout configuration that is configured to support at least one data format, a data source configured to provide data of a second data format that is different from the at least one data format, and a first multiplexer configured to selectively direct data from the data source towards the first port. The pinout configuration is modified to enable the first port to support the second data format. | 03-12-2015 |
| 20150074301 | HOST BUS DRIVER VERIFYING APPARATUS, HOST BUS VERIFICATION SYSTEM, AND COMPUTER PRODUCT - A host bus driver verifying apparatus is connected, through a host bus adapter, to a higher-order system and includes a storage device preliminarily storing correspondence relation information that correlates an operating system type operating in the higher-order system, a host bus adaptor type, and a driver type of the host bus adaptor; and a processor that obtains for the host bus adaptor, the driver type to be set in the higher-order system to which connection is made. The processor obtains the driver type based on the correspondence relation information, and connection information that includes information concerning the operating system type and the host adaptor type and that is received, via host bus adapter, from the higher-order system to which connection is made. The processor further verifies whether the obtained driver type matches a driver type set for a host bus adaptor in the higher-order system to which connection is made. | 03-12-2015 |
| 20150074302 | Automated Cabling Process for a Complex Environment - A method is provided for cabling a plurality of hardware components. A chassis controller establishes a wireless connection to a wireless device. The chassis controller, via a wireless interface, transmits a chassis map to the wireless device over the wireless connection. The chassis controller, via the wireless interface, transmits to the wireless device, an indication of a first port to be cabled over the wireless connection, the first port. The first port is of a first hardware component of the plurality of hardware components. The chassis controller tests the first port to determine whether cabling of the first port has been performed correctly. | 03-12-2015 |
| 20150095530 | DYNAMIC PORT NAMING IN A CHASSIS - A tool for dynamically naming network ports and switch ports in a chassis. The tool retrieves, by one or more computer processors, chassis specifications of the chassis. The tool retrieves, by one or more computer processors, identifying information for components of the chassis. The tool determines, by one or more computer processors, a plurality of network ports and a plurality of switch ports within the chassis not assigned an alternative port name. The tool constructs, by one or more computer processors, alternative port names for the plurality of network ports and the plurality of switch ports within the chassis not assigned an alternative port name. | 04-02-2015 |
| 20150127860 | SETTING A PCIE DEVICE ID - One embodiment of the present invention includes a hard-coded first device ID. The embodiment also includes a set of fuses that represents a second device ID. The hard-coded device ID and the set of fuses each designate a separate device ID for the device, and each device ID corresponds to a specific operating configuration of the device. The embodiment also includes selection logic to select between the hardcoded device ID and the set of fuses to set the device ID for the device. One advantage of the disclosed embodiments is providing flexibility for engineers who develop the devices while also reducing the likelihood that a third party can counterfeit the device. | 05-07-2015 |
| 20150143003 | High Speed, Parallel Configuration of Multiple Field Programmable Gate Arrays - Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (FPGAs). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more FPGAs are configured with a communication functionality such as PCIe using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the FPGAs, usually via PCIe lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a DMA engine, each FPGA obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. Primary FPGAs may further transmit the first configuration bit image to additional, secondary FPGAs, such as via JTAG lines, for their configuration. | 05-21-2015 |
| 20150149670 | SYSTEM AND METHOD FOR CONTROLLING BUS-NETWORKED DEVICES VIA AN OPEN FIELD BUS - A system for controlling bus-networked devices includes a gateway including a memory unit and having an interface to an open field bus. A power supply unit supplies primary power for the gateway and bus subscribers. An auxiliary power supply unit supplies auxiliary power for the bus subscribers independent of bus functionality. A pluggable connection cable is electrically connects the gateway to the bus subscribers and transmits the primary and the auxiliary power and control and/or status information between the gateway and the bus subscribers. An application bus networks the bus subscribers to each other and is operable by the connection cable. A bus controller writes a target bus configuration of the application bus and stores the target bus configuration in a non-volatile manner in the memory unit. The bus controller is also configured to overwrite the target bus configuration with a present, actual bus configuration. | 05-28-2015 |
| 20150293862 | HARDWARE CONFIGURATION APPARATUS - A hardware configuration apparatus is provided. The hardware configuration apparatus is a part of a hardware system and the hardware system includes at least one function. The hardware configuration apparatus includes an interface unit, a resolution unit, and an output generation unit. For each function of the hardware system, the resolution unit generates a current setting corresponding to the function based on a default setting corresponding to the function and function settings of a plurality of secure configuration entries (SCEs) corresponding to the function. The interface unit is coupled to the resolution unit and a storage storing the SCEs. The interface unit provides the SCEs to the resolution unit. The output generation unit is coupled to the resolution unit. For each function of the hardware system, the output generation unit outputs a configuration signal to enable or disable the function according to the current setting corresponding to the function. | 10-15-2015 |
| 20150317267 | GPIB BUS TO ZIGBEE INTERCONNECTION - An interface conversion device and a wireless communication system including the interface conversion device are disclosed. The interface conversion device is connected to GPIB-equipped devices in a GPIB network to convert data in the GPIB format to the ZigBee format and vice versa, thereby transforming a cable network to a wireless network to increase the mobility, range, and number of devices in the network. | 11-05-2015 |
| 20150324311 | ALLOCATING LANES OF A SERIAL COMPUTER EXPANSION BUS AMONG INSTALLED DEVICES - A computer program product includes program instructions executable by a processor, such as a supervisory controller within a computer to perform a method. The method includes identifying PCIe devices installed within the computer and identifying one or more configurable link width for each of the identified PCIe devices, wherein each PCIe device is determined to be installed in a particular PCIe slot. The method further includes granting a higher priority to a first one of the PCIe devices than to a second one of the PCIe devices, and controlling the allocation of a fixed number of serial communication lanes from a processor to the plurality of PCIe devices, wherein the first PCIe device is allocated the maximum configurable link width identified for the first PCIe device and the second PCIe device is allocated a link width less than the maximum configurable link width identified for the second PCIe device. | 11-12-2015 |
| 20150324312 | ALLOCATING LANES OF A SERIAL COMPUTER EXPANSION BUS AMONG INSTALLED DEVICES - A method includes a supervisory controller within a computer identifying a plurality of PCIe devices installed within the computer and identifying one or more configurable link width for each of the identified PCIe devices, wherein each of the identified PCIe devices is determined to be installed in a particular PCIe slot. The method further includes the supervisory controller granting a higher priority to a first one of the PCIe devices than to a second one of the PCIe devices, and the supervisory controller controlling the allocation of a fixed number of serial communication lanes from a processor to the plurality of PCIe devices, wherein the first PCIe device is allocated the maximum configurable link width identified for the first PCIe device and the second PCIe device is allocated a link width less than the maximum configurable link width identified for the second PCIe device. | 11-12-2015 |
| 20150324313 | HUB CONTROL METHOD AND ASSOCIATED CIRCUIT - A hub hub control method, wherein the hub possesses an uplink port and a plurality of downlink ports, includes: receiving link status of each downlink port to know whether each downlink port has built a link; and when none of the plurality of downlink ports has built a link, controlling the uplink port to be unable to build a link. A hub control circuit, the hub possessing an uplink port and a plurality of downlink ports, includes a link status reception unit and an uplink port control unit for respective execution of the two steps of the hub control method. | 11-12-2015 |
| 20150324320 | SERIAL PROTOCOL OVER DATA INTERFACE - It is inter alia disclosed to determine a type of a second apparatus being connected to a data interface of the first apparatus based on a state of an identification pin of the data interface, the data interface further comprising at least one data pin, wherein the type of the second apparatus relates to a communication via the at least one data pin, to check whether the second apparatus is configured to perform a further communication via the identification pin, and if said checking yields a positive result, to enable the further communication via the identification pin. | 11-12-2015 |
| 20150331828 | COMPUTER-IMPLEMENTED GATEWAY - Methods, systems, and computer program products for configuring an enterprise service bus. Based on user configuration settings, a configuration instance may be generated for the enterprise service bus. The configuration instance is communicated to the enterprise service bus. During run-time, the configuration instance may be configured to control an execution data flow for business data, such as travel data, through the enterprise service bus. Alternatively, a configuration instance at the enterprise service bus may be received by the enterprise service bus during run-time. The configuration instance is based on user configuration settings. The enterprise service bus may be configured to control an execution data flow for business data, such as travel data, through the enterprise service bus based on the configuration instance. | 11-19-2015 |
| 20150346790 | BASEBAND PD COMMUNICATION OVER USB STANDARD A CONNECTOR - In some example embodiments, there may be provided an apparatus. The apparatus may include a first interface including a first voltage terminal and at least one data interface terminal and a second interface including a second voltage terminal and at least one configuration channel terminal, wherein the first voltage terminal is coupled to the at least one configuration channel terminal by at least a pull-up circuitry configured to cause a predetermined voltage at the at least one configuration channel terminal, and wherein the at least one configuration channel terminal is coupled to the at least one data interface terminal to enable communication between the at least one data interface terminal and the at least one configuration channel terminal. Related methods, systems, and articles of manufacture are also disclosed. | 12-03-2015 |
| 20150347158 | GENERIC PHYSICAL LOCATION CODES FOR VIRTUAL SYSTEM AND PARTITION CLONING - A cloned configuration of a source machine is created by determining a first set of physical location codes for a source machine. A map is generated based on the sorted physical location codes that maps the first set of physical location codes to a first set of generic location codes. A second set of physical location codes associated with a second set of adapter slots in a target machine is generated. A second map is generated based on the sorted second set of physical location codes that maps the second set of physical location codes to a second set of generic location codes. A third set of physical location codes is generated based on the first set of generic location codes and the second map. If an entry in the third set of physical location codes is not present the second set of physical location codes, an error is generated. | 12-03-2015 |
| 20150347159 | GENERIC PHYSICAL LOCATION CODES FOR VIRTUAL SYSTEM AND PARTITION CLONING - A cloned configuration of a source machine is created by determining a first set of physical location codes for a source machine. A map is generated based on the sorted physical location codes that maps the first set of physical location codes to a first set of generic location codes. A second set of physical location codes associated with a second set of adapter slots in a target machine is generated. A second map is generated based on the sorted second set of physical location codes that maps the second set of physical location codes to a second set of generic location codes. A third set of physical location codes is generated based on the first set of generic location codes and the second map. If an entry in the third set of physical location codes is not present the second set of physical location codes, an error is generated. | 12-03-2015 |
| 20150347341 | APPARATUS FOR PROVIDING A SHARED REFERENCE DEVICE - Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that only one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time. | 12-03-2015 |
| 20150355917 | DATA PROCESSING APPARATUS AND COMMUNICATION SYSTEM - A communication unit receives from a BCM output data which is data to I/O devices from the BCM. A shared memory stores the output data received by the communication unit. An anomaly detection communication processing unit and the communication unit generate a communication frame for anomaly detection to request sending the output data held in the BCM. The communication unit sends the communication frame for the anomaly detection to the BCM, and receives the output data held in the BCM from the BCM as a response to the communication frame for the anomaly detection. The anomaly detection checking unit compares the output data received from the BCM with the output data stored in the shared memory. | 12-10-2015 |
| 20150356037 | Device And Method To Assign Device Pin Ownership For Multi-Processor Core Devices - An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device has an output. Furthermore, a housing with a plurality of assignable external pins and a protected pin ownership logic for each assignable external pin is provided and configured to be programmable to assign an output function of an associated assignable external pin to only one of the plurality of processor cores. | 12-10-2015 |
| 20150356039 | Device And Method To Assign Device Pin Functionality For Multi-Processor Core Devices - An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device may have an output, a housing with a plurality of assignable external pins, and a plurality of peripheral pin selection modules for each processing core, wherein each peripheral pin selection module is configured to be programmable to assign an assignable external pin to one of the plurality of peripheral devices of one of the processor cores. | 12-10-2015 |
| 20150356041 | IDENTIFYING INTERFACES - A method and apparatus is provided for identifying a particular computer port. A first instruction is sent to a computer. The first instruction specifies a particular port of the computer and relates to an indicator uniquely associated with, and located proximate to the specified particular port. Upon an execution of the first instruction, the indicator is configured to provide an identification signal. A current operative state of the port is maintained while the indicator associated therewith simultaneously provides the identification signal. | 12-10-2015 |
| 20150363343 | AUTO-CONFIGURATION OF A PORT - Embodiments of the present invention provide automatic provisioning of a port in an information handling system, such as a router, switch, bridge, etc., according to the cable type that is inserted into the port. In embodiments, if a user has inserted a break-out cable into a port that is not configured for break-out mode, the information handling system quickly and transparently changes the port configuration to a break-out mode. Conversely, when a user inserts a non-break-out cable that cannot be fanned out into a quad-mode port, the information handling system configures that port to native mode (i.e., non-break-out mode). In embodiments, the user may override auto-configuration. In embodiments, one or more port configurations may be stored and applied to a port by a user. | 12-17-2015 |
| 20150370580 | CONFIGURATION CONTROLLER FOR AND A METHOD OF CONTROLLING A CONFIGURATION OF A CIRCUITRY - A configuration controller for and a method of controlling a configuration of a circuitry are provided. The configuration controller comprises an input, a selection checker, a data selector and an output. The input receives an input configuration selection signal which is encoded according to a specific encoding scheme. The selection checker checks a correctness of the received input configuration selection signal and provides to the data selector a selection signal which indicates a specific configuration selection if the input configuration selection data is correct or indicates a default configuration selection if the input configuration selection signal is incorrect according to the specific encoding scheme. The data selector selects configuration data from its internal configuration data storage in accordance with the selection signal and provides the selected configuration data to the output. | 12-24-2015 |
| 20160012010 | METHOD, APPARATUS AND SYSTEM FOR MODULAR ON-DIE COHERENT INTERCONNECT | 01-14-2016 |
| 20160026479 | METHOD AND APPARATUS FOR SELECTING AN INTERCONNECT FREQUENCY IN A COMPUTING SYSTEM - In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (f | 01-28-2016 |
| 20160026588 | SYSTEM AND METHOD FOR BUS WIDTH CONVERSION IN A SYSTEM ON A CHIP - Various embodiments of methods and systems for precompensated bus width conversion (“PBWC”) in a portable computing device (“PCD”) are disclosed. Because starting memory addresses for data transfers emanating from a processing engine in a system on a chip (“SoC”) may be misaligned with a starting memory address of a main bus on the SoC, PBWC solutions seek to precompensate data transfers to align the starting addresses. Advantageously, by doing so PBWC embodiments may significantly reduce the amount of “filler” data chunks that are transferred through the main bus, thereby optimizing band width utilization of the main bus. | 01-28-2016 |
| 20160026599 | FLASH CONTROLLER TO PROVIDE A VALUE THAT REPRESENTS A PARAMETER TO A FLASH MEMORY - An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting. | 01-28-2016 |
| 20160026603 | BUS SYSTEM IN SOC - A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal. | 01-28-2016 |
| 20160034414 | Systems And Methods For Assigning Addresses to Serially Arranged Circuit Nodes - In order to control individual circuit nodes coupled to a common serial line, each of the different circuit nodes must be assigned a locally unique address. However, mass manufactured electronics are manufactured as identical electronic devices. Thus, several techniques are presented for assigning unique addresses to identical electronic devices coupled to a common serial line. One set of techniques uses a local sensor that is stimulated in order to specify a single device on the serial line. Another set of techniques measures a pulse presented onto the common serial by a circuit node to determine its relative position on the serial line. | 02-04-2016 |
| 20160050111 | METHOD AND APPARATUS FOR ADAPTIVE DEVICE RE-CONFIGURATION - An apparatus is provided comprising a memory and a processor configured to: execute a device driver for operating a device; detect a data throughput associated with the device driver; identify a configuration setting based on the data throughput; and re-configure the apparatus based on the configuration setting. | 02-18-2016 |
| 20160070582 | FREQUENCY AND POWER MANAGEMENT - Changing operating states of a PHY interface which includes a plurality of blocks, changing operating states of a PHY interface includes: receiving parameters indicating desired feature settings of the plurality of blocks for changing the operating state of the PHY interface; and enabling the desired feature settings in a sequence, the sequence based on dependencies between the feature settings, the dependencies being stored in a dependency table. | 03-10-2016 |
| 20160070668 | QUASI-OPTIMIZED INTERCONNECTION NETWORK FOR, AND METHOD OF, INTERCONNECTING NODES IN LARGE-SCALE, PARALLEL SYSTEMS - A plurality of data links interconnects a number (N) of nodes of a large-scale, parallel system with minimum data transfer latency. A maximum number (K) of the data links connect each node to the other nodes. The number (N) of the nodes is related to the maximum number (K) of the data links by the expression: N=2 | 03-10-2016 |
| 20160077858 | RESET OF SINGLE ROOT PCI MANAGER AND PHYSICAL FUNCTIONS WITHIN A FABRIC - Methods and systems for managing reset of a physical function of an I/O device in a computing system are disclosed, where the physical function is included in a single-root PCI manager. One method includes maintaining a count of active virtual functions associated with the physical function included in the single-root PCI manager, and, upon determining that no active virtual functions are associated with the physical function, allowing the physical function to be reset within the single-root PCI manager. The method further includes while resetting the physical function, persisting a configuration memory space associated with the physical function, and associating the persisted configuration memory space with the physical function after the physical function is reset. | 03-17-2016 |
| 20160077990 | BUS INTERFACE CIRCUIT - According to an embodiment, a bus interface circuit disposed in each of a plurality of slave devices to which a common data channel and a clock channel are supplied from a master device includes a head information detection circuit, an inner clock control circuit, and a data analyzing circuit. The head information detection circuit detects head information from the data channel indicating a head of the data from the data channel, destination information indicating a destination of the data, and a data body in this order. The data analyzing circuit is synchronized with the inner clock generated from the clock control circuit after the head information is detected, and detects the destination information from the data channel, and then analyzes the data body. The inner clock control circuit stops the inner clock when the destination information does not match the destination information of the bus interface circuit. | 03-17-2016 |
| 20160092381 | IN-BAND CONFIGURATION MODE - A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode. | 03-31-2016 |
| 20160092389 | UNIFIED DEVICE INTERFACE FOR A MULTI-BUS SYSTEM - The present disclosure is directed to a unified device interface for a multi-bus system. In at least one embodiment, a system may comprise more than one data bus. Each data bus may be to convey data between an operating system (OS) and at least one device in the system, wherein a plurality of driver instances may facilitate interaction between the OS and a device via one or more of the data buses. In one embodiment, a main driver instance may be determined from the plurality of driver instances to present the device to the OS and coordinate operation of other driver instances. The other driver instances may map addresses in the memory of processing entities corresponding to each of the data buses and report these mappings to the main driver instance. Alternatively, a supervisory driver may be loaded to present the device and to control operation of the driver instances. | 03-31-2016 |
| 20160092394 | INFORMATION PROCESSING APPARATUS, CONTROLLING METHOD FOR INFORMATION PROCESSING APPARATUS, AND STORAGE MEDIUM - In a case where a changeover request indicating to change over setting of an end point is received from an external apparatus, an information processing apparatus decides whether or not data is being transferred from the end point to a memory of the information processing apparatus. Then, in a case where it is decided that the data is being transferred from the end point to the memory, the information processing apparatus does not change over the setting of the end point. | 03-31-2016 |
| 20160098364 | RECONFIGURABLE HARDWARE STRUCTURES FOR FUNCTIONAL PIPELINING OF ON-CHIP SPECIAL PURPOSE FUNCTIONS - A method and apparatus for reconfiguring hardware structures to pipeline the execution of multiple special purpose hardware implemented functions, without saving intermediate results to memory, is provided. Pipelining functions in a program is typically performed by a first function saving its results (the “intermediate results”) to memory, and a second function subsequently accessing the memory to use the intermediate results as input. Saving and accessing intermediate results stored in memory incurs a heavy performance penalty, requires more power, consumes more memory bandwidth, and increases the memory footprint. Due to the ability to redirect the input and output of the hardware structures, intermediate results are passed directly from one special purpose hardware implemented function to another without storing the intermediate results in memory. Consequently, a program that utilizes the method or apparatus, reduces power consumption, consumes less memory bandwidth, and reduces the program's memory footprint. | 04-07-2016 |
| 20160098365 | EMULATED ENDPOINT CONFIGURATION - Techniques for emulating a configuration space by a peripheral device may include receiving a configuration access request, determining that the configuration access request is for a configuration space other than a native configuration space of the peripheral device, and retrieving an emulated configuration from an emulated configuration space. The configuration access request can then be serviced by using the emulated configuration. | 04-07-2016 |
| 20160098370 | DATA FLOW CIRCUITS FOR INTERVENTION IN DATA COMMUNICATION - A system may include date flow module circuits configured between electronic devices or circuits that may affect and/or intercept the flow of data being communicated between electronic devices. The data flow module circuits may communicate with an external controller that may want to intervene in the data communication. The data flow module circuits may be configured in a pass mode or in an intervention mode. In the pass mode, a data flow module circuit may pass on data it receives without intervention by the external controller. In the intervention mode, the data flow module circuit may receive instructions from the external controller as to the data that the external controller wants the data flow module to output. | 04-07-2016 |
| 20160132448 | HUB MODULE WITH A SINGLE BRIDGE SHARED AMONG MULTIPLE CONNECTION PORTS TO SUPPORT ROLE REVERSAL - An apparatus includes a multiport hub, a single bridge configured to communicatively couple together a plurality of hosts and to emulate a slave device to each such host, and a plurality of connection port. The apparatus further includes a configurable data path network coupled to the multiport hub, the single bridge, and the plurality of connection ports. The configurable data path network is configured to selectively provide for a connection port for which a host is detected, data communications through the single bridge between the multiport hub and the connection port, and for a connection port for which no host is detected, data communications between the multiport hub and the connection port that bypass the single bridge. Corresponding methods are also so disclosed. | 05-12-2016 |
| 20160140075 | AUTO DETECTION AND ADAPTIVE CONFIGURATION OF HDMI PORTS - Methods, systems, circuits, devices, and apparatuses are described for auto-detection and adaptive configuration of high-definition multimedia interface (HDMI) ports. Unique systems and circuits allow HDMI repeaters to automatically detect if an HDMI device that has been connected thereto, via an HDMI port, is an HDMI source (source mode) or an HDMI sink (sink mode). The unique systems and circuits may be adaptively configured to allow the HDMI port to function as an HDMI input or an HDMI output based on the automatic detection. Methods corresponding to the functions performed by the systems and apparatuses are provided, and computer readable storage media with computer program instructions encoded thereon for enabling processing devices to perform the methods are also provided. | 05-19-2016 |
| 20160147625 | DETECTING DEVICE FOR DETECTING USB 2.0 SPECIFICATION AND ELECTRONIC APPARATUS WITH DETECTING DEVICE - A detecting device for detecting USB specification includes a USB interface circuit, a USB 2.0 detecting circuit, and a prompting circuit. The USB interface circuit includes a USB 2.0 pin for receiving data under USB 2.0 specification, and a USB 3.0 pin coupled to a south bridge chip for receiving data under USB 3.0 specification. The USB 2.0 detecting circuit is coupled to the USB 2.0 pin. The USB 2.0 detecting circuit can send a control signal to the prompting circuit upon detecting a data exchange requirement from the USB 2.0 pin. The prompting circuit can prompt upon receiving the control signal. | 05-26-2016 |
| 20160147678 | METHOD AND APPARATUS FOR SELECTING ONE OF A PLURALITY OF BUS INTERFACE CONFIGURATIONS TO USE - Provided are a method and apparatus for selecting one of a plurality of bus interface configurations to use. Selection is made of a first bus interface configuration having a first bus width to send data over the bus in response to an interface parameter indicating a first interface parameter. Selection is made of a second bus interface configuration having a second bus width to send data over the bus in response to the interface parameter indicating a second interface parameter, wherein the first bus width has fewer bits than the second bus width. | 05-26-2016 |
| 20160147681 | DETECTING AND CONFIGURING OF EXTERNAL IO ENCLOSURE - A method, system and computer program product are provided for detecting and configuring an external input/output (IO) enclosure in a computer system. A PCIE Host Bridge (PHB) in a system unit is connected to a plurality of PCIE add-in card slots. One or more cables are connected between the PHB and the external enclosure. System firmware including detecting and configuring functions uses sideband structure for detecting a PCIE cable card and configuring the external input/output (IO) enclosure. | 05-26-2016 |
| 20160147697 | DETECTING AND CONFIGURING OF EXTERNAL IO ENCLOSURE - A method, system and computer program product are provided for detecting and configuring an external input/output (IO) enclosure in a computer system. A PCIE Host Bridge (PHB) in a system unit is connected to a plurality of PCIE add-in card slots. One or more cables are connected between the PHB and the external enclosure. System firmware including detecting and configuring functions uses sideband structure for detecting a PCIE cable card and configuring the external input/output (IO) enclosure. | 05-26-2016 |
| 20160154760 | SERVER ON A CHIP AND NODE CARDS COMPRISING ONE OR MORE OF SAME | 06-02-2016 |
| 20160170472 | LOW POWER CONFIGURATION FOR USB (UNIVERSAL SERIAL BUS) DEVICES | 06-16-2016 |
| 20160170935 | Accessory Device Architecture | 06-16-2016 |
| 20160179556 | INPUT/OUTPUT (I/O) DEVICE CONFIGURATION SIGNATURE | 06-23-2016 |
| 20160179737 | PIN-CONFIGURABLE INTERNAL BUS TERMINATION SYSTEM | 06-23-2016 |
| 20160188502 | Ring Bus Architecture for Use in a Memory Module - Ring bus architectures for use in a memory module are disclosed. A memory module may include a ring bus controller and a bus bridge positioned on a primary ring bus. The memory module also includes a secondary ring bus in communication with the bus bridge and a plurality of non-volatile memory units. The ring bus controller is configured to send a configuration command to the bus bridge via the primary bus ring, where the configuration command includes an indication to route future commands and/or data to the secondary ring bus extending from the bus bridge. The bus bridge is configuration to, in response to the configuration command, configure the bus bridge to route future commands and/or data from the primary ring bus to the secondary ring bus. | 06-30-2016 |
| 20160188518 | Opaque Bridge for Peripheral Component Interconnect Express Bus Systems - A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS. | 06-30-2016 |
| 20160253186 | SECURING PEER ZONING | 09-01-2016 |
| 20160378696 | EXPOSING MEMORY-MAPPED IO DEVICES TO DRIVERS BY EMULATING PCI BUS AND PCI DEVICE CONFIGURATION SPACE - Devices are emulated as PCI devices so that existing PCI drivers can be used for the devices. This is accomplished by creating a shim PCI device with a emulated PCI configuration space, accessed via a emulated PCI Extended Configuration Access Mechanism (ECAM) space which is emulated by accesses to trapped unbacked memory addresses. When system software accesses the PCI ECAM space to probe for PCI configuration data or program base address registers of the PCI ECAM space, an exception is raised and the exception is handled by a secure monitor that is executing at a higher privilege level than the system software. The secure monitor in handling the exception emulates the PCI configuration space access of the emulated PCI device corresponding to the ECAM address accessed, such that system software may discover the device and bind and appropriately configure a PCI driver to it with the right IRQ and memory base ranges. | 12-29-2016 |
| 20160378704 | DYNAMICALLY CONFIGURE CONNECTION MODES ON A SYSTEM BASED ON HOST DEVICE CAPABILITIES - An apparatus for configuring connection modes is described herein. The apparatus includes a plurality of ports and a processor. A first port is to couple a first device to the apparatus, the first port configurable to communicate via one mode of a plurality of modes. The processor is to include a policy manager, wherein the policy manager is to negotiate the one mode at the first port based on a mode of a second port of the plurality of ports. | 12-29-2016 |
| 20170235686 | ADAPTER CONFIGURATION FOR A STORAGE AREA NETWORK | 08-17-2017 |
| 20180024950 | RING BUS ARCHITECTURE FOR USE IN A MEMORY MODULE | 01-25-2018 |
