Class / Patent application number | Description | Number of patent applications / Date published |
710071000 | Serial-to-parallel or parallel-to-serial | 42 |
20080209089 | Packet-Based Parallel Interface Protocol For A Serial Buffer Having A Parallel Processor Port - A serial buffer is provided having a parallel port configured to couple the serial buffer to a first system via a parallel interface protocol. The serial buffer also includes a serial port configured to couple the serial buffer to a second system via a serial interface protocol and control logic that enables data to be transferred between the parallel port and the serial port in an efficient manner. In one embodiment, the parallel interface protocol is substantially identical to a quad-data rate burst of two (QDRII-B2) interface protocol. | 08-28-2008 |
20080250174 | Flashtoaster for Reading Several Types of Flash-Memory Cards, With or Without a PC - A flash-memory-card reader reads and writes multiple types of flash-memory cards, including CompactFlash, and the smaller SmartMedia, MultiMediaCard, Secure Digital, and Memory Stick. A converter chip converts the different card signals for transfer to a host personal computer (PC). Serial-to-parallel data conversion is performed for the smaller card formats with serial data interfaces, but not for CompactFlash with a parallel-data interface. A single slot has a 50-pin connector for CompactFlash cards or passive adapters. The passive adapters have the CompactFlash form factor and a smaller connector fitting smaller flash cards. Passive adapters have no components but simply wire the smaller connector to the CompactFlash connector. A pin mapping allows card-type detection by sensing the LSB address pins of the CompactFlash interface. A larger CompactFlash reader has multiple slots for each card type. The reader is connected to the PC by a cable, or located within the PC chassis in a drive bay. A stand-alone reader copies images from the flash-memory card to a removable disk media. Pressing a button initiates image transfer. | 10-09-2008 |
20080288679 | Resetting a Hypertransport Link in a Blade Server - Methods, apparatus, and computer program products are described for resetting a HyperTransport link in a blade server, including reassigning, by a blade management module, a gate signal from enabling a transceiver to signaling a HyperTransport link reset; sending, by the blade management module to a reset sync module on an out-of-band bus, the gate signal; and in response to the gate signal, sending, by the reset sync module to the blade processor, HyperTransport reset signals. The HyperTransport link includes a bidirectional, serial/parallel, high-bandwidth, low-latency, point to point data communications link. The blade server includes the blade processor, the reset sync module, and the baseboard management controller. The blade server is installed in the blade center. The blade center includes the blade management module. The blade management module is coupled to the baseboard management controller by the blade communication bus. | 11-20-2008 |
20090006679 | Data Flow Control and Bridging Architecture Enhancing Performance of Removable Data Storage Systems - A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface. | 01-01-2009 |
20090013108 | Memory buffers for merging local data from memory modules - An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift register, a multiplexer, and a transmitter. The PISO shift register serializes parallel data on a local data bus into serialized local data. The multiplexer selectively merges serialized local data and feed-through data into a serial data stream. The transmitter drives the serial data stream onto a serial data link. In another embodiment of the invention, a method for a memory module includes receiving an input serial data stream; merging local frames of data and feed-through frames of data together into an output serial data stream in response to a merge enable signal; and transmitting the output serial data stream on a northbound data output to a next memory module or a memory controller. Other embodiments of the invention are disclosed and claimed. | 01-08-2009 |
20090113092 | SIGNAL CONVERTER FOR DEBUGGING THAT EXPANDS FIFO CAPACITY - A signal converter includes an interconnect interface, a FIFO set, which comprises a transmitter FIFO and a receiver FIFO respectively connected to the interconnect interface through a data bus, a parallel/serial converter connected to the transmitter FIFO and the receiver FIFO by two data buses respectively and kept apart from the FIFO set, and a serial I/O interface connected to the parallel/serial converter. | 04-30-2009 |
20090119426 | Serial Data Interface System and Method Using A Selectively Accessed Tone Pattern Generator - A system and method performs speed and connection handshaking between Beta signal ports and/or Bilingual ports in a serial data interface system. A tone pattern generator (e.g., a flip-flop) can be used to generate a tone pattern signal representing approximately 49 MHz to approximately 62 MHz. A selecting system (e.g., a multiplexer, a digital multiplexer, or the like) selectively transmits either the tone pattern signal or a data input signal. These signals include a driver control signal. A serializer serializes either the tone pattern signal or the data input signal. A clock device (e.g., a clock divider) drives the tone pattern generator and the serializer. A driver receives and differentially transmits, along a twister-wire pair, either the serialized tone pattern signal or the serialized data input signal. | 05-07-2009 |
20090125652 | Physical layer device having a serdes pass through mode - A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively configurable to provide either (i) a first signal path between the first and second parallel ports, or (ii) a second signal path between the first and third parallel ports. | 05-14-2009 |
20090172221 | DATA TRANSFER SYSTEM AND DATA TRANSFER METHOD - The configuration of a system including a lot of receiving side devices can be simplified. The system includes a driver | 07-02-2009 |
20090177814 | Programmable Modular Circuit For Testing and Controlling A System-On-A-Chip Integrated Circuit, and Applications Thereof - The present invention provides a programmable modular circuit for testing and controlling a system-on-a-chip integrated circuit, and applications thereof. In an embodiment, the programmable modular circuit comprises a plurality of serial-to-parallel interface registers coupled together by a data line, a clock line, and an enable line. Each of the plurality of serial-to-parallel interface registers is coupled to a module of the system-on-a-chip. The data line and the clock line are used to serially clock data into the plurality of serial-to-parallel interface registers. Applying a first logical value to the enable line provides the data serially clocked into the plurality of serial-to-parallel interface registers to modules of the system-on-a-chip. Applying a second logical value to the enable line provides default values to modules of the system-on-a-chip. The data values serially clocked into the plurality of serial-to-parallel interface registers can be used to test and/or to modify selected operating characteristics of the system-on-a-chip. | 07-09-2009 |
20090177815 | SWITCHING SERIAL ADVANCED TECHNOLOGY ATTACHMENT (SATA) TO A PARALLEL INTERFACE - An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch. | 07-09-2009 |
20090187685 | INFORMATION RECORDING APPARATUS - An information recording apparatus is disclosed, in which a HDD is connected to an ATA bus as a master device, an optical disk drive is connected as a slave device to a connector by an eSATA interface, and a system control unit asserts a PDAIG signal at the time of activating the information recording apparatus. | 07-23-2009 |
20090198847 | Serial memory interface - A serial memory interface is described, including a memory array, a plurality of serial ports in data communication with the memory array, transferring data between the memory array and at least one of the plurality of serial ports, and a logic block that is configured to control access to the memory array by the plurality of serial ports, the logic block using the serial ports to transfer data between the memory array and at least one of the plurality of serial ports. | 08-06-2009 |
20090222601 | CONCURRENT ASYNCHRONOUS USB DATA STREAM DESTUFFER WITH VARIABLE WIDTH BIT-WISE MEMORY CONTROLLER - A concurrent asynchronous USB 2.0 data stream destuffer and separator with variable-width bit-wise memory controller is described. A parallel stream bit destuffer module identifies in parallel one or more stuffed bits in a decoded data field of a received data stream using a six-bit sliding window. The stuffed bits are bits that were inserted into the received USB data stream by a transmitter to force data transitions in the received USB data stream. A data separator module separates the one or more stuffed bits from a plurality of valid data bits in the decoded data field. A memory module generates an incremental pointer value representative of the number of valid bits and writes the plurality of valid data bits from the decoded data field into a variable sized bit-wise memory structure. | 09-03-2009 |
20090259781 | Serializer Architecture for Serial Communications - Methods, algorithms, circuits, and/or systems for serializing parallel data are disclosed. In one embodiment, a serializer can include a first stage configured to convert m-bit-wide parallel data into n-bit-wide parallel data, where n is 2 | 10-15-2009 |
20090265490 | High-Speed Video Serializer and Deserializer - A high-speed video serializer has an X bit parallel input bus and a Y bit parallel output bus, where X and Y are multiples of one another (e.g., 2). A multiplexer is connected between the input bus and the output bus and is operated such that a frequency of the signals on the output bus is a multiple of the frequency of the signals on the input bus. A circuit provides a clock signal substantially in sync with the signals on the output bus. A high speed video deserializer is also disclosed as are methods of operating the serializer and deserializer. | 10-22-2009 |
20090300243 | TRANSMITTING AND CONVERSION APPARATUS FOR UNIVERSAL SERIAL BUS (USB) TO HIGH DEFINITION MULTIMEDIA INTERFACE (HDMI) - A transmitting and conversion apparatus for universal serial bus (USB) to high definition multimedia interface (HDMI), comprises main body, at one end of the main body, there is a USB connection port, while there is a HDMI output port at the another end; in the main body, there is a USB interface, a USB Hub circuit, a USB to 12/24-bit RGB format output circuit, a USB audio signal conversion circuit, a HDMI conversion circuit and a micro-computer unit (MCU). By using the subject apparatus, the USB connection port can be connected to the interface port of a computer main frame, the computer main frame then outputs a USB packet video signal sequentially via USB Hub circuit, USB to 12/24-bit RGB format output circuit, USB audio signal conversion circuit, HDMI conversion circuit and convert the signal into signal of HDMI format, and finally, the signal of HDMI format is outputted via a HDMI output port for displaying. | 12-03-2009 |
20090307397 | MOBILE COMMUNICATION TERMINAL SYSTEM - A mobile communication terminal system includes a serial interface port, a multimedia output/input module, a multimedia processor, a frequency-signal output/input module, and a baseband processor. The serial interface port is coupled to a computer system via a serial interface. The multimedia output/input module provides a first input signal. The multimedia processor processes the first input signal to generate a first serial interface signal. The frequency-signal output/input module provides a second input signal. The baseband processor processes the second input signal to generate a second serial interface signal to the multimedia processor. The multimedia processor selectively establishes one of a communication connection between the multimedia processor and the serial interface port and a communication connection between the baseband processor and the serial interface port to correspondingly output one of the first serial interface signal and the second serial interface signal to the computer system via the serial interface port. | 12-10-2009 |
20090313404 | APPARATUS FOR ACCESSING CONDITIONAL ACCESS DEVICE BY UTILIZING SPECIFIC COMMUNICATION INTERFACE AND METHOD THEREOF - An apparatus for accessing a conditional access device, which utilizes an external communication interface for information transaction, is disclosed. The apparatus includes a host and an interface module. The host is utilized for receiving or transmitting information according to a specific communication interface. The interface module is coupled to the host and utilized for bridging the specific communication interface and the external communication interface. Another apparatus for accessing a conditional access device having a CPU interface/inband interface is disclosed. The apparatus includes a flash interface/serial interface and a data processing circuit. The data processing circuit is coupled to the flash interface/serial interface and utilized for receiving information outputted from the CPU interface/inband interface through the flash interface/serial interface or transmitting information to the CPU interface/inband interface through the flash interface/serial interface. | 12-17-2009 |
20100023660 | KVM SYSTEM - A keyboard-video-mouse (KVM) system is disclosed. The KVM system comprises a module, a KVM switch and a signal cable. The module transmits a single-ended video signal from a computer, converts a universal asynchronous receiver/transmitter (UART) signal to an input/output (IO) signal, and transmits the IO signal to the computer. The KVM switch receives the single-ended video signal from the module and outputs the UART signal to the module. The signal cable transmits the single-ended video signal from the module to the KVM switch and transmits the UART signal from the KVM switch to the first module. | 01-28-2010 |
20100100650 | Computing Module with Serial Data Connectivity - A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system. | 04-22-2010 |
20100100651 | Multipurpose and programmable pad for an integrated circuit - A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports. | 04-22-2010 |
20100121996 | AUTOMATICALLY SWITCHING CONSOLE CONNECTION - A method and system for configuring a network device is provided. In one implementation the method and system may include directing, via a multiplexer, a group of signals defined by a serial communication format from a primary serial configuration interface to a communication port in a CPU. A universal-serial-bus-to-serial (USB) signal may be detected at a USB interface and converted by a USB-to-serial converter circuit to the serial communication format and directed, via the same multiplexer, to the universal-asynchronous-receiver-transmitter instead of the serial signals from the primary serial configuration interface. A detection signal may be communicated from the USB-to-serial converter circuit to the multiplexer. Alternatively, the detection signal may be directed to the CPU, which may then communicate a selection signal to the multiplexer. | 05-13-2010 |
20100121997 | METHOD FOR WRITING DIGITAL CONTENTS TO A PLURALITY OF STORAGE CARDS AND THE SYSTEM FOR THE SAME - A method for writing digital contents to a plurality of storage card by using a mina console comprises the following steps of: placing a storage card to a respective one of a plurality of card writing devices; writing digital contents to a storage card through a Hub by using a main console; a plurality of cards can be recorded by serially connection or parallel connection so as to increase the writing speed; and placing the storage cards into card readers; and whether the process of writing digital contents is successful being displayed. A system for the same is also included. | 05-13-2010 |
20100153598 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status. | 06-17-2010 |
20100318698 | Data Flow Control and Bridging Architecture Enhancing Performance of Removable Data Storage Systems - A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface. | 12-16-2010 |
20100332701 | HOST COMPUTER, COMPUTER TERMINAL, AND CARD ACCESS METHOD - According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit includes a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock, and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information concerning an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information. | 12-30-2010 |
20110040909 | HIGH-SPEED WIRELESS SERIAL COMMUNICATION LINK FOR A STACKED DEVICE CONFIGURATION USING NEAR FIELD COUPLING - A memory module houses stacked memory devices and a memory controller each having a near-field interface coupled to loop antennas to communicate over-the-air data. A coil is formed on a memory device substrate or molded into a plastic mold to create near-field magnetic coupling with the stacked memory devices and the memory controller. | 02-17-2011 |
20110087811 | Semiconductor device, control method for the semiconductor device and information processing system including the same - The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side. | 04-14-2011 |
20110191511 | SERIAL TRANSMISSION DEVICE, METHOD, AND COMPUTER READABLE MEDIUM STORING PROGRAM - A serial transmission device includes a transmitting unit that transmits data, a receiving unit that receives the data, and a plurality of serial transmission paths that connect the transmitting unit with the receiving unit and are used to transmit data. The receiving unit includes an inter-lane skew information generation unit that generates inter-lane skew information about skew of each of the serial transmission paths and transmits the generated inter-lane skew information to the transmitting unit. The transmitting unit includes a data conversion rule generation unit that generates a conversion rule used to determine distribution of the data to each of the serial transmission paths based on the inter-lane skew information. | 08-04-2011 |
20110196997 | HYBRID INTERFACE FOR SERIAL AND PARALLEL COMMUNICATION - Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins. | 08-11-2011 |
20110276733 | Memory System And Device With Serialized Data Transfer - A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage. | 11-10-2011 |
20120011290 | DVI LINK WITH PARALLEL TEST DATA - An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image. | 01-12-2012 |
20120110227 | Device for transmitting data between a serial data bus and working modules such as actuator modules and/or I/O modules - The invention concerns a device for transmitting data between a serial data bus and working modules, wherein the data bus is connected to a bus node in a bus module having at least two serial communication ports which are connected to ports of a hub connected to or integrated with the bus node, wherein the communication ports are designed for the connection and for the power supply of the working modules and wherein at least one of the working modules is designed as an actuator and/or I/O module comprising a serial-to-parallel converter for the parallel connection of actuators and/or I/O interfaces provided on or connected to the respective working module. | 05-03-2012 |
20120198109 | ELECTRONIC MEASURING DEVICE AND METHOD OF CONVERTING SERIAL DATA TO PARALLEL DATA FOR STORAGE USING THE SAME - An electronic measuring device includes a detection channel module, a sampling module, a control unit, a data path selector and a memory device. A user will be able to selectively enable the desired detection channels and store only data collected from enabled channels. The data collected from the detection channels are in serial data form. The device utilizes a serial-parallel shifter in its sampling module to convert the serial data to parallel data bytes. Two indicators in the storage unit of the memory device allow users to effectively store the parallel data bytes in designated locations. The innovative data conversion and storage methods of this invention will significantly conserve memory space that otherwise will be occupied by data from the disabled channels and allow accurate and efficient reading of the stored data. | 08-02-2012 |
20120239835 | METHOD FOR WRITING DIGITAL CONTENTS TO A PLURALITY OF STORAGE CARDS AND THE SYSTEM FOR THE SAME - A method for writing digital contents to a plurality of storage card by using a mina console comprises the following steps of: placing a storage card to a respective one of a plurality of card writing devices; writing digital contents to a storage card through a Hub by using a main console; a plurality of cards can be recorded by serially connection or parallel connection so as to increase the writing speed; and placing the storage cards into card readers; and whether the process of writing digital contents is successful being displayed. A system for the same is also included. | 09-20-2012 |
20120254488 | DATA TRANSFERRING CIRCUIT AND DATA TRANSFERRING/RECEIVING SYSTEM - A data transferring circuit includes a data transferor configured to transfer data through a plurality of parallel data transfer lines, wherein the data transferor is further configured to partially invert the transferred data in response to an inversion signal, and a pattern sensor configured to enable the inversion signal when data transferred through the parallel data transfer lines is to cause three sequential lines to transfer data of a logic value through a middle one of the sequential lines and data of an inverse of the logic value through the remaining ones of the sequential lines or cause all of the transfer lines to transfer data of a same logic value. | 10-04-2012 |
20130117477 | WIRELESS SIGNAL TRANSMITTING/RECEIVING APPARATUS FOR SEMICONDUCTOR SYSTEM - A wireless signal transmitting/receiving apparatus for a semiconductor system is disclosed The apparatus includes a serializer/deserializer (SERDES) circuit and a coupling pad. The SERDES circuit outputs a parallel input signal as a serial signal during transmission, and outputs a serial input signal as a parallel signal during reception. The coupling pad generates an inductively coupled wireless signal according to the serial signal outputted from the SERDES circuit, and provides a signal generated by inductive coupling with an external device as the serial input signal of the SERDES circuit. | 05-09-2013 |
20130198422 | Method and apparatus for networking musical instruments - In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame. | 08-01-2013 |
20130275634 | DATA PROCESSING METHOD AND DATA PROCESSING UNIT USING THE SAME - A data processing unit includes a main controller configured to receive data requirement information from a host and to generate processing information based on the data requirement information; a pre-processing unit configured to pre-process n types of data output from the main controller according to the processing information and to generate n types of pre-processed data where n is an integer equal to or greater than 2; and a pre-processed data storing unit configured to store the n types of pre-processed data and to output the n types of pre-processed data in an output order determined based on the processing information, wherein the processing information includes information about at least one of type, format, order, size and transmission mode of the n types of pre-processed data. | 10-17-2013 |
20140215106 | SVID DATA TEST SYSTEM AND METHOD - An SVID data test system is applied on a test device and a display device, and the test device is electrically connected to a tested device via an SVID interface, and the display device via a serial interface. The system receives SVID signals, analyzes the SVID signals to obtain nine bit real signals, and performs parallel encoding on the nine bit real signals to obtain nine bit parallel signals. The system further converts the nine bit parallel signals to nine bit serial signals, transmits the serial signals in sequence to the display device, and parses the nine bit serial signals to obtain a packet in hexadecimal and controls the display device to display the packet in response to the display command. | 07-31-2014 |
20140223045 | SELF CORRECTION LOGIC FOR SERIAL-TO-PARALLEL CONVERTERS - Embodiments of the invention describe an apparatus, system and method for executing self-correction logic for serial-to-parallel data converters. Embodiments of the invention receive one of a plurality of serial data streams from a peripheral device, each of the serial data streams having one or more bits. In response to detecting that a shift register chain includes a register select value, embodiments of the invention may store the received serial data stream in one of a plurality of data registers, wherein the one data register is selected based, at least in part, on a position of the register select value in the shift register chain. In response to detecting the shift register chain does contain the register select value, embodiments of the invention may insert the register select value at a register of the shift register chain. | 08-07-2014 |