| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710061000 | Synchronous data transfer | 53 |
| 20080201502 | SYNC CIRCUIT OF DATA TRANSMISSION INTERFACE - A sync circuit of a data transmission interface connected between a first data port and a second data port is provided. The sync circuit includes a first resistor element, a capacitor element, a second resistor element, and an active element. When the signal generated by the first data port is logic 1, the active element is turned off, such that the power source end charges the capacitor element through the first resistor element. Otherwise, when the signal generated by the first data port is logic 0, the active element is turned on, such that the capacitor discharge through the second resistor element, for delaying the data of the first data port for a predetermined time and making the data of the second data port synchronously transmitted on the first data port. | 08-21-2008 |
| 20080201503 | Communications System for Implementation of Synchronous, Multichannel, Galvanically Isolated Instrumentation Devices - An apparatus and method for synchronous communications using a serial data stream employs a housing with a controller and a back plane. The housing accepts one or more modules for interconnection with the back plane. The back plane distributes power to the modules and provides a communication link from the controller to each module. Each communication link includes a data out line, a data in line and a clock line, where each clock line is derived from one clock source. | 08-21-2008 |
| 20080250170 | CLOCK MODE DETECTION IN AN ADAPTIVE TWO-WIRE BUS - Techniques for improving the quality or fidelity of a digital signal transmitted via a two-wire bus interconnect utilizing an open-terminal configuration at one or both end devices of the bus interconnect are disclosed. An intermediate two-wire bus is used to connect two open-terminal-based two-wire busses. A bus adapter device is utilized at each end of the intermediate two-wire bus, whereby the bus adapter device communicates signaling on the corresponding open-terminal-based two-wire bus using open-terminal ports and communicates signaling on the intermediate two-wire bus using push-pull ports. The bus adapter device can utilize control logic to implement a state machine or other function to control the interactions between the different two-wire buses. The bus adapter devices may be implemented as interchangeable integrated circuit devices that can change configuration based on connection, thereby permitting their implementation at either end of a bus transmission system. | 10-09-2008 |
| 20080250171 | Hybrid power relay using communications link - A control circuit for controlling an arc suppression circuit includes a serial communication link communicating a serial signal therethrough. The control circuit includes a microprocessor having a serial input communicating with the serial communication link. The microprocessor generates a control output signal in response to the serial signal. The control circuit further includes the arc suppression circuit having an electrical contact and operating in response to the control output signal to reduce an arc at the electrical contact. | 10-09-2008 |
| 20080256273 | SERIAL COMMUNICATION METHOD AND SERIAL COMMUNICATION SYSTEM - A host device continuously transmits a same command or a same piece of data to a remote device in serial format. The remote device receives the command or the data, and then determines whether the command or the data has an error. When the command or the data has no error, the remote device transmits a response to the host device. Upon reception of the response, the host device stops the continuous transmission of the command or the data. | 10-16-2008 |
| 20080263241 | Data transfer control device and electronic instrument - A data transfer control device includes: a link controller which analyzes a packet received from a host-side data transfer control device through a serial bus; and an interface circuit which generates interface signals and outputs the generated interface signals to an interface bus. A packet transferred from the host-side data transfer control device through the serial bus includes a synchronization signal code field for setting a synchronization signal code. The interface circuit generates synchronization signals FPFRAME and FPLINE included in the interface signals based on the synchronization signal code set in the packet. | 10-23-2008 |
| 20080282000 | INTERFACE CONTROLLER FOR CONTROLLING OPERATION OF EXTERNALLY COUPLED ELECTRONIC APPARATUS - The present invention relates to a technique to absorb a speed difference between a data transmission/reception unit, included in a host device which has a interface controller, and a data transmission/reception unit with a external device. The host device and the external apparatus are both electronic apparatus, and the interface controller outputs a transfer clock to the external apparatus, and controls the data transfer between the interface controller and the external apparatus, in accordance with a specific interface specification defined based on the transfer clock. | 11-13-2008 |
| 20080294812 | Data Transmission Method and Data Transmission System - A terminal of a plurality of terminals that is located at the farthest position from a host has a return signal generator section, the return signal generator section transmits a return signal at a timing when data transmitted from the host to the terminals arrives at the terminal located at the farthest position, the return signal is returned to the host successively passing through interfaces of the terminals connected to a data bus, and each terminal originates data to be transmitted from the terminal to the host or from the terminal to a particular another terminal in synchronization with the return signal and delivers the data from the terminals to the host or the terminal in synchronization with the return signal. | 11-27-2008 |
| 20080301338 | Data transfer control device and electronic instrument - A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates an interface signal and outputs the generated interface signal to an interface bus; and an internal register in which is set timing information for specifying a timing at which a signal level of the interface signal output from the interface circuit changes. The interface circuit generates the interface signal, a signal level of which changes at a timing according to the timing information set in the internal register. | 12-04-2008 |
| 20080301339 | CONTROL DEVICE FOR A USB INTERFACE AND CONTROL METHOD THEREOF - A control device for a USB interface including at least one first terminal for inputting the data to be transmitted and at least one second terminal for the transmission of the packet data on a bus; the packet data include one end-of-packet signal. The USB interface includes one circuit for the data transmission on said at least one second terminal; the USB interface is adapted to receive as an input a signal for the activation of the transmission circuit when data are received from the at least one first terminal and the transmission circuit includes a bias circuit. The control device includes a circuit for the detection of an end-of packet signal on said bus and a control circuit adapted to activate the bias circuit of the transmission circuit if said end-of-packet signal is detected by said detection circuit. | 12-04-2008 |
| 20090031060 | BUS CONVERTER, SEMICONDUCTOR DEVICE, AND NOISE REDUCTION METHOD OF BUS CONVERTER AND SEMICONDUCTOR DEVICE - A bus converter is disclosed that converts a signal of a synchronous bus into a signal of an asynchronous bus. The bus converter includes a control signal generation unit that generates n control signals synchronized at different timings of a predetermined synchronization signal, where n is an integer of two or more; and an output unit that outputs the signal of the synchronous bus divided into n signal groups based on a control using the n control signals. | 01-29-2009 |
| 20090043928 | INTERFACE DEVICE AND MASTER DEVICE OF A KVM SWITCH SYSTEM AND A RELATED METHOD THEREOF - The present invention centralizes the processing the combined horizontal and vertical sync signals in a master device and thereby keeps the interface devices as simple as possible so as to reduce the cost of the interface devices. The interface device mainly only converts the separate horizontal sync signal and vertical sync signal, or the combined horizontal and vertical sync signal to a default polarity. On the other hand, the separation of the combined horizontal and vertical sync signal into individual horizontal and vertical sync signals are all carried out by the master device. | 02-12-2009 |
| 20090043929 | DATA COMMUNICATION SYSTEM - This invention offers a data communication system that can perform data communication and detection of a data read-in request signal while reducing the number of communication lines to three, and is tolerant of noise. The data communication between a microcomputer and a key scan IC and the detection of the data read-in request signal are performed through a control line, a clock line and a data line. The data communication system is provided with a data line control circuit that controls the data line so that outputting of the data read-in signal RDRQ to the data line is disabled when first command data is inputted to the key scan IC through the data line, and that the outputting of the data read-in request signal RDRQ to the data line is enabled when second command data is inputted from the microcomputer to the key scan IC through the data line. | 02-12-2009 |
| 20090049211 | ESTIMATING BACKEND PROCESSING TIME FOR RETRIEVING AND PROCESSING DATA AND DISPLAYING APPROPRIATE SUPPLEMENTAL CONTENT - A method is complementary to processing a retrieve and process pipe specification. The pipe specification is characterized by at least one constituent pipe, each constituent pipe being characterized by at least one of a group consisting of an input node and an output node. The input node is configured to input data, such as a syndication data feed or other data accessible via a web service and the output node is configured to output data, such as a syndication data feed. At least one of the constituent pipes includes a module configured to retrieve data via a web service, such as a source syndication data feed. The wires are configured according to the retrieve and process pipe specification. An amount of time to process the pipe specification is estimated, including an amount of time to retrieve data via the web services as specified in the pipe specification. Based at least in part on the estimated amount of time, appropriate supplemental content is determined to present to a user while the pipe specification is being actually processed. | 02-19-2009 |
| 20090049212 | METHOD AND SYSTEMS FOR MESOCHRONOUS COMMUNICATIONS IN MULTIPLE CLOCK DOMAINS AND CORRESPONDING COMPUTER PROGRAM PRODUCT - Full-duplex communication over a communication link between an initiator operating with an initiator clock and a target operating with a target clock involves, in communication from the initiator to the target: storing data from the initiator in a first FIFO memory with the initiator clock, reading data from the initiator stored in the first FIFO memory, wherein reading is with the target clock transmitting the data read from the first FIFO memory over a first mesochronous link, and storing the data transmitted over the first mesochronous link in a buffer whereby the data are made available to the target. Communication from the target to the initiator includes: transmitting data from the target over a second mesochronous link, and storing the data transmitted over the second mesochronous link in a second FIFO memory, wherein storing is with the target clock, whereby the data are made available to the initiator for reading from the second FIFO memory with the initiator clock signal. | 02-19-2009 |
| 20090063736 | LOW POWER DIGITAL INTERFACE - This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided. | 03-05-2009 |
| 20090077279 | GENERAL PURPOSE INPUT/OUTPUT SYSTEM AND METHOD - A system for general purpose input-output (IO), including a first pad; an IO buffer comprising the first pad; and an IO datapath logic block operatively connected to the IO buffer, where the IO datapath logic block and the IO buffer are associated with a general purpose IO block in a heterogeneous configurable integrated circuit (HCIC). | 03-19-2009 |
| 20090177813 | Scalable Interface for a Memory Array - A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests. | 07-09-2009 |
| 20090259777 | METHODS AND APPARATUS FOR EXTENDING SHORT RANGE DATA INTERFACES - A data link for the transfer of data between first and second devices has first and second interfaces operative to transmit data according to a first data transmission protocol and an intermediate link connecting the first and second interfaces. The intermediate link is operative to transmit data according to a second data transmission protocol. Clock domains of the first and second interfaces are synchronized to a clock domain of the intermediate link. The intermediate link may have master and slave clocks synchronized by operation of the second protocol. In some applications the first and second interfaces are Firewire™ interfaces and the intermediate link is an ethernet link. The data link may be applied to deliver data from a peripheral, such as a camera, to a computer. | 10-15-2009 |
| 20090265487 | Method and System For Synchronization Indicator Enabled Sharing - A method and system for synchronization indicator enabled online meetings are disclosed. According to one embodiment, a computer implemented method comprises transmitting a screen change signal from a presenter system, the screen change signal indicating a change in presentation material. One or more synchronization signals are received at the presenter system, the one or more synchronization signals indicating current viewing status of one or more participant systems. The current viewing status of the one or more participant systems is updated based on the one or more synchronization signals. | 10-22-2009 |
| 20090292840 | POWER EFFICIENT METHOD FOR CONTROLLING AN OSCILLATOR IN A LOW POWER SYNCHRONOUS SYSTEM WITH AN ASYNCHRONOUS I2C BUS - In a method and apparatus for saving power in a device coupled to a bus, the device is placed to operate in a power saving mode by powering off a selective portion of the device including a device clock. If data communication over the bus is addressed to the device then the selective portion of the device, including the device clock, is triggered to return to a power on state from the power off state. The data communication is stored in shadow registers using a bus clock while the device clock is transitioning to the power on state. The data communication stored in the shadow registers is transferred to a register map under the control of the device clock operating in the power on state. Upon completion of the transfer of the data communication to the register map, the device is returned to operate in the power saving mode. | 11-26-2009 |
| 20090300237 | ASYNCHRONOUS/SYNCHRONOUS INTERFACE - The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. | 12-03-2009 |
| 20090307395 | Remote Control Method of External Devices - A method of controlling a plurality of external devices is performed on a computer which is set up with a plurality of remote control processes corresponding to the plurality of the external devices, and a management process for managing the remote control processes while communicating with the remote control processes. The management process is called to display icons corresponding to the remote control processes in a display field provided by the management process. Further, the management process acts when a specified operation is applied to one of the icons on the display field for sending a screen open instruction to one of the remote control processes corresponding to the icon to which the specified operation is applied. The remote control process which receives the screen open instruction is activated to display a control screen for use in remotely controlling the corresponding external device. | 12-10-2009 |
| 20100049888 | METHOD FOR SYNCHRONIZATION OF PERIPHERALS WITH A CENTRAL PROCESSING UNIT IN AN EMBEDDED SYSTEM - A method and apparatus for synchronizing I/O peripherals with a CPU in an embedded system is discussed. The method involves receiving an address from the CPU in response to a read and/or write access, translating the address received from the CPU to identify a I/O peripheral to be accessed, disabling the operation of the CPU and synchronizing a memory from the CPU clock domain to the clock domain of the identified I/O peripheral. Upon completion of the read/write access, the identified I/O peripheral sends an acknowledgment, the memory is then synchronized from the clock domain of the I/O peripheral to the CPU clock domain and the operation of the CPU is then enabled. | 02-25-2010 |
| 20100057955 | METHOD AND SYSTEM FOR REDUCING TRIGGERING LATENCY IN UNIVERSAL SERIAL BUS DATA ACQUISITION - A method of controlling one or more devices in data communication with a common controller to perform one or more functions, each of the devices having a synchronous clock, a synchronized real time clock register and a memory, the method comprising: arming the devices such that the devices commence performing the functions synchronously, receive and store to their respective memory data acquired as a result of performing the functions and store to their respective memory time stamp information indicative of the time of acquisition of the acquired data; a trigger device in data communication with the common controller responding to a command to perform the functions by sending a first message to the host controller that includes data indicative of a time of receipt of the command; the host controller responding to the first message by sending the devices a second message including data indicative of the time of receipt by the further device of the command; and the devices responding to the second message by reading their respective memories and sending the acquired data stored therein to the host controller commencing from a location in each respective memory corresponding to the time of receipt or a next available location. | 03-04-2010 |
| 20100064074 | SINGLE WIRE BUS INTERFACE - Embodiments disclosed herein address the need for a single wire bus interface. In one aspect, a device communicates with a second device via a single wire bus using a driver for driving the bus with a write frame comprising a start symbol, a write indicator symbol, an address, and data symbols. In another aspect, the device receives one or more data symbols on the single wire bus during a read frame. In yet another aspect, a device communicates with a second device via a single wire bus using a receiver for receiving a frame on the single wire bus comprising a start symbol, a write indicator symbol, an address, and one or more data symbols, and a driver for driving return read data associated with the address when the write indicator identifies a write frame. Various other aspects are also presented. These aspects provide for communication on a single wire bus, which allows for a reduction in pins, pads, or inter-block connections between devices. | 03-11-2010 |
| 20100199002 | INDUSTRIAL CONTROLLER - This invention realizes a synchronization control function without providing a bus dedicated for synchronization control by using a bus (system bus) used to transmit and receive data between units from the prior art. When a timer interruption occurs during the execution of a process performed in a normal cyclic, a CPU unit interrupts the process and transmits synchronization data by collective addressing using the system bus to other synchronization units performing the synchronization control. The synchronization unit executes a synchronization cycle upon the reception of the synchronization data by collective addressing as a trigger, acquires the received synchronization data with the start of the synchronization cycle, and performs a refresh process of the synchronization data of IN data after executing an input/output process. The CPU unit performs the refresh process of the synchronization data of the IN data, and obtains the synchronization data to be transmitted next by a synchronization interrupt task process. The synchronization unit constantly acquires the most recent synchronization data and simultaneously operates. | 08-05-2010 |
| 20100199003 | FIELD CONTROL SYSTEM - The field control system includes: a field device; a field controller which is connected to a control network and which executes a computation processing for controlling the field device according to a given control cycle while executing a data communication between the field controller and the field device, the field controller including a communication unit configured to execute the data communication with the field device, and a control computation unit configured to execute the computation processing independently from the communication unit; and an operation monitor which is connected to the control network and which operates and monitors the field device, the operation monitor including a network clock which provides a common network time to the control network. The control computation unit and the communication unit execute the computation processing and the data communication in synchronism with each other in accordance with a timer clock based on the network time. | 08-05-2010 |
| 20100205332 | MEDIA FILE SYNCHRONIZATION - The description generally relates to a system designed to synchronize the rendering of a media file between a master device and a sister device. The system is designed so that a media file is simultaneously rendered on a master device and a sister device beginning from identical temporal starting points. | 08-12-2010 |
| 20100223406 | MEMORY MODULES HAVING DAISY CHAIN WIRING CONFIGURATIONS AND FILTERS - Examples described include memory units coupled to a controller using a daisy chain wiring configuration. A filter located between a first memory unit and the controller attenuates a particular frequency, which may improve ringback in a signal received at the memory units. In some examples, a quarter-wavelength stub is used to implement the filter. In some examples, signal components at 800 MHz may be attenuated by a stub, which may improve ringback. | 09-02-2010 |
| 20100299462 | SIGNAL GENERATING APPARATUS AND SIGNAL GENERATING METHOD - A signal generating apparatus, applicable in a universal serial bus (USB) device, includes: a first determining circuit for receiving a data signal to determine if the data signal is generated by the universal serial bus device, and generating a first determined result; a second determining circuit coupled to the first determining circuit for receiving the data signal and the first determined result to determine a transmitting mode corresponding to the data signal according to the first determined result, and generating a second determined result; and a frequency generating circuit coupled to the second determining circuit for generating a first clock signal utilized for synchronizing the data signal according to the second determined result. | 11-25-2010 |
| 20110029700 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a clock input buffer, an asynchronous data input buffer, and a synchronous data input buffer. The clock input buffer is configured to buffer an external clocks in order to generate an internal clock. The asynchronous data input buffer is configured to buffer data input through a data pad and output the buffered data. The synchronous data input buffer is configured to be synchronous with the internal clock to buffer the buffered data. The semiconductor apparatus is arranged so that the length of a line for transferring the internal clock to the synchronous data input buffer and the length of a line for transferring the buffered data to the synchronous data input buffer are substantially equal to each other. | 02-03-2011 |
| 20110040907 | SERIAL COMMUNICATION DEVICE AND SERIAL COMMUNICATION METHOD - A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal. | 02-17-2011 |
| 20110213905 | COMMUNICATION PROTOCOL FOR CONTROLLING TRANSFER OF TEMPORAL DATA OVER A BUS BETWEEN DEVICES IN SYNCHRONIZATION WITH A PERIODIC REFERENCE SIGNAL - A communication protocol over the serial bus allows a peripheral device to control the flow of data between a host computer and the peripheral device so as to maintain synchronization to a periodic reference signal. The protocol involves transferring flow control messages between the peripheral device and the host computer, allowing the peripheral device to control how and when the host computer sends the uncompressed audio and video data. | 09-01-2011 |
| 20110296065 | CONTROL UNIT FOR THE EXCHANGE OF DATA WITH A PERIPHERAL UNIT, PERIPHERAL UNIT, AND METHOD FOR DATA EXCHANGE - A control unit is described that has at least one communications interface for the exchange of data with at least one peripheral unit, the communications interface being configured for transmitting synchronization signals to the peripheral unit in a first, synchronous operating mode. The communications interface is configured to change a time interval between two successive synchronization signals. | 12-01-2011 |
| 20120017013 | SYSTEM AND METHODS FOR AVOIDING DATA COLLISIONS OVER A DATA BUS - The disclosed system and methods involve controlling the timing and order in which numerous motors and sensors exchange data over a data bus. The method can be used with, for example, motion control, automotive, industrial automation, and medical equipment applications using data buses. As an example of one possible medical equipment application, the method of exchanging data on a bus can be used with a remote catheter guidance system. The disclosed system and methods help optimize data exchange over a bus and avoid collisions by grouping the transmission of sensor readings, by grouping the transmission of motor commands, and by predetermining the order of these groups. Further, the method provides a way of ensuring that incomplete data sets are not exchanged over the bus. The method also provides a way of synchronizing motor actuation based on data transmitted to the data bus. | 01-19-2012 |
| 20120066418 | SYNCHRONOUS NETWORK OF SUPERSPEED AND NON-SUPERSPEED USB DEVICES - A method of synchronising the operation of a plurality of SuperSpeed USB devices and a plurality of non-SuperSpeed USB devices is provided. The method includes establishing a SuperSpeed synchronisation channel for each of the plurality of SuperSpeed USB devices; establishing a non-SuperSpeed synchronisation channel for each of the plurality of non-SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of non-SuperSpeed USB devices; and synchronising the SuperSpeed and non-SuperSpeed synchronisation channels so that the SuperSpeed and non-SuperSpeed devices can operate in synchrony. | 03-15-2012 |
| 20120110225 | Method and communication system for determining the time of an event in an IO device - A method and communication system that provide an inexpensive approach that enables the times of events that are detected in IO device to be determined in a higher-level controller. The higher-level controller has a system clock and is connected to an IO link device to which multiple first IO devices are able to be connected. In addition, a second IO device is connected to the IO link device. The clock of the second IO device is synchronized by a synchronization device with the system clock of the higher-level controller. The status data that are provided by at least one of the first IO devices and the current time data that the second IO device supplies are transmitted simultaneously to the IO link device. The IO link device assigns the status data received to the received current time data, then transmits these data to the higher-level controller. | 05-03-2012 |
| 20120131242 | Method and Device for Asynchronous Communication of Data on a Single Conductor - The invention relates to the asynchronous communication of data in complex integrated systems, be it inside integrated circuit chips or between integrated circuit chips, for example in a compact stack of chips. According to the invention, the transmission is done on a single conductor of exchanges. The data are transmitted on this conductor in the form of at least three levels of potential, the first level representing a first value of data item transmitted, the second representing a second value of data item transmitted, and the third representing an inactive level. An acknowledgment signal is transmitted on the same exchange conductor as the data. This signal is preferably sent by the receiver in the form of the forcing of the exchange conductor by the receiver to the inactive potential level, the sender detecting this forcing. | 05-24-2012 |
| 20120173775 | PORT CONTROL APPARATUS AND ASSOCIATED METHODS - A method of controlling a port in an apparatus includes receiving an instruction for execution by a processor. The method further includes executing the instruction, by writing a value to a storage location corresponding to the port, and by initializing a count operation. The method further includes proceeding with the count operation until a final count value is reached, and providing to the port the value written to the storage location. | 07-05-2012 |
| 20130007315 | METHODS OF MULTI-SERVER APPLICATION SYNCHRONIZATION WITHOUT STOPPING I/O - A method according to one embodiment includes receiving, at an I/O Handler, an instruction to initiate a backup operation on data associated with an application running on multiple servers; and stretching communication between instances of the application and data storage volumes associated therewith during initiating the backup operation. Additional systems, methods, and computer program products are also disclosed. | 01-03-2013 |
| 20130042034 | SYNCHRONISATION OF DATA PROCESSING SYSTEMS - A centralised synchronising device for determining progress of at least a subset of transaction requests that are transmitted through a data processing system in response to receipt of a system synchronising request, the data processing system having a plurality of devices including a plurality of transaction request generating devices for generating the transaction requests and a plurality of recipient devices for receiving the transaction requests, the synchronising device and at least one interconnect for interconnecting at least some of the devices; wherein the system synchronising request comprising a request generated by one of the plurality of transaction generating devices and querying progress of the at least a subset of the transaction requests;
| 02-14-2013 |
| 20130042035 | Synchronization Of Data Between An Electronic Computing Mobile Device And An Electronic Computing Dockstation - Methods, apparatuses, and computer program products are provided for synchronization of data between an electronic mobile device and an electronic computing dockstation. Embodiments include detecting, by the dockstation, completion of a docking procedure connecting the mobile device to the dockstation; identifying, by the dockstation, applications that are open on the mobile device; opening, by the dockstation, the identified applications on the dockstation; identifying, by the dockstation, files that are open on the mobile device; syncing, by the dockstation, the identified files with corresponding files within the dockstation, including updating an existing file within the dockstation; and opening on the dockstation, by the dockstation, the synced files with the open applications on the dockstation. | 02-14-2013 |
| 20130103865 | FLEXIBLE COMMUNICATIONS - A method for transmitting data on a configurable bus of z physical links, including receiving input data on an input bus at at least one of a plurality of data rates, selecting a number of physical links n, amongst the z physical links, on which data is to be transmitted, selecting a clock frequency f at which the data is to be transmitted on the configurable bus, wherein the selections of n and f are based on information concerning the at least one of the plurality of data rates, the number of links used on the input bus. | 04-25-2013 |
| 20130191562 | SYNCHRONIZED MULTICHANNEL UNIVERSAL SERIAL BUS - The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB specification to provide synchronization information from an external source, and in another aspect comprising observing USB traffic and locking a local clock signal of a USB device to a periodic signal contained in USB data traffic, wherein the locking is in respect of phase and/or frequency. | 07-25-2013 |
| 20140281062 | APPARATUS, SYSTEM AND METHOD FOR PROVIDING ACCESS TO A DEVICE FUNCTION - Techniques and mechanisms for providing access to a function with an input/output (I/O) device. In an embodiment, a main memory of a computer system including the I/O device stores a function-context data structure associating a function with a context for an access to the function. The I/O device stores a configuration for the I/O device to provide the function. In another embodiment, the software process exchanges information with the function-context data structure for the access to the function. The I/O device performs a synchronization of the function-context data structure and the configuration data structure with respect to one another, wherein the function-context data structure operates as a register level interface which interfaces the I/O device and the software process with one another. | 09-18-2014 |
| 20150039791 | SYNCHRONISATION AND TRIGGER DISTRIBUTION ACROSS INSTRUMENTATION NETWORKS - A system for synchronising the operation of a measurement instrument having a microcontroller, a local oscillator and function circuitry to an external timebase is provided. The system includes a USB Host Controller; an interrupt generator adapted to respond to ITPs by generating respective interrupts and passing the interrupts to the microcontroller; and a timer for measuring an interval between receptions of the ITPs in a time domain of the local oscillator. | 02-05-2015 |
| 20150067202 | METHOD AND DEVICE FOR SYNCHRONIZING A CONTROL UNIT AND AT LEAST ONE ASSIGNED PERIPHERAL UNIT - In a method for synchronizing a control unit and at least one peripheral unit having actuators and/or sensors, the control unit and the peripheral unit exchange data with each other via a serial interface. The control unit transmits data to the at least one peripheral unit which is processed in the peripheral unit for the operation of the actuators and/or sensors, and at least one synchronization character is transmitted from the control unit to the peripheral unit for the synchronization. In this context, the synchronization character is appended by the control unit to a first data sequence of a data stream to be transmitted from the control unit to the peripheral unit, and the transmission of a second data sequence to be transmitted after the first data sequence is delayed in time on the part of the control unit, so that the second data sequence is transmitted by the control unit to the peripheral unit following the synchronization character. | 03-05-2015 |
| 20150089098 | SYNCHRONOUS NETWORK OF SUPERSPEED AND NON-SUPERSPEED USB DEVICES - A method of synchronising the operation of a plurality of SuperSpeed USB devices and a plurality of non-SuperSpeed USB devices is provided. The method includes establishing a SuperSpeed synchronisation channel for each of the plurality of SuperSpeed USB devices; establishing a non-SuperSpeed synchronisation channel for each of the plurality of non-SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of non-SuperSpeed USB devices; and synchronising the SuperSpeed and non-SuperSpeed synchronisation channels so that the SuperSpeed and non-SuperSpeed devices can operate in synchrony. | 03-26-2015 |
| 20150324322 | Adaptive Isochronous USB Audio To RF Communication Device - A method of and a system for synchronizing isochronous audio data frames provided by a USB interface to a clock of a wireless RF communication device is provided. The USB interface and the wireless RF communication device are connected via an I2S link, the method comprising receiving the isochronous audio data frames and the wireless RF communication device clock in a streaming controller, phase locking the isochronous audio data frames to a USB interface clock, counting start-of-frame pulses of the phase locked isochronous audio data frames, comparing the counted start-of-frame pulses with the wireless RF communication device clock to determine a difference signal, the difference signal triggering a synchronization event code when a threshold difference has been reached, rate matching the isochronous audio data frames to the wireless RF communication device clock upon receiving the synchronization event code. | 11-12-2015 |
| 20150331827 | METHOD AND CONTROL DEVICE FOR THE OPERATION OF A CONTACT-FREE TRANSMISSION SYSTEM FOR AN IO LINK - In a method and a control device for the operation of a transmission system for an IO link, wherein at least one cable-free transition between an IO link master and at least one IO link device is provided, and wherein the IO link device provides a minimal cycle time for a communication cycle, it is particularly provided that the minimal cycle time provided by the IO link device is increased in such a manner that a temporal delay caused by the cable-free transition is added to the minimal cycle time. | 11-19-2015 |
| 20150356031 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR PROVIDING PRECISE TIMING IN VIRTUAL DATA NETWORK OR STORAGE NETWORK TEST ENVIRONMENT - Methods, systems, and computer readable media for providing precise timing in a virtual data network or storage network test environment are provided. One method includes providing at least one peripheral device or peripheral device emulator including a timing source. The method further includes connecting the at least one peripheral or peripheral device emulator to a peripheral interface of a computing platform hosting a hypervisor on which at least one test or application under test virtual machine executes. The method further includes making the timing source available to the at least one virtual machine. The method further includes executing a test and using the timing source to provide precise timing for the test. | 12-10-2015 |
| 20160077983 | PROCESSOR COMMUNICATIONS - A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal. | 03-17-2016 |
