| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710057000 | Fullness indication | 40 |
| 20080215772 | SYSTEM METHOD STRUCTURE IN NETWORK PROCESSOR THAT INDICATES LAST DATA BUFFER OF FRAME PACKET BY LAST FLAG BIT THAT IS EITHER IN FIRST OR SECOND POSITION - A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one” or “zero” and indicates when the data buffer having the last bit is transmitted. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame. | 09-04-2008 |
| 20080256272 | Packet Scheduling for Data Stream Transmission - The invention relates to transmitting data elements of a data stream based on a priority and target buffer fill levels at a receiving device. A transmitter controller transmits data elements of a data element class with a highest priority first, for reaching an associated buffer fill level and then turns to data elements of successively lower priorities, until the available bandwidth is exhausted. | 10-16-2008 |
| 20080313368 | APPARATUS AND PROGRAM STORAGE DEVICE FOR MANAGING DATAFLOW THROUGH A PROCESSING SYSTEM - A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus. | 12-18-2008 |
| 20080320185 | Buffering device and buffering method - A buffering device buffers data to be subjected to any one of a first process that necessitates a sequential guarantee and a second process that does not necessitate the sequential guarantee, and includes a storage unit that stores therein plurality of target data to be processed; a reading unit that reads the target data from the storage unit one-by-one based on a waiting flag set corresponding to the target data; and a control unit that sets a waiting flag for each of the target data, the waiting flag of a specific target data indicating preceding target data that must be processed before the reading unit reads the specific target data. | 12-25-2008 |
| 20090037620 | Apparatus and Method for Efficient Communication of Producer/Consumer Buffer Status - An apparatus and method for efficient communication of producer/consumer buffer status are provided. With the apparatus and method, devices in a data processing system notify each other of updates to head and tail pointers of a shared buffer region when the devices perform operations on the shared buffer region using signal notification channels of the devices. Thus, when a producer device that produces data to the shared buffer region writes data to the shared buffer region, an update to the head pointer is written to a signal notification channel of a consumer device. When a consumer device reads data from the shared buffer region, the consumer device writes a tail pointer update to a signal notification channel of the producer device. In addition, channels may operate in a blocking mode so that the corresponding device is kept in a low power state until an update is received over the channel. | 02-05-2009 |
| 20090094391 | STORAGE DEVICE INCLUDING WRITE BUFFER AND METHOD FOR CONTROLLING THE SAME - A storage device having a write buffer and a method of controlling the same, in which data having a relatively lower temporal and spatial locality from an input/output (I/O) operation request requested from the storage device is filtered using a filter. Accordingly, the I/O operation request may be performed in the storage device without passing through the write buffer. | 04-09-2009 |
| 20090125649 | VARIABLE SPEED BUFFER SERVO CONTROL FOR LINEAR TAPE DRIVES - A variable speed linear tape drive includes a driver portion for rotating a supply reel of a tape cartridge having storage media spooled therein, a motor coupled to rotate the driver portion, a controller configured to control the motor in accordance with a control algorithm, an interface for one or more of sending data to and receiving data from a host; and a buffer for storing one or more of data received from the host and data to be transmitted to the host, the buffer operable to supply a buffer fill level indication to the controller, wherein the control algorithm is operable to generate a difference between a target buffer fill level and the buffer fill level indication and adjust at least one of an angular velocity or an acceleration of the motor to reduce the difference. | 05-14-2009 |
| 20090125650 | Buffer status reporting apparatus, system, and method - An apparatus, system and method for increasing buffer status reporting efficiency and adapting buffer status reporting according to uplink capacity. User equipment is configured a monitor a usage of a plurality of buffers, detect one of a plurality of pre-selected conditions corresponding to at least one of the plurality of buffers, designate one of a plurality of buffer status reporting formats depending on the pre-selected condition detected, communicate a buffer status report to a network device in accordance with the buffer status reporting format designated. The buffer status reporting format is configured to minimize buffer status reporting overhead created by the communicating of the buffer status report. | 05-14-2009 |
| 20090157919 | READ CONTROL IN A COMPUTER I/O INTERCONNECT - In one embodiment, a method for controlling reads in a computer input/output (I/O) interconnect is provided. A read request is received over the computer I/O interconnect from a first device, the request requesting data of a first size. Then it is determined whether fulfilling the read request would cause the total size of a completion queue to exceed a first predefined threshold. If fulfilling the read request would cause the total size of the completion queue to exceed the first predefined threshold, then the read request is temporarily restricted from being forwarded upstream | 06-18-2009 |
| 20090187682 | Method for Detecting Circular Buffer Overrun - A computer implemented method, data processing system, and computer program product for detecting circular buffer overrun in a credit-based data management system, wherein the system comprises a total credit exchange amount of at least one less than the total number of entries in a circular buffer. When data in a data item entry is processed in the circular buffer, a valid mark bit is set in the data item entry to an inactive state. A location of the data item entry previously processed is then stored. A valid mark bit of a next data item entry in the circular buffer and the valid mark bit in the data item entry previously processed are read. Responsive to a determination that the valid mark bit in the data item entry previously processed indicates the data item entry contains data to be processed, an indication may be generated that a circular buffer overflow has occurred. | 07-23-2009 |
| 20090204734 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR ENHANCED SHARED STORE BUFFER MANAGEMENT SCHEME WITH LIMITED RESOURCES FOR OPTIMIZED PERFORMANCE - The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise storage buffers that have the capability to efficiently support 128 byte or 256 byte I/O data transmission lines. The presently implemented storage buffer management scheme enables for a limited number of store buffers to be associated with a fixed number of storage state machines (i.e., queue positions) and thereafter the allowing for the matched pairs to be allocated in order to achieve maximum store throughput for varying combinations of store sizes of 128 and 256 bytes. | 08-13-2009 |
| 20100077113 | DATA COMMUNICATION SYSTEM AND METHOD - Provided is a data communication system including a first-in first-out (FIFO) buffer having a fixed size; a central processing unit (CPU) that writes data stored in a memory into the FIFO buffer; a modem that reads the data written by the CPU from the FIFO buffer; and a modem controller that is connected to the FIFO buffer, the CPU, and the modem, respectively, and controls the CPU such that data having a larger volume than the size of the FIFO buffer can be processed. | 03-25-2010 |
| 20100169520 | INFORMATION PROCESSOR - An information processor (program processing unit | 07-01-2010 |
| 20100299461 | INFORMATION PROCESSING APPARATUS AND IMAGE FORMING APPARATUS - An information processing apparatus includes a processing unit and a control unit connected with the processing unit through a transmission line. The processing unit has multiple devices including a predetermined low-speed device. The control unit has a processing circuit that issues access to the multiple devices of the processing unit, and the processing unit has a communication circuit that receives the access to the multiple devices through the transmission line and a queue that buffers the access, when the received access is to the predetermined low-speed device. | 11-25-2010 |
| 20100306426 | FIFO BUFFER - A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory ( | 12-02-2010 |
| 20100332698 | EFFICIENT BUFFER MANAGEMENT IN A MULTI-THREADED NETWORK INTERFACE - Some embodiments of the present invention provide a system for receiving packets on a multi-threaded computing device which uses a memory-buffer-usage scorecard (MBUS) to enable multiple hardware threads to share a common pool of memory buffers. During operation, the system can identify a memory-descriptor location for posting a memory descriptor for a memory buffer. Next, the system can post the memory descriptor for the memory buffer at the memory-descriptor location. The system can then update the MBUS to indicate that the memory buffer is in use. Next, the system can store a packet in the memory buffer, and post a completion descriptor in a completion-descriptor location to indicate that the packet is ready to be processed. If the completion-descriptor indicates that the memory buffer is ready to be reclaimed, the system can reclaim the memory buffer, and update the MBUS to indicate that the memory buffer has been reclaimed. | 12-30-2010 |
| 20110040906 | Multi-level Buffering of Transactional Data - An apparatus, method, and system for implementing a hardware transactional memory (HTM) system with multiple levels of transactional buffers. The apparatus comprises a data cache configured to buffer data in a shared (by a plurality of processing cores) memory accessed by speculative memory access operations and to retain the data during at least a portion of an attempt to execute the atomic memory transaction. The apparatus also comprises an overflow detection circuit configured to detect an overflow condition upon determining that the data cache has insufficient capacity to buffer a portion of data accessed as part of the atomic memory transaction, as well as a buffering circuit configured to respond to the detection of the overflow condition by preventing the portion of data from being buffered in the data cache and buffering the portion of data in a secondary buffer separate from the data cache. | 02-17-2011 |
| 20110055439 | BUS BRIDGE FROM PROCESSOR LOCAL BUS TO ADVANCED EXTENSIBLE INTERFACE - Disclosed is a method of processing a read/write request conforming to the PLB bus protocol and a bus bridge from PLB bus to AXI bus, the method comprising: receiving the read/write request conforming to the PLB bus protocol without waiting for an acknowledgement of successful execution of a previous read/write request conforming to the PLB bus protocol; buffering the read/write request conforming to the PLB bus protocol; mapping the buffered read/write request conforming to the PLB bus protocol to a read/write request conforming to a AXI bus protocol; and outputting the mapped read/write request conforming to the AXI bus protocol. The method and the bus bridge enable IP modules conforming to PLB bus protocol and AXI bus protocol to communicate and perform transaction mapping during communication, to guarantee that all the transactions are performed in an order desired by the PLB device, and improve communication efficiency of the SoC. | 03-03-2011 |
| 20110093629 | Control Function for Memory Based Buffers - Instantiating a plurality of buffers in a random access memory by storing in the random access memory (RAM) a plurality of descriptors each containing a base address, at least one address pointer and a size to define a corresponding one of the plurality of buffers. Transferring data in any one of the plurality of buffers by using a control function within an accessing module to generate a buffer address by accessing and updating the address pointer in the corresponding descriptor. In a processor that accesses the circular buffers, the control function is one or more complex instructions tailored for computing read and write addresses to access the circular buffer using fields within the corresponding descriptor. In a DMA module that accesses the circular buffers, the control function is a hardware controller that computes read and write addresses using the fields within the corresponding descriptor to access the circular buffer. | 04-21-2011 |
| 20110119415 | RECORDING DEVICE, METHOD OF CONTROLLING RECORDING DEVICE, PROGRAM, AND RECORDING MEDIUM - A recording device is connectable to a host computer and performs recording on the basis of received data including commands, received from the host computer. A receiving buffer stores therein the received data received from the host computer. A command detection section reads the received data stored in the receiving buffer while scanning the receiving buffer with a first read pointer to detect the commands included in the received data. A command execution section processes the commands detected by the command detection section in a stored order of the commands in the receiving buffer. An immediate processing command detection section reads the received data stored in the receiving buffer while scanning the receiving buffer with a second read pointer which is provided separately from the first read pointer to detect an immediate processing command included in the received data. The command execution section preferentially processes the immediate processing command detected by the immediate processing command detection section regardless of the stored order of the commands in the receiving buffer. | 05-19-2011 |
| 20110296064 | UPLINK DATA THROTTLING BY BUFFER STATUS REPORT (BSR) SCALING - A technique for uplink data throttling includes buffer status report (BSR) scaling. A target data flow rate may be determined based on at least on condition of a wireless device. The buffer status report may be adjusted to cause the target flow rate and transmitted by the wireless device. The wireless device may then receive a flow control command based on the buffer status report. | 12-01-2011 |
| 20110307637 | DATA TRANSFER DEVICE AND DATA TRANSFER METHOD - A data transfer device includes a data buffer, an odd number flag, and a control unit. The data buffer holds an even number of data blocks from a data transfer controller. The odd number flag is set when the number of data blocks to be transferred to a receiving device is odd. The control unit transfers an even number of data blocks to the receiving device for each data transfer cycle with respect to the receiving device, and transfers one data block to the receiving device in a last transfer cycle when the odd number flag is set. Thus, also when the data transfer controller which transfers data in a unit of an even number of data blocks is used, not only an even number of data blocks but an odd number of data blocks may be transferred to the receiving device. | 12-15-2011 |
| 20120079144 | Low Latency First-In-First-Out (FIFO) Buffer - Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data received from either the buffer input or the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input. Buffer control logic is configured to selectively route data from the buffer input or the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner. | 03-29-2012 |
| 20120110224 | DATA PROCESSING APPARATUS AND IMAGE PROCESSING APPARATUS - A data processing apparatus may include a buffer unit, a data write control unit, a data read control unit, and a buffer area determination unit. The data write control unit may write the input data to the storage area determined by the buffer area determination unit, and output a data write completion signal indicating that the writing of the data is completed when the writing of the input data is completed. The data read control unit may read the data from the storage area determined by the buffer area determination unit, and output a data read completion signal indicating that the reading of the data is completed when the output of the output data generated based on the read data is completed. | 05-03-2012 |
| 20120226833 | INTEGRATED CIRCUIT AND METHOD FOR REDUCING VIOLATIONS OF A TIMING COSTRAINT - An integrated circuit and a method for reducing violations of a timing constraint. The integrated circuit comprises a shared resource for providing data and a buffer for storing data. A buffer level monitor is coupled to the buffer, for monitoring a monitored level of data in the buffer. A retrieving circuit is coupled to the buffer, for retrieving the data from the buffer, according to a timing constraint. A filling circuit is coupled to the buffer for writing the data to the buffer and coupled to the shared resource for receiving the data from the shared resource when the filling circuit has access to the shared resource. An access-requesting circuit is coupled to the shared resource for receiving the data from the shared resource when the access-requesting circuit has access to the shared resource. An arbiter is coupled to the shared resource, the filling circuit, and the access-requesting circuit, for receiving access requests from the filling circuit and from the access-requesting circuit, and for granting to a selected one thereof access to the shared resource. A controller is coupled to the buffer level monitor and to the access-requesting circuit, for causing the access-requesting circuit to reduce a rate of access requests sent to the arbiter when a condition indicating an anticipated violation of the timing constraint is fulfilled, the condition at least involving the monitored level of data in the buffer. | 09-06-2012 |
| 20120317318 | METHOD OF ANALYZING THE WEAR OF A NON VOLATILE MEMORY EMBEDDED IN A SECURE ELECTRONIC TOKEN - The invention is a method of analyzing the wear of a non volatile memory embedded in a secure electronic token. A set of events are intended to generate writing and/or erasing operations in said memory. The token comprises a buffer. The method comprises the following steps: each time an event belonging to said set occurs, generating a data which reflects the event and storing said data in the buffer, sending the buffer to a remote machine, analyzing the buffer to determine the wear of the memory. | 12-13-2012 |
| 20120331190 | CPU CONNECTION CIRCUIT, DATA PROCESSING APPARATUS, ARITHMETIC PROCESSING DEVICE, PORTABLE COMMUNICATION TERMINAL USING THESE MODULES AND DATA TRANSFER - There are provided a CPU connection circuit and a method by two CPUs by alternately conducting a changeover between two buffers disposed there between to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller which monitors whether or not an amount of data stored by a CCPU | 12-27-2012 |
| 20130103864 | DEVICE FOR INDICATING STATUS OF HARD DISK - The present invention provides a device for indicating status of hard disk. The device includes a SGPIO (Serial General Purpose Input/Output) input terminal, a serial-parallel converting unit, a buffer unit, and a status indicating unit. The serial-parallel converting unit is connected with the SGPIO input terminal and converts the serial signals into parallel signals. The buffer unit is connected with the serial-parallel converting unit and stores the parallel signals temporally. The status indicating unit is connected with the buffer unit and indicates the status of the at least one hard disk according to the parallel signals from the buffer unit. | 04-25-2013 |
| 20130191560 | METHOD AND APPARATUS FOR BUFFER INITIALIZATION - A method, apparatus and computer program product are provided herein to enable buffer initialization and/or clearance to occur on, for example, a mobile terminal. In some example embodiments, a method is provided that comprises receiving an indication that a buffer has been initialized by a host. The method of this embodiment may also include receiving source code from the host. In some example embodiments, the source code is received from a program running on the host and is configured to cause the buffer that has been initialized by the host to be cleared. The method of this embodiment may also include executing the source code such that the buffer that has been initialized by the host is cleared. | 07-25-2013 |
| 20130191561 | DATA READING DEVICE, COMMUNICATION DEVICE, DATA READING METHOD AND PROGRAM - The wireless communication device of the present invention is provided with a received data FIFO for temporarily storing received data, and a data reading section for reading received data from the received data FIFO. The data reading section, when received data to be read is stored in the received data FIFO, reads and outputs the stored received data. Meanwhile, when the received data to be read is not stored in the received data FIFO and a predetermined condition is fulfilled, the data reading section outputs dummy received data. Furthermore, when the received data to be read is not stored in the received data FIFO and the predetermined condition is not fulfilled, the data reading section outputs an error. | 07-25-2013 |
| 20130198420 | CONTROLLER FOR STORAGE DEVICE AND METHOD FOR CONTROLLING STORAGE DEVICE - A controller for a storage device is connected to a host system and the storage device. A buffer memory includes first and second storage areas. A timer counts a preset given time in response to an instruction to start counting and sends a deadline notification when A given time is elapsed. A command responding portion, when receiving a read command from the host system, instructs the timer to start counting and thereafter outputs a read instruction to read data from the storage system. A data processing portion, in response to the read instruction by the command responding portion, reads specified data from the storage device and holds the read data in the second storage area of the buffer memory. A read control portion sends the host system the data held in the second storage area of the buffer memory when the deadline notification is received from the timer. | 08-01-2013 |
| 20130205052 | SYSTEM FOR MANAGING BUFFERS OF TIME-STAMPED EVENTS - A system for managing time-stamped events with uncertain events-sequence signalling, including a list of variables of which a change of value must lead to the detection of an event to be time-stamped and to be saved; means, for each variable, for positioning a marker indicating the quality of the time-stamping of said event; a buffer for the storage, before they are read by client software, of said events to be time-stamped and to be saved, associated respectively with a time-stamping time, said time-stamped events read by the client software being erased from the buffer; means for enabling and for disabling means for saving in a history the values of the variables corresponding to said time-stamped events that have been read. | 08-08-2013 |
| 20130238822 | FIRST-IN FIRST-OUT MEMORY DEVICE AND ELECTRONIC APPARATUS HAVING THE SAME - A first-in first-out (FIFO) memory device includes a main FIFO unit, an auxiliary FIFO unit and a control unit. The main FIFO unit includes first through N-th one-port memories, each of which including M entries, where N and M are integers greater than or equal to two. The auxiliary FIFO unit includes one dual-port memory having M entries. The control unit performs a write operation by receiving a write command and data and storing the data in one of the main FIFO unit and the auxiliary FIFO unit based on an operating mode, and performs a read operation by receiving a read command and reading the data from one of the main FIFO unit and the auxiliary FIFO unit based on the operating mode | 09-12-2013 |
| 20140075060 | GPU MEMORY BUFFER PRE-FETCH AND PRE-BACK SIGNALING TO AVOID PAGE-FAULT - This disclosure proposes techniques for demand paging for an IO device (e.g., a GPU) that utilize pre-fetch and pre-back notification event signaling to reduce latency associated with demand paging. Page faults are limited by performing the demand paging operations prior to the IO device actually requesting unbacked memory. | 03-13-2014 |
| 20140164655 | FOLDED FIFO MEMORY GENERATOR - Synthesizable code representing first-in-first out (FIFO) memories may be used to produce FIFO memories in a hardware element or system. To more efficiently use a memory element that stores the data in a FIFO, a code generator may generate a wrapper that enables the FIFO to use a memory element with different dimension (i.e., depth and width) than the FIFO's dimensions. For example, the wrapper enables a 128 deep, 1 bit wide FIFO to store data in a memory element with 16 rows that store 8 bits each. To any system communicating with the FIFO, the FIFO behaves like a 128×1 FIFO even though the FIFO is implemented using a 16×8 memory element. To do so, the code generator may generate a wrapper which enables the folded memory element to behave like a memory element that was not folded. | 06-12-2014 |
| 20140195703 | ELECTRONIC SYSTEM SUBJECT TO MEMORY OVERFLOW CONDITION - A method of operating an electronic system comprises storing information corresponding to an input data stream in a first memory having a first operating rate, detecting an overflow condition of the first memory, generating overflow information in response to the detection of the overflow condition, storing the overflow information in a second memory having a second operating rate slower than the first operating rate, transferring the overflow information from the detector to a third memory at a first transfer rate corresponding to the first operating rate, temporarily storing the overflow information in the third memory, and transferring the stored overflow information to the second memory at a second transfer rate corresponding to the second operating rate, and combining the information stored in the first memory with the overflow information stored in the second memory to produce an output data stream. | 07-10-2014 |
| 20140201398 | RATE CONTROLLED FIRST IN FIRST OUT (FIFO) QUEUES FOR CLOCK DOMAIN CROSSING - First in, first out (FIFO) queues may be used to transfer data between a producer clock domain and a number of consumer clock domains. In one implementation, a control component for the FIFO queues may include a number of counters, corresponding to each of the consumer clock domains, each of the counters maintaining a count value relating to an amount of data read by the corresponding consumer clock domain. The control component may additionally include a credit deduction component coupled to the count values of the counters, the credit deduction component determining whether any of the count values is above a threshold, and in response to the determination that any of the count values is above the threshold, reducing the count value of each of the counters and issuing a write pulse signal to the producer clock domain, the write pulse signal causing the producer clock domain to perform a write operation to the FIFO queues. | 07-17-2014 |
| 20140297907 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - A data processing apparatus includes a shared buffer; an issuing unit that issues a write address for writing incoming data to the shared buffer; a receiving unit that receives a returned read address for the data read from the shared buffer; a monitoring buffer that saves information indicating use status of an address for the shared buffer; and a monitoring unit that monitors write address issuance and returned read address reception, changes the information for the write address, from an unused state to a used state, when the write address is issued, and changes the information for a read address to be returned, from a used state to an unused state when the returned read address is received. The monitoring unit determines the address for the shared buffer is overlapping, when the information for the write address indicates a used state when the write address is issued. | 10-02-2014 |
| 20150039790 | DYNAMIC PRIORITY CONTROL BASED ON LATENCY TOLERANCE - A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel. | 02-05-2015 |
| 20160005963 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer including a hole over a substrate; a first nitride layer disposed on sidewalls of the hole; a selector disposed in a bottom portion of the hole and over the first nitride layer on the sidewalls of the hole; a stacked structure including a variable resistance pattern disposed over a lower structure including the selector; and a second nitride layer disposed in an upper portion and on sidewalls of the stacked structure. | 01-07-2016 |
