| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710028000 | With access regulating | 21 |
| 20080235411 | Peripheral Interface, Receiving Apparatus and Data Communication Method Using the Same - Peripheral interface(s), a receiving apparatus and a data communication method using the same are disclosed. According to an embodiment of the present invention, a peripheral interface comprises one or more pins for multiplexing at least two types of interfaces, wherein the pins transmit interface signals corresponding to an interface type and type-associated operating mode which are selected from those multiplexed by the pins. According to another embodiment, a receiving apparatus comprises: a peripheral interface for multiplexing at least two types of interfaces; a receiving module for receiving an instruction signal; a selecting module for selecting an interface type and type-associated operating mode which corresponds to an external device to be connected, based on the instruction signal; a controlling module for controlling the peripheral interface to communicate with the external device via at least one interface signal corresponding to the selected interface type and type-associated operating mode. | 09-25-2008 |
| 20080256267 | High-speed data readable information processing device - A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory. | 10-16-2008 |
| 20090024773 | HOST CONTROLLER - A versatile SDIO host controller capable of connecting to standardized general interfaces is provided. | 01-22-2009 |
| 20090043920 | SIMULTANEOUS PERSONAL SENSING AND DATA STORAGE - A personal sensing device that may be used for storing personal data and sensed data arbitrates and prioritizes competing requests for memory access from sensing, wireless, and wired interfaces. The personal sensing device enables power efficiency with burst-writes to the memory at higher data rates then an incoming sensor data stream without risk of data loss. Sensing operations coordinated by reconfigurable control logic are partitioned from storage operations coordinated by a multi-port memory controller. The interface between the functional partitioning uses message passing, status/control registers and buffering to reduce or eliminate system interdependencies. | 02-12-2009 |
| 20090150576 | Dynamic logical data channel assignment using channel bitmap - A method, system and program are provided for dynamically allocating DMA channel identifiers by virtualizing DMA transfer requests into available DMA channel identifiers using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once an input value associated with the DMA transfer request is mapped to the selected DMA channel identifier, the DMA transfer is performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfer. When there is a request to wait for completion of the data transfer, the same input value is used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing. | 06-11-2009 |
| 20090222598 | DMA CONTROLLER FOR DIGITAL SIGNAL PROCESSORS - A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses; and a multiplexer configured to supply first and second current memory addresses to selected ones of the first and second memory pipelines in response to a control signal. | 09-03-2009 |
| 20090271536 | DESCRIPTOR INTEGRITY CHECKING IN A DMA CONTROLLER - The present invention relates to a Direct Memory Access controller that, in an embodiment, executes I/O descriptors conditionally. A linked list item contains a checksum computed on the descriptor fields. When the linked list item is fetched, the checksum is computed on the descriptor. If both checksums are equal, the linked list item is considered valid and the descriptor is executed. At the end of a DMA I/O, the next descriptor in the linked list is fetched. When the checksum fails, the descriptor is corrupted and the channel is stopped and an error is reported to the operating system. | 10-29-2009 |
| 20090287861 | PROTECTING COMPUTER MEMORY FROM SIMULTANEOUS DIRECT MEMORY ACCESS OPERATIONS USING ACTIVE AND INACTIVE TRANSLATION TABLES - A method, apparatus, and program product access memory resources of a computer using a group of direct access memory (DMA) devices. A first DMA device is designated a primary device after association with an active translation table (ATT), while a second DMA device is designated a backup device after association with an inactive translation table (ITT). A translation is entered into the ATT for the first DMA device to permit it to perform a DMA operation, while a translation is inhibited from being entered into the ITT for a second DMA device to prevent it from performing a DMA operation. Thereafter, the roles of the first and second DMA devices may be swapped by associating the first DMA device with the ITT and associating the second DMA device with the ATT. The computer may be a logically partitioned computer of the type that includes a plurality of logical partitions. | 11-19-2009 |
| 20100023653 | SYSTEM AND METHOD FOR ARBITRATING BETWEEN MEMORY ACCESS REQUESTS - A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and to generate a DVFS indication that is indicative of the determination; (ii) a hardware access request determination module, adapted to determine a priority of memory access request issued by the first memory access requester in response to the DVFS indication; and (iii) a direct memory access arbitrator, adapted to arbitrate between memory access requests issued by the first memory access requester and another memory access requester in response to priorities associated with the memory access requests. | 01-28-2010 |
| 20100042756 | DATA TRANSFER DEVICE - A data transfer device for performing direct memory access (DMA) transfer of data stored in a storage unit to a plurality of other devices includes: a plurality of channel units arranged to correspond to the other devices, the channel units retaining DMA transfer instructions, and outputting number of the DMA transfer instructions retained; a plurality of priority controllers for determining priorities of the channel units on the basis of the number of the DMA transfer instructions retained in the channel units, respectively; an arbiter for selecting one of the DMA transfer instructions retained in one of the channel units on the basis of the priorities determined by the priority controller; and a data transfer processor for performing DMA transfer of data stored in the storage unit to one of the other devices in accordance with the DMA transfer instruction selected by the arbiter. | 02-18-2010 |
| 20100082850 | INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING SAME - Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected. | 04-01-2010 |
| 20100146160 | METHOD AND APPARATUS FOR PROVIDING DATA ACCESS - A method of providing access to first data stored at a first device to a second device, the first device storing the first data in a memory accessible to said second device. The method comprises, at a control element distinct from each of said first and second devices accessing the stored first data in said memory accessible to said second device before said first data is accessed in said memory accessible to said second device by said second device. | 06-10-2010 |
| 20110173353 | Virtualizing A Host USB Adapter - Virtualizing a host USB adapter in a virtualized environment maintained by a hypervisor, the hypervisor administering one or more logical partitions, where virtualizing includes receiving, by the hypervisor from a logical partition via a logical USB adapter, a USB Input/Output (‘I/O’) request, the logical USB adapter associated with a USB device coupled to the host USB adapter; placing, by the hypervisor, a work queue element (‘WQE’) in a queue of a queue pair associated with the logical USB adapter; and administering, by an interface device in dependence upon the WQE, USB data communications among the logical partition and the USB device including retrieving, with direct memory access (‘DMA’), USB data originating at the USB device from the host USB adapter into a dedicated memory region for the logical USB adapter. | 07-14-2011 |
| 20110179199 | SUPPORT FOR NON-LOCKING PARALLEL RECEPTION OF PACKETS BELONGING TO THE SAME RECEPTION FIFO - A method and apparatus for distributed parallel messaging in a parallel computing system. A plurality of DMA engine units are configured in a multiprocessor system to operate in parallel, one DMA engine unit for transferring a current packet received at a network reception queue to a memory location in a memory FIFO (rmFIFO) region of a memory. A control unit implements logic to determine whether any prior received packet destined for that rmFIFO is still in a process of being stored in the associated memory by another DMA engine unit of the plurality, and prevent the one DMA engine unit from indicating completion of storing the current received packet in the reception memory FIFO (rmFIFO) until all prior received packets destined for that rmFIFO are completely stored by the other DMA engine units. Thus, there is provided non-blocking support so that multiple packets destined for a single rmFIFO are transferred and stored in parallel to predetermined locations in a memory. | 07-21-2011 |
| 20120124250 | INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING SAME - Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected. | 05-17-2012 |
| 20120239829 | CONTROL METHOD OF DEVICE IN STORAGE SYSTEM FOR VIRTUALIZATION - In a system where a first storage system and a second storage system are connected to a third storage system, when the first storage system virtualizes and provides a device in the third storage system as a device in its own storage system, update data stored in a cache in the first storage system is written into the device of the third storage system to be reflected, attributes of the device are transferred to the second storage system, and the second storage system virtualizes the device of the third storage system as a device of its own storage system. | 09-20-2012 |
| 20130138842 | MULTI-PASS SYSTEM AND METHOD SUPPORTING MULTIPLE STREAMS OF VIDEO - Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data. | 05-30-2013 |
| 20130275631 | DIRECT I/O ACCESS FOR SYSTEM CO-PROCESSORS - Embodiments of the invention describe systems, apparatuses and methods that enable sharing Remote Direct Memory Access (RDMA) device hardware between a host and a peripheral device including a CPU and memory complex (alternatively referred to herein as a processor add-in card). Embodiments of the invention utilize interconnect hardware such as Peripheral Component Interconnect express (PCIe) hardware for peer-to-peer data transfers between processor add-in cards and RDMA devices. A host system may include modules or logic to map memory and registers to and/or from the RDMA device, thereby enabling I/O to be performed directly to and from user-mode applications on the processor add-in card, concurrently with host system I/O operations. | 10-17-2013 |
| 20130304949 | COMPUTER AND INPUT/OUTPUT CONTROL METHOD OF COMPUTER - An HBA driver manages a queue number for enqueuing and dequeuing data to an I/O queue by the main storage, and HBA-F/W manages a storage region at inside of HBA. The HBA driver reduces the number of access times by way of the PCIe bus by noticing an enqueued queue number or a dequeued queue number of an I/O queue to HBA-F/W by utilizing an MMIO area of the main storage in which a storage region on HBA is mapped. | 11-14-2013 |
| 20140032794 | USB VIRTUALIZATION - Described herein are methods and systems for virtualization of a USB device to enable sharing of the USB device among a plurality of host processors in a multi-processor computing system. A USB virtualization unit for sharing of the USB device include a per-host register unit, each corresponding to a host processor includes one or more of a host register interface, host data interface, configuration registers, and host control registers, configured to receive simultaneous requests from one or more host processors from amongst the plurality of host processors for the USB device. The USB virtualization unit also includes a pre-fetch direct memory access (DMA) configured to pre-fetch DMA descriptors associated with the requests to store in a buffer. The USB virtualization unit further includes an endpoint specific switching decision logic (ESL) configured to schedule data access based on the DMA descriptors from the host processor's local memory corresponding to each request. | 01-30-2014 |
| 20160048345 | ALLOCATION OF READ/WRITE CHANNELS FOR STORAGE DEVICES - Embodiments are disclosed for improving channel performance in a storage device, such as a flash memory or a flash-based solid state drive, by dynamically provisioning available data channels for both write and read operations. In one aspect, a set of available data channels on a storage device is partitioned into a set of write channels and a set of read channels according to a read-to-write ratio. Next, when an incoming data stream of mixed read requests and write requests arrives at the storage device, the allocated read channels process the read requests on a first group of memory blocks, which does not include garbage collection and write amplification on the first group of memory blocks. In parallel, the allocated write channels process the write requests on a second group of memory blocks, which does include garbage collection and write amplification on the second group of memory blocks. | 02-18-2016 |
