| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710027000 | Via separate bus | 8 |
| 20080301329 | Data Transfer Apparatus and Data Transfer Method - A data transfer apparatus includes a processor, a main memory, and a DMAC connected to the main memory via a plurality of buses. The DMAC transfers data to the main memory by bypassing the processor, writes flag data “1” indicating completion of the data transfer processing in a completion status storage area of the main memory, and finally outputs an interrupt signal to the processor. In response to the interrupt signal, an interrupt handler refers to the completion status storage area, and when the flag data is written, reads the data in the main memory and erases the flag data in the completion status storage area. | 12-04-2008 |
| 20090138628 | MULTI-BUS ARCHITECTURE FOR MASS STORAGE SYSTEM-ON-CHIP CONTROLLERS - Systems and methods that can facilitate an expedient and efficient transfer of data between memory components (e.g., flash memory) and host components (e.g., multimedia cards, secure digital cards, etc.) are presented. A memory controller component can be employed to facilitate transferring between the memory components and host components by utilizing a multi-bus architecture. A controller first bus can be utilized for code that can be executed by a controller processor while a controller second bus can be designated for the transfer of data to the mass storage devices. By architecting the memory controller component with two buses, this innovation can provide a higher data throughput than conventional memory controllers. | 05-28-2009 |
| 20100318689 | Device for real-time streaming of two or more streams in parallel to a solid state memory device array - Device for real-time streaming to an array of solid state memory device sets, said device comprising receiving means for receiving data from data streams of individual data rate in parallel, an input cache for buffering received data, a bus system for transferring data from the input buffer to the solid state memory device sets, and a controller adapted for using a page-receiving-time t_r, a page-writing-time wrt_tm, the data amount p and the individual data rates for dynamically controlling the bus system such that data received from the first data stream is transferred to solid state memory device sets comprised in a first subset of said array of solid state memory device sets, only, and data received from the at least a second data stream is transferred to solid state memory device sets comprised in a different second subset of said array of solid state memory device sets, only. | 12-16-2010 |
| 20130073753 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic. | 03-21-2013 |
| 20130246670 | INFORMATION PROCESSING SYSTEM - An information processing system includes a CPU that is connected to a bus; a device that is connected to the bus; a memory that is accessed by the CPU or the device; and a power mode control circuit that sets a power consumption mode. The power mode control circuit sets the power consumption mode based on first information that indicates a cache hit or a cache miss of a cache memory in the CPU and second information that indicates an activated state or a non-activated state of the device. | 09-19-2013 |
| 20140223041 | INTEGRATED CIRCUIT USING I2C BUS AND CONTROL METHOD THEREOF - An integrated circuit for controlling a slave device is provided. The integrated circuit includes a pin, a micro-controller and an inter integrated circuit (I | 08-07-2014 |
| 20140244866 | BANDWIDTH AWARE REQUEST THROTTLING - A method for managing bandwidth of a bus connecting a peripheral device to a host system includes sending, over the bus, a first read request to the host system, incrementing a pending read counter by an amount corresponding to the requested data, receiving, in response to sending the first read request, at least a portion of the requested data from the host system, decrementing the pending read counter by an amount corresponding to the at least the portion of the requested data, and comparing the counter and a threshold to obtain a result. Based on the result, a scheme is selected for managing the bandwidth of the bus. The scheme specifies a ratio of read requests and write requests to be sent on the bus. The method further includes sending, based on the scheme, a second request that is a write request or a second read request. | 08-28-2014 |
| 20150347012 | SYSTEM AND METHOD OF INTERLEAVING DATA RETRIEVED FROM FIRST AND SECOND BUFFERS - A host interface communicates with a non-volatile memory (NVM) device over a bus. The host interface includes a first buffer, a second buffer and a scatter/gather list (SGL). The first buffer stores blocks of application data to be communicated to the storage device. The second buffer stores blocks of protection data added by the host interface with respect to the blocks of application data stored in the first buffer. The SGL utilizes a first descriptor type that includes a first buffer address, a first buffer interleave burst length, and a burst count, and a second descriptor type that includes a second buffer address, and a second buffer interleave burst length, wherein only a first descriptor and a second descriptor is required to interleave application data from the first buffer with protection data from the second buffer. | 12-03-2015 |
