| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710026000 | Using addressing | 48 |
| 20080215769 | Operational circuit - An operational circuit for performing an operation of an arbitrary number of input data pieces by using a DMA transfer according to a descriptor control and output results. The arbitrary number of input data pieces are divided into a plurality of pieces to perform an operation processing without performing the operation of the arbitrary number of input data pieces at a time. The operational circuit once stores an intermediate result for each of the divided operations in an external storage device, performs an operation processing read with an intermediate result in the next operation processing, and obtains a final result by repeating these operation processings. The operation is performed at a cyclic unit of processing corresponding to the number of address registers provided in the operational circuit. | 09-04-2008 |
| 20080228961 | SYSTEM INCLUDING VIRTUAL DMA AND DRIVING METHOD THEREOF - A system having a virtual direct memory access (DMA) and a driving method thereof, in which the system includes a central processing unit (CPU), a plurality of intellectual property units (IPs), and a virtual DMA controlling data to be transferred from a first IP unit to a second IP unit according to select information that, selects the first and second IP units of the plurality of IP units, wherein the CPU provides the select information to the virtual DMA. As an example, the first IP transfers data and the second IP receives the data. | 09-18-2008 |
| 20080256266 | Computer system using remote I/O and I/O data transfer method - To improve throughput in data transfer in a remote I/O system, this invention provides a computer system including: a host computer; a device which communicates with the host computer; and a network which connects the host computer and the device, in which the device is coupled to the network via a device bridge including a bridge memory, and the host computer includes a host memory and a device driver. The device driver writes, when at least one of data and an address is written in the host memory, in the bridge memory the at least one of the data and address stored through the writing in the host memory; and sends a data transfer request to the device bridge, and the device bridge reads, upon reception of the data transfer request, an address from a predetermined area; and reads data from an area that is indicated by the read address. | 10-16-2008 |
| 20080294808 | DIRECT ACCESS TO A HARDWARE DEVICE FOR VIRTUAL MACHINES OF A VIRTUALIZED COMPUTER SYSTEM - In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device. | 11-27-2008 |
| 20090077273 | Control Data Transfer - An N-bit control word may be parsed into individual control bits and the individual bits may be inserted into the least significant bit (“LSB”) of N data words. The respective LSBs of the N data words may be mapped into particular bit positions of a control register. When a device receives the N data words, the respective LSBs of the N data may be stored in their designated bit position of the control register. The sender need not specify the address of the control register. | 03-19-2009 |
| 20090100200 | Channel-less multithreaded DMA controller - A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue. | 04-16-2009 |
| 20090164673 | DMA TRANSFER CONTROL DEVICE - A DMA transfer control device includes a setting register group for setting transfer informations, a number-of-transfers register to which the number of transfers to be performed is set, and which updates a value thereof every time one DMA transfer is completed, a transfer control unit, a secondary setting register group for setting other transfer informations different from the transfer informations, and a specified ordinal-number-of-transfer register. Every time one DMA transfer is initiated, either a value of the setting register group or a value of the secondary setting register group is selected for each of the transfer informations in accordance with a result of an arithmetic operation between a value of the number-of-transfers register and a value of the specified ordinal-number-of-transfer register, and inputted to the transfer control unit. As a result, by making settings for one DMA transfer, it is possible to temporarily change the transfer informations. | 06-25-2009 |
| 20090216918 | METHOD AND SYSTEM FOR TRACKING - A system for tracking using electronic addresses is disclosed. The system stores an identification code, an electronic address, and a counter. The electronic address is made up of either single values or pairs of single values. A pair of single values for at least one of value of the counter is made up of a pseudonumber and a unique address value. The pseudonumber is able to be disentangled to produce a second pair of single values for a different value of the counter, thereby producing a tracking history. | 08-27-2009 |
| 20090222597 | DATA TRANSFER DEVICE - A data transfer device for storing only transfer data for which updating is necessary in the storage unit of a transfer source, transferring the transfer data by a transfer control unit, temporarily storing the transfer data in a register provided in a transfer destination circuit, transferring the transfer data stored in the register to the discontinuous storage area of the transfer destination circuit according to the map information of a map register, and transferring data for which updating is necessary to the transfer destination circuit. | 09-03-2009 |
| 20090259775 | VIDEO MULTIVIEWER SYSTEM PROVIDING DIRECT VIDEO DATA TRANSER TO GRAPHICS PROCESSING UNIT (GPU) MEMORY AND RELATED METHODS - A video multiviewer system may include a video input/output (I/O) controller, a system memory, and a graphics processing unit (GPU) comprising a GPU memory. The system may further include a central processing unit (CPU) for operating the video I/O controller to transfer video data to the GPU memory via direct memory access (DMA) without being stored in the system memory, and a display for displaying multiple video windows based upon video data in the GPU memory. | 10-15-2009 |
| 20090313399 | DIRECT MEMORY ACCESS CHANNEL - A system and method for using a direct memory access (“DMA”) channel to reorganize data during transfer from one device to another are disclosed herein. A DMA channel includes demultiplexing logic and multiplexing logic. The demultiplexing logic is configurable to distribute each data value read into the DMA channel to a different one of a plurality of data streams than an immediately preceding value. The multiplexing logic is configurable to select a given one of the plurality of data streams. The DMA channel is configurable to write a value from the given data stream to a storage location external to the DMA channel. | 12-17-2009 |
| 20100036979 | External Direct Memory Access of Embedded Controller Memory - An embedded controller capable of providing direct memory access (DMA) to memory for a host. The controller may include a processor, a memory medium, and an interface coupled to the memory medium. The interface may be configured to couple to a host and receive a DMA request. The DMA request may include a request to read data from a memory location in the memory medium or a request to write data to a memory location in the memory medium. The DMA request may include a relative memory address. The interface may be configured to translate the relative memory address into a first address of the memory medium. Accordingly, the interface may perform operations according to the DMA request using the first address of the memory medium. The processor may be configured to operate according to data stored in the memory medium. | 02-11-2010 |
| 20100100649 | Direct memory access (DMA) address translation between peer input/output (I/O) devices - A method and apparatus is described herein for supporting direct memory accesses between peer I/O devices. It is determined whether a guest physical address (GPA) referenced by an access generated from an I/O device, is within a range of GPAs associated with local I/O devices based at least in part on a GPA base and a GPA window size. If the GPA is within the window, then the GPA is translated to an HPA based at least in part on a base HPA associated with a local device and then forwarded to that local device. However, if the GPA is not within the window, then the access is forwarded upstream. | 04-22-2010 |
| 20100121992 | METHOD, DEVICE AND SYSTEM FOR STORING DATA IN CACHE IN CASE OF POWER FAILURE - A method, device and system for storing data in a cache in case of power failure are disclosed. The method includes: in case of power failure of a storage system, receiving configuration information from a central processing unit (CPU); establishing a mapping relationship between an address of data in the cache and an address in a storage device according to the configuration information; sending a signaling message that carries the mapping relationship to the cache, so that the cache migrates the data to the storage device according to the signaling message. | 05-13-2010 |
| 20100131679 | APPARATUS FOR PERFORMING A DOWNLINK OR UPLINK PROCESSING IN A WIRELESS COMMUNICATION SYSTEM TO MAINTAIN THE EFFICIENCY OF SYSTEM BANDWIDTH, AND ASSOCIATED METHODS - An apparatus for performing downlink or uplink processing in a wireless communication system to maintain efficiency of system bandwidth includes at least one sharing-ring buffer, a MAC-PHY interface, a security engine, and a DMA processor. The sharing-ring buffer is for storing multi-format data. In a situation where the apparatus performs downlink processing, the MAC-PHY interface is for receiving input data, the security engine is for retrieving stored data from the sharing-ring buffer and decrypting the retrieved data, and the DMA processor is for accessing the sharing-ring buffer to obtain the decrypted data. In a situation where the apparatus performs uplink processing, the DMA processor is for receiving input data and storing the input data into the sharing-ring buffer, the security engine is for retrieving the stored data from the sharing-ring buffer and encrypting the retrieved data, and the MAC-PHY interface is for receiving the encrypted data from the sharing-ring buffer. | 05-27-2010 |
| 20100131680 | Unified DMA - In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations. | 05-27-2010 |
| 20100217896 | DIRECT ACCESS MEMORY SYSTEM AND DIRECT ACCESS MEMORY DEVICE - A direct access memory system includes n (n>1) memory arrays ( | 08-26-2010 |
| 20110087808 | DIRECT ACCESS MEMORY CONTROLLER WITH MULTIPLE SOURCES, CORRESPONDING METHOD AND COMPUTER PROGRAM - This direct access memory controller ( | 04-14-2011 |
| 20110125936 | Transmission of Data Bursts on a Constant Data Rate Channel - A system and method for transmitting asynchronous data bursts over a constant data rate channel that transmits a continuous stream of data with virtually no load on the CPU(s) of the receiving processing node is disclosed. The data channel has a defined frame structure with one or more data structures, wherein each data structure comprises a plurality of data locations. A receiver selects data from a fixed data location in each data structure as a data descriptor for each respective data structure. The receiver configures a direct memory access (DMA) function using each data descriptor. For each data structure, a block of payload data is transferred from the data channel to a memory buffer using the DMA function when the data descriptor associated with the data structure is an eligible data descriptor that indicates the block of payload data is present, otherwise a dummy DMA transfer is performed when the data descriptor is an ineligible data descriptor that indicates no payload data is present in the associated data structure. | 05-26-2011 |
| 20110138086 | DIRECT MEMORY ACCESS CONTROLLER AND METHOD OF OPERATING THE SAME - Provided is a Direct Memory Access (DMA) controller which provides a function of searching for a specific pattern from data being transmitted during DMA transmission. The DMA controller stores at least one pattern value. The DMA controller compares data being transmitted to a pattern value while transmitting the data using a DMA method, and generates, in response to data matching the pattern value being detected, a signal indicating that the data matching the pattern value has been detected. The DMA controller stores an address of the data matching the pattern value in response to the generated signal. | 06-09-2011 |
| 20110153877 | METHOD AND APPARATUS TO EXCHANGE DATA VIA AN INTERMEDIARY TRANSLATION AND QUEUE MANAGER - Techniques for performing direct memory access (“DMA”) in an architecture wherein an interconnect separates I/O means from a DMA engine for handling DMA requests of the I/O means. In an embodiment, the I/O means sends via the interconnect a DMA request including an address-non-specific identifier of a queue which is a target of the DMA request. In another embodiment, the DMA engine determines an address-specific identifier of a location in the queue in response to the sending of the DMA request. | 06-23-2011 |
| 20110153878 | MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS - Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller. | 06-23-2011 |
| 20110225325 | DATA TRANSFER CIRCUIT AND METHOD - In one cycle for transferring data, a controller forming a data transfer circuit stores pointer information P_A for periodic transfer and pointer information P_B for non-periodic transfer read from a memory respectively in first and second storage areas. The controller sequentially transfers, to a communication bus, data D_A for periodic transfer and data D_B for non-periodic transfer read from the memory by referring to the P_A and P_B. If transfer by a data length indicated in the P_B has not been completed upon the transfer of the D_B, the controller updates the data length to a data length of the remaining data, and updates an address indicated in the P_B to an address on the memory of the remaining data. In the next cycle for transferring data, the controller reads the remaining data from the memory by referring to the P_B, and transfers the remaining data to the communication bus. | 09-15-2011 |
| 20110314186 | Unified DMA - In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations. | 12-22-2011 |
| 20120066416 | Information processing apparatus, execution control method, and recording medium storing execution control program - An information processing apparatus, an execution control method, an execution control program, and an execution control medium storing the execution control program are described. The information processing apparatus has a processor, which concurrently performs: (1) initializing hardware resources needed for execution of the information processing apparatus; and (2) expanding an operating system and a file system image stored in a nonvolatile memory in a compressed format and transferring the expanded operating system and file system image to a volatile memory using a direct memory access controller. | 03-15-2012 |
| 20120072619 | Memory Overcommit by Using an Emulated IOMMU in a Computer System with a Host IOMMU - A method and system for managing direct memory access (DMA) in a computer system that hosts virtual machines and allows memory overcommit. The computer receives an indication that a bus address is to be used by a device to perform DMA to a buffer. In response to the indication, the computer determines a host device identifier for the device, and pins a memory page addressed by a host address that is associated with the bus address and a guest address. The computer also records, in a host I/O memory management unit (IOMMU), a mapping of the bus address and the host device identifier to the host address. After the device completes the DMA, the computer removes the mapping from the host IOMMU to prevent further direct access to the host address. | 03-22-2012 |
| 20120079141 | INFORMATION PROCESSING APPARATUS AND INTER-PROCESSOR COMMUNICATION CONTROL METHOD - An information processing apparatus includes a plurality of processors configured to form a pipeline, a plurality of communication units configured to transfer communication data between a processor in an upstream stage of the pipeline and another processor in a downstream stage and to temporarily store the communication data output from the processor in the upstream stage to the processor in the downstream stage into an internal FIFO buffer, and a memory configured to be accessible from each of the processors and each of the communication units. | 03-29-2012 |
| 20120151104 | PIO INTERJECTION BETWEEN BEATS OF A DMA OPERATION - Techniques are disclosed relating to detecting and interjecting a programmed input/output (PIO) operation into a direct memory access (DMA) operation. In one embodiment, an integrated circuit may include a DMA controller that may contain a control circuit, a DMA unit, and a PIO unit. The control circuit may be configured to detect a pending PIO operation during a DMA operation and interject the PIO operation onto a shared path during the same clock cycle as or the first clock cycle following the detection of the pending PIO operation. The DMA operation may consist of multiple single-clock-cycle beats. In one embodiment, a PIO operation may be interjected onto the shared path between beats of a DMA operation, on consecutive clock cycles. At the next clock cycle following the PIO operation, the control circuit may resume the next beat of the DMA operation. | 06-14-2012 |
| 20120159015 | DIRECT MEMORY ACCESS CONTROLLER AND OPERATING METHOD THEREOF - Disclosed is an operating method of a direct memory access (DMA) controller having first and second DMA channels. The operating method includes iteratively performing a DMA transfer operation of the first DMA channel based upon loop information and transfer information of the first DMA channel; iteratively performing a DMA transfer operation of the second DMA channel based upon loop information and transfer information of the second DMA channel; reconfiguring the transfer and loop information of the first and second DMA channels; and again performing the iteratively performing a DMA transfer operation of the first DMA channel and the iteratively performing a DMA transfer operation of the first DMA channel based upon the reconfigured transfer and loop information of the first and second DMA channels. | 06-21-2012 |
| 20120226831 | MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS - Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller. | 09-06-2012 |
| 20130007310 | INFORMATION PROCESSING DEVICE AND METHOD OF COLLECTION PROCESS OF DEVICE INFORMATION IN THE INFORMATION PROCESSING DEVICE - An information processing device collects status information for a large number of input and output devices simultaneously. A bridge circuit having a multicast function connects an information processing unit with a plurality of input and output devices. By setting the multicast to the bridge circuit, the bridge circuit forwards a packet which instructs a copy of the status information to the plurality of input and output devices by multicast, and a DMA circuit in the plurality of input and output devices simultaneously starts DMA transfer of the status information to the processing unit. | 01-03-2013 |
| 20130086285 | SHARING IOMMU MAPPINGS ACROSS DEVICES IN A DMA GROUP - A method that includes creating a DMA group, adding a first I/O device to the DMA group, and adding a second I/O device to the DMA group. The method further includes instructing an I/O MMU to create a shared virtual DMA address, mapping a memory location to the shared virtual DMA address in the DMA group translation table, and providing the shared virtual DMA address to the device drivers. The method further includes determining that the first I/O device has received DMA group data, instructing a first DMA controller to transfer the DMA group data from the first I/O device to the shared virtual DMA address, determining that the shared virtual DMA address has received the DMA group data, and instructing a second DMA controller to transfer the DMA group data from the memory location corresponding to the shared virtual DMA address to the second I/O device. | 04-04-2013 |
| 20130138841 | MESSAGE PASSING USING DIRECT MEMORY ACCESS UNIT IN A DATA PROCESSING SYSTEM - A method includes generating, by a first software process of the data processing system, a source partition descriptor for a DMA job which requires access to a first partition of a memory which is assigned to a second software process of the data processing system and not assigned to the first software process. The source partition descriptor comprises a partition identifier which identifies the first partition of the memory. The DMA unit receives the source partition descriptor and generates a destination partition descriptor for the DMA job. Generating the destination partition descriptor includes translating, by the DMA unit, the partition identifier to a buffer pool identifier which identifies a physical address within the first partition of the memory which is assigned to the second software process; and storing, by the DMA unit, the buffer pool identifier in the destination partition descriptor. | 05-30-2013 |
| 20130145055 | Peripheral Memory Management - The present system enables an input/output (I/O) device to request memory for performing a direct memory access (DMA) of system memory. Further, the system uses an input/output memory management unit (IOMMU) to determine whether or not the system memory is available. The IOMMU notifies an operating system associated with the system memory if the system memory is not available, such that the operating system allocates non-system memory for use by the I/O device to perform the DMA. | 06-06-2013 |
| 20130159564 | DIRECT DATA TRANSFER FOR DEVICE DRIVERS - A method for performing direct memory access includes obtaining, by a application executing on a host, a kernel address space identifier of a first driver kernel memory. The application sends the kernel address space identifier to a second device driver. The second device driver obtains, using the kernel address space identifier, a cookie structure binding the first driver kernel memory to a second device driver address space for the first driver kernel memory. The application sends a request for a direct memory access operation. The request includes a location identifier of a location storing a data object in the first driver kernel memory. Based on the cookie structure, the second device driver performs, using the location identifier, the direct memory access operation to transfer the data object from the first driver kernel memory to a second driver kernel memory. | 06-20-2013 |
| 20130166793 | HOST CHANNEL ADAPTER WITH PATTERN-TYPE DMA - An input/output (I/O) device includes a memory buffer and off-loading hardware. The off-loading hardware is configured to accept from a host a scatter/gather list including one or more entries. The entries include at least a pattern-type entry that specifies a period of a periodic pattern of addresses that are to be accessed in a memory of the host. The off-loading hardware is configured to transfer data between the memory buffer of the I/O device and the memory of the host by accessing the addresses in the memory of the host in accordance with the periodic pattern at intervals indicated in the period. | 06-27-2013 |
| 20140032793 | DATA SNOOPING DIRECT MEMORY ACCESS FOR PATTERN DETECTION - A direct memory access controller for efficiently detecting a character string within memory, the direct memory access controller generating signatures of character strings stored within the memory and comparing the generated signatures with the signature of the character string for which detection is desired. | 01-30-2014 |
| 20140101347 | Isochronous Data Transfer Between Memory-Mapped Domains of a Memory-Mapped Fabric - Techniques for isochronous data transfer between different memory-mapped domains in a distributed system. A method includes configuring an isochronous engine with an isochronous period. The method further includes transferring data over a memory-mapped fabric from a first memory to a second memory during a specified portion of a cycle of the isochronous period. The first memory is comprised in a first device in a first memory-mapped domain of the memory-mapped fabric and the second memory is comprised in a second device in a second memory-mapped domain of the memory-mapped fabric. The method may further comprise translating one or more addresses related to the transferring. The memory-mapped fabric may be a PCI-Express fabric. The transferring may be performed by a DMA controller. A non-transparent bridge may separate the first and the second memory-mapped domains and may perform the translating. | 04-10-2014 |
| 20140136736 | INFORMATION PROCESSING APPARATUS AND VERIFICATION METHOD - A verification method is executed by an information processing apparatus to verify priority control of transfer devices. The verification method includes: firstly generating pieces of data having different data amounts; secondly generating addresses in which a value is shifted; firstly associating the generated addresses in an ascending order of value of address with the generated pieces of data in a descending order of data amount; secondly associating device information indicating the transfer devices in a descending order of the degree of priority allocated to the transfer devices with the generated pieces of data in the descending order of data amount; instructing transfer of a generated piece of data to the address associated with the data, to the transfer device indicated by the device information associated with the data; and verifying the degree of priority according to a result of the transfer of the data. | 05-15-2014 |
| 20140143456 | DETERMINING A MAPPING MODE FOR A DMA DATA TRANSFER - According to embodiments of the invention, methods, computer readable storage medium, and a computer system for determining a mapping mode for a DMA data transfer are disclosed. The method may include receiving a request for a DMA data transfer within a computer system. The method may also include determining a mapping mode for the DMA data transfer based on available system profile data in response to receiving the request. The method may also include mapping the memory using the determined mapping mode. | 05-22-2014 |
| 20140143457 | DETERMINING A MAPPING MODE FOR A DMA DATA TRANSFER - According to embodiments of the invention, methods, computer readable storage medium, and a computer system for determining a mapping mode for a DMA data transfer are disclosed. The method may include receiving a request for a DMA data transfer within a computer system. The method may also include determining a mapping mode for the DMA data transfer based on available system profile data in response to receiving the request. The method may also include mapping the memory using the determined mapping mode. | 05-22-2014 |
| 20140156882 | MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE DEVICE INCLUDING THE SAME - A memory device includes a data read/write block configured to store data in memory cells and read data from the memory cells; an input/output buffer block configured to buffer input data inputted through data pads and control signals inputted through control signal pads, and provide buffered input data and control signals to the data read/write block, and buffer read data read out through the data read/write block, and output buffered read data to an external device through the data pads, and a control logic configured to activate or deactivate the input/output buffer block based on an address which is inputted from the external device. | 06-05-2014 |
| 20140281055 | LATENCY REDUCTION FOR DIRECT MEMORY ACCESS OPERATIONS INVOLVING ADDRESS TRANSLATION - Latency reduction for direct memory access operations involving address translation is disclosed. Example methods disclosed herein to perform direct memory access (DMA) operations include initializing a ring of descriptors, the descriptors to index respective buffers for storing received data in a first memory. Such example methods also include causing prefetching of a first address translation associated with a second descriptor in the ring of descriptors to be performed after a first DMA operation is performed to store first received data in a first buffer indexed by a first descriptor in the ring of descriptors and before second received data to be stored in the first memory is received, the first address translation being associated with a second DMA operation for storing the second received data in the first memory. | 09-18-2014 |
| 20140281056 | LATENCY REDUCTION FOR DIRECT MEMORY ACCESS OPERATIONS INVOLVING ADDRESS TRANSLATION - Latency reduction for direct memory access operations involving address translation is disclosed. Example methods disclosed herein to perform direct memory access (DMA) operations include initializing a ring of descriptors, the descriptors to index respective buffers for storing, in a first memory, data to be transmitted. Such example methods also include causing prefetching of a first address translation associated with a second descriptor in the ring of descriptors to be performed after a first DMA operation is performed to retrieve, for transmission, first data from a first buffer indexed by a first descriptor in the ring of descriptors and before second data is determined to be ready for transmission, the first address translation being associated with a second DMA operation for retrieving the second data from the first memory. | 09-18-2014 |
| 20150142995 | DETERMINING A DIRECT MEMORY ACCESS DATA TRANSFER MODE - In response to receiving a request for a DMA data transfer, a DMA transfer mode may be determined based on based on the size of the requested DMA data transfer and profile data of an I/O adapter. The profile data for the I/O adapter may include a physical location of the I/O adapter or a number of clients supported by the I/O adapter. The DMA transfer mode may also be determined based on a preference of an application or an I/O device. Moreover, the DMA transfer mode may be determined based on a CPU usage metric being outside of a threshold for the CPU usage metric or on a memory usage metric being outside of a threshold for the memory usage metric. | 05-21-2015 |
| 20150142996 | DMA TRANSMISSION METHOD AND SYSTEM THEREOF - A method for transmitting data between an information processing device and a storage device, in which the storage device includes a buffer memory and flash chips, includes: receiving a first write request including data to be written and an address used for the flash chip of the storage device; allocating a first memory unit in the information processing device for the first write request; sending a write command including data, the address used for the flash chip of the storage device and address used for the buffer memory, to the storage device, in which the address used for the buffer memory corresponds to the first memory unit; receiving a message indicating the performing of the write command by the storage device has been completed, from the storage device; and releasing the first memory unit. | 05-21-2015 |
| 20160062912 | DATA INPUT/OUTPUT (I/O) HANDLING FOR COMPUTER NETWORK COMMUNICATIONS LINKS - Systems and methods for performing data input/output (I/O) operations using a computer network communications link are described. A method may include assigning a block of virtual addresses for usage with at least one computer network communications link. The method may also include registering the entire block of virtual addresses prior to an operating system partition performing I/O operations using the at least one computer network communications link, wherein registering comprises setting a plurality of virtual page frame numbers of the block of virtual addresses to point to distinct pages of physical memory. In some embodiments, one or more I/O operations may be performed using the at least one computer network communications link and the registered block of virtual addresses. | 03-03-2016 |
| 20160170920 | MIGRATING BUFFER FOR DIRECT MEMORY ACCESS IN A COMPUTER SYSTEM | 06-16-2016 |
