| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710025000 | Timing | 22 |
| 20080244115 | PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING - Methods and structures are described for processing signals formatted according to a plurality of different wireless and broadband standards. In some embodiments, network resources are shared to enable energy efficient, pseudo-simultaneous processing. In some embodiments, a timestamp is prepended to input data to remove jitter associated with time division multiplexed processing using shared resources. Systems according to embodiments of the invention are also disclosed. | 10-02-2008 |
| 20080301328 | Method and system for improved communication between central processing units and input/output processors - A method and system for communicating information regarding input/output (IO) processing in a shared access to memory environment is disclosed. A central processing unit (CPU) and an input/output processor (IOP) are configured to write to and read from predetermined memory locations to manage the detection, performance, and completion of IOs. The CPU and the IOP may read from and write to memory as desired. | 12-04-2008 |
| 20090019190 | Low Latency, High Bandwidth Data Communications Between Compute Nodes in a Parallel Computer - Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core. | 01-15-2009 |
| 20090037615 | DATA TRANSFER DEVICE, REQUEST ISSUING UNIT, AND REQUEST ISSUE METHOD - A request issuing unit for issuing a request signal for requesting data transfer by direct memory access. The request issuing unit including a data presence determination section configured to determine whether or not transfer data, as an object of the data transfer, is present, and a signal outputting section configured to output a request signal for data transfer of a predetermined amount of data to be transferred at one time when the data presence determination section determines that the transfer data is present. The request issuing unit further including a determination timing control section configured to wait for a predetermined waiting period of time, required for completing the data transfer of at least the amount of data to be transferred at one time, after the signal outputting section outputs the request signal, and then makes the data presence determination section determine again whether or not transfer data is present. | 02-05-2009 |
| 20090150575 | Dynamic logical data channel assignment using time-grouped allocations - A method, system and program are provided for dynamically allocating DMA channel identifiers to multiple DMA transfer requests that are grouped in time by virtualizing DMA transfer requests into an available DMA channel identifier using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once the input values associated with the DMA transfer requests are mapped to the selected DMA channel identifier, the DMA transfers are performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfers. When there is a request to wait for completion of the data transfers, the same input values are used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing. | 06-11-2009 |
| 20090216917 | DEVICE AND METHOD FOR ARBITRATING BETWEEN DIRECT MEMORY ACCESS TASK REQUESTS - A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. | 08-27-2009 |
| 20090248911 | CLOCK CONTROL FOR DMA BUSSES - A method and system is disclosed for accessing I/O and memory devices utilizing a DMA controller. Each device may be connected to the DMA controller through an individual channel. Clocking circuitry in the DMA may allow the DMA controller to send signals to each device at a prescribed frequency. Furthermore, the DMA controller is capable of activating and deactivating a channel clock, used in sending signals to the devices, based on the operational status of the individual devices. The DMA controller is also capable of tuning the channel clock dependant on the capabilities of any active devices. In this manner, the amount of bandwidth used during a DMA data transfer can be tailored to the specific requirements of the devices involved with the data transfer. | 10-01-2009 |
| 20090292836 | DATA ACCESS DEVICE AND METHOD FOR COMMUNICATION SYSTEM - A data access device for a communication system includes: a write controller controlled by the host and outputting a write pointer; a read controller controlled by the write pointer and outputting a read pointer; a download timing controller comparing the write and read pointers to determine a timing of downloading data from the host, and including a pointer difference calculator and a comparator, the pointer difference calculator calculating a distance between the write and read pointers to obtain a pointer difference, the comparator outputting a download status indication according to the pointer difference and a first predetermined length to provide a basis for changing the write pointer; and a transmit buffer downloading data from the host according to the write pointer and transmitting data to the network interface according to the read pointer. A data access device for a network interface controller and a data access method are also disclosed. | 11-26-2009 |
| 20090307386 | Restore PCIe Transaction ID on the Fly - Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again. | 12-10-2009 |
| 20090327533 | Concatenating Secure Digital Input Output (SDIO) Interface - An apparatus and a process for transferring packet data includes receiving packets from a first interface such as a network interface and transferring data to a second interface such as an SD Bus interface such as SDIO using a protocol such as one described in SDCard.org. The SD Bus second interface operates as a slave device to a master device, and the packet transfer from first interface to second interface includes concatenating length fields and packet data fields from packets received on the first interface to form a superframe which is provided to the second interface at time of data transfer. The formation of each superframe includes starting a timer such that the superframe is transmitted to the second interface by asserting an interrupt on that interface when either the timer expires, the number of packet from the first interface exceeds a threshold, or the amount of data from the first interface exceeds a threshold. | 12-31-2009 |
| 20100064071 | DMA device having plural buffers storing transfer request information and DMA transfer method - A Direct Memory Access (DMA) device includes a first buffer which holds a first transfer information required for a first transfer request, and a second buffer which holds a second transfer information required for a second transfer request, and a transfer request comparison circuit which determines whether or not a current transfer request, which is newly inputted, matches with the first transfer request or the second transfer request. The DMA device includes a priority determination circuit that, in case where the transfer request comparison circuit determines that the current transfer request is not matched with the first transfer request or the second transfer request, updates the second transfer information to a transfer information for the current transfer request when a priority of the current transfer request is higher than a priority of the second transfer request, and updates the first transfer information to the transfer information for the current transfer request when the priority of the current transfer request is lower than the priority of the second transfer request. | 03-11-2010 |
| 20100228894 | DEVICE HAVING DATA SHARING CAPABILITIES AND A METHOD FOR SHARING DATA - A method and device for sharing data. The method include: receiving by a direct memory access controller, a data read instruction; wherein the read data instruction can be a shared data read instruction or a non-shared data read instruction; determining whether to fetch a requested data block from a first memory unit to a second memory unit by applying a direct memory address control operation; wherein the second memory unit is accessible by a processor that generated the shared data read instruction; fetching the requested data block from the first memory unit to the second memory unit by applying a direct memory access control operation, if the read data instruction is a non-shared data instruction or if the read data instruction is a shared data instruction but the requested data is not stored in the second memory unit; and retrieving a requested data block from a second memory unit. | 09-09-2010 |
| 20100262728 | DIRECT MEMORY ACCESS CONTROLLER FOR IMPROVING DATA TRANSMISSION EFFICIENCY IN MMoIP AND METHOD THEREFOR - A direct memory access controller (DMAC) for improving data transmission efficiency in multi-media over internet protocol (MMoIP) and a method therefor are provided. The DMAC requests and obtains a bus control right by determining that a DMA request signal is generated not only when a DMA request signal of a module for processing data in MMoIP is received but also when an operation of a timer operating during a predetermined period set considering periodicity of data in MMoIP is completed. Thus, the time taken to request a bus control right in a conventional DMAC can be reduced, thereby improving data transmission efficiency in MMoIP. | 10-14-2010 |
| 20100287314 | STORAGE DEVICE ESTIMATING A COMPLETION TIME FOR A STORAGE OPERATION - A storage device or system provides to a host processor an estimation of a completion time of a storage operation. The completion time may be based on the duration of automatic storage operations, which are not administered by the host processor. The storage device includes a non-volatile memory and a controller. The storage system includes: a storage device having a non-volatile memory; and a controller module. The controller or controller module estimates the completion time of a storage operation and provides to the processor the estimated completion time before the storage operation completes. | 11-11-2010 |
| 20100293304 | CONTROLLER AND METHOD FOR STATISTICAL ALLOCATION OF MULTICHANNEL DIRECT MEMORY ACCESS BANDWIDTH - A DMA controller and a method for statistical allocation of multichannel DMA bandwidth. In one embodiment, the DMA controller includes: ( | 11-18-2010 |
| 20120166684 | SEMICONDUCTOR DEVICE AND CONTROL METHOD - When a data request signal is inactivated while a DMA controller is executing DMA data transfer in a burst transfer mode, an address at this time is held and a remaining number of transfer times is counted. After the DMA data transfer in the burst transfer mode is finished, the address and the remaining number of transfer times are re-set in the DMA controller and then the DMA data transfer is executed. This makes it possible to re-transfer data remaining at the timing when the data request signal is inactivated, and the DMA data transfer using the burst transfer mode is executed to or from a module requesting the DMA data transfer by using level of the data request signal. | 06-28-2012 |
| 20120331187 | BANDWIDTH CONTROL FOR A DIRECT MEMORY ACCESS UNIT WITHIN A DATA PROCESSING SYSTEM - A method for controlling bandwidth in a direct memory access (DMA) unit of a computer processing system, the method comprising: assigning a DMA job to a selected DMA engine; starting a source timer; and issuing a request to read a next section of data for the DMA job. If a sufficient amount of the data was not obtained, allowing the DMA engine to wait until the source timer reaches a specified value before continuing to read additional data for the DMA job. | 12-27-2012 |
| 20130073752 | LOW LATENCY, HIGH BANDWIDTH DATA COMMUNICATIONS BETWEEN COMPUTE NODES IN A PARALLEL COMPUTER - Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core. | 03-21-2013 |
| 20130238821 | METHODS AND APPARATUS FOR PACKING RECEIVED FRAMES IN BUFFERS IN A SERIAL ATTACHED SCSI (SAS) DEVICE - Methods and apparatus for packing received Serial Attached SCSI (SAS) frames in buffers for transmission to a host system memory. SAS frames are received from another SAS device and stored in a frame buffer memory. User data in the received frames has appended SCSI Data Integrity Fields (DIF information) to enhance reliability. Features and aspects hereof use the DIF information to validate the user data and then strip the DIF information to densely pack the validated user data in a DMA staging buffer for transmission to a host's system buffer memory using DMA features of the SAS device. The DMA circuit is programmed and started when the staging buffer is filled to at least a threshold amount of data to thereby improve efficacy of the DMA transfer performance. Other criteria may also be employed to determine when to start the DMA circuit. | 09-12-2013 |
| 20130318259 | DIRECT MEMORY ACCESS (DMA) CONTROLLED MEDICAL DEVICES - A sub-system for controlling a medical device comprises memory including a first table and a second table. The first table stores blocks of event data corresponding to events that are to be performed during a period of time (e.g., a 0.5 sec. or 1 sec. period of time). The second table stores blocks of time data corresponding to the period of time. The implantable stimulation system also includes a direct memory access (DMA) controller including a first DMA channel and a second DMA channel. The first DMA channel selectively transfers one of the blocks event data from the first table to one or more registers that are used to control events. The second DMA channel selectively transfers one of the blocks of time data from the second table to a timer that is used to control timing associated with the events. | 11-28-2013 |
| 20140281054 | INTERFACES FOR DIGITAL MEDIA PROCESSING - APIs discussed herein promote efficient and timely interoperability between hardware and software components within the media processing pipelines of media content players. A PhysMemDataStructure API facilitates a hardware component's direct access to information within a memory used by a software component, to enable the hardware component to use direct memory access techniques to obtain the contents of the memory, instead of using processor cycles to execute copy commands. The PhysMemDataStructure API exposes one or more fields of data structures associated with units of media content stored in a memory used by a software component, and the exposed fields store information about the physical properties of the memory locations of the units of media content. SyncHelper APIs are used for obtaining information from, and passing information to, hardware components, which information is used to adjust the hardware components' timing for preparing media samples of synchronously-presentable media content streams. | 09-18-2014 |
| 20150032914 | System and Method for Direct Memory Access Transfers - A system and method for transferring data between a memory and peripheral units via a plurality of direct memory access (DMA) transactions, wherein a respective timestamp is assigned and/or appended to at least two of the plurality of the DMA transactions. | 01-29-2015 |
