| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710023000 | Programmed control memory accessing | 37 |
| 20080201496 | REDUCED PIN COUNT INTERFACE - An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices. | 08-21-2008 |
| 20080235410 | Usb-Sd Memory Device Having Dma Channels and Method of Storing Data in Usb-Sd Memory Device - Disclosed is a memory device having Universal Serial Bus (USB) interface and Secure Digital (SD) card interface, including: a plurality of flash memory units; a plurality of flash memory controllers each controlling reading and writing data on the flash memory unit; a Direct Memory Access (DMA) controller including a plurality of DMA channels each transmitting/receiving data to/from the flash memory unit in DMA mode; a Micom dividing a signal received from the USB interface and the SD card interface into data and an address and transmitting the data to the DMA controller; and an address decoder calculating positions of the received data to be written or read on the flash memory unit according to the address. | 09-25-2008 |
| 20080244113 | Method for using a memory device with a built-in memory array and a connector for a removable memory device - A method for using a memory device with a built-in memory array and a connector for a removable memory device is disclosed. In one embodiment, a determination is made regarding whether a removable memory device comprises a memory controller. If the removable memory device does not comprise a memory controller, circuitry in a memory device connected to the removable memory device is used to control read/write operations to a memory array in the removable memory device. In another embodiment, data stored in a built-in memory of a memory device is read, and the read data is stored in a memory array of a removable memory device. In yet another embodiment, a connection of a removable memory device to a memory device is detected. Pre-loaded content is read from a memory array in the removable memory device and stored in the built-in memory array of the memory device. | 10-02-2008 |
| 20080281999 | ELECTRONIC SYSTEM WITH DIRECT MEMORY ACCESS AND METHOD THEREOF - In an electronic system, a DMA circuit is supplied with a device selection signal that indicates a processor is accessing or going to access a memory. If the DMA circuit finds that the processor is not accessing or not going to access the memory, the DMA circuit starts its DMA operations. Once the DMA circuit finds that the processor is going to access the memory, the DMA circuit stops its DMA operation and return the use of the memory to the processor. | 11-13-2008 |
| 20080307122 | Autonomous mapping of protected data streams to Fibre channel frames - A hardware-based offload engine is disclosed for mapping protected data into frames. For a write operation, the HBA determines host addresses and the size of data to be read from those addresses. The HBA also determines the frame size and protection scheme for data to be written. A frame transmit engine reads each host descriptor in the host data descriptor list to determine the location and byte count of the data to be read. A DMA engine reads the protection information/scratch area to determine the exact data size used to fill each frame and the protection scheme, and retrieves one or more free frame buffers. Check bytes are inserted alongside the data and stored in free frame buffers. After each frame is filled, the frame transmit engine also generates and stores header information for that frame, and then combines header, data and check bytes for transmission over the network. | 12-11-2008 |
| 20090006666 | DMA SHARED BYTE COUNTERS IN A PARALLEL COMPUTER - A parallel computer system is constructed as a network of interconnected compute nodes. Each of the compute nodes includes at least one processor, a memory and a DMA engine. The DMA engine includes a processor interface for interfacing with the at least one processor, DMA logic, a memory interface for interfacing with the memory, a DMA network interface for interfacing with the network, injection and reception byte counters, injection and reception FIFO metadata, and status registers and control registers. The injection FIFOs maintain memory locations of the injection FIFO metadata memory locations including its current head and tail, and the reception FIFOs maintain the reception FIFO metadata memory locations including its current head and tail. The injection byte counters and reception byte counters may be shared between messages. | 01-01-2009 |
| 20090049209 | ATA HDD Interface for Personal Media Player With Increased Data Transfer Throughput - This invention is a method allowing for interfacing high speed hard disk drives (ATA-HDD) in high throughput PIO modes to currently available digital media processors (DMP). The prescribed interface programs signals available in the DMP external memory interface (EMIF) functions to match the requirements of ATA-HDD PIO functions. Selected signal redefinition and minimal glue logic is employed to form a seamless link between the EMIF I/O of the digital media processor DMP and the ATA-HDD hard drive. | 02-19-2009 |
| 20090138625 | SPLIT USER-MODE/KERNEL-MODE DEVICE DRIVER ARCHITECTURE - A device driver includes a kernel stub and a user-mode module. The device driver may access device registers while operating in user-mode to promote system stability while providing a low-latency software response from the system upon interrupts. Upon receipt of an interrupt, the kernel stub may run an interrupt service routine and write information to shared memory. Control is passed to the user-mode module by a reflector. The user-mode module may then read the information from the shared memory to continue servicing the interrupt. | 05-28-2009 |
| 20090138626 | SPI BANK ADDRESSING SCHEME FOR MEMORY DENSITIES ABOVE 128Mb - Systems and methods of addressing two or more banks of memory utilizing a single-bank serial peripheral interface and an at least three-byte address protocol are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to address one of the memory banks using the three-byte addressing scheme, and to write data to or read data from the addressed bank, and a bank register pointer component coupled to the serial processing component, the pointer component comprising two or more bank register pointers associated with respective memory banks, and configured to select one of the memory banks based on the two or more bank register pointers, wherein the bank register pointer component selects one of the two or more memory banks, and the serial processing component writes data to or reads data from the selected bank of memory according to the three-byte addressing scheme. | 05-28-2009 |
| 20090144462 | Method and System for Fully Trusted Adapter Validation of Addresses Referenced in a Virtual Host Transfer Request - A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to validate that a direct memory access address referenced by an incoming I/O transaction that was initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation is provided. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications. A single physical I/O adapter validates that one or more direct memory access addresses referenced by an incoming I/O transaction initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation. | 06-04-2009 |
| 20090254683 | VIDEO MULTIVIEWER SYSTEM USING DIRECT MEMORY ACCESS (DMA) REGISTERS AND BLOCK RAM - A video multiviewer system includes a Graphics Processing Unit (GPU) that includes a GPU memory. A video input module is operative with the GPU for receiving video data and transferring the video data to the GPU memory via a Direct Memory Access (DMA). A programmable circuit such as a Field Programmable Gate Array (FPGA) includes a multi-ported and in one aspect a dual ported block Random Access Memory (RAM) configured for a plurality of DMA channels for receiving video data and allowing uninterrupted operation of consecutive DMA transfers of video data to the GPU memory. A display displays the multiple video windows based upon video data received within the GPU memory. | 10-08-2009 |
| 20090287860 | Programmable Direct Memory Access Controller - A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data conversion and is pipeline connected in sequence to the data load unit. A data store unit is also pipeline connected in sequence to the data computation unit and is configured for performing burst store operations onto a system bus for storage in system memory. | 11-19-2009 |
| 20100030927 | GENERAL PURPOSE HARDWARE ACCELERATION VIA DEIRECT MEMORY ACCESS - A method and system in which one or more hardware accelerators are directly accessible via a direct memory access controller (DMAC) including an internal mechanism. In some embodiments, the internal mechanism may include a local interconnect in the DMAC. In other embodiments, a DMAC structure includes a mechanism that provides for streaming data through hardware accelerators and allows for simultaneous reads and writes among multiple endpoint pairs transferring data. For added flexibility and increased independence from a microprocessor, a DMAC may include a command decoder that discovers, decodes and interprets commands in a data stream. | 02-04-2010 |
| 20100030928 | MEDIA PROCESSING METHOD AND DEVICE - A media processing system and device with improved power usage characteristics, improved audio functionality and improved media security is provided. Embodiments of the media processing system include an audio processing subsystem that operates independently of the host processor for long periods of time, allowing the host processor to enter a low power state. Other aspects of the media processing system provide for enhanced audio effects such as mixing stored audio samples into real-time telephone audio. Still other aspects of the media processing system provide for improved media security due to the isolation of decrypted audio data from the host processor. | 02-04-2010 |
| 20100146159 | Memory Flash Apparatus and Method For Providing Device Upgrades Over A Standard Interface - An electronic device includes routing logic operatively coupled to a communication port that is externally accessible so that there is no need to disassemble the electronic device to gain access. The port may be a USB port and provides access to an internal bus. The routing logic is also operatively coupled to a memory subsystem such that it may route data from an external device, connected at the port, to the memory subsystem to modify or replace a boot code, including a BIOS code. A memory interface device includes an interface module, a memory interface module for communicating with a memory subsystem including a boot PROM, and a routing logic coupled to the interface module and the memory interface module. The routing logic routes data from the external device to the boot PROM, so that a boot code, including a BIOS, may be modified or replaced. | 06-10-2010 |
| 20100161848 | Programmable Direct Memory Access Engine - A mechanism for programming a direct memory access engine operating as a single thread processor is provided. A program is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the program located in the local memory is to be executed. The direct memory access engine executes the program without intervention by a host processor. Responsive to the program completing execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution. | 06-24-2010 |
| 20100161849 | MULTI CHANNEL DATA TRANSFER DEVICE - Provided is a multi channel data transfer device. The multi channel data transfer device includes: a plurality of channel control unit connected to a plurality of peripheral devices, respectively; a plurality of control registers storing setting data for controlling an operation of each of the plurality of channel controllers; and a common register controller delivering common setting data to all or part of the plurality of control registers, the common setting data being applied in common to all or part of the plurality of channel controllers. | 06-24-2010 |
| 20100161850 | Methods And Apparatus For Providing User Level DMA And Memory Access Management - A memory access control apparatus receives from a DMA requestor an access request command, which contains an IOID, for a DMA address space that is a memory area used for a DMA transfer, and determines whether the access is permitted or not and executes the access if it is permitted. The operating system on the PU sets in MMU the correspondence relationship between the logical address space of a user process and the DMA address space. When the user process instructs to access the DMA address space by specifying a logical address, the MMU translates the logical address into a physical address of the DMA address space. | 06-24-2010 |
| 20100198998 | I/O CONTROLLER AND DESCRIPTOR TRANSFER METHOD - An I/O controller and method are provided. The I/O controller to which an I/O device can be connected, and instructs the I/O device to execute a process includes a descriptor transfer device that transfers a descriptor indicating contents of a process to be executed, and execution instruction unit that instructs the I/O device to execute the process, based on the descriptor transferred from the descriptor transfer device, wherein the descriptor transfer device includes a memory for storing the descriptor; descriptor reading unit that reads, according to an indication regarding a descriptor read source from a processor, an indicated descriptor from a main memory or said memory which stores the descriptor, and descriptor transfer unit that transfers the read descriptor to the execution instruction unit. | 08-05-2010 |
| 20100332694 | METHOD AND APPARATUS FOR USING A SINGLE MULTI-FUNCTION ADAPTER WITH DIFFERENT OPERATING SYSTEMS - A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface. | 12-30-2010 |
| 20110022740 | SYSTEM AND METHOD FOR DATA TRANSFER USING ATA INTERFACE - An ATA compatible data transfer system includes a system processor having system memory, the system processor configured to issue a Programmable I/O (PIO) type command to effect data transfer between a peripheral device and the system memory through a host controller and an ATA controller. The host controller accesses data to/from the host memory directly. The host controller and the ATA controller complete data transfer between the peripheral device and the system memory by executing the PIO type command without requiring interrupt servicing by the system processor. | 01-27-2011 |
| 20110145447 | METHOD OF TRANSFERRING DATA, A METHOD OF PROCESSING DATA, AN ACCELERATOR, A COMPUTER SYSTEM AND A COMPUTER PROGRAM - The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream. | 06-16-2011 |
| 20110191507 | DMA ENGINE - A circuit comprising: an execution unit; a plurality of addressable devices; and a data transfer engine coupled to the execution unit and to the devices, operable to fetch a plurality of descriptors under control of the execution unit, and based on each of the fetched descriptors to perform a transfer of data from a respective first to a respective second of the devices. The DMA engine comprises delay circuitry operable to block, during a delay period running from an earlier of the transfers, any later of the transfers involving at least one of the same devices as the earlier transfer, the delay circuitry being arranged to control the blocking in dependence on an indication received in one of the descriptors. | 08-04-2011 |
| 20110307634 | PROGRAMMABLE I/O INTERFACE - The invention provides an architecture and method for implementing a programmable I/O interface. The primary function provides a generic reconfigurable interface for serial communications between a laser printer controller and the print mechanism. The design also supports vertical page synchronization (top of page detection). | 12-15-2011 |
| 20120036289 | Data Flow Control Within and Between DMA Channels - In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure. | 02-09-2012 |
| 20120066415 | METHODS AND SYSTEMS FOR DIRECT MEMORY ACCESS (DMA) IN-FLIGHT STATUS - In accordance with at least some embodiments, a system includes a processing entity configured to run multiple threads. The system also includes a direct memory access (DMA) engine coupled to the processing entity, the DMA engine being configured to track DMA in-flight status information for each of a plurality of DMA channels. The processing entity is configured to manage overlapping DMA requests to a DMA channel of the DMA engine based on said DMA in-flight status information. | 03-15-2012 |
| 20120131236 | COMMUNICATION BETWEEN A COMPUTER AND A DATA STORAGE DEVICE - A method for communicating between a computer and a data storage device comprises receiving, by a data storage device, information indicative of a plurality of commands and information indicative of a memory location in a computer associated with each of the plurality of commands. The method further comprises executing, by the data storage device, one of the plurality of commands. In one embodiment, executing the command comprises directly accessing the computer memory location associated with the command. | 05-24-2012 |
| 20120233360 | Unified DMA - In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations. | 09-13-2012 |
| 20120246354 | Multithreaded Programmable Direct Memory Access Engine - A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution. | 09-27-2012 |
| 20130031281 | USING A DMA ENGINE TO AUTOMATICALLY VALIDATE DMA DATA PATHS - The disclosed embodiments provide a system that uses a DMA engine to automatically validate DMA data paths for a computing device. During operation, the system configures the DMA engine to perform a programmable DMA operation that generates a sequence of memory accesses which validate the memory subsystem and DMA paths of the computing device. For instance, the operation may include a sequence of reads and/or writes that generate sufficient data traffic to exercise the computing device's I/O controller interface and DMA data paths to memory to a specified level. The system initiates this programmable DMA operation, and then checks outputs for the operation to confirm that the operation executed successfully. | 01-31-2013 |
| 20130111078 | DATA TRANSFER CONTROL APPARATUS, DATA TRANSFER CONTROL METHOD, AND COMPUTER PRODUCT | 05-02-2013 |
| 20130111079 | DATA PROCESSING DEVICE, CHAIN AND METHOD, AND CORRESPONDING COMPUTER PROGRAM | 05-02-2013 |
| 20130232284 | STORAGE SYSTEM AND DATA TRANSFER CONTROL METHOD - It is provided a storage system for inputting and outputting data in accordance with a request from a host computer, comprising: at least one processor for processing data requested to be input or output; a plurality of transfer controllers for transferring data between memories in the storage system; and at least one transfer sequencer for requesting a data transfer to the plurality of transfer controllers in accordance with an instruction from the processor. The processor transmits a series of data transfer requests to the at least one transfer sequencer. The at least one transfer sequencer requests a data transfer to each of the plurality of transfer controllers based on the series of data transfer requests. The each transfer controller transfers data between the memories in accordance with an instruction from the at least one transfer sequencer. | 09-05-2013 |
| 20130254435 | STORAGE SYSTEM WITH MULTICAST DMA AND UNIFIED ADDRESS SPACE - A system and method for clients, a control module, and storage modules to participate in a unified address space in order to and read and write data efficiently using direct-memory access. The method for reading data includes determining a first location in a first memory to write a first copy of the data, a second location in a second memory to write a second copy of the data, where the first memory is located in a first storage module including a first persistent storage and the second memory is located in a second storage module including a second persistent storage. The method further includes programming a direct memory access engine to read the data from client memory and issue a first write request to a multicast address, where the first location, the second location, and a third location are associated with the multicast address. | 09-26-2013 |
| 20140215103 | DECOUPLED LOCKING DMA ARCHITECTURE - A decoupled Direct Memory Access (DMA) architecture includes at least two DMA controllers, and optionally at least one of the DMA controllers is operable to assert a lock signal operable to selectively inhibit write access to at least a portion of one system data storage element. The DMA controllers are optionally operable to communicate pending task information and to reschedule pending tasks of at least one the DMA controllers. Optionally data is transferred from at least a first one of the DMA controllers to one or more function units, and processed data from the function units is provided to at least a second one of the DMA controllers. Optionally the DMA controllers and one or more memory elements accessible to the DMA controllers are implemented as part of an I/O device. | 07-31-2014 |
| 20150052268 | DATA PROCESSING - A data processing apparatus comprises a processor having an internal state dependent upon execution of application program code, the processor being configured to generate display data relating to images to be displayed and to buffer display data relating to a most recent period of execution of a currently executing application. The apparatus includes RAM for storing temporary data relating to a current operational state of program execution. The apparatus also includes a data transfer controller configured to transfer data from the RAM relating to the currently executing application, data relating to a current internal state of the processor and buffered display data to suspend data memory, and to transfer data from the suspend data memory to RAM and to the processor to recreate an execution state of an application at a time the suspend instruction was executed, and to retrieve display data relating to the resumed application. | 02-19-2015 |
| 20150149664 | AN ELECTRONIC DEVICE HAVING A PLURALITY OF CPUs AND A METHOD - An electronic device includes a first CPU, a second CPU, an auxiliary storage unit, and a controller. The auxiliary storage unit includes a first starting program for the first CPU and a second starting program for the second CPU. The first CPU loads the first starting program via the controller, and causes the controller to load the second starting program in DMA transfer. The controller, if the controller is caused by the first CPU to transfer part of the first starting program while the controller is loading the second starting program, stops loading the second starting program. When completing the transfer of the part of the first starting program, the controller restarts loading the second starting program. | 05-28-2015 |
