| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708800000 | ELECTRICAL ANALOG CALCULATING COMPUTER | 22 |
| 20130007087 | ANALOG PROCESSOR COMPRISING QUANTUM DEVICES - Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices. | 01-03-2013 |
| 708801000 | Particular function performed | 21 |
| 20090198759 | Circuits for computational set theory - The present invention provides a set of analog circuit modules and procedures for assembling them into circuits that represent fundamental expressions and operations in mathematics, and more specifically to circuits for performing computations on problems formulated as constraints in Set Theory. | 08-06-2009 |
| 20090259709 | METHOD AND APPARATUS FOR ADAPTIVE REAL-TIME SIGNAL CONDITIONING, PROCESSING, ANALYSIS, QUANTIFICATION, COMPARISON, AND CONTROL - Various components of the present invention are collectively designated as Adaptive Real-Time Embodiments for Multivariate Investigation of Signals (ARTEMIS). It is a method, processes, and apparatus for measurement and analysis of variables of different type and origin. In this invention, different features of a variable can be quantified either locally as individual events, or on an arbitrary spatio-temporal scale as scalar fields in properly chosen threshold space. The method proposed herein overcomes limitations of the prior art by directly processing the data in real-time in the analog domain, identifying the events of interest so that continuous digitization and digital processing is not required, performing direct, noise-resistant measurements of salient signal characteristics, and outputting a signal proportional to these characteristics that can be digitized without the need for high-speed front-end sampling. The application areas of ARTEMIS are numerous, e.g., it can be used for adaptive content-sentient real-time signal conditioning, processing, analysis, quantification, comparison, and control, and for detection, quantification, and prediction of changes in signals, and can be deployed in automatic and autonomous measurement, information, and control systems. ARTEMIS can be implemented through various physical means in continuous action machines as well as through digital means or computer calculations. Particular embodiments of the invention include various analog as well as digital devices, computer programs, and simulation tools. | 10-15-2009 |
| 708802000 | Evaluation of equation | 5 |
| 20100161701 | POLYNOMIAL REPRESENTATION FOR SYMBOLIC COMPUTATION - A method for converting a polynomial expression to a data structure for symbolic computation. One or more variables in the polynomial expression may be determined. The variables may be stored in a first array. One or more terms in the polynomial expression may be determined. One or more exponents of the variables in each term may be determined. The exponents may be stored in a second array. One or more coefficients of the terms may be determined. The coefficients may be stored in a third array. | 06-24-2010 |
| 20100161702 | Fluid Dynamics Simulator - In some embodiments, the Navier-Stokes matrix A may be developed on the fly using arrays of Dirichlet and von Neumann boundary conditions. As a result, the storage requirements are dramatically reduced and hardware accelerators or single instruction multiple data processors may be used to solve the Navier-Stokes equations. | 06-24-2010 |
| 20120030270 | METHOD FOR GENERATING A CHALLENGE-RESPONSE PAIR IN AN ELECTRIC MACHINE, AND ELECTRIC MACHINE - A method is described for generating a challenge-response pair in an electric machine as the basis for an authentication. The electric machine has at least one stator and at least one rotor. A voltage signal or current signal which causes induction between the rotor and the stator is generated as the challenge, and a variable which is a function of the caused. induction is determined as the response. | 02-02-2012 |
| 20220138441 | MULTIPLY AND ACCUMULATE CALCULATION DEVICE, NEUROMORPHIC DEVICE, AND MULTIPLY AND ACCUMULATE CALCULATION METHOD - A multiply and accumulate calculation device including a variable resistor array unit having a plurality of variable resistance elements, a reference array unit having a reference resistance element having a fixed resistance value, a signal input unit that generates an input signal from input data, and inputs the input signal to the variable and reference resistance elements, a first detection unit that detects a current flowing through the variable resistor array unit, based on the input signal applied to the variable resistance elements, a second detection unit that detects a current flowing through the reference array unit, based on the input signal applied to the reference resistance element, and a correction calculation unit that performs a predetermined calculation on the output from the first detection unit, based on the output from the second. | 05-05-2022 |
| 708804000 | Differential (e.g., differential analyzer) | 1 |
| 20110225225 | METHOD, PROGRAM, AND SYSTEM FOR SOLVING ORDINARY DIFFERENTIAL EQUATION - Each ordinary differential equation of simultaneous ordinary differential equations is solved with an embedded Runge-Kutta method. A difference Δ between an N-th order approximation and an (N+1)th order approximation is computed, and it is determined whether the difference is smaller than a predetermined threshold Δ | 09-15-2011 |
| 708806000 | Variance or standard deviation determination | 1 |
| 20090172071 | METHOD AND SYSTEM FOR DATA DECOMPOSITION VIA GRAPHICAL MULTIVARIATE ANALYSIS - A method for multivariate analysis using a mathematical model for generating model data and actual data for more than one variable includes for each variable, determining a difference between the model data and the actual data. The model data is substantially representative of more than one variable. The method also includes for each variable, determining a fractional impact on performance. The method further includes for each variable, determining a weighted deviation based on the determined difference and the determined fractional impact. The method also includes transmitting the weighted deviation to an output device. | 07-02-2009 |
| 708809000 | Coordinate conversion or vector resolver | 1 |
| 20090193067 | SERVER-BASED RECALCULATION OF VECTOR GRAPHICS - Technologies are described herein for recalculating data-bound vector graphics on a server computer. A drawing program allows formulas to define how external data is utilized modify the attributes of a shape. When a request is received to publish a drawing to a server computer, any formulas are converted to server-optimized formulas. Once the formulas have been converted to server-optimized formulas, a published drawing is generated that includes the server-optimized formulas, a representation of the drawing in a vector format, and data identifying bindings between shapes within the drawing and external data. When a request to view the published drawing is received, the data bindings for the drawing are refreshed. The server-optimized formulas are then recalculated using updated values to generate new values for the shape attributes. The vector representation of the drawing is then updated with the new values and rasterized for display in a browser. | 07-30-2009 |
| 708813000 | Correlation or convolution | 1 |
| 708816000 | Optical | 1 |
| 20130080496 | OPTICAL PROCESSOR - An optical processor that incorporates optical computing in a monolithic, i.e. single unit, structure that can take the place of, or operate as a coprocessor with, traditional processor devices such as vector processors, digital signal processors, RISCs, CISCs, ASICs, FPGAs among others. The optical processor incorporates photonic devices that perform algorithmic functions on optical signals. The optical processor takes one or more incoming digital signals, converts the digital signal into an optical signal, performs the algorithmic function(s) in the optical domain, and then converts the result back into a digital signal, all in a monolithic or single unit structure. | 03-28-2013 |
| 708819000 | Filtering | 5 |
| 20120136913 | SYSTEM AND METHOD FOR COGNITIVE PROCESSING FOR DATA FUSION - A system and method for cognitive processing of sensor data. A processor array receiving analog sensor data and having programmable interconnects, multiplication weights, and filters provides for adaptive learning in real-time. A static random access memory contains the programmable data for the processor array and the stored data is modified to provide for adaptive learning. | 05-31-2012 |
| 20130254253 | Buffer-less Rotating Coefficient Filter - A circuit that provides a rotating coefficient FIR filter with all necessary coefficient sets present at the same time, without the need for delay elements, devices providing for adjustable impedances, or buffers is described. An input signal is sampled in a round robin fashion by a plurality of switches and capacitors. The capacitors are connected directly to sets of impedance devices. Each set of impedance devices implements the coefficients of the desired frequency response of the filter, adjusted to compensate for the decay of samples in the capacitors between samples. The impedance devices in each set are connected to the capacitors in a different order from each other set, so that each set of impedance devices will produce the desired frequency response when a different one of the capacitor contains a new sample of the input signal. Switches connect the sets of impedance devices to an output and a virtual ground, only one switch being connected to the output at a time to provide the output signal. | 09-26-2013 |
| 20130339418 | Method and Apparatus for Signal Filtering and for Improving Properties of Electronic Devices - The present invention relates to nonlinear signal processing, and, in particular, to adaptive nonlinear filtering of real-, complex-, and vector-valued signals utilizing analog Nonlinear Differential Limiters (NDLs), and to adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. More generally, this invention relates to methods, processes and apparatus for real-time measuring and analysis of variables, and to generic measurement systems and processes. This invention also relates to methods and corresponding apparatus for measuring which extend to different applications and provide results other than instantaneous values of variables. The invention further relates to post-processing analysis of measured variables and to statistical analysis. The NDL-based filtering method and apparatus enable improvements in the overall properties of electronic devices including, but not limited to, improvements in performance, reduction in size, weight, cost, and power consumption, and, in particular for wireless devices, NDLs enable improvements in spectrum usage efficiency. | 12-19-2013 |
| 20140082040 | Passive switched-capacitor filters conforming to power constraint - Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner. | 03-20-2014 |
| 20150032788 | LINEARIZER - The present invention is an improved linearizer that implements more complex transfer functions to provide the necessary linearization performance with a reasonable amount of signal processing resources. Particularly, the linearizer operates on an analog-to-digital converter and comprises a distortion compensator and one or more factored Volterra compensators, which may include a second-order factored Volterra compensator, a third-order factored Volterra compensator, and additional higher-order factored Volterra compensators. Inclusion of factored Volterra distortion compensators improves linearization processing performance while significantly reducing the computational complexity compared to a traditional Volterra-based compensator. | 01-29-2015 |
| 708820000 | Transform | 2 |
| 20080208948 | METHODS AND APPARATUS FOR USING BOOLEAN DERIVATIVES TO PROCESS DATA - Method and apparatus for generating an Nth order Boolean derivative from r bit-array Qth order partial derivatives combined using fusion. Exemplary applications include multimedia, e.g., signal, image and video, processing systems; security systems; edge detection, compression, filtering, multimedia data, e.g., signal, image, video, interpolation and resizing systems; biometrics and recognition systems; networking and communication systems; static hazard free circuit design, simplifying gates in circuits; circuit testing, fault detection, and analysis systems. | 08-28-2008 |
| 708821000 | Fourier | 1 |
| 20130080497 | ANALOG COMPUTATION - Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute. | 03-28-2013 |
| 708835000 | Multiplication | 4 |
| 20110010412 | SYSTEMS, METHODS AND APPARATUS FOR FACTORING NUMBERS - Systems, methods and apparatus for factoring numbers are provided. The factoring may be accomplished by creating a factor graph, mapping the factor graph onto an analog processor, initializing the analog processor to an initial state, evolving the analog processor to a final state, and receiving an output from the analog processor, the output comprising a set of factors of the number. | 01-13-2011 |
| 20130246497 | ADAPTIVE PRECISION ARITHMETIC UNIT FOR ERROR TOLERANT APPLICATIONS - Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision computation given the underlying speed of the circuit. The resulting improvement can be allocated to increasing yield or dynamically trading off between reduced power consumption, faster computation, or higher-fidelity computation. | 09-19-2013 |
| 20140280430 | Multiplier Circuit with Dynamic Energy Consumption Adjustment - A fixed point multiplier that can be used in mobile computer systems operating under limited power constraints provides a trade-off between computational accuracy and energy consumption that may be changed dynamically for energy conservation purposes. In one embodiment, the multiplier pre-stores multiplication shift coefficients to eliminate leading-one circuitry normally used in shift and accumulate multipliers. | 09-18-2014 |
| 708838000 | Having charging or discharging of energy storage device | 1 |
| 20090144354 | IMAGING DEVICE - An imaging device that improves properties for multiplying signal charges. The imaging device includes an accumulation section which accumulates signal charges. A transfer section transfers the signal charges accumulated in the accumulation section. A multiplier section increases the signal charges accumulated in the accumulation section. The transfer section includes a first insulating member arranged on a substrate and a first electrode arranged on the first insulating member. The multiplier section includes a second insulating member arranged on the substrate and a second electrode arranged on the second insulating member. The second insulating member has a thickness which is greater than that of the first insulating member. | 06-04-2009 |
