Class / Patent application number | Description | Number of patent applications / Date published |
708190000 | Integrated circuit | 15 |
20090100117 | SEMICONDUCTOR INTEGRATED CIRCUIT - The invention reduces unnecessary electromagnetic radiation noise due to an operation clock signal generated by an oscillator circuit. Random number data outputted by a random number generation circuit is stored in a frequency variable data register. The data stored in the frequency variable data register is replaced by random number data sequentially generated by the random number generation circuit. An oscillator circuit is a circuit generating a clock signal, and the clock signal is supplied as an operation clock signal to an internal circuit through an operation clock signal generation circuit. The frequency of the clock signal from the oscillator circuit is variably controlled in response to the random number data stored in the frequency variable data register. A frequency variable range control register which stores control data for controlling the range of the frequency variably controlled in response to the random number data stored in the frequency variable data register is further provided. | 04-16-2009 |
20090271461 | SEMICONDUCTOR INTEGRATED CIRCUIT - There is provided a semiconductor integrated circuit including: a plurality of first logic blocks which are reconfigurable, the plurality of first logic blocks inputting data of a first bit width and performing computation; a first network connecting the plurality of first logic blocks in a dynamically reconfigurable manner; a plurality of second logic blocks inputting data of a second bit width different from the first bit width and performing computation; a second network connected to outputs of the plurality of second logic blocks; and a third network connecting a carry bit output of a computing unit included in the first logic block to an input of a computing unit included in the second logic block in a dynamically reconfigurable manner. | 10-29-2009 |
20150100608 | RECONFIGURING AN ASIC AT RUNTIME - Methods for reconfiguring an ASIC at runtime without using voltage over scaling. A functional criticality of a set of logic in the ASIC is identified. Then, the set of logic are classified into a set of regions based on the functional criticality, each region of the set of regions having a target error threshold. Further, each region is power gated at runtime based on the functional criticality such that the target error threshold is achieved without using voltage over scaling. | 04-09-2015 |
20150149517 | LOGIC DEVICE AND METHOD OF PERFORMING A LOGICAL OPERATION - The invention provides a logic device, e.g. a Boolean logic gate, comprising: a memristor having: an input for receiving a sequence of voltage states which represent a sequence of logical inputs for a logical operation, and an output for an output current response triggered by the sequence of voltage states; and a determining unit arranged to determine an output of the logical operation from the output current response. | 05-28-2015 |
20150301802 | RANDOM NUMBER PROCESSING APPARATUS AND RANDOM NUMBER PROCESSING METHOD - A random number processing apparatus includes a memory cell and a control circuitry. The memory cell has a characteristic in which a resistance value reversibly shifts between a plurality of resistance value ranges in accordance with an electric signal applied. The control circuitry generates random number data on the basis of a plurality of items of resistance value information obtained, at a plurality of different times, from the memory cell whose resistance value is in a certain resistance value range of the plurality of resistance value ranges. The resistance value of the memory cell randomly changes over time while the resistance value is within the certain resistance value range. | 10-22-2015 |
20160041813 | Multiplication Circuit Providing Dynamic Truncation - A fixed-point multiplier providing reduced energy usage dynamically truncates received operands according to the location of computationally important bits in the operands and provides the truncated operands to a reduced width multiplier offering reduced energy usage. Information about the location of the dynamic truncation is used to properly shift the result of the multiplier to provide an approximation of full multiplication of the operands. | 02-11-2016 |
20160062733 | MULTIPLICATION OPERATIONS IN MEMORY - Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line. | 03-03-2016 |
20160062951 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of spin units individually including a memory cell configured to store values of spins in an Ising model, a memory cell configured to store an interaction coefficient from an adjacent spin that exerts an interaction on the spin, a memory cell configured to store an external magnetic field coefficient of the spin, and an interaction circuit configured to determine a subsequent state of the spin. The spin units individually include a random number generator configured to supply the random number to the plurality of the spin units and generate two-valued simulated coefficients of two values or simulated coefficients of three values in performing an interaction to determine a subsequent state of a spin of the spin units from a value of a spin from an adjacent spin unit, an interaction coefficient, and an external magnetic field coefficient. | 03-03-2016 |
20160077803 | SYSTEMS AND METHODS FOR COMPUTING MATHEMATICAL FUNCTIONS - Mathematical functions are computed in a single pipeline performing a polynomial approximation (e.g. a quadratic approximation, or the like) using data tables for RCP, SQRT, EXP or LOG using a single pipeline according and opcodes. SIN and COS are also computed using the pipeline according to the approximation ((−1)̂IntX)*Sin(π*Min(FracX, 1.0−FracX)/Min(FracX, 1.0−FracX). A pipeline portion approximates Sin(π*FracX) using tables and interpolation and a subsequent stage multiplies this approximation by FracX. For input arguments of x close 1.0. LOG 2(x−1)/(x−1) is computed using a first pipeline portion using tables and interpolation and subsequently multiplied by (x−1). A DIV operation may also be performed with input arguments scaled up to avoid underflow as needed. Inverse trigonometric functions may be calculated using a pre-processing stage and post processing stage in order to obtain multiple inverse trigonometric functions from a single pipeline. | 03-17-2016 |
20160098378 | Method and System for Performing Robust Regular Gridded Data Resampling - During data resampling, bad samples are ignored or replaced with some combination of the good sample values in the neighborhood being processed. The sample replacement can be performed using a number of approaches, including serial and parallel implementations, such as branch-based implementations, matrix-based implementations, and function table-based implementations, and can use a number of modes, such as nearest neighbor, bilinear and cubic convolution. | 04-07-2016 |
20160124711 | SIGNIFICANCE ALIGNMENT - A data processing system uses alignment circuitry to align input operands in accordance with a programmable significance parameter to form aligned input operands. The aligned input operands are supplied to arithmetic circuitry, such as an integer adder or an integer multiplier, where a result value is formed. The result value is stored in an output operand storage element, such as a result register. The programmable significance parameter is independent of the result value. | 05-05-2016 |
20160124905 | APPARATUS AND METHOD FOR VECTOR PROCESSING - An apparatus comprises processing circuitry for performing, in response to a vector instruction, a plurality of lanes of processing or respective data elements with at least one operand vector to generate corresponding result data elements of a result vector. The processing circuitry may support performing at least two of the lanes of processing with different rounding modes for generating rounding values for the corresponding result data elements of the result vector. This allows two or more calculations with different rounding modes to be executed in response to a single instruction, to improve performance. | 05-05-2016 |
20160142042 | ELIMINATION METHOD FOR COMMON SUB-EXPRESSION - A common sub-expression elimination method for simplifying hardware logic of a hardware filter circuit by eliminating a common sub-expression included in a plurality of sub-expressions is provided. Each of the sub-expressions includes a corresponding two or more of inputs constituting a plurality of coefficients used by the hardware filter circuit. The method is implemented on a computing device and includes: identifying for each coefficient of the plurality of coefficients, a combination of the inputs constituting the coefficient; counting occurrences of the sub-expressions in each of the coefficients; identifying one or more of the sub-expressions having a maximum one of the counts and including the corresponding two or more of the inputs; selecting one of the one or more of the sub-expressions as the common sub-expression; eliminating the common sub-expression; and repeating these steps to eliminate more of the sub-expressions common to multiple ones of the coefficients. | 05-19-2016 |
20160156358 | COMPRESSOR CIRCUIT AND COMPRESSOR CIRCUIT LAYOUT | 06-02-2016 |
20160188296 | SYSTEMS AND METHODS FOR ANALYZING STABILITY USING METAL RESISTANCE VARIATIONS - This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks. | 06-30-2016 |