| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 703026000 | Of instruction | 78 |
| 20080215306 | Device and Method for Managing a Retransmit Operation - A method and device for managing retransmit operations. The device, includes a FIFO memory unit, a read pointer, a retry pointer and a write pointer. The device is characterized by including a gray code stat e machine connected to an emulated read pointer logic; whereas the gray code state machine is adapted to provide a gray code word representative of a state of a read logic that comprises the read pointer; whereas the emulated read pointer logic is adapted to process at least one gray code word and to provide an emulated read pointer that tracks a FIFO memory unit entry that stores data that was not accepted; whereas the emulated read pointer logic is connected to a write control logic adapted to control writing operations to the FIFO memory unit in response to the emulated read pointer logic; and whereas the read logic receives a read clock that differs from a write clock provided to the emulated read pointer logic and to the write control logic. | 09-04-2008 |
| 20080221861 | Verification Apparatus and Verification Method - When performing a process in an object to be authenticated, there is a case that an execution result depends on the reference data value to be referenced and remains undefined. When the execution result is undefined and a process after that references the execution result, the execution results may have different values. As a result, the execution results cannot be compared and authentication cannot be continued. There is provided an authentication device for giving the same test pattern to an object to be authenticated and an expectation value generation device, performing simulation, and comparing the execution results. Data being simulated is extracted. According to the analysis result of the extracted data, the simulation is controlled. Alternatively, simulation after the undefined result is obtained is controlled. Thus, it is possible to prevent execution of a process which becomes an undefined result. | 09-11-2008 |
| 20080234999 | Implementing performance-dependent transfer or execution decisions from service emulation indications - A system, method, computer program product, and carrier are described for obtaining data from a first emulator and from a first emulation environment hosting software and signaling a decision whether to transfer any of the data to a second emulator at least partly as a result of the first emulation environment hosting the software. | 09-25-2008 |
| 20080235000 | Implementing security control practice omission decisions from service emulation indications - A system, method, computer program product, and carrier are described for obtaining an indication of an emulation of a service in a first environment with a first security control practice or obtaining one or more gradational norms of software performance in an emulation environment; and signaling a decision whether to allow a software object to execute in another environment at least partly as a result of whether the software object apparently performed in conformity with the one or more gradational norms of software performance in the emulation environment or signaling a decision whether to use a second environment without the first security control practice in performing at least a portion of the service as a result of the indication of the emulation of the service in the first environment with the first security control practice. | 09-25-2008 |
| 20080235001 | Implementing emulation decisions in response to software evaluations or the like - A system, method, computer program product, and carrier are described for to obtaining a decision whether to host an instruction sequence natively in a physical environment in response to an operational history of software apparently containing the instruction sequence or obtaining a decision whether to host an instruction sequence in an emulation environment at least in response to an evaluation of software containing the instruction sequence; and causing another environment to host the instruction sequence in response to the decision whether to host the instruction sequence in the emulation environment or signaling a decision whether to cause an emulation environment to host the instruction sequence in response to the decision whether to host the instruction sequence natively in the physical environment. | 09-25-2008 |
| 20080235002 | Implementing performance-dependent transfer or execution decisions from service emulation indications - A system, method, computer program product, and carrier are described for obtaining data from a first emulator and from a first emulation environment hosting software; and signaling a decision whether to transfer any of the data to a second emulator at least partly as a result of the first emulation environment hosting the software. | 09-25-2008 |
| 20080243468 | PROVIDING MEMORY CONSISTENCY IN AN EMULATED PROCESSING ENVIRONMENT - Memory consistency is provided in an emulated processing environment. A processor architected with a weak memory consistency emulates an architecture having a firm memory consistency. This memory consistency is provided without requiring serialization instructions or special hardware. | 10-02-2008 |
| 20080243469 | Emulation system - An emulation system emulates a sound IC having a built-in ROM and reproducing sound data stored in the built-in ROM or received sound data. The emulation system includes: a sound data storage section storing sound data to be stored in the built-in ROM; a command reception section; a command conversion section that performs a command conversion process that converts a built-in ROM data reproduction command into a data-attached reproduction command having a format interpretable by the sound IC when the command conversion section has received the built-in ROM data reproduction command; and a converted command transmission section. The command conversion section reads sound data from the sound data storage section based on the received built-in ROM data reproduction command, and generates the data-attached reproduction command to which the read sound data is attached. | 10-02-2008 |
| 20090024381 | Simulation device for co-verifying hardware and software - A simulation device capable of verifying coordinated operation of software and hardware faster and more accurately. The simulation device has a framework including a virtual OS and a virtual CPU to execute software under test. The virtual OS and CPU also serve as a first scheduler that manages an execution schedule for the software under test. The framework includes a communication interface for communication between the software under test and hardware models. A second scheduler manages simulation processes of the framework and the hardware model. The virtual OS and CPU release their execution right to the second scheduler according to the execution schedule of the software under test. | 01-22-2009 |
| 20090030668 | SIGNED/UNSIGNED INTEGER GUEST COMPARE INSTRUCTIONS USING UNSIGNED HOST COMPARE INSTRUCTIONS FOR PRECISE ARCHITECTURE EMULATION - Architecture for efficient translation and processing of PowerPC guest instructions on an x86 host machine. In an x86-based architecture, signed integer values are projected into the unsigned integer value space for processing by the host using the negation of the left-most (sign) bit. Compare operations are performed in the unsigned space and the compare results are written into the host flags register. Once the compare results are written into the host flags register, the flag values can be read out and used in a table lookup to retrieve the corresponding values for the guest register. The guest flag values are then passed into the guest flags register for processing by the guest application. | 01-29-2009 |
| 20090089040 | SYSTEM AND METHOD FOR DETECTING MULTI-COMPONENT MALWARE - Malicious behavior of a computer program is detected using an emulation engine, an event detector and an event analyzer. The emulation engine includes a system emulator configured to emulate, in an isolated computer environment, at least a part of a computer system and a program emulator configured to emulate in the isolated computer environment execution of the computer program, including execution of a plurality of executable components of the computer program, such as execution processes and threads. The event detector is configured to monitor events being generated by two or more of the executable components. The event analyzer is configured to determine, substantially in real time, based at least on one or more events generated by each of two or more of the plurality of executable components whether or not the computer program exhibits malicious behavior, wherein individually one or more of the plurality of executable components may exhibit benign behavior. | 04-02-2009 |
| 20090089041 | COMPUTER EMULATOR EMPLOYING DIRECT EXECUTION OF COMPILED FUNCTIONS - An emulation system that provides the functionality of an emulated computer on a host computer pre-processes the object code file to be emulated to reduce the run-time overhead due to parsing the object code. The emulator uses pre-programmed functions that model each instruction of the emulated computer. An object code file is pre-parsed to generate a translated file which includes a sequence of function calls corresponding to the sequence of instructions in the code file. The translated file is compiled to generate a corresponding translated object-code file. The translated object-code file is executed in the emulation environment on the host computer. The emulation system also includes a standard mode in which the object code file is emulated by sequentially parsing each instruction in the object code file and invoking an appropriate one of the preprogrammed functions in the emulated environment. | 04-02-2009 |
| 20090094015 | COMPUTER EMULATOR EMPLOYING DIRECT EXECUTION OF COMPILED FUNCTIONS - An emulation system that provides the functionality of an emulated computer on a host computer pre-processes the object code file to be emulated to reduce the run-time overhead due to parsing the object code. The emulator uses preprogrammed functions that model each instruction of the emulated computer. An object code file is pre-parsed to generate a translated file which includes a sequence of function calls corresponding to the sequence of instructions in the code file. The translated file is compiled to generate a corresponding translated object-code file. The translated object-code file is executed in the emulation environment on the host computer. The emulation system also includes a standard mode in which the object code file is emulated by sequentially parsing each instruction in the object code file and invoking an appropriate one of the preprogrammed functions in the emulated environment. | 04-09-2009 |
| 20090164205 | PROCESSOR EMULATION USING FRAGMENT LEVEL TRANSALTION - Processor emulation using fragment level translation is disclosed. A target system having a main target processor, a secondary target processor element and an instruction memory associated with the secondary target processor element may be emulated with a host system having one or more host processors and a host memory. Two or more target system code instructions for the secondary target processor may be grouped into one or more fragments with known starts and ends. A data structure that maps the host memory locations of the starts and ends may be maintained. Each fragment may be translated into a corresponding set of position-independent translated fragments executable by the host system. The translated fragments may be loaded into one or more of the host processors. If a memory layout for target system code corresponding to the one or more fragments has changed, the fragments may be dynamically re-linked, without re-translation, and executed. | 06-25-2009 |
| 20090171651 | SDRAM-BASED TCAM EMULATOR FOR IMPLEMENTING MULTIWAY BRANCH CAPABILITIES IN AN XML PROCESSOR - The system and method of the present invention “emulates” the TCAM function using a data structure which is stored in an SDRAM device in such way that the size of emulated TCAM is substantially larger than the original TCAM device, thereby allowing the increase of the number of PPE programs which can be resident in memory. The present invention provides a new “emulCAM” algorithm which builds partially on BaRT, but is extended by providing multiple results per hash table entry with flexible assignment to “match-condition-combinations”, by utilizing MUX control vectors for extracting hash index instead of “index-mask-based extraction”, by moving part of CAM function to invoking emulCAM instruction and by providing “Pathological case handling” using multiple emulCAM instructions. | 07-02-2009 |
| 20090171652 | VIRTUALIZATION PROGRAM, SIMULATION APPARATUS AND VIRTUALIZATION METHOD - A virtualization program for being able to execute a simulation at high speed, allows a native code simulator to have a stack specific to each task that is managed by a multitask OS. Processes of creation, save, restoration and erasure of a context that a target CPU executes by means of a special control register operation is executed by an API provided by the native code simulator. When porting the multitask OS, the source code is altered so as to call the API. A stack specific to a task is assigned at the API and the stack is switched for switching the task to make context switching possible. | 07-02-2009 |
| 20090216520 | SYSTEM AND METHOD FOR INTERFACING A MEDIA PROCESSING APPARATUS WITH A COMPUTER - A system comprising a media processing apparatus and a computer where the media processing apparatus emulates a mass storage device and interfaces with the computer is disclosed. In one embodiment the media processing apparatus appears to the computer as a Universal serial bus (USB) mass storage device, and the operating system (OS) on the computer, using its pre-installed USB mass storage device driver, establishes bi-directional communication channel with the media processing apparatus. Thus, the need to develop an OS specific kernel-mode device driver for the media processing apparatus is eliminated. The system may employ a proprietary communication protocol on the USB bus to send and receive data between the computer and the media processing apparatus. In one embodiment, the computer sends and receives data by executing read and write operations to sectors of the emulated USB mass storage device; while the media processing apparatus deciphers the read and write operations on emulated sectors and takes appropriate actions. User-mode applications on the computer and the media processing apparatus may employ Remote Procedure Call (RPC) mechanisms to issue commands and share their respective resources with each other. | 08-27-2009 |
| 20090216521 | Emulation export sequence with distrubuted control - Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into information blocks, and outputting a sequence of the information blocks from the data processor. Some of the information blocks of the sequence have relative proportions of emulation control information and emulation data that differ from the relative proportions of emulation control information and emulation data in other blocks of the sequence. | 08-27-2009 |
| 20090271172 | Emulating A Computer Run Time Environment - Emulating a computer run time environment as a component of a dynamic binary translation loop that translates target executable code compiled for execution on a target computer to code executable on a host computer of a kind other than the target computer, the target executable code including function calls to functions to be translated. Embodiments of the present invention include: determining, upon encountering in the binary translation loop a function call to a function to be translated, that the function call is a call to a host library function in a host native library; hashing a target executable image of the function to be translated from the target executable code, thereby producing a hash value; and using the hash value as an index to retrieve from a thunk table a host native address of the host library function in the host native library. | 10-29-2009 |
| 20090276205 | STABLIZING OPERATION OF AN EMULATED SYSTEM - Disclosure of approaches for stabilizing an emulated system. In one approach, a first operating system (OS) is executed on an instruction processor, the first OS including instructions native to the instruction processor. A second OS and a plurality of application programs are emulated on the first OS. The second OS polls the first OS for memory statistics of the first OS. The memory statistics indicate a current state of operating parameters of the memory of the data processing system used by the first OS in managing the data processing system. The second OS controls a number of the application programs allowed to execute in response to the memory statistics provided by the first OS to the second OS. | 11-05-2009 |
| 20090319256 | DECOUPLING DYNAMIC PROGRAM ANALYSIS FROM EXECUTION ACROSS HETEROGENEOUS SYSTEMS - Dynamic program analysis is decoupled from execution in virtual computer environments so that program analysis can be performed on a running computer program without affecting or perturbing the workload of the system on which the program is executing. Decoupled dynamic program analysis is enabled by separating execution and analysis into two tasks: (1) recording, where system execution is recorded with minimal interference, and (2) analysis, where the execution is replayed and analyzed. Recording and analysis are carried out on heterogeneous systems so that they can be separately optimized. | 12-24-2009 |
| 20100106479 | CPU EMULATION SYSTEM, CPU EMULATION METHOD, AND RECORDING MEDIUM HAVING A CPU EMULATION PROGRAM RECORDED THEREON - A CPU emulation system includes; a plurality of virtual CPUs each operating on a different physical CPU; an instruction sequence selecting section for selecting an instruction sequence to be optimized; a virtual CPU selecting section for selecting one of the plurality of virtual CPUs, which is to perform optimization processing of the selected instruction sequence, based on usage rates of the plurality of virtual CPUs; and an optimization level selecting section for determining an optimization level of the optimization processing that is to be executed by the selected one of the plurality of virtual CPUs, and giving a direction to perform the optimization processing to the selected one of the plurality of virtual CPUs. | 04-29-2010 |
| 20100114555 | HANDLING MUTEX LOCKS IN A DYNAMIC BINARY TRANSLATION ACROSS HETEROGENOUS COMPUTER SYSTEMS - A method for executing non-native binaries on a host computer architecture comprises receiving a guest executable binary encoded on a computer readable medium. The guest executable binary is executable on a first computer architecture. Moreover, the guest executable binary includes a mutex lock encoded instructions for implementing a mutex lock. The guest executable binary is then executed on the host computer architecture by first translating the guest executable binary to a translated executable binary. The encoded instructions for implementing a mutex lock are translated by mapping the mutex lock to an instance of a compound mutex lock data structure. A computer system implementing methods for executing non-native binaries on a host computer architecture is also provided. | 05-06-2010 |
| 20100125444 | Method And Apparatus For Reducing Read Latency In A Pseudo Nor Device - A NOR emulating memory device has a memory controller with a first bus for receiving a NOR command signal, and for servicing a read operation from a desired address in a NOR memory. The memory controller has a second bus for communicating with a NAND memory in a NAND memory protocol, and a third bus for communicating with a RAM memory. A NAND memory is connected to the second bus. The NAND memory has an array of memory cells divided into a plurality of pages with each page divided into a plurality of sectors, with each sector having a plurality of bits. The NAND memory further has a page buffer for storing a page of bits read from the array during the read operation of the NAND memory. A RAM memory is connected to the third bus. The memory controller has a NOR memory for storing program code for initiating the operation of the memory controller, and for receiving NOR commands from the first bus and issuing NAND protocol commands on the second bus, in response thereto, to emulate the operation of a NOR memory device. The program code causes the memory controller to read a first sector of bits from the page buffer of the NAND memory and to write the sector of bits into the RAM memory, wherein the first sector contains the location of the desired address, and supplying data from said RAM memory in response to the read operation. | 05-20-2010 |
| 20100125445 | APPARATUS AND METHOD FOR TESTING ELECTRONIC APPARATUSES - A method for testing electronic apparatuses is provided. The method includes: reading an identification (ID) of an emulator adapter; searching for the script name in a test table according to the ID; fetching the script from a storage according to the determined script name and running the fetched script to pass each of input commands; and receiving and identifying each of the input commands to simulate a key input via an electrical conductive path, correspondingly to the input command, of the emulator adapter, such that an input key corresponding to the key input of the to-be-tested electronic apparatus is activated and the to-be-tested electronic apparatus performs a function associated with the input key correspondingly. A related test apparatus is also provided. | 05-20-2010 |
| 20100250230 | ENLIGHTENMENT FOR LOW OVERHEAD HARDWARE ACCESS - A computing system in which a software component executing on a platform can reliably and efficiently obtain state information about a component supported by the platform through the use of a shared memory page. State information may be supplied by the platform, but any state translation information needed to map the state information as supplied to a format as used may be provided through the shared page. In a virtualized environment, the state translation information can be used to map the value of a virtual timer counter or other component from a value provided by a virtual processor to a normalized reference time that will yield the same result, regardless of whether the software component is migrated to or from another virtual processor. Use of a shared page avoids the inefficiency of an intercept into a virtualized environment or a system calls in native mode operation. | 09-30-2010 |
| 20100274551 | SUPPORT FOR A NON-NATIVE APPLICATION - Aspects of the invention are directed to a systems and methods for operating a non-native binary in dynamic binary translation environment. In accordance with an embodiment, there is provided a computer program product in a computer readable medium. The product includes program code for receiving a non-native binary in a computer readable medium and program code for translating the non-native binary. Additionally, the product includes program code for executing the translated non-native binary, the non-native binary including one or more threads, and program code for pausing execution of the translated non-native binary. The product also includes program code for providing guest instruction boundary information to a monitoring process and program code for analyzing a state of each thread of the translated non-native binary. Moreover, the product includes program code for fast-forwarding at least one thread so that its state is consistent with the guest instruction boundary | 10-28-2010 |
| 20100299130 | Apparatus, method and program for processing information - Apparatus and method for processing information may determine whether a migration condition exists by a source information processing unit executing a program. When a migration condition is determined to exist by the source information processing unit, a destination information processing unit may determine whether an instruction to be executed of the program is a predetermined instruction. The instruction to be executed is converted by an instruction emulator, when a result of a determination by the destination information processing unit is the predetermined instruction. | 11-25-2010 |
| 20100305937 | COPROCESSOR SUPPORT IN A COMPUTING DEVICE - Coprocessor support on a computing device is provided by means of external modules attaching themselves to the operating system (OS) kernel controlling the device at system boot time, with the modules registering themselves as valid coprocessor handlers. Threads initially execute with coprocessors disabled; the consequent exceptions caused by executing coprocessor instructions are then passed to the relevant registered handler. The technique can be used either to support installed coprocessors or to emulate absent coprocessors. | 12-02-2010 |
| 20100305938 | TRANSLATION BLOCK INVALIDATION PREHINTS IN EMULATION OF A TARGET SYSTEM ON A HOST SYSTEM - Emulation systems and method involving invalidating blocks of translated code in emulation of a target system on a host system in are disclosed. One or more blocks of target system code are translated by the host system to produce one or more corresponding blocks of translated code. The host system uses one or more native target system instructions as hints to invalidate or potentially invalidate one or more blocks of translated code. Blocks containing such hints cause the host system to mark some or all of the one or more blocks of translated code as potentially invalid. The potentially invalid blocks may be re-translated immediately. Alternatively, the potentially invalid blocks may be checked to see if the code in these blocks has been modified. If the code has been modified, corresponding blocks of target code may be re-translated. | 12-02-2010 |
| 20110071813 | Page Mapped Spatially Aware Emulation of a Computer Instruction Set - Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page. | 03-24-2011 |
| 20110071814 | Self Initialized Host Cell Spatially Aware Emulation of a Computer Instruction Set - A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed | 03-24-2011 |
| 20110071815 | Host Cell Spatially Aware Emulation of a Guest Wild Branch - A instructions of a Guest program to be emulated by a Host computer occupy one or more Guest cells of Guest memory, each Guest cell having a corresponding Host cell in Host memory. The emulator selects a Host cell for emulating a Guest instruction. When the Host cell corresponds to a Guest cell other than a cell aligned with the beginning of the Guest instruction, a wild branch handling routine is executed. | 03-24-2011 |
| 20110071816 | Just In Time Compiler in Spatially Aware Emulation of a Guest Computer Instruction Set - A selected group of Guest machine instructions in an emulation environment are translated to a semantic routine of Host machine instructions, wherein Guest cells corresponding to an opcode portion of a Guest instruction are mapped to corresponding Host cells, wherein the semantic routine of Host machine instructions are patched into a Host cell corresponding to the first Guest cell of the group of Guest machine instructions, wherein other Host cells of the corresponding Host cells are patched with semantic routines for emulating single instructions associated with the corresponding Guest cell. | 03-24-2011 |
| 20110106521 | Extended Input/Output Measurement Word Facility and Emulation of That Facility - An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond. | 05-05-2011 |
| 20110112820 | Reusing Invalidated Traces in a System Emulator - Native code corresponding to an invalidated trace is re-used in a system emulator. A first trace is identified. A dropped second trace is identified. The dropped second trace is associated with a first native code for emulating the second trace. If the identified first trace corresponds to the dropped second trace, the first native code is associated to the first trace, and the first native code is executed. If the identified first trace does not correspond to the dropped second trace, a second native code for emulating the first trace is created, the second native code is associated with the first trace, and the second native code is executed. | 05-12-2011 |
| 20110153307 | Transitioning From Source Instruction Set Architecture (ISA) Code To Translated Code In A Partial Emulation Environment - In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed. | 06-23-2011 |
| 20110153308 | VIRTUALIZATION APPARATUS AND PROCESSING METHOD THEREOF - A virtualization apparatus includes: an emulation manager for searching a basic block cache for an entry with an entry point, and, if there exists no entry with the entry point in the basic block cache, requesting the identification of a basic block corresponding to the entry point; a basic block identifier for identifying the basic block by sequentially analyzing instructions of a source binary in response to a request from the emulation manager; and an instruction replacer for writing an entry of the identified basic block in an replaced instruction table, writing a branch instruction for the entry of the basic block in the source binary, and then branching to the entry point. The apparatus further includes an instruction emulator for executing an instruction of the basic block when a branch to the entry point is made. | 06-23-2011 |
| 20110172986 | Mainframe data stream proxy and method for caching communication between emulators and mainframes - The present invention concerns a mainframe data stream proxy (MDSP) ( | 07-14-2011 |
| 20110208505 | ASSIGNING FLOATING-POINT OPERATIONS TO A FLOATING-POINT UNIT AND AN ARITHMETIC LOGIC UNIT - A processor may include a floating-point unit (FPU) and an arithmetic logic unit (ALU). Instructions to the processor may include greater or lesser amounts of floating-point operations and integer operations. In a circumstance where instructions include predominantly integer operations, power to the FPU may be reduced or turned completely off. In such a circumstance, occasional floating-point operations may be emulated and performed by the ALU. If the processor subsequently determines that incoming instructions include a greater proportion of floating-point operations, the FPU may be powered back on and used to perform the floating-point operations. | 08-25-2011 |
| 20110231179 | METHODS FOR CONVERTING INSTRUCTIONS WITH BASE REGISTER-RELATIVE ADDRESSING IN AN EMULATION - An original processor uses addresses with a first length of n bits for addressing in a cyclical address space and a target processor uses addresses with a second length of m bits, where the second length m is greater than the first length n. In the original processor, distance values that lie between a lower value min and an upper value max are permissible for the base register-relative addressing. The supported address space on the original processor for the code to be emulated is limited in such a manner that the conversion of address operands as described in the following steps leads to semantically equivalent behavior on the target processor. A projected address on the target processor is initially determined by forming the sum of the content of the base register (R) and an offset (D) that is greater than or equal to a first offset (D | 09-22-2011 |
| 20110238403 | TRANSLATION BLOCK INVALIDATION PREHINTS IN EMULATION OF A TARGET SYSTEM ON A HOST SYSTEM - In emulation of a target system on a host system one or more blocks of target system code may be translated with the host system to produce one or more corresponding blocks of translated code. Translating the target system code may include linking two or more blocks of translated code together to form a chain such that a look-up in a first translated block in the chain will directly branch to a second translated block. The target system code may be analyzed for the presence of one or more native target system instructions indicating modification of the target system code during execution. If such native target system instructions are present some or all of the blocks of translated code may be marked potentially invalid. The one or more blocks marked as potentially invalid may be re-translated and one or more instructions in the blocks of translated code may be overridden without undoing the chain. | 09-29-2011 |
| 20110307238 | Methods for utilizing a javascript emulator in a web content proxy server and devices thereof - A method, computer readable medium and apparatus that utilize a JavaScript emulator in a proxy server to create and store an object model of a web page which has one or more JavaScript instruction sets. At least one of the one or more JavaScript instruction sets are extracted from the web page and a JavaScript field identifier is inserted into the web page to optimize the web page which is then provided. | 12-15-2011 |
| 20120059643 | PROCESSOR EMULATION USING FRAGMENT LEVEL TRANSLATION - Emulation of a target system with a host system is disclosed. Two or more target system code instructions may be grouped into one or more fragments. A main translation function may be implemented by translating each fragment into a corresponding set of position-independent instructions executable by the host system. A target processor may be emulated by executing the corresponding set of position-independent executable instructions with the host system. | 03-08-2012 |
| 20120109622 | EXTRACT CPU TIME FACILITY - An efficient facility for determining resource usage, such as a processor time used by tasks. The determination is performed on behalf of user applications that do not require a call to operating system services. The facility includes an instruction that determines elapsed time and reports it to the user as a single unit of operation. | 05-03-2012 |
| 20120143589 | MULTI-MODAL COMPILING APPARATUS AND METHOD FOR GENERATING A HYBRID CODEFILE - A non-native, multi-modal compiler and an emulated computing environment for use in a native computing environment. The multi-modal compiler includes a parser configured to parse or divide received source code into a plurality of token elements, whereby at least one statement is recognized from a collection of token elements. The multi-modal compiler also includes a code emitter configured to emit machine code to implement the at least one statement, whereby the emitted machine code is compiled multi-modal object code that includes non-native operators (e.g., E-Mode operators) and NATV operators. The compiled multi-modal object code is configured in such a way that when translated by a code translation unit, the compiled multi-modal object code generates a merged codefile having translated native code segments corresponding to the non-native operators and native code segments corresponding to the NATV operators. The merged codefile is executable by a native processor in the native computing environment. | 06-07-2012 |
| 20120158397 | INSTRUCTION-SET ARCHITECTURE SIMULATION TECHNIQUES USING JUST IN TIME COMPILATION - A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator. | 06-21-2012 |
| 20120271615 | FAST EMULATION OF VIRTUALLY ADDRESSED CONTROL FLOW - A method, system and computer program product is provided for emulating two or more processes for executing a source application, comprising: providing virtual trampoline memory whereby each emulated process has a respective private trampoline memory; providing shared code heap memory, wherein each emulated process only sees the code heap and its respective private trampoline memory; fetching a fragment of source instructions from the application; generating equivalent target instructions for writing to the code heap, the fragment of target instruction being indexed by its physical address in the code heap; generating, for each jump instruction in the fragment, a jump to a slot in the virtual trampoline memory; and writing a trap in each private trampoline slot, each trap adapted to be replaced by a jump to a physical address in the code heap corresponding the start of the same or a different target instruction fragment. | 10-25-2012 |
| 20120284011 | PROCESSOR EMULATION USING SPECULATIVE FORWARD TRANSLATION - A method and apparatus for processor emulation using speculative forward translation are disclosed. A potential candidate for forward translation is identified from one or more portions of target system code. A priority for forward translation is assigned to the potential candidate. It is determined whether the potential candidate is a valid candidate for forward translation. If valid, the potential candidate is translated with a host system to produce one or more corresponding blocks of translated code executable by the host system. | 11-08-2012 |
| 20120296626 | INSTRUCTION SET EMULATION FOR GUEST OPERATING SYSTEMS - The described implementations relate to virtual computing techniques. One implementation provides a technique that can include receiving a request to execute an application. The application can include first application instructions from a guest instruction set architecture. The technique can also include loading an emulator and a guest operating system into an execution context with the application. The emulator can translate the first application instructions into second application instructions from a host instruction set architecture. The technique can also include running the application by executing the second application instructions. | 11-22-2012 |
| 20120323552 | Apparatus and Method for Hardware Initiation of Emulated Instructions - A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register. | 12-20-2012 |
| 20130090913 | STREAMLINED EXECUTION OF EMULATED CODE USING BLOCK-BASED TRANSLATION MODE - Methods and systems are disclosed, including a method for executing a non-native code stream on a computing system. The method includes forming one or more blocks of emulated mode code for execution on a computing system. Each of the one or more blocks includes a preamble and a plurality of operators ordered for execution in a predetermined sequence, wherein for a specified block the preamble defines one or more conditions required for uninterrupted execution of the operators included in the specified block. The method also includes assessing the one or more conditions associated with the specified block, and, after assessing the one or more conditions, executing each of the operators included in the specified block without assessing any of the one or more conditions between execution of the operators within the specified block. | 04-11-2013 |
| 20130096907 | EMPLOYING NATIVE ROUTINES INSTEAD OF EMULATED ROUTINES IN AN APPLICATION BEING EMULATED - Processing within an emulated computing environment is facilitated. Code used to implement system-provided (e.g., standard or frequently used) routines referenced in an application being emulated is native code available for the computing environment, rather than emulated code. Responsive to encountering a reference to a system-provided routine in the application being emulated, the processor is directed to native code, rather than emulated code, even though the application is being emulated. | 04-18-2013 |
| 20130096908 | EMPLOYING NATIVE ROUTINES INSTEAD OF EMULATED ROUTINES IN AN APPLICATION BEING EMULATED - Processing within an emulated computing environment is facilitated. Code used to implement system-provided (e.g., standard or frequently used) routines referenced in an application being emulated is native code available for the computing environment, rather than emulated code. Responsive to encountering a reference to a system-provided routine in the application being emulated, the processor is directed to native code, rather than emulated code, even though the application is being emulated. | 04-18-2013 |
| 20130103380 | SYSTEM AND METHOD FOR CONTROLLING MULTIPLE COMPUTER PERIPHERAL DEVICES USING A GENERIC DRIVER - A method for controlling a peripheral hardware device connected to a computer system is disclosed, the computer system includes an operating system, acting as the host operating system, running on a processor platform, and a generic device driver configured to operate on the combination of the operating system and a processor platform. The peripheral hardware device is delivered with an original peripheral hardware device driver file written for at least one of another operating system and a another processor platform, handling, by the generic device driver, interfaces between the operating system, the peripheral hardware devices and a software application. These are configured to interact with the original peripheral device driver file, and emulating, by the generic device driver, at least a part of the another operating system and the another processor that are required for the peripheral hardware device to operate on the operating system and the processor. | 04-25-2013 |
| 20130132061 | JUST-IN-TIME STATIC TRANSLATION SYSTEM FOR EMULATED COMPUTING ENVIRONMENTS - A computing system and method of executing a software program and translation of instructions for an emulated computing environment. The computing system includes a programmable circuit capable of executing native instructions of a first instruction set architecture and incapable of executing non-native instructions of a second instruction set architecture. The emulator operates within an interface layer and translates non-native applications hosted within an emulated operating system for execution. The computing system includes translated memory banks defined at least in part by the emulated operating system and capable of native execution on the programmable circuit, where the emulated operating system is incapable of execution on the programmable circuit. The computing system includes a linker configured to manage association of at least one of the one or more translated memory banks to the interface layer for native execution by the programmable circuit in place of a corresponding bank of non-native instructions. | 05-23-2013 |
| 20130132062 | CPU EMULATION SYSTEM, CPU EMULATION METHOD, AND RECORDING MEDIUM HAVING A CPU EMULATION PROGRAM RECORDED THEREON - A CPU emulation system includes; a plurality of virtual CPUs each operating on a different physical CPU; an instruction sequence selecting section for selecting an instruction sequence to be optimized; a virtual CPU selecting section for selecting one of the plurality of virtual CPUs, which is to perform optimization processing of the selected instruction sequence, based on usage rates of the plurality of virtual CPUs; and an optimization level selecting section for determining an optimization level of the optimization processing that is to be executed by the selected one of the plurality of virtual CPUs, and giving a direction to perform the optimization processing to the selected one of the plurality of virtual CPUs. | 05-23-2013 |
| 20130231913 | Self Initialized Host Cell Spatially Aware Emulation of a Computer Instruction Set - A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed | 09-05-2013 |
| 20130275114 | COORDINATION SIMULATION SYSTEM AND COORDINATION SIMULATION METHOD - A coordination simulation system, in which a system simulator including a plant model and a CPU simulator that controls by a microcomputer model are configured via a feedback loop, comprises a synchronization adapter that synchronizes the system simulator and the CPU simulator, wherein the synchronization adapter is provided with a function that provides alignment information per control cycle to the microcomputer model in accordance with a synchronizing signal generated in the plant model. | 10-17-2013 |
| 20140006002 | EMULATION TIME CORRECTION | 01-02-2014 |
| 20140032205 | JAVA PROGRAM FOR EMULATING THE MEMORY MANAGEMENT OF A C PROGRAM AND CORRESPONDING METHOD - Certain example embodiments relate to a computer program written in the programming language Java for emulating the memory management of a computer program written in the programming language C. The C program includes instructions for allocating a memory area, instructions for defining at least one data structure, and instructions for defining at least one pointer to the allocated memory area in accordance with the at least one data structure. The Java program may include instructions for: providing a Java byte array for emulating the allocated memory area of the C program; and providing at least one Java object for emulating the at least one data structure of the C program. The at least one Java object uses at least one Java ByteBuffer object for emulating the at least one pointer of the C program. | 01-30-2014 |
| 20140046649 | ISA BRIDGING INCLUDING SUPPORT FOR CALL TO OVERIDDING VIRTUAL FUNCTIONS - Methods, apparatuses and storage medium associated with ISA bridging with support for virtual functions, are disclosed. In embodiments, at least one computer-readable storage medium may include instructions configured to enable a target device with a target ISA, in response to execution, to provide an ISA bridging layer to the target device to facilitate a library service of a library of the target device to call a virtual function of the library, while servicing an application operating on the target device, where the application has an overriding implementation. The ISA bridging layer may include a loader configured to load the application for execution, and as part of loading the application, detect the virtual function and modify a virtual function table of the application to enable the call. Other embodiments may be disclosed or claimed. | 02-13-2014 |
| 20140114641 | MULTI-FUNCTION INSTRUCTION THAT DETERMINES WHETHER FUNCTIONS ARE INSTALLED ON A SYSTEM - A method, system and program product for executing a multi-function instruction in an emulated computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query determines which optional functions of the one or more optional functions are installed on the computer system. | 04-24-2014 |
| 20140136179 | Page Mapped Spatially Aware Emulation of Computer Instruction Set - Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page. | 05-15-2014 |
| 20140249796 | SIMULATOR GENERATION METHOD AND APPARATUS - The present invention discloses a simulator generation method and apparatus, relating to the field of simulator generation, which are used to implement rapid portability and high efficiency of a simulator. The solutions in the present invention are applicable to simulator generation. | 09-04-2014 |
| 20140358515 | PRESERVING OBJECT CODE TRANSLATIONS OF A LIBRARY FOR FUTURE REUSE BY AN EMULATOR - Provided is a method of preserving object code translations of a library for future reuse by an emulator. A munmap( | 12-04-2014 |
| 20150019199 | COMMAND LINE INTERFACE - Systems, apparatus and methods described herein are configured to receive a user command line instruction, of a first type, for transmission to a device and convert the user command line instruction to a device specific command line instruction. In some embodiments, the systems, apparatus and methods described herein are further configured to transmit the device specific command line instruction to the device, and convert a device specific response received from the device to a response of the first type. | 01-15-2015 |
| 20150081268 | INFORMATION PROCESSING SYSTEM, INFORMATON PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM PRODUCT - Disclosed is an information processing system having one or more computers. The information processing system includes a request receiver configured to receive a request from a program causing an apparatus to execute a predetermined process, a simulator configured to simulate the process executed by the apparatus in accordance with the request, an instruction receiver configured to receive a status change instruction for changing a status of the simulator from a user, and a status changer configured to cause the simulator to change a status of the simulator in accordance with the status change instruction. In the information processing system, the simulator simulates the process executed by the apparatus in the status changed by the status changer. | 03-19-2015 |
| 20150355920 | SYSTEM AND METHODS FOR GENERATING AND MANAGING A VIRTUAL DEVICE - Embodiments of the present disclosure may be configured to permit development and validation of a device driver or a device application program by using improved virtual devices. Such improved virtual devices may facilitate driver development without use of physical devices or hardware prototypes. In various embodiments, advanced validation of a device-driver combination may be permitted that would be difficult to achieve even with a physical device. Certain embodiments also may detect inconsistencies between virtual and physical devices, which may be used to improve drivers and device application programs and increase compatibility of such drivers and device application programs with physical devices. | 12-10-2015 |
| 20150370584 | COMPUTER SYSTEM AND PROGRAM - Provided is a computer system in which computer environments | 12-24-2015 |
| 20150379169 | EFFICIENT EMULATION FOR PSEUDO-WRAPPED CALLBACK HANDLING IN BINARY TRANSLATION SOFTWARE - Systems and methods may provide efficient emulation for pseudo-wrapped callback (PWC) handling in binary translation software. The systems and methods may provide a process virtual machine (PVM) that includes an ISA emulator and PVM runtime configured to identify a target ISA wrapper (TW) as a unique representation of the target ISA code (TB), install an additional translation index entry that directly maps an Instruction Pointer (IP) for TW to a translation of a source ISA code B (SB). The PVM may also an emulation “fast path” that allows the emulation to bypass the trapping of TW and jump to SB's emulation without breaking the emulation flow (e.g., in instances where SB's translation is already available). The PVM may thereby improve performance by removing the context switch from the executor to the PVM runtime for PWC callback emulation. | 12-31-2015 |
| 20160026482 | USING A PLURALITY OF CONVERSION TABLES TO IMPLEMENT AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE - A system for an agnostic runtime architecture is disclosed. The system includes a system emulation/virtualization converter, an application code converter, and a system converter wherein the system emulation/virtualization converter and the application code converter implement a system emulation process, and wherein the system converter implements a system conversion process for executing code from a guest image. The system converter further comprises a guest fetch logic component for accessing a plurality of guest instructions, a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling the plurality of guest instructions into a guest instruction block, and a plurality of conversion tables including a first level conversion table and a second level conversion table coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The system further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache, and in response to the hit the conversion look aside buffer forwards the translated native instruction for execution. | 01-28-2016 |
| 20160026486 | AN ALLOCATION AND ISSUE STAGE FOR REORDERING A MICROINSTRUCTION SEQUENCE INTO AN OPTIMIZED MICROINSTRUCTION SEQUENCE TO IMPLEMENT AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE - A system for an agnostic runtime architecture. The system includes a system emulation/virtualization converter, an application code converter, and a system converter wherein the system emulation/virtualization converter and the application code converter implement a system emulation process, and wherein the system converter implements a system conversion process for executing code from a guest image. The system converter further comprises an instruction fetch component for fetching an incoming microinstruction sequence, a decoding component coupled to the instruction fetch component to receive the fetched macro instruction sequence and decode into a microinstruction sequence, and an allocation and issue stage coupled to the decoding component to receive the microinstruction sequence perform optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. A microprocessor pipeline is coupled to the allocation and issue stage to receive and execute the optimized microinstruction sequence. A sequence cache is coupled to the allocation and issue stage to receive and store a copy of the optimized microinstruction sequence for subsequent use upon a subsequent hit on the optimized microinstruction sequence, and a hardware component is coupled for moving instructions in the incoming microinstruction sequence. | 01-28-2016 |
| 20160026487 | USING A CONVERSION LOOK ASIDE BUFFER TO IMPLEMENT AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE - A system for an agnostic runtime architecture. The system includes a system emulation/virtualization converter, an application code converter, and a converter, wherein a system emulation/virtualization converter and an application code converter implement a system emulation process. The system converter implements a system and application conversion process for executing code from a guest image, wherein the system converter or the system emulator accesses a plurality of guest instructions that comprise multiple guest branch instructions, and assembles the plurality of guest instructions into a guest instruction block. The system converter also translates the guest instruction block into a corresponding native conversion block, stores the native conversion block into a native cache, and stores a mapping of the guest instruction block to corresponding native conversion block in a conversion look aside buffer. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache, and forwards the converted native instruction for execution in response to the hit. | 01-28-2016 |
| 20160110209 | APPARATUS AND METHOD FOR PERFORMING MULTI-CORE EMULATION BASED ON MULTI-THREADING - The present invention relates to multi-core emulation, more specifically to a method and an apparatus for high-speed multi-core emulation using a multi-threading functionality of a computer. | 04-21-2016 |
| 20160170779 | DEVICE EMULATOR | 06-16-2016 |
| 20160179557 | EMULATED DEVICE FIRMWARE TESTABLE BY NATIVE OPERATING SYSTEM TOOLS | 06-23-2016 |
| 20160203009 | METHODS FOR EMULATING COMPUTING DEVICES AND DEVICES THEREOF | 07-14-2016 |
