| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 703019000 | Timing | 18 |
| 20080294415 | TROUBLESHOOTING TEMPORAL BEHAVIOR IN "COMBINATIONAL" CIRCUITS - A method and computer product is provided to generate a signal model for use in analyzing a model system including imposing an explicit time assumption for each time instant of the system model. The time assumptions are defined so that any two assumptions contradict each other, thereby separating all inferences into the respective times. A non-monotonic rule is applied to instantiate component models of the model system. Results are defined as not depending on the existence of a previous time instant and, a simplified signal model is generated, wherein the signal model represents the evolution of a value in the model system over time. | 11-27-2008 |
| 20080294416 | FACILITATING SIMULATION OF A MODEL WITHIN A DISTRIBUTED ENVIRONMENT - Simulation of models within a distributed environment is facilitated. A model is partitioned based on clock domains, and communication between partitions on different processors is performed on synchronous clock boundaries. Further, data is exchanged across the network on latch boundaries. Thus, management aspects of the simulation, such as management associated with the global simulation time, are simplified. | 11-27-2008 |
| 20080319730 | Method and Apparatus for Modifying a Virtual Processor Model for Hardware/Software Simulation - A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model. | 12-25-2008 |
| 20090319254 | CHARGE-BASED MILLER COEFFICIENT COMPUTATION - A method of estimating a Miller coefficient for an aggressor network and a victim network coupled by a coupling capacitor includes synthesizing a reduced order system from the aggressor network and the victim network, estimating an active area across the coupling capacitor for an aggressor induced noise signal based on the reduced order system, calculating an estimate of the Miller coefficient based on the active area of the aggressor induced noise signal, and outputting the calculated estimate of the Miller coefficient. | 12-24-2009 |
| 20100057429 | METHOD AND APPARATUS FOR PARALLELIZATION OF SEQUENTIAL POWER SIMULATION - One particular implementation takes the form of an apparatus or method for parallelizing a sequential power simulation of an integrated circuit device. The implementation may temporally divide the simulation so that separate time segments of the simulation can be run at the same time, thereby reducing he required time necessary to perform the power simulation. More particularly, a logic simulation may be performed on the integrated circuit and snapshots of the logic devices of the integrated circuit may be taken at a specified period. The separate time segments of the simulation may then be simulated in a parallel manner to simulate power consumption of the integrated circuit. Performing the power simulation on the separate time segments may reduce the required time of a typical power consumption simulation of an integrated circuit. | 03-04-2010 |
| 20100235158 | Automated System Latency Detection for Fabric Simulation - A configuration manager identifies a first device and a second device within a simulated system. Each device within the simulated system includes an inbound port and an outbound port. Next, the configuration manager injects a simulation only packet, at an “outbound time,” on the first device's outbound port and detects that the second device's inbound port receives the simulation only packet at an “inbound time.” As such, the configuration manager identifies a direct connection between the first device and the second device and computes a latency time for the connection. In turn, the configuration manager configures one or more first device configuration registers and one or more second device configuration registers based upon the computed latency time. | 09-16-2010 |
| 20110004456 | VIRTUAL NETWORK EMBEDDING METHOD IN WIRELESS TEST-BED NETWORK - Provided is a technology for providing an efficient embedding method in virtualizing a wireless test-bed network. In a virtual network embedding method in a wireless test-bed network, at least one packing point is generated in a two-dimensional strip comprised of time and frequency bandwidth, and the best virtual network slice according to the packing point is disposed. To dispose the virtual network slice, a set of packing points on the strip is collected, the suitability of the network slice according to each packing point is determined, and the network slice is disposed such that a left bottom point of the network slice is disposed at a suitable packing point. Accordingly, the length of a TDM super frame in the virtual test-bed network can be minimized. | 01-06-2011 |
| 20110015916 | SIMULATION METHOD, SYSTEM AND PROGRAM - A simulation system having multiple peripherals that communicate with each other. The system includes a weighted graph with weights set as communication times. The peripherals are represented as nodes and connection paths are represented as edges. Among the communication times in the loop, the minimum time is set as first synchronization timing. Timing with an acceptable delay added is set as second synchronization timing. Timing set by a user to be longer than the first and second timings is set as third synchronization timing. The third synchronization timing is used in a portion where the timing is usable, thus synchronizing the peripherals at the longest possible synchronization timing. | 01-20-2011 |
| 20110046937 | DELAY ANALYSIS PROCESSING OF SEMICONDUCTOR INTEGRATED CIRCUIT - A delay analysis device composed of a storage device and a data processing device analyzes a chip fabricating a semiconductor integrated circuit. Delay calculation is performed via an RC simulation with reference to a layout-implemented macro net list, macro layout data, and a cell timing library, thus producing macro delay information. An initial stage of a macro is annotated by the global clock path delay information including the edge information so as to produce a global clock delay-annotated macro net list, which is then converted into a macro delay-annotated net list. Based on the macro delay-annotated net list and timing constraint, the delay analysis device calculates delay times of signal paths and clock paths as well as clock skews with a high precision. It checks whether or not the relationship between the delay times of signal paths and clock paths meets the timing constraint, thus producing delay analysis information. | 02-24-2011 |
| 20110282641 | METHOD AND SYSTEM FOR REAL-TIME PARTICLE SIMULATION - A method and system for particle simulation are provided in which the number of particles is held as close as possible below a prescribed particle limit. When adding new particles to the simulation results in approaches the particle limit, new particles which contribute most to the visual quality of the simulation are added first, followed by deleting or merging existing particles which contribute least before adding the remaining new particles. Visual quality is also optimized by splitting particles into two or more new particles until the target particle count is reached. The criteria for performing insertions, deletions, splitting, or merging are governed by the results of predefined fitness functions by which the visual effect of each operation is estimated. | 11-17-2011 |
| 20110288847 | PREDICTING DATABASE SYSTEM PERFORMANCE - A prediction system may perform capacity planning for one or more resources of a database systems, such as by understanding how different workloads are using the system resources and/or predicting how the performance of the workloads will change when the hardware configuration of the resource is changed and/or when the workload changes. The prediction system may use a detailed, low-level tracing of a live database system running an application workload to monitor the performance of the current database system. In this manner, the current monitoring traces and analysis may be combined with a simulation to predict the workload's performance on a different hardware configuration. More specifically, performance may be indicated as throughput and/or latency, which may be for all transactions, for a particular transaction type, and/or for an individual transaction. Database system performance prediction may include instrumentation and tracing, demand trace extraction, cache simulation, disk scaling, CPU scaling, background activity prediction, throughput analysis, latency analysis, visualization, optimization, and the like. | 11-24-2011 |
| 20120065955 | Modeling Output Delay of a Clocked Storage Element(s) - Methods, apparatuses, systems, and computer-readable mediums for modeling output delay of a clocked storage element(s) are disclosed. An output delay model is employed that includes variations in the output delays for the clocked storage element over an operating range of the clocked storage element, including during transitions from transparent operation to non-transparent operation, and vice versa. Errors in the model output delay are reduced or avoided as a result. In one embodiment, the model output delay is determined for the clocked storage element as a function of the differential timing between the arrival time of a clock signal and input data to the clocked storage element. The differential timing allows determination of a model output delay from a plurality of model output delays representing a model output delay curve for the clocked storage element. Time borrowing can also be modeled automatically without the need for a second output delay model. | 03-15-2012 |
| 20120089385 | MEMORY MODELING METHODS AND MODEL GENERATORS - A memory modeling method is provided. According to the memory modeling method, a memory model is provided. The memory model includes an array unit, and the array unit includes an array declaration module and a calculation module. A virtual array is defined in a storage device by the array declaration module. The virtual array is configured to simulate a real memory. Further, according to the memory modeling method, an access instruction is received, and an access operation corresponding to the access instruction is performed to the virtual array, wherein the access operation is performed with a transaction level modeling method. Then, an access time or a delay time of the access operation according to the access instruction is estimated by the calculation module. | 04-12-2012 |
| 20120101798 | EFFICIENT CLOCK MODELS AND THEIR USE IN SIMULATION - Methods simulating a system of devices are described. A model that simulates the system is executed. The system model includes a plurality of modules. A clock object for a module can be disabled when it is not needed or not being used. | 04-26-2012 |
| 20120221313 | PARALLEL FLIP-FLOP SETUP AND HOLD TIMING ANALYSIS - A computer aided design system determines the acceptable timing for a flip-flop cell. The system generates a search window having a pass edge and a fail edge and divides the search window into four sections using three quadsection values. For each of the quadsection values, the system simulates a timing analysis of the flip-flop and determines if each of the quadsection values pass or fail the analysis. The analysis may be done in parallel. If at least one of the quadsection values passes the analysis, the system causes one of the passed quadsection values to be a new pass edge for the search window. If at least one of the quadsection values fails the analysis, the system causes one of the failed quadsection values to be a new fail edge for the search window. If the search window is less than a predetermined window width, the system assigns the new pass edge as the determined timing. If the search window is not less than the predetermined window width, the system repeats the above, starting with dividing the new search window into four sections using three quadsection values. | 08-30-2012 |
| 20130096903 | SIMULATION APPARATUS AND SIMULATION METHOD - A simulation apparatus includes: operations of: dividing code of a program in a target processor into blocks; setting an execution result of an externally-dependant instruction depending on an external environment as a prediction result; carrying out function simulation based on the prediction result; calculating an execution time of the externally-dependant instruction according to instruction execution timing information and a function simulation result; generating host code which makes a host processor execute performance simulation based on the function simulation result: correcting the execution time of the externally-dependant instruction based on a delay time of the externally-dependent instruction and a execution time of an instruction executed before or after the externally-dependent function if an execution result of the externally-dependent function when the host processor executes the host code differs from the prediction result; and setting a corrected execution time of the external-dependent instruction as the execution time of the externally-dependant instruction. | 04-18-2013 |
| 20130218549 | DYNAMIC TIME VIRTUALIZATION FOR SCALABLE AND HIGH FIDELITY HYBRID NETWORK EMULATION - A system and method for measurement of the performance of a network by simulation, wherein time divergence is addressed by using discrete event simulation time to control and synchronize time advance or time slow down on virtual machines for large-scale hybrid network emulation, particularly where the loss of fidelity could otherwise be substantial. A dynamic time control and synchronization mechanism is implemented in a hypervisor clock control module on each test bed machine, which enables tight control of virtual machine time using time information from the simulation. A simulator state introspection and control module, running alongside the simulator, enables extraction of time information from the simulation and control of simulation time, which is supplied to the virtual machines. This is accomplished with a small footprint and low overhead. | 08-22-2013 |
| 20150066469 | DYNAMICALLY SELECTING MASTER CLOCK TO MANAGE NON-LINEAR SIMULATION CLOCKS - Systems and methods that efficiently simulate controlled systems are presented. A simulation management component (SMC) controls simulation of a controlled system by controlling a desired number of nodes, each comprising a controller (e.g., soft controller) and a simulated component or process, which are part of the controlled system. The simulation can be performed in a step-wise manner, wherein the simulation can comprise a desired number of steps of respectively desired lengths of time. For each step, the SMC dynamically selects a desired clock (e.g., currently identified slowest clock) as a master clock for the next step. The SMC predicts a length of time of the next step to facilitate setting a desired length of time for the next step based in part on the predicted length of time. As part of each step, components can synchronously exchange data via intra-node or inter-node connections to facilitate simulation. | 03-05-2015 |
