| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 703016000 | Event-driven | 38 |
| 20080208557 | SIMULATION METHOD AND SIMULATION SYSTEM - A simulation executing unit | 08-28-2008 |
| 20080208558 | SYSTEM AND METHOD FOR SIMULATING A MULTIPROCESSOR SYSTEM - Disclosed are techniques for simulating a multiprocessor system is disclosed. Aspects of the present invention are based on such an observation that most memory accesses from different simulated processors do not conflict, and therefore the conservative policy for performing synchronization of all the memory accesses can waste a large amount of processing time. By identifying possibly conflicting memory accesses and only performing synchronization of these memory accesses, the synchronization cost can be reduced considerably. Since the function simulator is able to operate faster and to perform the same memory accesses, the possibly conflicting memory accesses can be identified by first executing the function simulator. | 08-28-2008 |
| 20080208559 | METHOD AND APPARATUS FOR FORMALLY CHECKING EQUIVALENCE USING EQUIVALENCE RELATIONSHIPS - An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLM | 08-28-2008 |
| 20080221853 | SIMULATING AND VERIFYING SIGNAL GLITCHING - A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals between the hardware design units. The simulation system includes a stimulation module with a set of drivers to input simulation patterns into the design units. Some inputs to software models are driven by the outputs of software models of another design unit. The stimulation module can monitor these signals driven by the software model but it is difficult for the stimulation module to directly drive these signals. The added glitch circuitry allows injection of errors into the simulated hardware by the stimulation module on signals that are not directly driven by the stimulation module but are driven by the outputs of hardware design units. | 09-11-2008 |
| 20080228461 | Method of Simulating a Complex System Including Scheduler Hierarchy, and Corresponding Storage Means and Computer Program Product - A method is provided for simulating a complex system including a scheduler hierarchy. The complex system includes at least one processor that executes a set of functions under the control of a hierarchical group of schedulers. The method includes a step of constructing an architectural model of the complex system comprising a hierarchical group of components, each of said components comprising an instance of an object class belonging to the group containing: a first class, known as the Processor class, which represents an abstract model of any processor included in the complex system, a second class, known as the Function class, which represents an abstract model of any function executed by the complex system; and a third class, known as the Scheduler class, which represents an abstract model of any scheduler. Each instance is initialised with at least one attribute that characterises the behaviour desired therefrom. | 09-18-2008 |
| 20080262819 | Programmable Logic Array for Schedule-Controlled Processing - The electronic data processing circuit targets the emulation of a logic function. The circuit includes a single clock providing time unit signals, a programmable synchronous logic array for processing values on a time unit basis, detection of internal or external value state changes known as events, programmer for state changes or event signals, processor for a series of scheduled times providing the logic array with scheduled time signals depending on the signals from the detection or the event programmer and the signals from the clock. The processor can determine subsequent scheduled times having delayed deadlines programmed by the programmer, depending on the signals from the detection or the programmer. The processing performed by the logic array is thus dependent on the series of scheduled times triggered by internal or external value state changes and by determination of the series of scheduled times. | 10-23-2008 |
| 20080281572 | INTEGRATED CIRCUIT (IC) DESIGN METHOD AND METHOD OF ANALYZING RADIATION-INDUCED SINGLE-EVENT UPSETS IN CMOS LOGIC DESIGNS - A logic design tool, a tool for analyzing soft error sensitivities in logic, and a program product for logic design. A particle generator simulates events likely to occur for a given operating environment. A pre-characterizer provides circuit block responses to simulated events. A circuit response simulator simulates events in a logic design and provides an indication of soft error sensitivity for the design. Based on the soft error sensitivity indication, the design may be modified to reduce the overall soft error sensitivity. | 11-13-2008 |
| 20080294413 | PROGRAM PRODUCT SUPPORTING PHASE EVENTS IN A SIMULATION MODEL OF A DIGITAL SYSTEM - According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase. | 11-27-2008 |
| 20080312896 | Optimal bus operation performance in a logic simulation environment - Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction. | 12-18-2008 |
| 20090006067 | STAGE EVALUATION OF A STATE MACHINE - The present invention provides a method a system for facilitating enhanced processing of state diagrams in a state diagram environment. The method may include top-down processing a current state in a state diagram environment; determining whether processing of the current state results in an exception event; and passing the exception event to a superstate that includes the current state when it is determined that the current state results in an exception event. The superstate may be made the current state and it may be determined whether the current state can handle the exception event. When it is determined that the current state cannot handle the exception event, it may be determined whether the current state has a second superstate that includes the current state. An error event may be output from the state diagram environment when it is determined that the current state does not have a second superstate. | 01-01-2009 |
| 20090006068 | SOFTWARE EXECUTING DEVICE AND CO-OPERATION METHOD - There is provided with a software executing device co-operating with a hardware circuit or a hardware simulator, including: a software executing unit configured to execute a software; an execution monitoring unit configured to monitor execution of the software by the software executing unit to sequentially obtain an execution state of the software; a determining unit configured to determine whether the software executing unit and the hardware circuit or the hardware simulator are to be synchronized based on an obtained execution state of the software; and a synchronization controlling unit configured to control synchronization between the software executing unit and the hardware circuit or the hardware simulator. | 01-01-2009 |
| 20090012770 | CIRCUIT SIMULATION - A system, method, and apparatus select state variables for, build state equations of, and simulate time-domain operation of an electronic circuit. The circuit is modeled with three branch types (inductor, resistor, voltage source in series; capacitor, resistor, current source in parallel; and switch), including four pre-defined switch types (unidirectional unlatched, bidirectional unlatched, unidirectional latched, and bidirectional latched). Automated analyses determine efficient state variables based on the currently active circuit topology, and state equations are built and applied. Switching logic determines when switch states change, and state equations for the new topology are either drawn from a cache (if the topology has already been processed) or derived anew. The switch control signals may be combined into a single switching variable, defined as a function of the state output. | 01-08-2009 |
| 20090024379 | EVALUATION DEVICE - Evaluation by logic simulation can be favorably performed. A target packet determination part determines if a target packet which is a response packet that is to be transmitted with respect to a request packet that is received is in a simulation result table. When there is a target packet, a response packet output reads out and transmits the target packet from the simulation result table. On the other hand, when there is no target packet, a system controller forces a logic simulator to perform logic simulation regarding the received request packet, disconnects a connection with an opposing connection device, so as to perform reconnection after completion of the logic simulation by the logic simulator. A table generating part writes the request packet and the response packet obtained by the logic simulator into the simulation result table, the request packet and the response packet being made correspondent to each other. | 01-22-2009 |
| 20090030666 | Software Entity for the Creation of a Hybrid Cycle Simulation Model - Disclosed is a software entity for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs, optimized for simulation accuracy, or a mixture thereof. Utilizing a netlist tool extracting hierarchical design source components for use, the construction checks that all inputs and outputs of any hierarchical design source components bind, and employs Object Traversal Directives for incorporating the selected CDUs into the simulation model. A data management method is used for tracking the validity of the components in the model. Additionally, a software entity (FACDDR) permits high bandwidth simulation of design components normally requiring cycle accurate simulation. FACDDR provides linkages for standard logic elements for abstracting one or more design interface components out of a cycle simulation environment and design interface emulation of an interface which interacts with a cycle simulation model through an API to extract present value of driving side signals of an interface and to set the cycle simulation model on the receiving side. | 01-29-2009 |
| 20090043559 | Hardware Verification Batch Computing Farm Simulator - The exemplary embodiments provide a computer implemented method, apparatus, and computer usable program code for calculating the expected behavior of a group of hardware verification test cases. Batch simulation parameters are configured. A test case is submitted for evaluation. Historical performance data for test cases associated with the submitted test case is gathered. A set of performance statistics for the submitted test case is generated based on the historical performance data and the configured batch simulation parameters. A set of values for the submitted test is generated based on the generated performance statistics for the submitted test case and the historical performance data. The generated set of values and the generated set of performance statistics for the submitted test case are displayed to a user. | 02-12-2009 |
| 20090048818 | SIMULATION METHOD OF LOGIC CIRCUIT - A simulation method of a logic circuit is provided. The simulation method includes operations dividing the logic circuit into a plurality of divided circuits, determining the divided circuit constructing a path circuit of the logic circuit, determining an auxiliary divided circuit that is the divided circuit not constructing the path circuit and affects on a simulation result of the path circuit. The method also includes executing a simulation calculation of a part of the circuit including the divide circuit constructing the path circuit and the auxiliary divided circuit. | 02-19-2009 |
| 20090094014 | Software System For Binding Model Data To View Components - A flexible method of mapping view components to data model objects in an object oriented system. The mapping manages navigating the data model graph to access data needed by the view component and to listen for events indicating changes within the data model graph and relevant to the view component. This mapping is extremely flexible in that the component can elect to receive one result for one input, one result for each of many inputs, multiple results for one input, or multiple results for each of multiple inputs, and the association used in the mapping internalizes the event management required for keeping the component up to date with the latest changes in the mapped data model. | 04-09-2009 |
| 20090112558 | METHOD FOR SIMULTANEOUS CIRCUIT BOARD AND INTEGRATED CIRCUIT SWITCHING NOISE ANALYSIS AND MITIGATION - A method and a design structure. The method includes: generating a board model of a circuit board design; generating a impedance spectrum of the board model; generating a chip model of an integrated circuit chip design; performing a transient analysis of the chip model using an ideal board power supply to generate an initial chip noise signature; based on the transient analysis, adding noise generators to the board model to generate a modified board model and to generate a latest board power supply; performing an additional transient analysis of the chip model using the modified board model and the latest board power supply to generate a latest noise signature; determining if the latest noise signature is within a predetermined chip noise specification; and if the latest noise signature is not within the predetermined chip noise specification, adding at least one decoupling capacitor to the modified board model. | 04-30-2009 |
| 20090157376 | Techniques for Incorporating Timing Jitter and/or Amplitude Noise into Hardware Description Language-based Input Stimuli - Methods for generating waveforms with realistic transitions, controllable timing jitter, and controllable amplitude noise in a computer-based simulation environment are disclosed. A first method includes obtaining signal information for one or more parallel data signals. In one embodiment, signal information for the one or more parallel data signals is mapped from an HDL format to a new time scale, and during this operation, timing jitter is added independently to the parallel data signals. These jittery parallel data signals may then be returned to the original HDL format, or another format, for simulation. In another embodiment, rather than mapping to a single time vector, information from each signal is modified to have a time scale commensurate with noise and jitter to be added. Timing jitter is superimposed onto each transition, rise and fall times are incorporated, and missing voltage and timing information for each data signal is interpolated into vectors representing the signals. Each data signal may additionally be scaled to one or more true voltage values and filtered. Finally, amplitude noise is added to each signal, and one or more final signals are output to a desired format for simulation. | 06-18-2009 |
| 20090164198 | PARALLEL SIMULATION USING AN ORDERED PRIORITY OF EVENT REGIONS - In one embodiment, a plurality of kernels are provided. Each kernel may simulate a partition of a design under test. A plurality of event regions are provided. The regions may be in an ordered priority. Events for the device under test may be determined for event regions in each of the kernels. An event region to execute events in is then determined and all kernels may execute events in the same event region. Kernels then execute events for the determined event region. When finished executing events in the event queue, data synchronization may occur. In this case, information may be synced among kernels, such as status and state values for shared objected are synchronized. | 06-25-2009 |
| 20090171646 | METHOD FOR ESTIMATING POWER CONSUMPTION - A method for determining system and software configuration that includes: calculating a power consumption estimate of a modeled system associated with an execution of a certain software code; and altering, in response to the power consumption estimate, the certain software code or the modeled system. A method of determining a power consumption of a system that executed a software code, the method includes the stages of: providing a reduced instruction set representation of the software code; and calculating a power consumption estimate of a modeled system associated with an execution of the reduced instruction set representation of the software code. | 07-02-2009 |
| 20090192777 | Method for Estimating a Noise Generated in an Electronic System and Related Method for Testing Noise Immunity - The invention concerns a method for testing immunity to noise derived from interferences between components in a mixed analogic and digital electronic system. The method comprises determining by simulating the highest-level noise observed in the system, or the worst noise generated by interferences. If a test for noise sensitivity is successful with this injected worst noise, then the system is accepted. In the case where the worst noise test fails, the method comprises calculating by simulating the lowest-level noise observed in the system, or the injected best noise. If a test for noise sensitivity fails with this injected best signal, then the system is rejected. | 07-30-2009 |
| 20090222253 | System and Method for Switch-Level Linear Simulation Using Verilog - A method for rapidly simulating combined analog circuits and digital circuits includes separating the combined circuits into a linear sub-network and logic sub-network. Shared nodes, shared by the linear sub-network and logic sub-network, are identified. The values of the shared nodes represent logic state values, or digital values, in the logic sub-network, and represent voltages, currents, control inputs and/or circuit parameters in the linear sub-network. Operation of the logic sub-network is simulated using logic node values for the shared nodes. Operation of the linear sub-network is simulated using linear node values for the shared nodes. The method allows fast simulation and rapid revision of mixed signal designs, saving design time and computing resources. | 09-03-2009 |
| 20090240484 | SIMULATION APPARATUS, SIMULATION METHOD, AND PROGRAM - A simulation apparatus that performs simulation of design data of a verification target circuit including a logic circuit that operates as a multi-cycle path of N cycles in synchronization with a clock signal, the simulation apparatus includes a design data generation section that generates design data of a multi-cycle verification circuit for selectively providing an undefined value signal in place of a signal in a multi-cycle part in the verification target circuit; a logical simulation section that performs logical simulation, without delay, on the basis of design data of the verification target circuit and the design data of the multi-cycle verification circuit; and a comparison section that compares the signal of the verification target circuit with a signal of an expected value in the verification target circuit in the logical simulation. | 09-24-2009 |
| 20090248387 | Method and apparatus for sampling and predicting rare events in complex electronic devices, circuits and systems - The invention provides methods for enhancing circuit reliability under statistical process variation. For highly replicated circuits such as SRAMs and flip flops, a rare statistical event for one circuit may induce a not-so-rare system failure. To combat this, the invention discloses the method called “Statistical Blockade,” a Monte Carlo-type technique that allows the efficient filtering—blocking—of unwanted samples insufficiently rare in the tail distributions of interest, with speedups of 10-100×. Additionally, the core Statistical Blockade technique is further extended in a “recursive” or “bootstrap” formulation to create even greater efficiencies under a much wider variety of circuit performance metrics, in particular two-sided metrics such a Data Retention Voltage (DRV) which prior Monte Carlo techniques could not handle. | 10-01-2009 |
| 20090248388 | SELECTIVELY REDUCING THE NUMBER OF CELL EVALUATIONS IN A HARDWARE SIMULATION - An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulation time. | 10-01-2009 |
| 20090299721 | APPARATUS AND METHODS FOR MODELING POWER CHARACTERISTICS OF ELECTRONIC CIRCUITRY - Apparatus and methods for calculating power consumption of circuitry within integrated circuits (ICs), such as programmable logic devices (PLDs) are disclosed and described. A method of estimating power consumption of a circuit in an IC includes decomposing the IC into a plurality of overlapping blocks. Each block in the plurality of blocks includes a portion of the circuitry in the IC. The method further includes estimating power consumption of each block in the plurality of blocks, and estimating power consumption of the IC based on the power consumption of the plurality of blocks. | 12-03-2009 |
| 20090319253 | FPGA Simulated Annealing Accelerator - Iterative repair problems are generally solved using a combinatorial search method such as simulated annealing are addressed with a FPGA-based coarse-grain pipelined architecture to accelerate a simulated annealing based iterative repair-type event scheduling application. Over 99% of the work done by any simulated annealing algorithm is the repeated execution of three high-level steps: (1) generating, (2) evaluating, and (3) determining the acceptability of a new problem solution. A pipelined processor is designed to take advantage of these steps. | 12-24-2009 |
| 20090326903 | SOFTWARE CONTROLLED LAB-ON-A-CHIP EMULATION - A software-controlled chemical process emulation system and environment having individually-addressable and/or group-addressable software-controlled chemical system processing modules, software-controlled chemical system handling modules, and related components. The software-controlled modules may be designed and interconnected to emulate various fixed, configurable, and reconfigurable “Lab-on-a-Chip” (“LoC”) devices. The software-controlled modules may be designed as separate units with well-defined ports and interfaces that can be used in the construction of larger systems. Alternatively, the software-controlled modules may be integrated into more complex subsystems that can be used in similar or other ways. These aspects may be used to design a LoC device, develop software for the operation of a LoC device, or may be used together with actual LoC devices as part of a larger system. Some applications may be used to implement laboratory automation features in experimental set-ups and laboratory-scale chemical production. | 12-31-2009 |
| 20100070257 | Methods, Systems, and Computer Program Products for Evaluating Electrical Circuits From Information Stored in Simulation Dump Files - Disclosed are methods, systems, and computer program products for evaluating performance aspects of electrical circuits, and particularly digital logic circuits. An exemplary method comprises obtaining access to a simulation dump file comprising state indications of the values of a plurality of signals of an electrical circuit at a plurality of simulation time points, and receiving an evaluation task that defines an output based on one or more input signals, with each input signal being a signal for which state indications are provided in the simulation dump file. The method further comprises generating, from the simulation dump file, one or more state representations for the input signals of the evaluation task, with each state representation being representative of the state of an input signal over a period of simulation time, and generating values of the output of the evaluation task at a plurality of simulation time points from the state representations. | 03-18-2010 |
| 20100169065 | SIMULATING LOSS OF LOGIC POWER STATE DUE TO PROCESSOR POWER CONSERVATION STATE - In general, in one aspect, the disclosure describes creation of a randomization list that includes only a subset of the logic states of an integrated circuit (IC). The subset being selectable by signal so as to define logic states that can be randomized for specific events. The randomization list is during simulation to randomize the logic states defined therein to simulate a specific event occurring during operation of the IC. For example, the randomization list may include those signals that can be randomized upon exiting from a powered down state (e.g., deep power down, C6). The signals that can be randomized may be defined by excluding the signals that cannot be randomized (those still receiving power in the C6 mode). The contents of registers of the IC can be confirmed after the randomization and exit from the C6 mode. | 07-01-2010 |
| 20100280814 | LOGIC SIMULATION AND/OR EMULATION WHICH FOLLOWS HARDWARE SEMANTICS - Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure that the simulation follows hardware semantics by properly handling race conditions in state elements and/or glitches in clock trees that can occur during logic simulation. Each logic simulation cycle can include two stages: a stimuli application stage in which the system evaluates signal values of the circuit design which do not depend on a clock signal, and a clock propagation stage in which the system evaluates signal values that depend on a clock signal. Some embodiments of the present invention sample signal values during the stimuli application stage, and use the sampled signal values during the clock propagation stage to handle race conditions in state elements and/or glitches in clock trees that may occur during logic simulation. | 11-04-2010 |
| 20110178789 | RESPONSE CHARACTERIZATION OF AN ELECTRONIC SYSTEM UNDER VARIABILITY EFFECTS - A method and device for performing a characterization of a description of the composition of an electronic system in terms of components used are disclosed. Performances of the components are described by at least two statistical parameters and one deterministic parameter. In one aspect, the method includes selecting a plurality of design of experiments (DoE) points, performing simulations on the selected DoE points, thus obtaining system responses, and determining a response model using the selected DoE points and the system responses. Selecting the DoE points includes making a first selection of a reduced set of chosen DoE points for the statistical parameters representing the statistical properties of the many possible statistical parameter realizations, and making a second selection of DoE points for the deterministic parameter representing the possible limited set of values that such parameter can take. | 07-21-2011 |
| 20110218791 | System for Simulating Processor Power Consumption and Method of the Same - The present invention provides a method for simulating processor power consumption, the method comprises: simulating a simulated processor; utilizing a power analysis model to analyze the simulated processor's execution of at least one fragment of a program, for generating power analysis of a plurality of basic blocks of the at least one fragment; computing at least one power correction factor between the plurality of basic block; utilizing a processing apparatus to generate a simulation model with power annotation based on the power analysis and the at least one power correction factor; and predicting power consumption of the simulated processor based on the simulation model with power annotation. | 09-08-2011 |
| 20110218792 | Mixed Concurrent And Serial Logic Simulation Of Hardware Designs - A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second modules for simulation by a concurrent simulation engine. The first and second modules can be prioritized for simulation based on classes of events consistent with an execution model of the HDL. Simulations of the serial and concurrent simulation engines can be synchronized for each class of events. Synchronizing can include transferring updated interface variable values, which are shared by the second modules and at least a subset of the first modules, between the serial simulation engine and the concurrent simulation engine. This transferring can include translating representations of the updated interface variable values. | 09-08-2011 |
| 20110224965 | Modeling Loading Effects of a Transistor Network - A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element. | 09-15-2011 |
| 20120215516 | IR Drop Analysis in Integrated Circuit Timing - In one embodiment, an IR drop analysis methodology may include characterizing standard cells without including power parasitic impedances, extracting the power parasitic impedances for the standard cells, and characterizing the standard cells with the power parasitic impedances. A set of timing parameters (such as minimum delays and maximum delays through the cells) may be generated from each characterization. The methodology may include comparing the timing parameters from each characterization, and identifying cells for which additional design effort should be expended to improve the power supply grid (e.g. to reduce the power parasitic impedances). For example, a margin may be budgeted for speed loss (delay increase) due to IR drop. If the difference in the timing parameters exceeds the margin, additional design effort may be warranted. | 08-23-2012 |
| 20140156249 | MODELING A BUS FOR A SYSTEM DESIGN INCORPORATING ONE OR MORE PROGRAMMABLE PROCESSORS - Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload. | 06-05-2014 |
