| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 702119000 | Including program initialization (e.g., program loading) or code selection (e.g., program creation) | 85 |
| 20080234967 | Test Sequence Optimization Method and Design Tool - A method for defining a sequence of tests for testing a plurality of electronic devices including integrated circuits is disclosed. A reference group of devices is defined ( | 09-25-2008 |
| 20080255791 | INTERFACE TO FULL AND REDUCE PIN JTAG DEVICES - The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices ( | 10-16-2008 |
| 20080255792 | TEST SYSTEM AND COMPUTER PROGRAM FOR DETERMINING THRESHOLD VOLTAGE VARIATION USING A DEVICE ARRAY - A test system and computer program for measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The test system and computer program control a characterization array circuit that imposes a fixed drain-source voltage and a constant channel current at individual devices within the array. Another circuit senses the source voltage of the individual device within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically. | 10-16-2008 |
| 20080262778 | RECORDING MEDIUM, TEST APPARATUS AND PROGRAM - A recording medium recording thereon a program for a test apparatus including test modules that test devices under test is provided. The program includes: a common function provision program which is executed on a controller for controlling the test apparatus and provides a function common to each type of the test modules; and a plug-in processing program which is executed on the controller and plugs-in an individual function provision program for providing a function appropriate for the type of each of the test modules. | 10-23-2008 |
| 20080270064 | M1 Testable Addressable Array for Device Parameter Characterization - An integrated circuit device and device parameter characterization method are provided. The integrated circuit device has a padset with plurality of pads. The integrated circuit device also includes one or more arrays of devices under test, each of the one or more arrays disposed between two of the plurality of pads. The integrated circuit device further includes one or more n-bit decoders, each disposed between two of the plurality of pads and electrically coupled to a corresponding one of the one or more arrays. Each n-bit decoder comprises one or more outputs that deliver a defined voltage to each device under test in the corresponding one of the one or more arrays of devices under test. The integrated circuit device and corresponding electrical connections are implemented in a single level of metal. | 10-30-2008 |
| 20080270065 | AUTOMATED SIMULATION TESTBENCH GENERATION FOR SERIALIZER/DESERIALIZER DATAPATH SYSTEMS - Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers. | 10-30-2008 |
| 20080275662 | Generating transmission-code compliant test sequences - Disclosed herein are exemplary methods, apparatus, and systems for generating test sequences that can be used to evaluate high-speed circuit pathways. The disclosed methods, apparatus, and systems can be used, for example, in a printed circuit board or integrated circuit design flow to analyze signal integrity or other electrical behavior. For example, in one exemplary embodiment, a sequence of code words to be input on a circuit channel is determined in a nonrandom manner. In this embodiment, the sequence of code words complies with a transmission code (for example, the 8b10b transmission code) and is designed to cause the output voltage of the channel to be reduced during a time period in which the channel outputs a logic high value. | 11-06-2008 |
| 20080281545 | DETERMINING DIE TEST PROTOCOLS BASED ON PROCESS HEALTH - A method includes receiving a first set of parameters associated with a subset of a plurality of die on a wafer. A die health metric is determined for at least a portion of the plurality of die based on the first set of parameters. The die health metric includes at least one process component associated with the fabrication of the die and at least one performance component associated with an electrical performance characteristic of the die. At least one of the die is tested. A protocol of the testing is determined based on the associated die health metric. | 11-13-2008 |
| 20090037132 | Parallel Test System - A method and a system for defining groups of tests that may be concurrently performed or overlapped are provided. Channel-independent test groups are determined such that each group includes tests that the input/output channels may be utilized simultaneously without conflicts. The channel-independent test groups are divided into block-under-test (BUT) conflict test groups and total-independence test groups. The total-independence test groups may be performed concurrently. Performance of the BUT-conflict test groups may be overlapped such that the input/output channels are used concurrently, but the execution of the tests by the blocks of the device-under-test (DUT) is performed sequentially. | 02-05-2009 |
| 20090048800 | TEST INSTRUMENT NETWORK - A test instrument network for testing a plurality of DUTs includes a plurality of communicating script processors, the script processors being adapted to execute computer code; and a plurality of measurement resources controllable by the script processors in response to executed computer code, the measurement resources being adapted to test the DUTs. Each script processor and measurement resource may be arbitrarily assigned by the controller to one of at least two groups, only one script processor being assigned to be a master script processor, any other script processor being a slave script processor and any group not including the master script processor being a remote group. The master script processor is exclusively authorized to initiate code execution on any script processor in a remote group. Any slave script processor is only able to initiate operation of measurement resources in it own group. When a particular script processor is executing computer code, the master script processor may not initiate execution of computer code on a member script processor in the group of the particular script processor and may not initiate operation of a member measurement resource in the group of the particular script processor. | 02-19-2009 |
| 20090119054 | TEST EQUIPMENT, METHOD FOR LOADING TEST PLAN AND PROGRAM PRODUCT - The test equipment includes a memory to which a test plan consisting of a plurality of sub-test plans is loaded; and a controller that loads the test plan to the memory by the unit of the sub-test plan and supplies a test signal to the DUT by interpreting the loaded test plan. | 05-07-2009 |
| 20090187368 | Burn-In Tests To Produce Fabricated Integrated Circuits With Reduced Variations Due To Process Spread - An aspect of the present invention enables burn-in tests to reduce variations due to process spread in fabricated integrated circuits (IC). Fabricated ICs are classified into multiple categories based on performance characteristics (e.g., operational speed) indicative of the extent of process spread in the ICs. The ICs are subjected to burn-in tests, with the severity of stress parameters applied during a burn-in test being proportional to the performance characteristics. As a result, process spread exhibited by the ICs (post burn-in) is reduced. | 07-23-2009 |
| 20090222234 | Generating Worst Case Test Sequences For Non-Linearly Driven Channels - Various implementations of the invention provide methods and apparatuses for generating a test sequence for a driver and channel combination, wherein the driver is non-linear. In various implementations of the invention, a test sequence is generated that produces the worst or near worst error rate of the channel. With various implementations of the invention, voltage waves at the driver and impulse response waves of the channel are generated. In various implementations of the invention, the driver voltage waves and impulse response waves are simulated responses of the driver and channel to a digital signal input. With further implementations of the invention, receiver voltage waves are generated by combining the impulse response wave and the driver voltage waves. Subsequently, a test sequence is selected based upon the combined receiver voltage wave. | 09-03-2009 |
| 20090240457 | TESTING IN A HARDWARE EMULATION ENVIRONMENT - A system and method is disclosed for testing emulation boards in a hardware emulation environment. In one embodiment, test files can be maintained that identify a list of test commands. Such a list can be easily changed without recompiling. In another embodiment, the list of commands can be read by a first server. The commands can be passed (e.g., sequentially) to a second server associated with one or more emulator boards. The second server can ensure that the commands are executed on the specified emulator boards for testing the emulator boards. In yet another embodiment, a user can request a series of tests to be executed. The tests can be included in a list of test names. Each test name can correspond to a list of test commands associated with the test name. Thus, a first server can read a test name, read a file of test commands associated with the test name and pass the test commands to a second server to ensure the test commands are executed. | 09-24-2009 |
| 20090299678 | METHOD AND APPARATUS FOR DETERMINING A PRODUCT LOADING PLAN FOR A TESTING SYSTEM - A method for determining a loading plan for a testing system includes determining demand quotas for a plurality of devices to be processed through the testing system. Each demand quota specifies a number of required devices and an associated performance specification. A bin classification distribution for devices processed through the testing system is estimated. Each device has an associated product type. Each bin classification indicates a performance grade of the associated devices. A number of devices matching each performance specification exiting the testing system is estimated based on the bin classification distribution. A device loading plan specifying a count of devices for each of a plurality of the product types to be dispatched to the testing system to provide the estimated number of devices matching each performance specification exiting the testing system to substantially meet the demand quota associated with each performance specification is determined. | 12-03-2009 |
| 20090299679 | Method of Adaptively Selecting Chips for Reducing In-line Testing in a Semiconductor Manufacturing Line - A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs. | 12-03-2009 |
| 20090299680 | System and method for message-queue-based server testing - A system for testing a banking transactions server. The system includes a storage medium storing a plurality a simulated banking transactions. The system also includes a script engine executing on a processor. The system also includes a plurality of templates useable by the script engine. The script engine tests a banking transactions server by transmitting a series of simulated banking transactions to a message queue on the banking transactions server. There is also a method including storing a plurality a simulated banking transactions in a storage medium. The method also includes executing a script engine on a processor. The method also includes testing a banking transactions server by transmitting a series of simulated banking transactions to a message queue on the banking transactions server. | 12-03-2009 |
| 20090326854 | TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS - A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence. | 12-31-2009 |
| 20100042353 | SYSTEM AND METHOD FOR TESTING WORKING CONDITION OF LED INDICATORS ON HARD DISK DRIVES - A method is provided to test working condition of LED indicators on hard disk drives connected to a computer. The method calls an API function from an operating system of the computer to create a main thread, and creates a sub thread for each of the hard disk drives connected to the computer using the main thread. The method further activates an LED indicator on each of the hard disk drives by interchanging data between the hard disk drive and the computer according to the sub thread. In addition, the method determines whether the LED indicator is workable by checking a working state of the LED indicator on each of the hard disk drive drives, and generates a working condition report for the LED indicator on each of the hard disk drives by integrating the determination results. | 02-18-2010 |
| 20100070230 | INTEGRATED TESTING SYSTEMS AND METHODS - An exemplary method includes parsing data representative of an automated test case into at least one transaction defined in accordance with a global test language, translating the transaction into at least one command specific to an automated test tool, and providing the command to the automated test tool for execution. In certain examples, the method further includes parsing the data representative of the automated test case into at least one other transaction defined in accordance with the global test language, translating the other transaction into at least one other command specific to another automated test tool, and providing other command to the other automated test tool for execution. | 03-18-2010 |
| 20100082283 | TESTING DEVICE FOR PORTABLE ELECTRONIC DEVICES - A testing device for portable electronic devices includes a processor storing test programs corresponding to various portable electronic devices, a control module connected to the processor, and a testing apparatus connected to the control module and connecting to tested portable electronic devices. The processor directs the control module and the testing apparatus to test portable electronic devices according to predetermined test programs in a main control mode, and the control module cooperates with the testing apparatus to test portable electronic devices and directs the processor to select test programs according to the tested portable electronic device in a subsidiary control mode. | 04-01-2010 |
| 20100153053 | Stream Based Stimulus Definition and Delivery via Interworking - An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor. | 06-17-2010 |
| 20100235135 | General Purpose Protocol Engine - In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table. | 09-16-2010 |
| 20100312517 | Test Method Using Memory Programmed with Tests and Protocol To Communicate between Device Under Test and Tester - In an embodiment, a test method is implemented to test an integrated circuit that includes at least one processor. The method may include programming a memory to which the integrated circuit is coupled during testing with one or more test programs. The integrated circuit may be booted, and the processor may execute the test programs from the memory. In one embodiment, the memory may also store a control program that may manage the execution of the tests. In an embodiment, the control program may also implement a protocol to communicate with the ATE to perform the testing. The protocol may be implemented over a set of general purpose input/output (I/O) pins, for example. Using the protocol and test vectors on the ATE, the tests may be selected and executed, and test results may be reported. | 12-09-2010 |
| 20100324855 | SYSTEMS AND METHODS FOR REMOTE ELECTRONICS DEVICE TESTING - Testing systems and methods are operable to perform diagnostic testing of a remote electronic device under test (DUT). An exemplary embodiment establishes a communication link between a diagnostic test device and the electronic DUT, receives a plurality of diagnostic commands from the electronic DUT, each of the plurality of diagnostic commands defined by at least one device diagnostic instruction (DDI) and a corresponding DDI description; generates a diagnostics script based upon selection of at least one of the diagnostic commands, wherein the generated diagnostics script includes at least one return device diagnostic instruction (RDDI) corresponding to the selected at least one diagnostic command; and transmits the at least one RDDI from the diagnostic test device to the DUT. | 12-23-2010 |
| 20110035178 | SYSTEM AND METHOD FOR GENERATING A TEST FILE OF A PRINTED CIRCUIT BOARD - A system and method generates a test file of a print circuit board (PCB). The system and method loads trace information of the PCB into a storage system of a test computer, searches the storage system for the trace information matching keywords received and selects traces to test from the searched results. The system and method further acquires length and test points of each selected trace, and sets test parameters of each test item. In addition, the system and method generates a test file of the PCB according to the test parameters, the length, and the test points of each selected trace. | 02-10-2011 |
| 20110106482 | GENERATING A COMBINATION EXERCISER FOR EXECUTING TESTS ON A CIRCUIT - A first and second test templates are combined to a combination test template. The combination test template may be configured to execute the first and second test templates in combination, and based upon a definition. The combination test template may execute tests in sequential order, concurrently, a combination thereof or the like. The first test template may be configured to be executed by a single-core machine and may be transformed to a multi-core test template that is configured to be executed on a multi-core machine in parallel to other tests. By utilizing the disclosed subject matter, a reduction in overhead of executing the first and second test templates may be achieved; a predetermined interleaving may be performed and a user may control the manner in which the combination test template is executing the first and second test templates. Additionally, reuse of pre-silicon test templates in post-silicon stage may be achieved. | 05-05-2011 |
| 20110172945 | METHOD FOR MONITORING BURN-IN PROCEDURE OF ELECTRONIC DEVICE - A method for monitoring a burn-in procedure of an electronic device is performed by a host computer, an external storage device, and a display device. The external storage device stores the burn-in procedure and a monitor procedure. The host computer copies the monitor procedure to the at least one electronic device and activates the monitor procedure. The monitor procedure activates the burn-in procedure for the electronic device and determines a state of the burn-in procedure. The monitor procedure then outputs a monitor result corresponding to the state of the burn-in procedure into the display device. The display device displays the monitor result. | 07-14-2011 |
| 20110172946 | MULTIFUNCTIONAL DISTRIBUTED ANALYSIS TOOL AND METHOD FOR USING SAME - A multi-function, intelligent, distributed analysis test tool (MFDAT) suitable for performing maintenance on complex, 5 sophisticated electronic systems. MFDAT replaces ordinary test instruments such as spectrum analyzers, oscilloscopes, power meters, frequency counters and digital multimeters with modular virtual test instruments that perform the identical functions but use a single display and human interface. Setup | 07-14-2011 |
| 20110178757 | ERROR ASSESSMENT METHOD FOR TEST STIMULUS SIGNAL OF ANALOG TO DIGITAL CONVERTER - An error assessment method for a test stimulus signal of an analog to digital converter is disclosed. The method provides random uniform-distribution test signals for an analog to digital converter (ADC), derives the piecewise linearity relationship between the input signals and the output signals of the ADC and thus develops an error assessment method for a test stimulus signal of the ADC. The method is able to reduce the computational complexity but still accurate and effective, and thereby provides correct information of the test stimulus signals for testing the ADC to improve its correctness. | 07-21-2011 |
| 20110301907 | Accelerating Automatic Test Pattern Generation in a Multi-Core Computing Environment via Speculatively Scheduled Sequential Multi-Level Parameter Value Optimization - Systems and methods provide acceleration of automatic test pattern generation in a multi-core computing environment via multi-level parameter value optimization for a parameter set with speculative scheduling. The methods described herein use multi-core based parallel runs to parallelize sequential execution, speculative software execution to explore possible parameter sets, and terminate/prune runs when the optimum parameter value is found at a previous level. The present invention evaluates the design prior to the implementation of the compression IP so that it can define the configuration of DFT and ATPG to maximize the results of compression as measured by test data volume and test application time. | 12-08-2011 |
| 20120016619 | DELAY FAULT TEST QUALITY CALCULATION APPARATUS, DELAY FAULT TEST QUALITY CALCULATION METHOD, AND DELAY FAULT TEST PATTERN GENERATION APPARATUS - A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit. | 01-19-2012 |
| 20120041707 | COLD BOOT TEST SYSTEM AND METHOD FOR ELECTRONIC DEVICES - A cold boot test system and method can control an electronic device to perform a cold boot process to test whether the electronic device is operable. The method sets time parameters for a test period of the cold boot process, drives a data communication interface of a computer to generate a period control signal according to the time parameters, and sends the period control signal to a controller via the data communication interface. The method further transfers the period control signal to the electronic device by controlling a power switch to switch on and switch off, controls the electronic device to execute the cold boot process to generate test information correspondingly. In addition, the method obtains the test information from the electronic device, and displays the test information on a display screen of the computer upon the condition that the cold boot process is abnormal. | 02-16-2012 |
| 20120078566 | Network Test Conflict Checking - There is disclosed a system and method for network test conflict checking. The method may be performed by a network testing system and may be implemented as software. The method may include receiving user selected test features and user selected hardware for a network test. When receiving user selected features, incompatible features are made unselectable by reference to a feature database. A compatibility check is performed by referring to a hardware database and a feature database. Suggestive corrective changes may be provided to a user or automatically made to the selected features and/or selected hardware. The network test is written to hardware when the compatibility test is successful. | 03-29-2012 |
| 20120089360 | Algorithm Integrating System and Integrating Method Thereof - The present invention discloses an algorithm integrating system and an integrating method thereof. The algorithm integrating system comprises a receiving module, an analyzing module, and a processing module. The receiving module receives at least one test algorithm. The analyzing module is connected to the receiving module and analyzes the at least one test algorithm to obtain at least one basic element from the at least one test algorithm. The processing module is connected to the analyzing module and screen out the at least one non-duplicate basic element based on the at least one basic element. Then, the processing module integrates the at least one non-duplicate basic element and generates a testing module. | 04-12-2012 |
| 20120095718 | AUTOMATIC TESTING SYSTEM AND METHOD - An automatic testing system includes an equipment group and an electronic device. The equipment group includes plural equipments. The electronic device includes an input unit, a storage unit, a controller, an output unit and an integrated transmission interface. The input unit is used for inputting an instruction. The controller is electrically connected with the input unit and the storage unit for accessing the storage unit according to the instruction, thereby controlling and activating an automatic testing process and issuing a test command. The output unit is connected with the controller. The interface has a first terminal connected with the controller and a second terminal connected with the equipment group for integrating and transmitting the test command to at least one of the equipments of the equipment group, thereby allowing the equipment to perform the automatic testing process. | 04-19-2012 |
| 20120123727 | SELF-SERVICE CIRCUIT TESTING SYSTEMS AND METHODS - In one of many possible embodiments, an exemplary system includes a test management subsystem configured to provide a user portal to a user of a circuit provided by a service provider, the user portal including a tool enabling the user to select a signal loop for testing at least a section of the circuit, the signal loop being selected from a plurality of signal loop options. The system also includes a network management subsystem communicatively coupled to the test management subsystem, the network management subsystem being configured to receive data representative of the selection from the test management subsystem and instruct, based on the selection, a network device along the circuit to execute a loop-back mode. In certain embodiments, the selected signal loop defines a test pattern signal flow for testing a subsection of the circuit. | 05-17-2012 |
| 20120123728 | TESTING AN ELECTRONIC DEVICE - Disclosed embodiments relate to an electronic device including a processor and a machine-readable storage medium, which may include instructions for testing an electronic device, including instructions for executing an executable and instructions for signaling the executable to initiate a test on an electronic device. The machine-readable storage medium may also comprise instructions for receiving information from the executable about the test before the booting of an operating system on the electronic device and before the executable finishes executing. | 05-17-2012 |
| 20120136612 | HDMI DEVICE AND INTEROPERABILITY TESTING SYSTEMS AND METHODS - An exemplary system includes a High-Definition Multimedia Interface (“HDMI”) analyzer and an HDMI router-switch having one or more input ports connected to one or more HDMI source devices and output ports connected to the HDMI analyzer and one or more HDMI sink devices. The HDMI router-switch is configured to establish and disestablish HDMI connections between the HDMI source devices and the HDMI analyzer and HDMI sink devices. The system further includes a control subsystem configured to control the HDMI analyzer, the HDMI router-switch, the HDMI source devices, and the HDMI sink devices, wherein the control subsystem is configured to direct one or more of the HDMI analyzer, the HDMI router-switch, the HDMI source devices, and the HDMI sink devices to perform one or more operations to execute one or more automated HDMI test routines. Corresponding methods and systems are also disclosed. | 05-31-2012 |
| 20120136613 | EXTENSIBLE TESTING SYSTEM - A computer implemented system for testing electronic equipment where a plurality of types of systems can be tested using a single test specification. | 05-31-2012 |
| 20120158346 | IDDQ TESTING OF CMOS DEVICES - IDDQ testing of CMOS devices. An embodiment of a method includes applying a test pattern of inputs to a device, the device including one or more CMOS (Complementary Metal-Oxide Semiconductor) transistors, and obtaining current measurements for the device, each of the current measurements being a measurement of a current after applying an input of the test pattern to the device. A filter function is applied to the current measurements, applying the filter function including separating defect current values from the current measurements. The method further includes determining whether a defect is present in the device based at least in part on a comparison of the defect current values with a threshold value. | 06-21-2012 |
| 20120191400 | BUILT-IN SELF-TEST METHODS, CIRCUITS AND APPARATUS FOR CONCURRENT TEST OF RF MODULES WITH A DYNAMICALLY CONFIGURABLE TEST STRUCTURE - A testable integrated circuit chip ( | 07-26-2012 |
| 20120191401 | METHOD AND APPARATUS FOR GENERATING TEST PATTERNS FOR USE IN AT-SPEED TESTING - In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns. | 07-26-2012 |
| 20120191402 | FLEXIBLE STORAGE INTERFACE TESTER WITH VARIABLE PARALLELISM AND FIRMWARE UPGRADEABILITY - A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmable to provide test patterns for use in automated test equipment. The configurable IC includes a configurable interface core that is programmable to provide functionality of one or more protocol based interfaces for a device under test (DUT) and is programmable to interface with the DUT. The system also includes a connection configurable to couple the configurable IC to the DUT. | 07-26-2012 |
| 20120221283 | METHOD AND APPARATUS FOR DETERMINING A SUBSET OF TESTS - Methods and apparatuses are described for determining a small subset of tests that provides substantially the same coverage as the set of tests. During operation, a system (e.g., a computer system) can determine a set of tests by, for each object in a set of objects, selecting up to a pre-determined number of tests that provide test coverage for the object. Next, the system can determine a subset of tests by iteratively performing a loop, which can comprise: selecting a test in the set of tests; removing, from the set of objects, one or more objects that are covered by the selected test; and optionally removing, from the set of tests, one or more tests that do not cover any objects in the remaining set of objects. The system can terminate the loop after a termination condition is met and report the selected tests as the subset of tests. | 08-30-2012 |
| 20120221284 | ARCHITECTURE, SYSTEM, METHOD, AND COMPUTER-ACCESSIBLE MEDIUM FOR PARTIAL-SCAN TESTING - Exemplary method, computer-accessible medium, test architecture, and system can be provided for a partial-scan test of at least one integrated circuit. For example, it is possible to obtain a plurality of test cubes using a first combinational automatic test pattern generation (ATPG) and identify at least one flip-flop of the integrated circuit using the test cubes to convert to a non-scan flip-flop and facilitate the partial-scan test to utilize the cubes without a utilization of a sequential ATPG or a second combinational ATPG. | 08-30-2012 |
| 20120221285 | GENERAL PURPOSE PROTOCOL ENGINE - In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table. | 08-30-2012 |
| 20120226464 | SYSTEM AND METHOD FOR TESTING POWER SUPPLIES OF SERVER - A computing system connects to a server that comprises a plurality of power supplies. The computing system sends a power on command to one or more alternating current (AC) relays which are connected to the power supplies. Each of the one or more AC relays powers on the corresponding power supply according to the power on command The server starts if the all the power supplies are powered on. The computing system sends a power off command to each predefined AC relay to power off the power supply corresponding each predefined AC relay in sequence. An execution unit of the server tests application programs of the server when each power supply corresponding to the predefined AC relay has been powered off. A result of testing the server denotes if the server is abnormal when the power supply has been powered off. | 09-06-2012 |
| 20120239337 | SEMICONDUCTOR INTEGRATED CIRCUIT, TEST METHOD AND INFORMATION PROCESSING APPARATUS - A semiconductor integrated circuit includes a plurality of shift registers to which test patterns are supplied, a pseudorandom number generator configured to generate, based on the test patterns supplied to the shift registers, pseudorandom numbers utilized as masking information corresponding to output responses of the shift registers, a masking information inverter configured to invert, on receiving a first control signal, the masking information corresponding to the output responses of the shift registers indicated by the first control signal, and an initial value storage configured to store initial values of the pseudorandom numbers. In the semiconductor integrated circuit, the pseudorandom numbers generated by the pseudorandom number generator are, on receiving a second control signal, initialized with the initial values of the pseudorandom numbers stored in the initial value storage. | 09-20-2012 |
| 20120253731 | FUNCTIONAL ASIC VERIFICATION USING INITIALIZATION MICROCODE SEQUENCE - A method of wafer-level testing of a register programmable integrated circuit may be provided. The method may comprise transforming a microcode instruction and related data from an initializing processor format into tester format data, and applying the tester format data to the integrated circuit on a wafer. | 10-04-2012 |
| 20120253732 | METHOD AND SYSTEM FOR IMPLEMENTING PARALLEL EXECUTION IN A COMPUTING SYSTEM AND IN A CIRCUIT SIMULATOR - A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. | 10-04-2012 |
| 20120271586 | TESTING MODULE FOR GENERATING ANALOG TESTING SIGNAL TO EXTERNAL DEVICE UNDER TEST, AND RELATED TESTING METHOD AND TESTING SYSTEM THEREOF - A testing module for generating an analog testing signal for a device under test includes a control circuit, a core circuit, and a connector. The core circuit is coupled to the control circuit, and arranged to generate the analog testing signal under control of the control circuit. The connector is coupled to the core circuit, and arranged to receive the analog testing signal generated from the core circuit and output the received analog testing signal. In addition, a testing method for generating an analog testing signal for a device under test includes: generating the analog testing signal by utilizing a testing module with a connector; and outputting the analog testing signal through the connector. | 10-25-2012 |
| 20120310584 | AUTOMATED AND COORDINATED SIMULATION OF MULTIPLE CONCURRENT USER INTERACTIONS - A method and associated system are provided for testing components of a vehicle entertainment system, comprising: interconnecting, via a network, a server computer comprising media content, and a plurality of user computers comprising software and hardware via which the user can interact with the media content; loading a test agent component onto a first of the user computers; loading a first scenario file comprising a series of user entry events that emulate user entry actions via a user interface device of the first user computer; executing the user entry events of the first scenario file by the test agent to generate system events that would normally be generated by a user operating the first user computer to interact with media server; and responding to the first user computer, by the server computer, to the system events. | 12-06-2012 |
| 20120310585 | IN-FLIGHT ENTERTAINMENT SEAT END SIMULATOR - A system and method are provided for testing a vehicle entertainment (IFE) system, comprising: functionally replicating each of a plurality of IFE components selected from the group consisting of an aircraft interface unit, a content server unit, a network distribution unit, and a seat unit with a corresponding simulator unit model that simulates functions of the respective IFE component; providing each simulator unit model on a simulator server having a processor, the simulator server connecting to an IFE network that also connects at least one of actual or simulated seat units to at least one of actual or simulated content servers; providing a test controller that controls each simulator unit model; transmitting scenario information containing operation instructions to the simulator unit model; and executing the scenario information by the simulator unit model to perform operations corresponding to the operation instructions that cause the simulator unit model to communicate over the IFE network. | 12-06-2012 |
| 20130018624 | System For Manufacturing CablesAANM Bhatnagar; AnujAACI SunnyvaleAAST CAAACO USAAGP Bhatnagar; Anuj Sunnyvale CA USAANM McPeak; James L.AACI FremontAAST CAAACO USAAGP McPeak; James L. Fremont CA US - During manufacturing, devices under test may be tested at test stations. Test cables may be used to couple the test stations to the devices under test. To ensure that cables have been assembled properly, a test system may be used to convey test data through the cables. Status indictors in the cables can be activated using the test data. The test system may include a test board for performing loop-back tests. During testing, test data may be transmitted through the cable to the test board. The test board may convert the test data from a first format such as a Universal Serial Bus format to a second format such as a Universal Asynchronous Receiver Transmitter format. Test signals that have been received by the test board may be sent back to the cable to direct the cable to activate the status indicators. | 01-17-2013 |
| 20130030753 | TESTING SYSTEM AND METHOD USING SAME - A remote server in electronic communication with a data center for testing one or more different types of electronic devices and method automatically tests one or more electronic devices. The data center stores a plurality of test programs correspondingly designed to test different types of electronic device. The remote server download one or more specified test programs corresponding to the electronic devices from the data center according to an identification code of each electronic device. The remote server tests the electronic devices by running the corresponding test programs. | 01-31-2013 |
| 20130035891 | TEST PATTERN GENERATOR, METHOD OF GENERATING TEST PATTERN, AND COMPUTER READABLE STORAGE MEDIUM HAVING TEST GENERATION PROGRAM STORED THEREON - A second computing device determines whether or not a conflict occurs wherein at least two of a plurality of first computing devices set different request values to an input point to which a request value is to be set, based on the request value stored in the request value buffer. When it is determined by the second computing device that a conflict occurs wherein one of the plurality of first computing devices is about to set a request value different from a request value that is set to that input point by another first computing device, the one of the first computing devices stops setting the request value. This prevents any increase in the test pattern count due to parallel processing. | 02-07-2013 |
| 20130066580 | AUTOMATIC MEASURING METHOD AND APPARATUS FOR MEASURING CONNECTING LINES - An automatic measuring method for measuring connecting lines includes the steps of: S | 03-14-2013 |
| 20130096866 | Method And Apparatus For Designing A Custom Test System - Methods, apparatus, and computer readable media for designing a custom test system are described. Examples of the invention can relate to a method of generating test system software for a semiconductor test system. In some examples, a method can include obtaining a configuration of the semiconductor test system, the configuration including a description of a device under test (DUT) and a description of test hardware; and generating an application programming interface (API) specific to the configuration of the semiconductor test system, the API being generated based on the description of the DUT and the description of the test hardware, the API providing a programming interface between the test system software and the test hardware to facilitate testing of the DUT. | 04-18-2013 |
| 20130211769 | REDUCING POWER CONSUMPTION DURING MANUFACTURING TEST OF AN INTEGRATED CIRCUIT - Aspects of the invention provide for reducing power consumption during manufacturing testing of an IC. In one embodiment, aspects of the invention include a method for reducing power consumption during a manufacturing test of an integrated circuit (IC), the method including: providing a plurality of domains, each domain associated with a clock phase; grouping, based on each domain, a first plurality of scan chains into a first test group; grouping, based on each domain, a second plurality of scan chains into a second test group, wherein the grouping of the first test group and of the second test group includes determining which domains can be tested simultaneously; and performing the manufacturing test of the IC. | 08-15-2013 |
| 20130218507 | TESTING AN INTEGRATED CIRCUIT DEVICE WITH MULTIPLE TESTING PROTOCOLS - Various exemplary embodiments relate to an integrated circuit device that includes a plurality of input/output pins, device circuitry, a first testing protocol interface connected to the device circuitry and to the plurality of input/output pins, and a second testing protocol interface connected to the device circuitry and to the same plurality of input/output pins as the first testing protocol interface. The first testing protocol interface is configured to test the device circuitry with a first testing protocol, and the second testing protocol interface is configured to test the device circuitry with a second testing protocol. | 08-22-2013 |
| 20130231885 | TEST APPARATUS AND TEST MODULE - In order to shorten testing time, provided is a test apparatus that tests a device under test, comprising one or more test modules that each include a plurality of testing sections testing the device under test by exchanging signals with the device under test; and a control apparatus that controls operation of the testing sections. The control apparatus executes in parallel a plurality of test programs for testing the device under test, to control in parallel the operation of the testing sections assigned respectively to the test programs, and the testing sections test the device under test by exchanging signals in parallel with the device under test. | 09-05-2013 |
| 20130231886 | TEST APPARATUS AND TEST MODULE - In order to efficiently test a plurality of types of devices under test, provided is a test apparatus that tests a device under test, comprising one or more test modules that each include a plurality of testing sections testing the device under test by exchanging signals with the device under test; and a plurality of control apparatuses that control operation of the testing sections. In each of the one or more test modules, the plurality of testing sections are each allocated to one of the plurality of control apparatuses, and each of the control apparatuses is capable of executing a test program managed by a different user, and controls operation of the testing sections allocated thereto. | 09-05-2013 |
| 20130275074 | Generating Transmission-Code Compliant Test Sequences - Disclosed herein are exemplary methods, apparatus, and systems for generating test sequences that can be used to evaluate high-speed circuit pathways. The disclosed methods, apparatus, and systems can be used, for example, in a printed circuit board or integrated circuit design flow to analyze signal integrity or other electrical behavior. For example, in one exemplary embodiment, a sequence of code words to be input on a circuit channel is determined in a nonrandom manner. In this embodiment, the sequence of code words complies with a transmission code (for example, the 8b10b transmission code) and is designed to cause the output voltage of the channel to be reduced during a time period in which the channel outputs a logic high value. | 10-17-2013 |
| 20130304413 | COMPUTING DEVICE AND METHOD FOR TESTING ELECTROMAGNETIC COMPATIBLITY OF PRINTED CIRCUIT BOARD - An electromagnetic compatibility (EMC) testing system includes a layout information obtaining module, a script loading module, a script executing module, and a report generating module. The layout information obtaining module obtains layout information of a printed circuit board. The script loading module loads an EMC testing script which includes EMC rules. The script executing module executes the EMC testing script to determine whether the layout information of the printed circuit board complies with the EMC rules. The report generating module generates an EMC report describing whether the layout information of the printed circuit board complies with the EMC rules. | 11-14-2013 |
| 20130332101 | SERIAL DATA LINK MEASUREMENT AND SIMULATION SYSTEM - A serial data link measurement and simulation system for use on a test and measurement instrument presents on a display device a main menu having elements representing a measurement circuit, a simulation circuit and a transmitter. The main menu includes processing flow lines pointing from the measurement circuit to the transmitter and from the transmitter to the simulation circuit. The main menu includes a source input to the measurement circuit and one or more test points from which waveforms may be obtained. The simulation circuit includes a receiver. The measurement and simulation circuits are defined by a user, and the transmitter is common to both circuits so all aspects of the serial data link system are tied together. | 12-12-2013 |
| 20140032156 | LAYOUT-AWARE TEST PATTERN GENERATION AND FAULT DETECTION - Methods and apparatuses to generate test patterns for detecting faults in an integrated circuit (IC) are described. During operation, the system receives a netlist and a layout for the IC. The system then generates a set of faults associated with the netlist to model a set of defects associated with the IC. Next, the system determines a set of likelihoods of occurrence for the set of faults based at least on a portion of the layout associated with each fault in the set of faults. The system subsequently generates a set of test patterns to target the set of faults, wherein the set of test patterns are generated based at least on the set of likelihoods of occurrence associated with the set of faults. | 01-30-2014 |
| 20140046615 | Test Case Crash Recovery - A safe operating region of a complex integrated circuit may be determined by selecting an operating point for the integrated circuit (IC) at a first voltage and first frequency. A test program is executed by a central processing unit (CPU) comprised within the IC to test a portion of the IC. Communication activity between the IC and a host system is recorded to form a data log while the test program is being executed. A crash is detected by storing and examining the data log periodically, and assuming that the test program has crashed when any one of a predetermined set of crash conditions is detected during examination of the data log. The operating point may be iteratively changed and execution of the test program repeated while continuing to check for a crash until a crash is detected. | 02-13-2014 |
| 20140052403 | TEST SYSTEM AND TEST METHOD THEREOF - An embodiment of a test system is provided. The system includes an electronic device to be tested and a network connection device. The electronic device to be tested includes a central processing unit (CPU) and a first universal serial bus (USB) interface. The network connection device includes a LAN module coupled to a remote server via a LAN port, and a second USB interface. When the second USB interface of the network connection device is coupled to the first USB interface of the electronic device to be tested, the CPU of the electronic device to be tested obtains a specific program from the remote server via the LAN port and the LAN module of the network connection device according to a preboot execution environment (PXE) code from the network connection device. | 02-20-2014 |
| 20140074423 | BUILT-OFF TEST DEVICE AND TEST SYSTEM INCLUDING THE SAME - A built-off test (BOT) device includes a signal processing block, an output selection block and a signal control block. The signal processing block duplicates a test signal to apply a plurality of duplicated test signals to each of a plurality of devices under test (DUTs) through each of corresponding channels, and the signal processing block provides a plurality of decision signals based upon a plurality of test result signals received from each of the DUTs. The output selection block merges the decision signals as a final decision signal or sequentially outputs the decision signals as the final decision signal, in response to an output mode selection signal. The signal control block provides the test signal to the signal processing block or provides the final decision signal externally, in response to a first switching control signal. | 03-13-2014 |
| 20140156212 | METHOD AND APPARATUS FOR TESTING THE EXCITATION CHARACTERISTIC OF CURRENT TRANSFORMER - This disclosure relates to the field of current transformers, for testing the excitation characteristic of a current transformer is disclosed. The method comprise applying alternately positive and negative DC voltages across terminals of secondary winding of a CT to be tested and acquiring a secondary current; constructing a mathematical model of the relationship between the secondary current and a root mean square (rms) equivalent voltage at rated frequency of the CT from the relationship between a magnetic flux of a secondary winding iron-core of the CT and the rms equivalent voltage; and generating an excitation characteristic curve according to the mathematical model. The method and apparatus of the embodiments may test CTs requiring lower testing voltage as well as CTs with knee-point up to tens of kV by supplying a relatively low voltage and power, which makes the embodiments widely applicable. | 06-05-2014 |
| 20140195191 | VOLTAGE TESTING DEVICE AND METHOD FOR MEMORY - The disclosure provides a voltage testing device and a method. The voltage testing method includes following steps. The computer sets initial setting parameters for an oscillograph and a signal producer. The signal producer sends an initial pulse signal to an input terminal of a memory. The computer receives initial testing parameters of an output terminal of the memory and the initial voltage value of the input terminal sent by the oscillograph, and sends a current voltage offset and a current voltage undulating value to the control unit. The computer sends a current voltage value to the signal producer. The signal producer sends a current pulse signal to the input terminal. The oscillograph obtaining voltage values of the input and output terminals, produces two voltage waves, and sends the two voltage waves and the voltage values to the computer. The computer displays the two voltage waves and the voltage values. | 07-10-2014 |
| 20140207402 | EMBEDDED TESTER - A tester on a device under test to test component circuitry of the device under test, the tester comprising: logic configured with firmware to implement test circuitry comprising: protocol generators that are configurable to generate protocols; pattern generators that are configurable to provide test patterns that are drivable according to one or more of the protocols; and a system controller to select, in response to a program input, a test pattern and a protocol with which to test the component circuitry. | 07-24-2014 |
| 20140236525 | TEST ARCHITECTURE HAVING MULTIPLE FPGA BASED HARDWARE ACCELERATOR BLOCKS FOR TESTING MULTIPLE DUTS INDEPENDENTLY - Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components. | 08-21-2014 |
| 20140236526 | TESTER WITH MIXED PROTOCOL ENGINE IN A FPGA BLOCK - Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment comprises a system controller for controlling a test program, wherein the system controller is coupled to a bus. The tester system further comprises a plurality of modules also coupled to the bus, where each module is operable to test a plurality of DUTs. Each of the modules comprises a tester processor coupled to the bus and a plurality of configurable blocks communicatively coupled to the tester processor. Each of the configurable blocks is operable to communicate with an associated DUT and further operable to be programmed with a communication protocol for communicating test data to and from said associated device under test. | 08-21-2014 |
| 20140236527 | CLOUD BASED INFRASTRUCTURE FOR SUPPORTING PROTOCOL RECONFIGURATIONS IN PROTOCOL INDEPENDENT DEVICE TESTING SYSTEMS - A method for performing tests using automated test equipment (ATE) is presented. The method comprises obtaining a protocol selection for programming a programmable tester module using a graphical user interface (GUI). It further comprises accessing a configuration file associated with a protocol from a remote computer through a network. Subsequently, it comprises configuring a programmable tester module with a communication protocol for application to at least one device under test (DUT) using the configuration file. Finally, it comprises transmitting instructions to the programmable tester module for executing a program flow, wherein the program flow comprises a sequence of tests for testing the at least one DUT, and receiving results for those tests from the programmable tester module. | 08-21-2014 |
| 20140244204 | TESTER WITH ACCELERATION FOR PACKET BUILDING WITHIN A FPGA BLOCK - A method for testing using an automated test equipment is presented. The method comprises transmitting instructions for performing an automated test from a system controller to a tester processor, wherein the instructions comprise parameters for a descriptor module. The method also comprises programming a reconfigurable circuit for implementing the descriptor module onto an instantiated FPGA block coupled to the tester processor. Further, the method comprises interpreting the parameters from the descriptor module using the reconfigurable circuit, wherein the parameters control execution of a plurality of test operations on a DUT coupled to the instantiated FPGA block. Additionally, the method comprises constructing at least one packet in accordance with the parameters, wherein each one of the at least one packet comprises a command for executing a test operation on the DUT. Finally, the method comprises performing a handshake with the DUT to route the at least one packet to the DUT. | 08-28-2014 |
| 20140257738 | HIERARCHICALLY DIVIDED SIGNAL PATH FOR CHARACTERIZING INTEGRATED CIRCUITS - An apparatus includes an output pad, a plurality of arrays of test devices, a hierarchy of selection devices, and address logic. The hierarchy of selection devices includes a plurality of levels coupled between the output pad and the arrays of test devices. Each test device is coupled to a selection device in a first level of the hierarchy, and the selection devices for each array are coupled to one selection device in a second level of the hierarchy. The address logic is coupled to the hierarchy of selection devices and operable to enable one selection device in each level of the hierarchy to couple a selected test device in a selected array to the output pad. | 09-11-2014 |
| 20150012237 | SYSTEMS AND METHODS FOR TEST TIME OUTLIER DETECTION AND CORRECTION IN INTEGRATED CIRCUIT TESTING - Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner. | 01-08-2015 |
| 20150025829 | PERFORMANCE, THERMAL AND POWER MANAGEMENT SYSTEM ASSOCIATED WITH AN INTEGRATED CIRCUIT AND RELATED METHOD - The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC maybe set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC. | 01-22-2015 |
| 20150066415 | Apparatus and Method for Measuring Microelectronic Electromagnetic Emissions to Detect Characteristics - A system and process can be adapted to determine if a device under test (DUT) is within predetermined acceptability or unacceptability pattern parameters based on configuration data and detectable emission or detectable signal profile data associated with a known good device under test (KGDUT). The system can include a sensor array which includes different electromagnetic or optical sensors that can include electrical and/or thermal sensors, a control section operable to position elements of the sensor array in proximity to different areas of interest of the KGDUT and DUT, a KGDUT/DUT control system operable to input a pattern of testing control signals adapted to generate the detectable emissions or detectable signal profile data from the KGDUT/DUT's areas of interest during KGDUT/DUT testing, an analysis system operable to compare the detectable emissions or detectable signal profile data from the KGDUT/DUT, and an input/output system operable to display results. | 03-05-2015 |
| 20150377966 | MONITORING CIRCUIT OF SEMICONDUCTOR DEVICE - The monitoring circuit of a semiconductor device includes: a boot-up controller configured to generate a boot-up enable signal in response to a power-up signal and a boot-up command signal; a read-period generator configured to output a read-period signal in response to a boot-up read signal; and a monitoring unit configured to output the read-period signal to an external output terminal during activation of the boot-up enable signal to allow the read-period signal to be monitored. | 12-31-2015 |
| 20160169961 | CONTROLLING A TEST RUN ON A DEVICE UNDER TEST WITHOUT CONTROLLING THE TEST EQUIPMENT TESTING THE DEVICE UNDER TEST | 06-16-2016 |
| 20160169973 | CONTROLLING A TEST RUN ON A DEVICE UNDER TEST WITHOUT CONTROLLING THE TEST EQUIPMENT TESTING THE DEVICE UNDER TEST | 06-16-2016 |
| 20180024194 | CONFIGURATION AND TESTING METHOD AND SYSTEM FOR FPGA CHIP USING BUMPING PROCESS | 01-25-2018 |
