| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 702118000 | Testing multiple circuits | 43 |
| 20080201099 | PULSE WIDTH ADJUSTMENT CIRCUIT, PULSE WIDTH ADJUSTMENT METHOD, AND TEST APPARATUS FOR SEMICONDUCTOR DEVICE - A semiconductor test apparatus to test a semiconductor circuit includes a pattern generator which generates a test pattern for testing the semiconductor circuit, a waveform shaper which shapes a test signal to be supplied to the semiconductor circuit based on the test pattern, a pulse width adjusting circuit which generates a timing signal for determining a phase of the test signal by adjusting a pulse width of an input pulse signal and outputs the timing signal to the waveform shaper, and a judging section which judges whether the semiconductor circuit is good or bad based on an output signal output from the semiconductor circuit. The pulse width adjusting circuit includes a first delay circuit which outputs a first delay signal generated by delaying the pulse signal by a certain delay time, a second delay circuit which outputs a second delay signal generated by delaying the pulse signal by a different delay time from the first delay circuit, and an output section which, in accordance with the first and second delay signals, generates and outputs the timing signal having a pulse width corresponding to a difference between the delay times respectively achieved by the first and second delay circuits. | 08-21-2008 |
| 20080221824 | TEST APPARATUS, TEST METHOD AND RECORDING MEDIUM - There is provided a test apparatus for testing a plurality of DUTs. The test apparatus includes a plurality of test modules that are connected to the plurality of DUTs and test the plurality of DUTs, and a CPU that controls test operations performed by the plurality of test modules in accordance with a designated one of operation modes including (i) a parallel test mode in which at least the plurality of test modules are caused to perform a same test simultaneously and in parallel and (ii) an independent test mode in which each of the plurality of test modules is caused to perform a different test independently. | 09-11-2008 |
| 20090006021 | METHOD AND APPARATUS FOR IMPLEMENTING SCALED DEVICE TESTS - A method includes defining a hierarchy of test routines in a test program for testing integrated circuit devices. A first device is tested at a first screening level in the hierarchy. The first device is tested at a second detailed level in the hierarchy responsive to the first device failing the testing at the first screening level. | 01-01-2009 |
| 20090138227 | Characterizing Across-Die Process Variation - Measurement of individual quiescent supply currents from multiple power supply pads located across a semiconductor die provides a means of characterizing across-die variation. A ratio is created by combining the individual pad supply current with the sum of all pad supply currents for a given die. An n-tuple is formed from the set of ratios for all pad supply currents to provide a unique signature for different across-die variation profiles. | 05-28-2009 |
| 20090150112 | SCAN METHOD AND SYSTEM OF TESTING CHIP HAVING MULTIPLE CORES - A method of testing chips for manufacturing defects or operational based defects. The method may be used with any chip having logically function elements, including chips having multiple cores configured to be physically and logically identical. The method may be used to limit the total number of bits required to test the cores by demultiplexing and/or compacting the bits provided to the cores and/or outputted from the cores during a scan test. | 06-11-2009 |
| 20090216480 | DEVICE UNDER TEST DE-EMBEDDING - A method of determining the intrinsic electrical characteristics of a device under test (DUT) includes determining a set of test measurements for a test structure including the device and determining test measurements for a number of de-embedding test structures. Based on the test measurements, DUT measurements are determined using both open-short and three-step de-embedding processes. The DUT measurements are combined to determine an imperfection error, which is used to adjust the calculations of a four-port de-embedding method. The adjusted calculations provide for a more accurate measurement of the parasitic elements in the test structure, thereby improving the determination of the intrinsic electrical characteristics of the device. | 08-27-2009 |
| 20090259430 | Method and Apparatus for Synchronizing Signals in a Testing System - The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal. Additionally, in other embodiments, the timing signal associated with various DUTs is used as a timing reference for other devices. | 10-15-2009 |
| 20090299677 | CIRCUIT CARD ASSEMBLY TESTING SYSTEM FOR A MISSILE AND LAUNCHER TEST SET - The invention generally relates to a circuit card assembly testing system for testing and troubleshooting new and failed circuit card assemblies. Specifically, circuit card assemblies that are part of a guided missile and launcher test set are tested using a board testing system (BTS), the preferred embodiment, to isolate faults or to verify final assembly. The BTS is used for testing and troubleshooting a wide variety of circuit card assemblies at the end of final assembly and upon their return as a failed item from the field. The BTS is designed to rapidly isolate faults in failed circuit card assemblies that have been returned to a maintenance facility by providing an improved means of fault isolation. The BTS is designed to aid in the production of circuit card assemblies by providing an improved means of rapidly verifying the proper operation of circuit boards after final assembly. | 12-03-2009 |
| 20100036637 | METHODS AND APPARATUS FOR HYBRID OUTLIER DETECTION - Methods and apparatus for data analysis according to various aspects of the present invention are configured to identify statistical outliers in test data for components, including hybrid outliers representing outliers within subsets of larger data populations. A method and apparatus according to various aspects of the present invention may operate in conjunction with a test system having a tester, such as automatic test equipment (ATE) for testing semiconductors. | 02-11-2010 |
| 20100042352 | PLATFORM SPECIFIC TEST FOR COMPUTING HARDWARE - A platform specific test for computing hardware and method using same, wherein the method supplies a plurality of test procedures, and provides a computing device to be evaluated, where the computing device comprises (M) physical objects. The method identifies, for each value of (i), an (i)th physical object disposed in the computing device. The method then determines, for each value of (i), if the plurality of test procedures comprises one or more test procedures associated with the (i)th physical object. If, for each value of (i), the plurality of test procedures comprises one or more (i)th test procedures associated with the (i)th physical object, then the method adds, as one or more (i)th test procedures, the one or more test procedures associated with the (i)th physical object to a test algorithm, and saves that test algorithm. | 02-18-2010 |
| 20100082282 | REDUCTION OF THE NUMBER OF INTEROPERABILITY TEST CANDIDATES AND THE TIME FOR INTEROPERABILITY TESTING - Provided are a method, system, and article of manufacture wherein a determination is made of a subset of all possible interoperable combinations of components of a computing system, wherein the components comprise selected elements of the computing system. One or more testing criteria are stored, wherein a testing criteria provides indications of characteristics of one or more of the components of the computing system. A selection is made of a number of interoperable combinations of the components from the subset of interoperable combinations of the components, based on the stored one or more testing criteria. The selected interoperable combinations are tested, wherein the selected interoperable combinations are fewer in number than the subset of interoperable combinations. | 04-01-2010 |
| 20100106449 | METHOD TO EFFICIENTLY SYNCHRONIZE MULTIPLE MEASUREMENTS ACROSS MULTIPLE SENSOR INPUTS - A system for synchronizing multiple measurements across multiple sensors is provided. The system implements an algorithm in combination with highly flexible hardware architecture that generally comprises of multiple sensor inputs correspondingly from multiple sensors, and multiple analog signal conditioning circuits, and an array of switches situated between the sensor inputs and the analog signal conditioning circuits that enable the multiple sensor inputs to be routed to any one of the analog signal conditioning circuits or to any combination of analog signal conditioning circuits simultaneously. The algorithm looks at all configured measurements for all configured sensors to determine which measurements should be performed in parallel. Any measurements that are in common among enabled sensors are performed simultaneously while other measurements consume analog signal conditioning paths as they are available. | 04-29-2010 |
| 20100114520 | TEST APPARATUS, TEST METHOD, PROGRAM, AND RECORDING MEDIUM REDUCING THE INFLUENCE OF VARIATIONS - Provided is a test apparatus that tests a device under test, including a vector expanding section that sequentially generates a plurality of test vectors; a predicting section that calculates a predicted value for each test vector by simulating an operation of the device under test, the predicted value indicating a prescribed characteristic value of the device under test to be measured while the device under test is supplied with a test signal corresponding to the test vector; a measuring section that obtains a measured value for each test vector by measuring the prescribed characteristic value of the device under test each time the device under test is supplied with a test vector; and a judging section that judges whether the device under test is defective based on a ratio between the predicted value and the measured value corresponding to each test vector. | 05-06-2010 |
| 20110131000 | CHIP TESTER, METHOD FOR PROVIDING TIMING INFORMATION, TEST FIXTURE SET, APPARATUS FOR POST-PROCESSING PROPAGATION DELAY INFORMATION, METHOD FOR POST-PROCESSING DELAY INFORMATION, CHIP TEST SET UP AND METHOD FOR TESTING DEVICES UNDER TEST - A chip tester for testing at least two devices under test connected to the chip tester has a timing calculator for generating a timing information for the channels of the chip tester. The timing calculator is adapted to obtain a propagation delay difference information describing a difference between, on the one hand, a propagation delay from the first channel port of the chip tester to the first terminal of the first device under test and, on the other hand, a propagation delay from the first channel port of the chip tester to the second terminal of the second device under test. The timing calculator is adapted to provide a timing information for a second channel of the chip tester connected to the first device under test or to the second device under test on the basis of the propagation delay difference information. The channel module configurator is adapted to configure the second channel of the chip tester on the basis of the timing information. | 06-02-2011 |
| 20110184687 | TEST APPARATUS AND TEST METHOD - A test apparatus for testing a device under test includes a test module that exchanges signals with the device under test to test the device under test, a test controller that includes a processor and a memory, where the test controller controls the test module, and a network that transfers communication packets between the test module and the test controller. Here, the test controller includes a receiving section that receives an interrupt packet requesting an interrupt to the test controller, from the test module via the network, a memory writing section that writes interrupt information included in the interrupt packet into the memory, and an interrupt notifying section that notifies the processor of the interrupt to cause the processor to reference the interrupt information written into the memory. | 07-28-2011 |
| 20110208468 | POWER DISTRIBUTION NETWORK ESTIMATION DEVICE - A device that estimates a positional relationship between loads individually connected through sensors to electric power-supply ends provided in a power distribution network includes a communication unit configured to change a resistance value located between each of electric power-supply ends and a ground terminal of each of sensors and measure a voltage value produced between each of the electric power-supply ends and the ground terminal; and a determination unit configured to acquire voltage values from the two selected sensors from among the sensors after a resistance value of one of the two sensors that has a higher acquired voltage value is changed, calculate a ratio between voltage values acquired before and after the resistance value is changed, and determine that the two sensors are connected to a branch circuit in a same system in the power distribution network, when each ratio about the two sensors is within a specified range. | 08-25-2011 |
| 20110288808 | OPTIMAL TEST FLOW SCHEDULING WITHIN AUTOMATED TEST EQUIPMENT FOR MINIMIZED MEAN TIME TO DETECT FAILURE - The present invention describes a method and system for optimizing a test flow within each ATE (Automated Test Equipment) station. The test flow includes a plurality of test blocks. A test block includes a plurality of individual tests. A computing system schedule the test flow based one or more of: a test failure model, test block duration and a yield model. The failure model determines an order or sequence of the test blocks. There are at least two failure models: independent failure model and dependant failure model. The yield model describes whether a semiconductor chip is defective or not. Upon completing the scheduling, the ATE station conducts tests according to the scheduled test flow. The present invention can also be applied to software testing. | 11-24-2011 |
| 20110295543 | PERFORMANCE IMPROVEMENT FOR A MULTI-CHIP SYSTEM VIA KERF AREA INTERCONNECT - A semiconductor wafer comprises a first chip and a second chip, each chip comprising a core, link layer and physical layer. A kerf area physically connects the two chips on the wafer, and a kerf area interconnect selectively couples the link layers of the two chips while the two physical layers are disabled. | 12-01-2011 |
| 20110313710 | Simultaneous Testing of Semiconductor Components on a Wafer - Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation. | 12-22-2011 |
| 20110313711 | Identifying Defective Semiconductor Components on a Wafer Using Component Triangulation - Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation. | 12-22-2011 |
| 20120041706 | TESTING SYSTEM FOR PORTABLE ELECTRONIC DEVICE - A testing system for a portable electronic device includes a sequential control card, a plurality of test devices, and a plurality of switches. The sequential control card provides and outputs command signals according to a predetermined test sequence. The test devices test the portable electronic devices according to the test sequence. The switches are connected between the sequential control card and the corresponding test devices, and are switched on, in order, under the control of the command signal from the sequential control card according to the test sequence to activate the corresponding test devices. The test devices test the portable electronic device according to the predetermined test sequence. | 02-16-2012 |
| 20120136611 | SEMICONDUCTOR APPARATUS AND TEST METHOD THEREOF - A semiconductor apparatus includes first and second chips sharing first and second data channels. The first chip compresses first test data of the first chip and outputs the compressed first test data through the first data channel in a first test mode, and the second chip compresses second test data of the second chip and outputs the compressed second test data through the second data channel in the first test mode. | 05-31-2012 |
| 20120143558 | TEST APPARATUS FOR MULTI-CHIP PACKAGE AND TEST METHOD THEREOF - A multi-chip package test apparatus is for testing a plurality of semiconductor packages including a plurality of flash memories and an application specific integrated circuit (ASIC) stacked on a single substrate. The multi-chip package test apparatus includes a plurality of test sockets configured to receive the plurality of semiconductor packages, respectively, a plurality of central processing units (CPUs) mounted on a test board and each configured to execute a package test of a respective one of the semiconductor packages received by the plurality of sockets, and a plurality of multiple access dynamic random access memory (DRAM) device operatively interposed between the CPUs and test sockets, respectively, each of the multiple access DRAM devices configured with separate memory areas for access by a respective CPU and a respective ASIC of the semiconductor packages. | 06-07-2012 |
| 20120150476 | METHODS OF MONITORING ELECTRONIC DISPLAYS WITHIN A DISPLAY NETWORK - Methods of monitoring one or more electronic displays are disclosed. A method may include performing at least one diagnostic operation on at least one electronic display having at least one camera, a display element, and a display server. Further, the method may include transmitting data relating to the at least one diagnostic operation to a network remote from the at least one electronic display. Additionally, the method may include displaying the data within the remote network. | 06-14-2012 |
| 20120185201 | AUTOMATIC POWER SUPPLY TESTING SYSTEM AND METHOD - An automatic power supply testing system records a preset test order of first and second power supplies with a recording module. The automatic power supply testing system controls a first control unit to connect a first connector connected to the first power supply to a simulation load to test the first power supply according to the preset test order by a determination control module and obtains a first test result. The automatic power supply testing system controls a second control unit to connect a second connector connected to the second power supply to the simulation load to test the second power supply after determining that the first test result is displayed and obtain a second test result. A display module displays the electrical stability of the first and second power supplies. | 07-19-2012 |
| 20120197581 | MEMORY DEVICE WITH INTERNAL MEASUREMENT OF FUNCTIONAL PARAMETERS - A non-volatile memory device may be integrated in a chip of semiconductor material. The memory device may include circuitry for receiving a measure instruction for obtaining a numerical measure value of a selected one among a plurality of predefined memory operations of the memory device. The memory device may also include circuitry for enabling the execution of the selected memory operation in response to the measure instruction. The execution of the selected memory operation may generate a corresponding result. The memory device may further include circuitry for providing at least one time signal, different from the corresponding result, relating to the execution of each memory operation, and circuitry for determining the measure value according to the at least one time signal of the selected memory operation. | 08-02-2012 |
| 20120253730 | DIRECT CURRENT CIRCUIT TESTING DEVICE AND METHOD FOR USING SAME - A method for testing electronic devices that are correspondingly connected to test units includes generating control signals for the electronic devices that are connected to one or more test units selected from the test units. A control unit adds ID codes corresponding to the selected test units to the control signals, and wirelessly transmits the control signals with the ID codes to all of the test units. Each of the test units compares the ID codes added to the control signals with its own stored ID code. When the ID code added to a control signal is in accordance with the ID code stored in one of the test units, the test unit controls the electronic device connected thereto to be turned on and off according to the control signal. | 10-04-2012 |
| 20120278027 | SYSTEM FOR PERFORMING ELECTRICAL CHARACTERIZATION OF ASYNCHRONOUS INTEGRATED CIRCUIT INTERFACES - An integrated circuit with a single-channel input/output (I/O) interface and a multi-channel I/O interface includes functional circuits that operate in different clock domains and a test circuit. For a single-channel I/O interface, the test circuit simulates read/write operations by bypassing the functional circuits and performs electrical characterization of the single-channel I/O interface. For a multi-channel I/O interface, the test circuit configures a plurality of channels of the multi-channel interface in a half-duplex mode and performs electrical characterization using data loop back by bypassing the functional circuits. | 11-01-2012 |
| 20130085704 | METHODS AND APPARATUS FOR TESTING MULTIPLE-IC DEVICES - Embodiments include systems that include at least one integrated circuit (IC) and methods for their testing. Each IC includes an input interconnect to receive an input signal, a test enable interconnect to receive a test enable signal, and a controller (e.g., a TAP controller) for performing testing of the integrated circuit based on values in at least one register (values corresponding to the input signal). Each IC also includes an input port and a multiplexer coupled to the first input interconnect, the at least one register, and the input port. The multiplexer is controllable to pass the input signal to the input port in response to non-assertion of the test enable signal, and to pass the input signal to the at least one register in response to assertion of the test enable signal. When the system includes multiple controllers, each controller may implement a different opcode-to-instruction mapping. | 04-04-2013 |
| 20130132023 | STRUCTURE FOR CHARACTERIZING THROUGH-SILICON VIAS AND METHODS THEREOF - An integrated circuit device can include a number of test structures, whereby each test structure includes a TSV and a plurality of devices-under-test (DUTs). Each of the DUTs in a test structure has a different positional relationship, such as proximity or orientation, to the TSV. A test system can measure selected parameters such as transistor threshold voltage, leakage current, or other parameters, for each of the DUTs in the test structure. The measurements for different test structures can be combined to characterize nominal values of the measured parameter and its statistical distribution. This information provides an indication of how the measured parameter varies according to the positional relationship of a TSV to a DUT. | 05-23-2013 |
| 20130197851 | TEST CONTROLLER FOR 3D STACKED INTEGRATED CIRCUITS - Stacked IC devices (or 3D semiconductor devices) have two or more semiconductor devices stacked so they occupy less space than two or more conventionally arranged semiconductor devices. Access to test infrastructures of stacked ICs is provided, regardless of configuration, while using a reduced number of interface pins. A master test controller is provided in a base die and at least one slave test controller is provided in another die. The master test controller is coupled to a test data control (TDC) bus and is configured to broadcast test instructions, test data, and an ID of a slave test controller. The slave test controller is also coupled to the TDC bus, is configured to recognize the broadcast test instructions and test data addressed to the slave test controller, and responds to the instructions when the instructions are addressed to the slave test controller. | 08-01-2013 |
| 20130311127 | Identifying Defective Components on a Wafer Using Component Triangulation - Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation. | 11-21-2013 |
| 20140058699 | INFORMATION PROCESSING APPARATUS, TEST DATA GENERATING APPARATUS, AND TEST DATA GENERATING METHOD - An apparatus has a first operation model containing connection information indicating a connecting relation between pins of the integrated circuits including a first integrated circuit and a second integrated circuit and containing a designation of an output pin for outputting data to the outside of the first integrated circuit or a designation of an input pin for inputting the data from the outside of the first integrated circuit, and a second operation model containing a designation of the output pin or the input pin outside the second integrated circuit and having a definition of an interface specification for inputting and outputting the data to the input pin and the output pin of the second integrated circuit via the communication pin. | 02-27-2014 |
| 20140074422 | ADAPTIVE POWER CONTROL USING TIMING CANONICALS - A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data. | 03-13-2014 |
| 20140114603 | PSEUDO TESTER-PER-SITE FUNCTIONALITY ON NATIVELY TESTER-PER-PIN AUTOMATIC TEST EQUIPMENT FOR SEMICONDUCTOR TEST - A system and method for testing devices are presented. Embodiments of the present invention use a central controller to coordinate the testing of a plurality of devices under test as well as a plurality of channel circuits that are each operable to be coupled to at least one I/O pin of a device under test of the aforementioned plurality of devices under test. Also, embodiments of the present invention include a plurality of intermediate processors that are each coupled to the central controller and operable to receive and send control signals. These intermediate processors are each coupled to a different set of channel circuits of the plurality of channel circuits and are operable to execute their own instantiation of a test program that is independent of any other intermediate processor of the plurality of intermediate processors for the testing of a device under test associated therewith. | 04-24-2014 |
| 20140172346 | SYSTEMS AND METHODS FOR PERFORMING REDUNDANCY TESTS ON TURBINE CONTROLS - A computing device for use in performing a redundancy test on a turbine assembly and a turbine control system including a plurality of controllers each configured to independently control operation of the turbine assembly is provided. The computing device configured to be coupled to the turbine control system and configured to determine whether a plurality of test conditions are satisfied, display to a user an indication of which test conditions are satisfied, and test, in response to a user input, the plurality of controllers. | 06-19-2014 |
| 20140214355 | METHOD AND APPARATUS FOR VERIFYING CIRCUIT DESIGN - A verification test is performed on a device containing master and slave units connected via a bus. In the verification test, a first signal is transferred between a first master unit and a first slave unit during a first transfer period while a second signal is transferred between a second master unit and a second slave unit during a second transfer period. The second transfer period overlaps at least a part of the first transfer period. When the first transfer period is longer than a third transfer period, first combination information indicating the combination of the first master unit and first slave unit is stored in a storage unit, in conjunction with second combination information indicating the combination of the second master unit and second slave unit. | 07-31-2014 |
| 20140244203 | TESTING SYSTEM AND METHOD OF INTER-INTEGRATED CIRCUIT BUS - A testing system configured to test real-time signals of an I | 08-28-2014 |
| 20140288871 | TEST APPARATUS AND TEST SYSTEM - A test apparatus of the present embodiment has a logic cell, a host and a first bus. The host includes: a conversion section configured to analyze a test vector and convert the test vector to signal control data and a waveform shape; and a judgment section configured to analyze an expected value comparison result to perform success/failure judgment of a test of a semiconductor circuit. The logic cell is provided with a first storage section configured to store the signal control data, a second storage section configured to store the waveform shape as a waveform shape table, a waveform generating section configured to generate an output waveform for controlling the semiconductor circuit and output the output waveform, and an expected value comparing section configured to obtain the expected value comparison result on the basis of the signal control data and the waveform shape table. | 09-25-2014 |
| 20140379288 | CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS - A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link. | 12-25-2014 |
| 20150120234 | SMART HANDLER RESOURCE DISTRIBUTION SYSTEM - A system for concurrently testing multiple semiconductor components includes multiple testers, each including a processor and a memory configured to store and execute control signals for completing testing of one of the semiconductor components, a tester side docking board, and a tester communication port. A handler has multiple test sites, each of which is configured to receive one of the semiconductor components, a handler side docking board, and a handler communication port. A controller is located externally from the testers and the handler and is in communication with each of the testers and the handler through the tester and handler communication ports. Communication between each of the testers and the handler occurs through the controller, and each of the testers is connected, via the tester side docking board, to a corresponding one of the semiconductor components through the handler side docking board. | 04-30-2015 |
| 20150309111 | Multiple Rate Signature Test to Verify Integrated Circuit Identity - Screening a batch of integrated circuits (IC) may be done with test patterns provided in a sequence of test vectors. The sequence of test vectors may be fetched from a memory coupled to a tester and then one or more bits from each test vector may be provided to the tester. A test pattern is formed by updating a latch in a periodic manner with a bit value from a same bit position from each of the sequence of test vectors. The test pattern may then be applied to an input pin of a device under test and a resulting signal may be monitored on an output pin of each one of the batch of ICs. A slow speed ICs may be screened by treating each IC that passes both a fast pattern test and a slow speed pattern test as a failure, for example. | 10-29-2015 |
| 20150362548 | WAFER MAP IDENTIFICATION SYSTEM FOR WAFER TEST DATA - A wafer map identification system for wafer test data includes a capturing unit configured to collect the test data of each wafer chip from the wafer testing device; an execution interface for receiving the test data from the capturing unit and generating a wafer map, the wafer map defining a plurality of color blocks with respect to locations of the test chips, each of the color blocks having a color defined by a grade of the respective test chip. Moreover, each color block reveals the associated test data as being pointed. | 12-17-2015 |
