Class / Patent application number | Description | Number of patent applications / Date published |
702079000 | Time-related parameter (e.g., pulse-width, period, delay, etc.) | 62 |
20080208497 | METHOD AND DEVICE FOR CHECKING THE INTEGRITY OF A LOGIC SIGNAL, IN PARTICULAR A CLOCK SIGNAL - A device and a method detect an acceleration of a logic signal expressed by a closure, beyond a closure threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit. | 08-28-2008 |
20080255785 | Length-of-the-curve stress metric for improved characterization of computer system reliability - Embodiments of the present invention provide a system that characterizes the reliability of a computer system. The system first collects samples of a performance parameter from the computer system. Next, the system computes the length of a line between the samples, wherein the line includes a component which is proportionate to a difference between values of the samples and a component which is proportionate to a time interval between the samples. The system then adds the computed length to a cumulative length variable which can be used to characterize the reliability of the computer system. | 10-16-2008 |
20080288196 | Correction of Delay-Based Metric Measurements Using Delay Circuits Having Differing Metric Sensitivities - Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature. Temperature results can then be corrected for supply voltage variation and vice-versa. | 11-20-2008 |
20080288197 | Calibration of Multi-Metric Sensitive Delay Measurement Circuits - A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits. | 11-20-2008 |
20080319693 | Method, Device And Computer Program For Evaluating A Signal Transmission - A method comprises the step of obtaining a first signal of the signal from a first position of a transmission channel, and a second signal of the signal from a second position of the transmission channel, determining a delay time between the first signal and the second signal by a first degree of alikeness of the first signal and the second signal trace, and determining a direction function vector of the signal by a second degree of alikeness of the first signal and the second signal trace. | 12-25-2008 |
20090037126 | PILEUP REJECTION IN AN ENERGY-DISPERSIVE RADIATION SPECTROMETRY SYSTEM - A method of detecting pileups includes testing an instantaneous slope of a preamplifier signal against a noise trigger value and, after the instantaneous slope has been determined to exceed the noise trigger value, identifying a first subsequent portion of the preamplifier signal wherein the instantaneous slope of the preamplifier signal increases to a maximum. The method further includes, following the first subsequent portion, identifying a second subsequent portion of the preamplifier signal wherein the instantaneous slope still exceeds the noise trigger level but has decreased by more than the noise trigger level from the maximum, and, following the second subsequent portion and before the instantaneous slope declines below the noise trigger level, identifying a third subsequent portion of the preamplifier signal wherein the instantaneous slope of the preamplifier output signal increases by more than the noise trigger value, and, in response thereto, determining that a pileup has occurred. | 02-05-2009 |
20090055113 | Method, system and apparatus for measuring an idle value of a central processing unit - In a method, system and apparatus for measuring an idle value of a Central Processing Unit (CPU) in an embedded system, the CPU increments a hardware counter in accordance with clock signals. The CPU also increments an idle counter during a predetermined period of time in accordance with the clock signals while an idle task is running. The CPU calculates the idle value as a ratio of total increments of the idle counter to total increments of the hardware counter after the predetermined period of time has expired. | 02-26-2009 |
20090076753 | FLEXIBLE ON CHIP TESTING CIRCUIT FOR I/O'S CHARACTERIZATION - The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules. | 03-19-2009 |
20090125262 | Absolute Duty Cycle Measurement Method and Apparatus - A method and apparatus for measuring the absolute duty cycle of a signal are provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values. | 05-14-2009 |
20090125263 | High Resolution Time Measurement in a FPGA - Various techniques are described for high resolution time measurement using a programmable device, such as an FPGA. The timing may be triggered by any event, depending on the applications of use. Once triggering has occurred, a START pulse begins propagating through the FPGA. The pulse is able to propagate through the FPGA in a staggered manner traversing multiple FPGA columns to maximize the amount of time delay that may be achieved while minimizing the overall array size, and thus minimizing the resource utilization, of the FPGA. The FPGA timing delay is calibrated by measuring for the linear and non-linear differences in delay time of each unit circuit forming the staggered delay line path for the timing circuit. The FPGA is able to achieve nanosecond and sub-nanosecond time resolutions and thus may be used in applications such as various time of flight systems. | 05-14-2009 |
20090132190 | METHOD AND APPARATUS FOR REMOTELY BUFFERING TEST CHANNELS - A system is provided to enable leakage current measurement or parametric tests to be performed with an isolation buffer provided in a channel line. Multiple such isolation buffers are used to connect a single signal channel to multiple lines. Leakage current measurement is provided by providing a buffer bypass element, such as a resistor or transmission gate, between the input and output of each buffer. The buffer bypass element can be used to calibrate buffer delay out of the test system by using TDR measurements to determine the buffer delay based on reflected pulses through the buffer bypass element. Buffer delay can likewise be calibrated out by comparing measurements of a buffered and non-buffered channel line, or by measuring a device having a known delay. | 05-21-2009 |
20090144006 | CALIBRATION OF MULTI-METRIC SENSITIVE DELAY MEASUREMENT CIRCUITS - A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits. | 06-04-2009 |
20090150103 | Computer-Based Method and System for Simulating Static Timing Clocking Results - A method, system and computer-readable medium are presented for creating unique clock waveform checking commands for an event simulator to validate that the logical creation matches the timing definitions. The method includes selecting one or more clock signals for validation; specifying timing definitions of the selected clock signals; automatically categorizing the selected clock signals based on their synchrony; automatically matching each selected clock signal to a corresponding clock cycle by parsing the specified timing definitions; specifying one or more test cases for an event simulator, wherein the test cases simulate logic for generating each selected clock signal; validating that the logic for generating each selected clock signal matches the specified timing definitions for each selected clock signal. | 06-11-2009 |
20090177424 | 3-Dimensional method for determining the clock-to-Q delay of a flipflop - A 3-dimensional flipflop timing model is described, which allows a flipflop to be presented with a smaller setup time in comparison to a 2-dimensional timing model. Because of this, fewer timing errors will be encountered during chip timing analysis, fewer timing errors will have to be fixed, and the user can often avoid redesigning logic that fails to meet its timing specs, thus saving valuable design time. Furthermore, in many cases, the user can avoid the necessity of using larger standard cells that employ larger transistor sizes, thus minimizing chip size and chip power dissipation. | 07-09-2009 |
20090240453 | METHOD AND SYSTEM OF DETERMINING FORTHCOMING FAILURE OF TRANSDUCERS - A method and system of determining forthcoming failure of transducers. At least some of the illustrative embodiments are methods comprising creating a first electrical signal representative of acoustic energy propagating between a first pair of transducers of a fluid meter, creating a second electrical signal representative of acoustic energy propagating between a second pair of transducers of the fluid meter (the creating the second electrical signal substantially concurrently with create the first electrical signal), calculating a value indicative of a relationship between a parameter of the first electrical signal a parameter of the second electrical signal, and determining whether performance of the first pair of transducers indicates upcoming failure of at least one transducer of the first pair of transducers, the determining using the value. | 09-24-2009 |
20090271134 | Methods and Apparatus for Determining a Switching History Time Constant in an Integrated Circuit Device - Techniques for inline measurement of a switching history time constant in an integrated circuit device are provided. A series of pulses is launched into a first stage of a delay chain comprising a plurality of delay stages connected in series and having a length greater than a decay length of at least an initial one of the series of pulses, such that the at least initial one of the series of pulses does not appear at a second stage of the delay chain. An amount of time between the launching of the initial one of the series of pulses and the appearance of at least one of the series of pulses at the second stage of the delay chain is determined. The switching history time constant is calculated as a function of a number of stages traversed by the at least one pulse, the determined amount of time, and the decay length of the at least initial one of the series of pulses based at least in part on a switching history of the integrated circuit device. | 10-29-2009 |
20090271135 | Detecting Device for Detecting an Operating Mode of a System and Detecting Method Thereof - A detecting device for detecting an operating mode is disclosed. The detecting device includes a pulse generator and a hold-up unit. The pulse generator is disposed for issuing a one-shot pulse signal in response to each of button signals respectively. The hold-up unit is disposed for receiving the button signals to respectively generate delayed button signals by way of clock delay determined by a clock signal. The one-shot pulse signal and the delayed button signals are used to determine an operating mode of a system. | 10-29-2009 |
20100057390 | SYSTEM AND METHOD FOR PRECISION PHASE SHIFT MEASUREMENT - In one embodiment, a frequency generator produces an excitation signal, a local oscillator signal, and a reference signal at a difference frequency of the excitation signal and local oscillator signal. The excitation signal is applied to a physical system to produce a response signal, which is mixed with the local oscillator signal. A filter selects a difference frequency component. The frequencies of the excitation signal and/or local oscillator signal are varied, such that the magnitude of the difference frequency is constant, but a sign of the difference frequency changes from positive to negative. The phase shift of the difference frequency component, with respect to the reference signal, at each of the two signs of the difference frequency, is measured. The measured phase shift at the negative sign is subtracted from the measured phase shift at the positive sign, and the difference is divided in half, to produce a result. | 03-04-2010 |
20100070228 | DETECTING NONLINEARITY IN A CABLE PLANT AND DETERMINING A CABLE LENGTH TO A SOURCE OF THE NONLINEARITY - An apparatus and a method for detecting a nonlinearity in a cable plant and for determining cable length to a source of the nonlinearity are disclosed. Upstream signal peaks are detected by averaging upstream signal waveforms. The upstream signal peaks are generated at the source of the nonlinearity from naturally occurring downstream signal peaks propagating in the cable plant. The downstream signal peaks occur due to constructive superposition of the downstream channel signals. Acquisition of the upstream signal waveforms is triggered by the downstream signal peaks. The cable length to the source of nonlinearity is determined from a time delay between the downstream signal peaks and the upstream signal peaks. | 03-18-2010 |
20100100347 | Method and System for Calculating Timing Delay in a Repeater Network in an Electronic Circuit - Calculating a timing delay in a repeater network in an electronic circuit. The repeater network comprises a plurality of driving cells. At least one loop comprising one or more pins and one or more driving cells for driving the loop is implemented. Each driving cell in the loop is arranged between two branches of the loop. For each driving cell, the loop is opened a plurality of times per driving cell, with one open at a time. A dedicated arrival time of a signal at each sink of the repeater network for the one open at a time per driving cell is calculated. The dedicated arrival time is stored. The calculation step and the storing step is repeated until the dedicated arrival time at each sink of the repeater network is available for each of the opens per driving cell. | 04-22-2010 |
20100121597 | Method for Determining Time Differences Between Signals Measured by at Least Two Coupled Measuring Devices and Measurement System and Corresponding Switching Device - The invention relates to a method and to a switching device ( | 05-13-2010 |
20100174503 | Monitoring NFET/PFET Skew in Complementary Metal Oxide Semiconductor Devices - An apparatus for directly measuring performance offset of NFET transistors with respect to PFET transistors in CMOS device processing includes a ring oscillator whose frequency is used to measure random across chip variations, as well as correlated across chip variations; a balanced inverter having a input driven by the ring oscillator, wherein the balanced inverter is designed to be formed such that a current drive capability of one or more NFET devices of the inverter is substantially equal to a current drive capability of one or more PFET devices of the inverter at a given operating temperature; and a capacitor coupled to an output of the inverter, with a voltage across the capacitor indicative of whether a skew exists between NFET device performance and PFET device performance. | 07-08-2010 |
20100262393 | System and Method for Determining a Phase Conductor Supplying Power to a Device - A system and method for determining one of a plurality of power line phase conductors to which a remote device is electrically connected via a low voltage power line and transformer, and wherein each power line conductor carries a different phase of power is provided. In one embodiment, the method includes transmitting a different data beacon at a zero crossing of a voltage of the power of each of a plurality of power line phase conductors and storing in a memory information of the data beacon transmitted at the zero crossing of each phase conductor. At the remote device the method includes receiving a first data beacon, determining whether the first data beacon was received at a zero crossing of the voltage, and if the first data beacon was received at a zero crossing of the voltage, transmitting a phase notification that includes information of the first beacon and information identifying the remote device from the remote device. Finally, at a computer system, the method includes receiving the phase notification accessing the memory to determine a power line conductor to which the remote device is electrically connected. | 10-14-2010 |
20100262394 | METHOD AND AN APPARATUS FOR EVALUATING SMALL DELAY DEFECT COVERAGE OF A TEST PATTERN SET ON AN IC - A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path. | 10-14-2010 |
20100262395 | System and Method for Determining a Phase Conductor Supplying Power to a Device - A system and method for determining one of a plurality of power line conductors to which a remote device is electrically connected is provided. In one embodiment the method includes transmitting a data beacon, determining a relative time period associated with each power line conductor between a zero crossing of the voltage of the power line conductor and the transmission of the data beacon, receiving the data beacon with the remote device, determining a first time period between reception of the data beacon and a zero crossing of a voltage at the first remote device, and transmitting data of the first time period to a computer system. The method further includes with the computer system receiving the data of the first time period, determining that the first time period satisfies a similarity threshold with a relative time period associated with a first power line conductor, and storing in a memory information associating the first remote device with the first power line conductor. | 10-14-2010 |
20100268500 | METHOD AND DEVICE FOR THE IDENTIFICATION OF A DELAY-SUSCEPTIBLE CONTROL PATH, CONTROL DEVICE AND COMPUTER PROGRAM PRODUCT - A method for identifying a delay-susceptible control path in the control of a steam generator and a device constructed for carrying out the method are provided. A model structure of the steam generator is specified, consisting of an unknown time-variable Nth-order delay element and a known integrator. Also used for the identification are measurements of the fuel mass flow, the turbine stream mass flow, and the live stream pressure which arises in the steam accumulator behind the steam generator after the removal of the turbine steam mass flow. Using these online measurements and the model structure, the live steam mass flow at the output of the steam generator is derived by calculation. In this way, the input value and the output value of the Nth-order delay element are determined and, using an estimation method, the parameters of a continuous transmission function of the Nth-order delay element are also determined online. | 10-21-2010 |
20100280779 | SYSTEM AND METHOD TO MEASURE THE TRANSIT TIME POSITION(S) OF PULSES IN TIME DOMAIN DATA - A system and method to measure, with increased precision, the transit time position(s) of pulses in a time domain data. An example data set would be the transit time of pulses in Time-Domain Terahertz (TD-THz) data. The precision of the pulse timing directly affects the precision of determined sample properties measurements (e.g., thickness). Additionally, an internal calibration etalon structure and algorithm method provides for continuous system precision/accuracy check method to increase sample measurement integrity. The etalon structure can improve the precision of sample property measurements (e.g., absolute thickness). Various hardware and system implementations of the above are described. | 11-04-2010 |
20100305895 | DISTRIBUTING A CLOCK IN A SUBTERRANEAN SURVEY DATA ACQUISITION SYSTEM - A technique includes determining a first difference between a time that a first network element of a seismic acquisition network receives a first frame pulse from a second network element of the seismic acquisition network and a time that the first network element transmits a second frame pulse to the second network element. The technique includes determining a second difference between a time that the second network element receives the second frame pulse and a time that the second network element transmits the first frame pulse. The technique includes determining a transmission delay between the first and second network elements based on the first and second time differences. | 12-02-2010 |
20110035170 | Time-of-Flight Measurement Based on Transfer Function and Simulated Exponential Stimulus - Systems and methods are described for transmitting a waveform having a controllable attenuation and propagation velocity. An exemplary method comprises: generating an exponential waveform, the exponential waveform (a) being characterized by the equation V | 02-10-2011 |
20110040509 | High Resolution Time Interpolator - The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy. | 02-17-2011 |
20110082657 | DELAY ANALYSIS DEVICE, DELAY ANALYSIS METHOD, AND DELAY ANALYSIS PROGRAM - A delay analysis device includes an acquisition section that acquires circuit information relating to a path through which signal propagation can be delayed, a determination section that sets up an assumed fault for each of pins disposed in the path, and determines whether a signal change output from a beginning latch can be propagated to an ending latch for each of pins for which the assumed faults are set up, and an analysis section that calculates a delay distribution by accumulating delay distributions expressed by probability density functions of delays that occur in individual delay elements included in the path determined that a signal change output from the beginning latch can be propagated to the ending latch, and by not accumulating the delay distributions at a pin through which it has been determined that the signal change cannot be propagated to the ending latch based on the acquired circuit information. | 04-07-2011 |
20110125439 | DISTANCE-DEPENDENT SPECTRA WITH UNIFORM SAMPLING SPECTROMETRY - In a receiver of electromagnetic or other waves, scaling of received frequencies in proportion to the respective source distances, so as to reveal the source distances and permit isolation of signals from a particular source by simple spectral filtering. Phase differences between transmitted frequencies due to the common source path lead to chirp eigenfunctions registering in the receiver as scaled frequencies. The chirps are extracted by implementing exponentially varying path delays in autocorrelators and diffractive spectrometers say using a medium with variable refractive index. Analogous exponentially varying phase shifts are applied to successive samples in the kernel of discrete Fourier transform implementations. Advantage lies in enabling distance-dependent frequency scaling in autocorrelation spectroscopy, as well as in conventional diffractive or refractive spectrometers or digital signal processing with uniform sampling. | 05-26-2011 |
20110130994 | CIRCUIT AND METHOD FOR DETERMINING A VALUE, PARTICULARLY A DURATION, OF A TEST SIGNAL - The invention is related to a method and a circuit for determining a value, particularly a duration, of a test signal, in which a timer is executed with a first clock-state change of a clock to apply a control signal to at least a first of at least two delay elements. The delay elements are executed to produce different time-delayed comparison signals. A comparator arrangement with at least one comparator with comparator inputs, to apply the differently delayed comparison signals and the instantaneous test signal, is designed to determine, from the respective applied comparison signal and the test signal, a comparison result, whereby the sequence of the comparison results forms a differential value for the test signal. | 06-02-2011 |
20110202296 | TEST APPARATUS AND TEST METHOD - A data signal is transmitted synchronously with a clock signal, and contains n phases (n represents an integer of 2 or more) of data for each cycle of the clock signal. A first time to digital converter generates clock change point information which represents the change timing of the clock signal. A second time to digital converter receives a data sequence in increments of cycles of the clock signal, and generates data change point information items which represent the change timing of the data in increments of phases of the data. A calculation unit calculates difference data between the change timing represented by the data change point information and the change point timing represented by the clock change point information in increments of phases. A judgment unit judges a DUT based upon the difference data received from the calculation unit. | 08-18-2011 |
20110218751 | DYNAMIC SYNCHRONIZATION SYSTEM AND METHODS - A method and system for continuously predicting an input line power waveform frequency of alternating current having maximum and minimum values, and a reference value located therebetween by specifying an outer window defining a sense point of the waveform between lower and upper limits of the outer window, the sense point being located away from the reference value and having a corresponding predicted sense point time; providing an inner window having an inner time interval less than an outer time interval corresponding to time between the lower and upper limits; positioning the inner window at the predicted sense point time; identifying an actual sense point time of a measured inner sense point value and excluding one or more identified actual outer sense point values being both outside of the inner time interval and within the outer time interval; and calculating the frequency of a future cycle of the waveform. | 09-08-2011 |
20110301896 | DELAY ANALYSIS APPARATUS, COMPUTER-READABLE RECORDING MEDIUM HAVING DELAY ANALYSIS PROGRAM STORED THEREON, AND DELAY ANALYSIS METHOD - If there are a plurality of activation paths on which a signal propagates during a delay test, multiple-input cells receiving two or more activation paths are extracted by an extraction unit. For the extracted multiple-input cells, whether there is a possibility of occurrence of a multiple-input switching in a multiple-input cell is determined by a determination unit, based on an input timing to each signal multiple-input cell in the two or more activation paths. Then, an occurrence situation of a multiple-input switching is analyzed as one delay cause by an analysis unit, based on a determination result by the determination unit and a result of the delay test. | 12-08-2011 |
20120010837 | Design-Dependent Integrated Circuit Disposition - A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure. | 01-12-2012 |
20120072153 | TECHNIQUE FOR DETERMINING PERFORMANCE CHARACTERISTICS OF ELECTRONIC DEVICES AND SYSTEMS - A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line. | 03-22-2012 |
20120084036 | Signal Acquisition Probe Storing Compressed or Compressed and Filtered Time Domain Impulse or Step Response Data for Use in a Signal Measurement System - A signal acquisition probe stores compressed or compressed and filtered time domain data samples representing at least one of an impulse response or step response characterizing the signal acquisition probe. The compressed or compressed and filtered time domain data samples of the impulse response or the step response are provided to a signal measurement instrument for compensating the signal measurement instrument for the impulse or step response of the signal measurement instrument. | 04-05-2012 |
20120158335 | Systems and Methods for Synchronizing Sensor Data - A magnetic field sensor including a bidirectional node is configured to perform at least one of generating sensor data, storing sensor data, or communicating sensor data in a serial data signal in response to a trigger signal received at the bidirectional node. An alternative sensor having a node that may or may not be a bidirectional node is configured to reset at least one of a sensor data signal, a clock, a register, or a counter in response to a trigger signal received at the node and is further configured to communicate the sensor data signal in response to the trigger signal. | 06-21-2012 |
20120166121 | APPARATUS FOR DETECTING REAL TIME CLOCK FREQUENCY OFFSET AND METHOD THEREOF - An apparatus for detecting a real time clock frequency offset includes: an overlap detecting unit detecting an overlap signal having overlap information of a predetermined reference clock and a predetermined real time clock; an envelope signal creating unit creating an envelope signal having envelope information of the overlap signal; and a frequency counter unit calculating a frequency of the envelope signal that is a frequency offset of the real time clock, by using a first clock number created by counting the reference clock for one period of the envelope signal and a frequency of the reference clock. | 06-28-2012 |
20120191394 | Latency Measurement - Touchscreen testing techniques are described. In one or more implementations, a piece of conductor (e.g., metal) is positioned as proximal to a touchscreen device and the touchscreen device is tested by simulating a touch of a user. This technique may be utilized to perform a variety of different testing of a touchscreen device, such as to test latency and probabilistic latency. Additional techniques are also described including contact geometry testing techniques. | 07-26-2012 |
20120197570 | Measurement of Parameters Within an Integrated Circuit Chip Using a Nano-Probe - At least a method and a system are described for monitoring and measuring one or more parameters in an integrated circuit chip by way of receiving a first voltage, a second voltage, and a control signal. In a representative embodiment, the first voltage is used for powering a probe and the second voltage is used as a voltage reference for voltage measurement within the integrated circuit chip. In one or more representative embodiments, the one or more parameters measured comprise minimum and maximum voltage levels of a signal, sampled voltage levels of a signal, a period of a signal, a duty cycle of a clock signal, a jitter of a clock signal, and/or a temperature at a location within the integrated circuit chip. | 08-02-2012 |
20120253721 | DETERMINING CHARACTERISTICS OF ULTRASHORT PULSES - Various systems and methods for analysis of optical pulses are provided. In one embodiment, a method is provided including obtaining a plurality of traces produced by propagating an unknown pulse and a reference pulse along a pair of crossing trajectories through a spectrometer, where each trace is associated with a delay between the unknown pulse and the reference pulse. Each trace is spatially filtered to generate a plurality of spatially filtered electric field measurements, which are temporally filtered to generate a plurality of temporally filtered electric field measurements. The plurality of temporally filtered electric field measurements are concatenated based at least in part upon the delay associated with the corresponding trace to generate a concatenated wave form corresponding to the unknown pulse. | 10-04-2012 |
20130006561 | COMPUTING DEVICE, STORAGE MEDIUM, AND METHOD FOR ANALYZING SIGNAL GROUP DELAY OF PRINTED CIRCUIT BOARD - In a method for analyzing a signal group delay of a printed circuit board (PCB) using a computing device, the computing device connects to a signal measuring device that measures S-parameters from a pair of data signal line and clock signal line of the PCB. The method analyzes a differential loss coefficient of the data signal line and the clock signal line based on the S-parameters, and calculates a first signal delay of the data signal line and a second signal delay of the clock signal line according to the differential loss coefficient. The method further analyzes a signal group delay of the PCB according to the first signal delay and the second signal delay, and displays the signal group delay on a display device if the signal group delay does not satisfy a PCB design specification. | 01-03-2013 |
20130041608 | CRITICAL PATH DELAY PREDICTION - Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator. | 02-14-2013 |
20130046497 | SYSTEM AND METHOD FOR BUILT IN SELF TEST FOR TIMING MODULE HOLDOVER - Aspects of the embodiments include a method for synchronizing a device having an oscillator to a reference signal. A correction signal can be determined based on the reference signal. A mathematical model of the oscillator can be trained based at least upon the correction signal. A predicted correction signal for the trained mathematical model can be determined. A time error using the predicted correction signal can be generated to assess suitability of the trained mathematical model for disciplining drift in the oscillator and synchronizing the device when the reference signal is not available. | 02-21-2013 |
20130211759 | METHOD FOR EVALUATING THE EFFECTS OF AN INTERCONNECTION ON ELECTRICAL VARIABLES - The invention relates to a method for evaluating the effects of a multiconductor interconnection on electrical variables in an electronic circuit or system, which takes into account the frequency dependent couplings between the conductors to obtain an accurate evaluation of effects such as propagation delay, attenuation, linear distortions, echo and crosstalk. | 08-15-2013 |
20130218498 | Method of Interrogation of a Differential Sensor of Acoustic Type Having Two Resonances and Device Implementing the Method of Interrogation - A method of interrogating a surface acoustic wave differential sensor formed by two resonators is provided, wherein the method allows the measurement of a physical parameter by determination of the difference between the natural resonant frequencies of the two resonators, which difference is determined on the basis of the analysis of a signal representative of the level of a signal received as echo of an interrogation signal, for a plurality of values of a frequency of the interrogation signal in a domain of predetermined values; the analysis can be based on the cross-correlation of the said signal representative of the level according to a splitting into two distinct frequency sub-bands. An advantage is that it may be implemented in a radio-modem. | 08-22-2013 |
20130253868 | ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS - A method for estimating delay deterioration in an integrated circuit comprising estimating degradation in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the digital circuit. Generating an end-of-life netlist in which the at least one device characteristic of each device has been modified to reflect the estimated degradation or estimating a change in timing delay of each device directly from the estimated degradation of the at least one characteristic of each device. Performing a timing analysis using the estimated change in timing delay of each device to determine circuit path delays. The timing analysis being static or statistical. | 09-26-2013 |
20130268224 | METHOD FOR MEASURING THE COINCIDENCE COUNT RATE, USING A TIME-TO-DIGITAL CONVERSION AND AN EXTENDIBLE DEAD TIME METHOD WITH MEASUREMENT OF THE LIVE TIME - A method for measuring the coincidence count rate, using a time-to-digital conversion and an extendible dead time method with measurement of the live time. The count rate of coincident events between radiation detectors operating in parallel is measured, the time fluctuations of the coincident events are converted into digital form, and the extendible dead time method is used with measurement of the live time to eliminate all the other correlated events which may occur in a given detector. The time distributions of the time intervals separating the pulses are recorded, and the count rate of the coincident events is measured using recorded time distributions. | 10-10-2013 |
20130282318 | ESTIMATION APPARATUS AND METHOD FOR ESTIMATING CLOCK SKEW - A method for estimating a clock skew between a first clock and a second clock. The method includes the steps of detecting the clock skew to generate a detection resultant signal representing the clock skew; and determining time unit of a signal processing process, and estimating the clock skew according to the time unit of the signal processing process and the detection resultant signal. | 10-24-2013 |
20130282319 | METHOD AND SYSTEM FOR THE ESTIMATION AND CANCELLATION OF MULTIPATH DELAY OF ELECTROMAGNETIC SIGNALS, IN PARTICULAR SSR REPLIES - A method and system for the estimation and correction of the multipath delay is described. The method comprising analyzing the distortion of the autocorrelation function of each single impulse received with that of an ideal impulse, deriving back the variation of the impulse parameters and estimating the effect of the multipart to be taken into account for compensation on the estimation of the time of arrival (TOA) of the electromagnetic signal. | 10-24-2013 |
20140005966 | METHOD AND SYSTEM FOR PERFORMING COMPLEX SAMPLING OF SIGNALS BY USING TWO OR MORE SAMPLING CHANNELS AND FOR CALCULATING TIME DELAYS BETWEEN THESE CHANNELS | 01-02-2014 |
20140032150 | SYSTEM FOR IMPROVING PROBABILITY OF TRANSIENT EVENT DETECTION - A test and measurement instrument provides for increased transient event detection by adjusting data sampling periods. The test and measurement instrument includes a data sampler for acquiring first sampled data and a data processor structured to process the first sampled data. The data processor operates during a first data processing period. Also included in the instrument is a sample time adjustor structured to allow a user to select a time for the data sampler to acquire second sampled data. The time for the data sampler to acquire the second sampled data occurs during the first data processing period. The time for acquiring the second sampled data may be determined by generating a probability distribution function, then applying the distribution function to the available times during the first data processing period that the second sample data may be collected. Methods of use of the test and measurement instrument are also provided. | 01-30-2014 |
20140188419 | METHOD FOR MEASURING THE WAVEFORM CAPTURE RATE OF PARALLEL DIGITAL STORAGE OSCILLOSCOPE - The present invention provides a method for measuring the waveform capture rate of parallel digital storage oscilloscope. On the basis of double pulse measurement, and in consideration of the asymmetry of acquisition and the refreshing time of parallel DSO, the present invention provides a step amplitude-frequency combined pulse measurement to measure the time for waveform acquisition and mapping T | 07-03-2014 |
20150051858 | PULSE FREQUENCY MEASUREMENT DEVICE AND METHOD AND CONTROL SYSTEM - The present invention discloses a pulse frequency measurement device and method and a control system, the device including: a hardware counter configured to perform a counting operation on an input pulse sequence to output a counting result; and a processing unit configured to obtain number of pulses from the counting result outputted by the hardware counter and measure a first time period during which the obtained number of pulses occupy, in which the processing unit includes a frequency calculation module configured to calculate a frequency of the input pulse sequence based on the obtained number of pulses and the first time period. According to the invention, it is possible to achieve adaptive pulse frequency measurement and multi-channel sampling for multiple input pulse sequences with a relatively low cost while ensuring the accuracy of the measurement result. | 02-19-2015 |
20150081239 | METHOD, SYSTEMS AND/OR DEVICE FOR ADJUSTING EXPECTED RECEIVED SIGNAL STRENGTH SIGNATURE VALUES - Disclosed are systems, methods and devices for application of determining position information for mobile devices. In specific implementations, measurement of a signal travel time and a signal's strength may be combined to characterize a transmission power of the signal's transmitter. The characterized transmission power may be applied to affect expected signal strength signature values for use of the signal's transmitter may be updated in order to enhance a location based service where location may be effected by accuracy of a transmitter's power. | 03-19-2015 |
20150142359 | LUMINAIRE ASSOCIATE STATUS TRANSPONDER - Monitoring street lighting infrastructure using special signaling devices and techniques for locating key components of the infrastructure and assessing their status. The integrity of common powerline connections may also be assessed. | 05-21-2015 |
20150362541 | CIRCUIT AND METHOD FOR BANDWIDTH MEASUREMENT - A circuit for measuring a bandwidth of an amplifier includes a switch-capacitor circuit and a controller. The switch-capacitor circuit is coupled to an output and an input of the amplifier. The switch-capacitor circuit is switchable between a sampling mode and an amplification mode. The controller is coupled to the switch-capacitor circuit and the output of the amplifier. The controller is configured to switch the switch-capacitor circuit between the sampling mode and the amplification mode, control the amplification mode to have various durations, and determine the bandwidth of the amplifier based on the various durations of the amplification mode and corresponding voltages at the output of the amplifier. | 12-17-2015 |
20160011283 | ACCELERATING FIRST ORDER REVERSAL CURVE DISTRIBUTION MEASURMENTS | 01-14-2016 |
20160047842 | SIGNAL ACQUISITION PROBE STORING COMPRESSED OR COMPRESSED AND FILTERED TIME DOMAIN IMPULSE OR STEP RESPONSE DATA FOR USE IN A SIGNAL MEASUREMENT SYSTEM - A signal acquisition probe stores compressed or compressed and filtered time domain data samples representing at least one of an impulse response or step response characterizing the signal acquisition probe. The compressed or compressed and filtered time domain data samples of the impulse response or the step response are provided to a signal measurement instrument for compensating the signal measurement instrument for the impulse or step response of the signal measurement instrument. | 02-18-2016 |