| Entries |
| Document | Title | Date |
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| 20080206949 | APPARATUS FOR FORMING CONDUCTOR, METHOD FOR FORMING CONDUCTOR, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A conductor forming apparatus includes a reaction container having housed therein a processing target on a surface of which a recess in which a conductor is to be provided is formed, and a process for providing the conductor in the recess being carried out inside the container after a supercritical fluid dissolved with a metal compound is supplied into the container, a supply device which supplies the fluid from an outside to the inside of the container, and a discharge device which discharges the fluid that is not submitted for the process from the inside to the outside of the container, wherein while an amount of the fluid in the container is adjusted by continuously supplying the fluid into the container by the supply device and continuously discharging the fluid that is not submitted for the process to the outside of the container by the discharge device. | 08-28-2008 |
| 20080213967 | TRENCH CAPACITOR AND METHOD FOR MANUFACTURING THE SAME - Method of manufacturing a trench capacitor includes providing a substrate having a memory array region and a logic region, performing a shallow trench isolation (STI) process for forming at least a STI in the substrate within each of the memory array regions and the logic regions, forming a patterned hard mask and the hard mask exposing a portion of the STI and a portion of the substrate surrounding the STI on the substrate, performing a first etching process to form first deep trenches through the patterned hard mask, performing a second etching process to form second deep trenches extending downwardly from the first deep trenches respectively, and forming a capacitor structure in each of the first deep trenches and the second deep trenches. | 09-04-2008 |
| 20080227263 | Semiconductor device and method for fabricating the same - A semiconductor device of the present invention includes a plurality of lower electrodes covering the entire surfaces of a plurality of trenches formed in a first interlayer insulating film, a capacitive insulating film covering the entire surfaces of the plurality of lower electrodes, and an upper electrode covering the surfaces of the plurality of lower electrodes from above with the capacitive insulating film interposed between the upper electrode and the plurality of lower electrodes. The upper electrode is formed with a stress-relieving part, such as a crack, a notch or a recess. | 09-18-2008 |
| 20080233705 | METHOD FOR SELECTIVELY FORMING ELECTRIC CONDUCTOR AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for selectively forming an electric conductor, the method including disposing a processing target and a metal compound in an atmosphere including a supercritical fluid, the processing target having formed thereon at least one recess for providing an electric conductor, the metal compound including a metal serving as a main component of the electric conductor, and dissolving at least part of the metal compound in the supercritical fluid, selectively introducing the metal compound dissolved in the supercritical fluid into the recess in contact with a surface of the processing target, and coagulating in the recess the metal compound introduced into the recess to precipitate the metal from the metal compound, and coagulating the metal precipitated in the recess, thereby providing the electric conductor in the recess. | 09-25-2008 |
| 20080248625 | METHODS FOR ENHANCING TRENCH CAPACITANCE AND TRENCH CAPACITOR - Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost. | 10-09-2008 |
| 20080268605 | Capacitors and methods with praseodymium oxide insulators - Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties. | 10-30-2008 |
| 20080274602 | METHOD OF MANUFACTURING DYNAMIC RANDOM ACCESS MEMORY - A method of manufacturing a DRAM includes firstly providing a substrate. Many transistors are then formed on the substrate. Next, a first and a second LPCs are formed between the transistors. A first dielectric layer is then formed on the substrate, and a first opening exposing the first LPC is formed in the first dielectric layer. Thereafter, a barrier layer is formed on the first dielectric layer. Afterwards, a BLC is formed in the first opening, and a BL is formed on the first dielectric layer. A liner layer is then formed on a sidewall of the BL. Next, a second dielectric layer having a dry etching rate substantially equal to that of the liner layer and having a wet etching rate larger than that of the liner layer is formed on the substrate. Finally, an SNC is formed in the first and the second dielectric layers. | 11-06-2008 |
| 20080305604 | DEEP TRENCH AND FABRICATING METHOD THEREOF, TRENCH CAPACITOR AND FABRICATING METHOD THEREOF - A method of fabricating a deep trench is provided, by which a trench is formed in the substrate initially. Then, a block layer is formed on the substrate surface of the upper portion of the trench. After that, a pad oxide layer is formed on the substrate surface of the lower portion of the trench. Next, a plurality of hemispherical silicon grains is formed on the substrate and exposes a portion of the pad oxide layer. Then, by using the hemispherical silicon grains as a mask, a portion of the pad oxide layer is removed so as to form a patterned pad oxide layer. Continually, the hemispherical silicon grains and the substrate exposed by the patterned pad oxide layer are removed. Finally, the patterned pad oxide layer is removed. | 12-11-2008 |
| 20080318388 | METHOD FOR FABRICATING MOS TRANSISTOR WITH RECESS CHANNEL - A method for fabricating a MOS transistor with a recess channel, including: providing a substrate with a plurality of trench capacitors therein, wherein a trench top oxide is positioned on top of each trench capacitor and extended away from the substrate surface; forming a first spacer on side walls of the trench top oxide; forming a second spacer on the first spacer; defining a plurality of active areas, wherein each of the active areas is parallel with each other and comprises at least two of the trench capacitors; forming an isolation area between each of the active area; etching the substrate of the active area by using the second spacer as a mask to form a trench in the active area; removing the second spacer to expose a portion of the substrate, and etching the exposed substrate to enlarge the trench; and forming a gate structure in the trench. | 12-25-2008 |
| 20090004808 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a capacitor includes forming a sacrificial layer having a plurality of trenches on an upper portion of a substrate, forming storage nodes in the trenches, exposing upper portions of the storage nodes by removing a portion of the sacrificial layer, forming supporters to support the exposed upper portions of the storage nodes, removing the sacrificial layer under the supporters, and removing the supporters. | 01-01-2009 |
| 20090061588 | METHOD FOR FABRICATING DYNAMIC RANDOM ACCESS MEMORY - A method for fabricating a dynamic random access memory is provided. A substrate having two trench capacitors therein is provided, an isolation structure protruding from a surface of the substrate is formed on each trench capacitor, a spacer is formed on the substrate at two sides of each of the isolation structures, and a block layer is formed between each spacer and each isolation structure and between each spacer and the substrate. A trench is formed in the substrate between the trench capacitors, and partial of the trench is located under partial of the spacers and partial of the block layer. The spacers, the block layer, and partial of the isolation structures above the trench are removed. A gate structure protruding from the surface of the substrate is formed in the trench. A doped region is formed in the substrate at each of two sides of the gate structure. | 03-05-2009 |
| 20090061589 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING CYLINDER-TYPE CAPACITOR STRUCTURE - A method of manufacturing a semiconductor device includes forming an inter-layer insulating film; arranging a plurality of grooves in a surface layer of the inter-layer insulating film; forming embedded insulating films which are embedded in the grooves; arranging a plurality of holes in the inter-layer insulating film and between the embedded insulating films, in a manner such that each hole between the embedded insulating films partially overlaps therewith; forming lower electrodes, each of which has a bottom and a side face, and covers the bottom and side faces of the corresponding hole; forming a capacitance insulating film which covers the lower electrodes; and forming an upper electrode which further covers the capacitance insulating film. | 03-05-2009 |
| 20090068813 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity. | 03-12-2009 |
| 20090068814 | Semiconductor Devices Including Capacitor Support Pads and Related Methods - A semiconductor device may include a semiconductor substrate and a plurality of first capacitor electrodes arranged in a plurality of parallel lines on the semiconductor substrate with each of the first capacitor electrodes extending away from the semiconductor substrate. A plurality of capacitor support pads may be provided with each capacitor support pad being connected to first capacitor electrodes of at least two adjacent parallel lines of the first capacitor electrodes and with adjacent capacitor support pads being spaced apart. A dielectric layer may be provided on each of the first capacitor electrodes, and a second capacitor electrode may be provided on the dielectric layer so that the dielectric layer is between the second capacitor electrode and each of the first capacitor electrodes. Related methods are also discussed. | 03-12-2009 |
| 20090075448 | Method of Forming Inside Rough and Outside Smooth HSG Electrodes and Capacitor Structure - A container capacitor and method of forming the container capacitor are provided. The container capacitor comprises a lower electrode fabricated by forming a layer of doped polysilicon within a container in an insulative layer disposed on a substrate; forming a barrier layer over the polysilicon layer within the container; removing the insulative layer to expose the polysilicon layer outside the container; nitridizing the exposed polysilicon layer at a low temperature, preferably by remote plasma nitridation; removing the barrier layer to expose the inner surface of the polysilicon layer within the container; and forming HSG polysilicon over the inner surface of the polysilicon layer. The capacitor can be completed by forming a dielectric layer over the lower electrode, and an upper electrode over the dielectric layer. The cup-shaped bottom electrode formed within the container defines an interior surface comprising HSG polysilicon, and an exterior surface comprising smooth polysilicon. | 03-19-2009 |
| 20090087957 | Method of fabricating semiconductor device - Photoresist on a metal is removed with less oxidation of the metal surface by the invented ashing. During process, the matching of oxygen gas ratio and wafer temperature under downstream plasma which means no RF bias plasma is controlled for oxidation amount not to depend on ashing time with required photo resist rate in manufacturing. | 04-02-2009 |
| 20090104747 | METHOD FOR FABRICATING DEEP TRENCH DRAM ARRAY - A method for fabricating deep trench DRAM array is disclosed. A substrate having thereon a memory array area is provided. An array of deep trench patterns is formed in the memory array area. The deep trench (DT) capacitor patterns include first dummy DT patterns in a first column, second dummy DT patterns in a first row and a plurality of effective DT capacitor patterns. Each of the first dummy DT patterns has an extended width (W) along a first direction, which is greater than or equal to a photomask's shift tolerance. Each of the second dummy DT patterns has an extended length (L) along a second direction, which is greater than or equal to the photomask's shift tolerance. The first direction is normal to the second direction. | 04-23-2009 |
| 20090104748 | METHOD FOR FABRICATING SELF-ALIGNED RECESS GATE TRENCH - A method for forming a recess gate trench includes a plurality of trench capacitors formed into a substrate having thereon a pad layer. A portion of the trench top oxide layer of each trench capacitor is etched away to form a hole. The hole is filled with a silicon layer that is coplanar with the pad layer. Shallow trench isolation (STI) structure is formed. A portion of the STI structure is etched away. The pad layer is then stripped. A spacer is formed on a sidewall of the silicon layer. A gate trench is then etched into the substrate in a self-aligned fashion. | 04-23-2009 |
| 20090111235 | Semiconductor Integrated Circuit Devices Having High-Q Wafer Back-Side Capacitors - Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit. | 04-30-2009 |
| 20090162986 | Copolymers, polymer resin composition for buffer layer method of forming a pattern using the same and method of manufacturing a capacitor using the same - The invention is directed to particular polymer compositions that may be generally characterized by the formula: | 06-25-2009 |
| 20090170274 | METHOD OF FORMING METAL TRENCH PATTERN IN THIN-FILM DEVICE - A method of forming a metal trench pattern in a thin-film device includes a step of depositing an electrode film on a substrate or on a base layer, a step of forming a resist pattern layer having a trench forming portion used to make a trench pattern, on the deposited electrode film, a step of forming a metal layer for filling spaces in the trench forming portion and for covering the trench forming portion, by performing plating through the formed resist pattern layer using the deposited electrode film as an electrode, a step of planarizing at least a top surface of the formed metal layer until the trench forming portion of the resist pattern layer is at least exposed, and a step of removing the exposed trench forming portion of the resist pattern layer. | 07-02-2009 |
| 20090191685 | METHOD FOR FORMING CAPACITOR IN DYNAMIC RANDOM ACCESS MEMORY - A method for forming a capacitor in a dynamic random access memory, comprising steps of: providing a semiconductor substrate having at least a transistor, whereon an interlayer dielectric layer having at least a first plug is formed so that the first plug is connected to the drain of the transistor; depositing an etching stop layer on the first plug and the interlayer dielectric layer; depositing a first insulating layer on the etching stop layer; forming at least a second plug on the first insulating layer and the etching stop layer so that the second plug is connected to the first plug; depositing a second insulating layer on the first insulating layer and the second plug; forming at least a mold cavity in the second insulating layer so that the aperture of the mold cavity is larger than the diameter of the second plug and there is a deviation between the mold cavity and the second plug; removing the first insulating layer in the mold cavity until the etching stop layer; depositing a first electrode layer to cover the second insulating layer, a sidewall portion of the mold cavity, the second plug and the etching stop layer; removing the second insulating layer so that the first electrode layer forms a single open-ended cavity; and depositing a dielectric layer and a second electrode layer. | 07-30-2009 |
| 20090197384 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a semiconductor memory device. The semiconductor memory device is provided with an insulator and a capacitor. The capacitor is provided with a lower electrode provided with an inner portion and an outer portion, a dielectric portion on the lower electrode, and an upper electrode on the dielectric portion. The inner portion is provided with a lower part and an upper part upwardly extending from the lower part. The insulator laterally holds the lower part. The outer portion is arranged on the insulator and is electrically connected with the upper part. | 08-06-2009 |
| 20090221126 | Method of Fabricating Capacitor of Semiconductor Device - Disclosed herein is a method of fabricating a capacitor of a semiconductor device that includes sequentially forming an interlayer insulating film defining a contact plug, a lower electrode oxide film, and a hard mask film over a semiconductor substrate; etching the hard mask film with a mask comprising a dummy pattern and a cell pattern to form a hard mask pattern wherein a first trench is formed in a dummy pattern region and a second trench is formed in a cell pattern region; forming a capping film that buries the first trench; and etching the lower electrode oxide film with the capping film and the hard mask pattern as a mask to form a lower electrode trench that exposes the contact plug. | 09-03-2009 |
| 20090258469 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a carbon-containing film having electrical conductivity is formed so as to cover a first insulating film, a discharge plug and a conductor plug. A first conductive film is formed so as to pass through the carbon-containing film and to be in contact with the conductor plug. The first conductive film is exposed by removing the carbon-containing film. | 10-15-2009 |
| 20090258470 | Method of Manufacturing a Semiconductor Device Using an Atomic Layer Deposition Process - Methods of manufacturing a semiconductor device include forming an absorption layer on a surface of a substrate by exposing the surface of the substrate to a first reaction gas at a first temperature. A metal oxide layer is then formed on the surface of the substrate by exposing the absorption layer to a second reaction gas at a second temperature. The first reaction gas may include a precursor containing zirconium (e.g., tetrakis(ethylmethylamino)zirconium) and the second reaction gas may include an oxidizing agent. | 10-15-2009 |
| 20090280617 | FABRICATING PROCESS FOR SUBSTRATE WITH EMBEDDED PASSIVE COMPONENT - A fabricating process for a substrate with an embedded passive component is provided. The fabricating process includes the following steps. First, a substrate including a top conductive layer, a bottom conductive layer, and at least a dielectric layer is provided. The top conductive layer and the bottom conductive layer are separately disposed on a top surface and a bottom surface of the dielectric layer. Next, a plurality of plating through holes is formed in the substrate. Then, the top and the bottom conductive layers are patterned to form a patterned top conductive layer and a patterned bottom conductive layer separately, and the dielectric layer is exposed in part. The patterned top conductive layer and the patterned bottom conductive layer have many traces and many trenches formed by the traces. Thereafter, the trenches are filled with a material, wherein the traces and the material are adapted for forming the passive component. | 11-12-2009 |
| 20100022065 | DEEP TRENCH DEVICE WITH SINGLE SIDED CONNECTING STRUCTURE AND FABRICATION METHOD THEREOF - A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed. | 01-28-2010 |
| 20100029055 | METHOD OF MANUFACTURING A DUAL CONTACT TRENCH CAPACITOR. - A method of manufacturing a dual contact trench capacitor is provided. The method includes forming a first plate provided within a trench and isolated from a wafer body by a first insulator layer formed in the trench. The method further includes forming a second plate provided within the trench and isolated from the wafer body and the first plate by a second insulator layer formed in the trench. | 02-04-2010 |
| 20100029056 | METHOD OF MANUFACTURING A DUAL CONTACT TRENCH CAPACITOR - A method of manufacturing a dual contact trench capacitor is provided. The method includes a first plate extending from a trench and isolated from a wafer body, and forming a second plate extending from the trench and isolated from the wafer body and the first plate. | 02-04-2010 |
| 20100041203 | Structure, Design Structure and Method of Manufacturing a Structure Having VIAS and High Density Capacitors - A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate. | 02-18-2010 |
| 20100047991 | HIGH-K DIELECTRIC FILM, METHOD OF FORMING THE SAME AND RELATED SEMICONDUCTOR DEVICE - A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content. | 02-25-2010 |
| 20100055861 | METHOD FOR FABRICATING CAPACITOR IN SEMICONDUCTOR DEVICE - A method for fabricating a capacitor in a semiconductor device includes forming an insulation layer over a substrate, forming a storage node contact plug passing through the insulation layer and coupled to the substrate, recessing the storage node contact plug to a certain depth to obtain a sloped profile, forming a barrier metal over the surface profile of the recessed storage node contact plug, forming a sacrificial layer over the substrate structure, etching the sacrificial layer to form an opening exposing the barrier metal, forming a bottom electrode over the surface profile of the opening, and removing the etched sacrificial layer. | 03-04-2010 |
| 20100081248 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises forming a first plate electrode that defines a storage node region over a semiconductor substrate, forming a first dielectric film at sidewalls of the storage node region, forming a storage node over the storage node region, and forming a second dielectric film and a second plate electrode over the resulting structure, thereby preventing collapse of the storage node and also preventing generation of defects by electric short between capacitors. | 04-01-2010 |
| 20100093149 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A conductive film is formed to extend from a bottom and a sidewall of a recess formed in an interlayer insulating film onto a top surface of the interlayer insulating film. Dry etching of the conductive film is performed such that a portion of the conductive film remains on the bottom and sidewall of the recess. The dry etching is also performed such that a deposition film is formed on a top portion of the recess. | 04-15-2010 |
| 20100112776 | APPARATUS FOR FORMING CONDUCTOR, METHOD FOR FORMING CONDUCTOR, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A conductor forming apparatus includes a reaction container having housed therein a processing target on a surface of which a recess in which a conductor is to be provided is formed, and a process for providing the conductor in the recess being carried out inside the container after a supercritical fluid dissolved with a metal compound is supplied into the container, a supply device which supplies the fluid from an outside to the inside of the container, and a discharge device which discharges the fluid that is not submitted for the process from the inside to the outside of the container, wherein while an amount of the fluid in the container is adjusted by continuously supplying the fluid into the container by the supply device and continuously discharging the fluid that is not submitted for the process to the outside of the container by the discharge device. | 05-06-2010 |
| 20100124811 | Method for fabricating capacitor in semiconductor device - A method for fabricating a capacitor in a semiconductor device includes forming a sacrificial layer over a substrate, forming an opening by selectively etching the sacrificial layer, forming a conductive layer for a lower electrode over a whole surface of a resultant structure including the opening, forming the lower electrode by performing a first blanket dry etching process on the conductive layer until the sacrificial layer is exposed, etching the sacrificial layer to a predetermined depth to protrude a top of the lower electrode over the sacrificial layer, and performing a second blanket dry etching process on the lower electrode to remove a hornlike part on top of the lower electrode. Since a blanket dry etching is performed twice, it is possible to easily remove a hornlike part of a lower electrode and prevent a device failure induced by a micro-bridge between adjacent lower electrodes. | 05-20-2010 |
| 20100178747 | Minimum Cost Method for Forming High Density Passive Capacitors for Replacement of Discrete Board Capacitors Using a Minimum Cost 3D Wafer-to-Wafer Modular Integration Scheme - Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed. | 07-15-2010 |
| 20100240190 | METHOD FOR FABRICATING DEEP TRENCH CAPACITOR - A method for fabricating the deep trench capacitor is described as follows. A substrate of a first conductivity type is provided, which includes a deep band region of a second conductivity type therein. A deep trench is formed in the substrate and through the deep band region. A collar oxide is then formed in an upper portion of the trench, wherein at least a portion of the deep band region is exposed. A bottom electrode, a capacitor dielectric layer and a top electrode are formed in the trench sequentially. | 09-23-2010 |
| 20100240191 | METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A CAPACITOR - A method of forming a semiconductor device includes forming a lower electrode layer on a substrate, forming a surface oxide layer on the lower electrode layer, partially removing the lower electrode layer to form a lower electrode, removing the surface oxide layer to expose the lower electrode, forming a capacitor dielectric layer on the lower electrode, and forming an upper electrode on the capacitor dielectric layer. | 09-23-2010 |
| 20100261331 | Methods Of Forming A Plurality Of Capacitors - The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node locations. Insulative material is deposited over the first material laterally about sidewalls of the projecting pillars, and is anisotropically etched effective to expose underlying first material and leave electrically insulative material received laterally about the sidewalls of the projecting pillars. Openings are formed within a second material to the pillars. The pillars are etched from the substrate through the openings in the second material, and individual capacitor electrodes are formed within the openings in electrical connection with the storage node locations. The individual capacitor electrodes have the anisotropically etched insulative material received laterally about their outer sidewalls. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other implementations and aspects are contemplated. | 10-14-2010 |
| 20100317171 | Method of Manufacturing a Capacitor - An etching composition for preventing from leaning a capacitor contains hydrofluoric acid (HF), ammonium fluoride (NH | 12-16-2010 |
| 20110021001 | Vapor Deposition Methods for Forming a Metal-Containing Layer on a Substrate - Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as described herein can form a strontium titanate layer that has low carbon content (e.g., low strontium carbonate content), which can result in layer with a high dielectric constant. | 01-27-2011 |
| 20110027962 | TRENCH DECOUPLING CAPACITOR FORMED BY RIE LAG OF THROUGH SILICON VIA (TSV) ETCH - A trench decoupling capacitor is formed using RIE lag of a through silicon via (TSV) etch. A method includes etching a via trench and a capacitor trench in a wafer in a single RIE process. The via trench has a first depth and the capacitor trench has a second depth less than the first depth due to RIE lag. | 02-03-2011 |
| 20110039393 | METHOD OF FABRICATING A SEMICONDUCTOR MICROSTRUCTURE - Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer. | 02-17-2011 |
| 20110065253 | MANUFACTURING METHOD FOR DOUBLE-SIDE CAPACITOR OF STACK DRAM - A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors. | 03-17-2011 |
| 20110070716 | MANUFACTURING METHOD OF CAPACITOR IN SEMICONDUCTOR DEVICE - Example embodiment is provided to a method for manufacturing a semiconductor device, including forming a hard mask layer on a buried bit line and forming a storage node contact hole by using the selectivity between an interlayer insulating layer and the hard mask layer, thereby forming a contact hole using a mask of a line pattern instead of a hole pattern. Accordingly, a mask for the contact hole can be easily fabricated and the contact area can be maximized, thereby reducing the contact resistance. | 03-24-2011 |
| 20110086489 | METHODS OF MANUFACTURING A HYBRID ELECTRICAL CONTACT - Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact. | 04-14-2011 |
| 20110092043 | DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP - A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall. | 04-21-2011 |
| 20110097869 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING MIM CAPACITOR AND METHOD OF FABRICATING THE SAME - In a semiconductor integrated circuit device and a method of formation thereof, a semiconductor device comprises: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, the conductive layer pattern being patterned from a common conductive layer, the conductive layer pattern including a first pattern portion on the insulator in the insulator region and a second pattern portion on the substrate in an active region of the substrate, wherein the second pattern portion comprises a gate of a transistor in the active region; and a capacitor on the insulator in the insulator region, the capacitor including: a lower electrode on the first pattern portion of the conductive layer pattern, a dielectric layer pattern on the lower electrode, and an upper electrode on the dielectric layer pattern. | 04-28-2011 |
| 20110165755 | Semiconductor Component Arrangement Comprising a Trench Transistor - Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps. | 07-07-2011 |
| 20110256686 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole. | 10-20-2011 |
| 20110294277 | METHODS FOR MANUFACTURING MULTILAYER WAFERS WITH TRENCH STRUCTURES - The present invention provides methods for the manufacture of a trench structure in a multilayer wafer that comprises a substrate, an oxide layer on the substrate and a semiconductor layer on the oxide layer. These methods include the steps of forming a trench through the semiconductor layer and the oxide layer and extending into the substrate, and of performing an anneal treatment of the formed trench such that at the inner surface of the trench some material of the semiconductor layer flows at least over a portion of the part of the oxide layer exposed at the inner surface of the trench. Substrates manufactured according to this invention are advantageous for fabricating various semiconductor devices, e.g., MOSFETs, trench capacitors, and the like. | 12-01-2011 |
| 20110318899 | Methods of Forming Capacitors - Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O | 12-29-2011 |
| 20120015494 | METHOD FOR FABRICATING BOTTOM ELECTRODE OF CAPACITORS OF DRAM - A method for manufacturing a capacitor bottom electrode of a dynamic random access memory is provided. The method comprises providing a substrate having a memory cell region and forming a polysilicon template layer on the memory cell region of the substrate. A supporting layer is formed on the polysilicon template layer and plural openings penetrating through the supporting layer and the polysilicon template layer are formed and a liner layer is formed on at least a portion of the polysilicon template layer exposed by the openings A conductive layer substantially conformal to the substrate is formed on the substrate. A portion of the conductive layer on the supporting layer is removed so as to form plural capacitor bottom electrodes. Using the polysilicon template layer, the openings with relatively better profiles are formed and the dimension of the device can be decreased. | 01-19-2012 |
| 20120083092 | STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM - A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures. | 04-05-2012 |
| 20120129314 | METHOD AND RESULTING STRUCTURE FOR DEEP TRENCH POLYSILICON HARD MASK REMOVAL - A method of forming a capacitor structure includes forming a pad oxide layer overlying a substrate, a nitride layer overlying the pad oxide layer, an interlayer dielectric layer overlying the nitride layer, and a patterned polysilicon mask layer overlying the interlayer dielectric layer. The method then applies a first RIE process to form a trench region through a portion of the interlayer dielectric layer using the patterned polysilicon mask layer and maintaining the first RIE to etch through a portion of the nitride layer and through a portion of the pad oxide layer. The method stops the first RIE when a portion of the substrate has been exposed. The method then forms an oxide layer overlying the exposed portion of the substrate and applies a second RIE process to continue to form the trench region by removing the oxide layer and removing a portion of the substrate to a predetermined depth. | 05-24-2012 |
| 20120149169 | METHOD FOR MANUFACTURING MASK - Openings are formed in first and second mask layers. Next, diameter of the opening in the second mask layer is enlarged so that the diameter of the opening in the second mask layer becomes larger by a length X than diameter of the opening in the first mask layer. Thereafter, mask material is formed into the opening in the second mask layer, to form a cavity with a diameter X within the opening in the second mask layer. There is formed a mask which includes the second mask layer and the mask material having therein opening including the cavity. | 06-14-2012 |
| 20120190166 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD FOR FORMING HARD MASK - A method for manufacturing a semiconductor device comprises forming a base film on a semiconductor substrate, forming an amorphous carbon film on the base film, forming a pattern of the amorphous carbon film, and etching the base film using the amorphous carbon film as a mask. The film density of the amorphous carbon film is reduced from surface of the amorphous carbon film to face of the amorphous carbon film adjacent to the base film. | 07-26-2012 |
| 20120208340 | METHODS OF FABRICATING A STORAGE NODE IN A SEMICONDUCTOR DEVICE AND METHODS OF FABRICATING A CAPACITOR USING THE SAME - A storage node is formed in a semiconductor device by forming an interlayer insulation layer on a substrate, forming an etch stop layer and a first sacrificial layer on the interlayer insulation layer, patterning the first sacrificial layer and the etch stop layer to form a first sacrificial layer pattern and an etch stop layer pattern that define a storage node contact hole, forming a recessed first storage node conductive pattern that conformally covers a lower sidewall and a bottom surface of the storage node contact hole, forming a second storage node conductive pattern that includes a first portion surrounded by the recessed first storage node conductive pattern and a second portion conformally covering an upper sidewall of the storage node contact hole, and removing the first sacrificial layer pattern. The recessed first storage node conductive pattern and the second storage node conductive pattern constitute a storage node. | 08-16-2012 |
| 20120289021 | METAL-INSULATOR-METAL STRUCTURE FOR SYSTEM-ON-CHIP TECHNOLOGY - The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer. | 11-15-2012 |
| 20120302030 | METHOD OF FABRICATING A DEEP TRENCH DEVICE - A method of fabricating a deep trench capacitor includes the steps as follows. Firstly, a substrate having a trench therein is provided. Then, a bottom electrode is formed in the substrate around the trench. Later, a capacitor dielectric layer is formed to surround an inner sidewall of the trench. After that, a first conductive layer is form to fill up the trench. Subsequently, a material layer is formed on the substrate. Later, a hole is formed in the material layer, wherein the hole is directly above the trench. Finally, a second conductive layer is form to fill in the hole. | 11-29-2012 |
| 20130040436 | THROUGH SUBSTRATE VIA WITH EMBEDDED DECOUPLING CAPACITOR - A method of manufacturing a semiconductor die having a substrate with a front side and a back side includes fabricating openings for through substrate vias on the front side of the semiconductor die. The method also includes depositing a first conductor in the through substrate vias, depositing a dielectric on the first conductor and depositing a second conductor on the dielectric. The method further includes depositing a protective insulator layer on the back side of the substrate covering the through substrate vias. | 02-14-2013 |
| 20130102123 | METHOD FOR FABRICATING SINGLE-SIDED BURIED STRAP IN A SEMICONDUCTOR DEVICE - A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess. | 04-25-2013 |
| 20130115749 | Semiconductor Package Having Passive Device and Method for Making the Same - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first capacitor, a first protective layer, a first metal layer and a second protective layer. The substrate has at least one via structure. The first capacitor is disposed on a first surface of the substrate. The first protective layer encapsulates the first capacitor. The first metal layer is disposed on the first protective layer, and includes a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced. | 05-09-2013 |
| 20130164905 | 3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY - The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided. | 06-27-2013 |
| 20130203233 | MANUFACTURING METHOD OF MEMORY CAPACITOR WITHOUT MOAT STRUCTURE - A manufacturing method of a memory capacitor without a moat structure includes the steps of: providing a semiconductor substrate defined with an array region and a peripheral region; forming a first oxidized layer on the array region; forming a second oxidized layer on the peripheral region; planarizing the first and the second oxidized layers; forming an insulating layer on the first and the second oxidized layers; forming a plurality of trenches on the array region, where the trenches pass through the first oxidized layer and the insulating layer on the first oxidized layer; forming a conductive layer on the side and base surfaces of each trench; removing a portion of the conductive layer and a portion of the insulating layer to form a plurality of notches to expose the first oxidized layer; and removing the first oxidized layers which are exposed from the notches. | 08-08-2013 |
| 20130203234 | HIGHLY SCALABLE TRENCH CAPACITOR - An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application. | 08-08-2013 |
| 20130252397 | MANUFACTURING METHOD FOR HIGH CAPACITANCE CAPACITOR STRUCTURE - A manufacturing method of a capacitor structure is provided, which includes the steps of: on a substrate having a first oxide layer, (a) forming a first suspension layer on the first oxide layer; (b) forming a first shallow trench into the first oxide layer above the substrate; (c) forming a second oxide layer filling the first shallow trench; (d) forming a second suspension layer on the second oxide layer; (e) forming a second shallow trench through the second suspension layer into the second oxide layer above the first suspension layer; (f) forming at least one deep trench on the bottom surface of the second shallow trench through the second and the first oxide layers, (g) forming an electrode layer on the inner surface of the deep trench; and (h) removing the first and second oxide layers through the trench openings in the first and the second suspension layers. | 09-26-2013 |
| 20130252398 | Methods for Forming Semiconductor Constructions, and Methods for Selectively Etching Silicon Nitride Relative to Conductive Material - The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl | 09-26-2013 |
| 20130260529 | METHODS OF FORMING CAPACITORS AND SEMICONDUCTOR DEVICES INCLUDING A RUTILE TITANIUM DIOXIDE MATERIAL - Methods of forming a capacitor including forming at least one aperture in a support material, forming a titanium nitride material within the at least one aperture, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The support material may then be removed and the titanium nitride material may be oxidized to form a titanium dioxide material. A second conductive material may then be formed over an outer surface of the titanium dioxide material. | 10-03-2013 |
| 20140030864 | Method of eDRAM DT Strap Formation In FinFET Device Structure - The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors. | 01-30-2014 |
| 20140106536 | Cylindrical Embedded Capacitors - A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate. | 04-17-2014 |
| 20140120687 | Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process - In one aspect, a method of fabricating a memory cell capacitor includes the following steps. At least one trench is formed in a silicon wafer. A thin layer of metal is deposited onto the silicon wafer, lining the trench, using a conformal deposition process under conditions sufficient to cause at least a portion of the metal to self-diffuse into portions of the silicon wafer exposed within the trench forming a metal-semiconductor alloy. The metal is removed from the silicon wafer selective to the metal-semiconductor alloy such that the metal-semiconductor alloy remains. The silicon wafer is annealed to react the metal-semiconductor alloy with the silicon wafer to form a silicide, wherein the silicide serves as a bottom electrode of the memory cell capacitor. A dielectric is deposited into the trench covering the bottom electrode. A top electrode is formed in the trench separated from the bottom electrode by the dielectric. | 05-01-2014 |
| 20140120688 | DEEP ISOLATION TRENCH STRUCTURE AND DEEP TRENCH CAPACITOR ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE - Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions. | 05-01-2014 |
| 20140120689 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first insulating layer over a semiconductor substrate, a contact plug within the first insulating layer, an etch stop layer over the first insulating layer, and a second insulating layer over the etch stop layer. The second insulating layer has an opening over the contact plug. A first metal layer, a dielectric material, and a second metal layer are deposited in the opening. The first metal layer engages the contact plug and is free of direct contact with the first insulating layer. | 05-01-2014 |
| 20140154863 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming semiconductor device includes forming a landing pad, forming a stopping insulating layer on the landing pad, forming a lower molding layer including a first material on the stopping insulating layer, forming an upper molding layer including a second material different from the first material on the lower molding layer, forming a hole vertically passing through the upper molding layer and the lower molding layer and exposing the landing pad, forming a first electrode in the hole, removing the upper molding layer to expose a part of a surface of the first electrode, removing the lower molding layer to expose another part of the surface of the first electrode, forming a capacitor dielectric layer on the exposed parts of the surface of the first electrode, and forming a second electrode on the dielectric layer. | 06-05-2014 |
| 20140220758 | Method for Producing a Semiconductor Device with a Vertical Dielectric Layer - A method for producing a semiconductor device is disclosed. The method includes providing a semiconductor body having a first surface, and a second surface opposite the first surface, producing a first trench having a bottom and sidewalls and extending from the first surface into the semiconductor body, forming a dielectric layer along at least one sidewall of the trench, and filling the trench with a filling material. Forming the dielectric layer includes forming a protection layer on the least one sidewall such that the protection layer leaves a section of the at least one sidewall uncovered, oxidizing the semiconductor body in the region of the uncovered sidewall section to form a first section of the dielectric layer, removing the protection layer, and forming a second section of the dielectric layer on the at least one sidewall. | 08-07-2014 |
| 20140322890 | POLISHING SYSTEMS AND METHODS FOR REMOVING CONDUCTIVE MATERIAL FROM MICROELECTRONIC SUBSTRATES - Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material. | 10-30-2014 |
| 20140370684 | METHODS FOR FORMING SUB-RESOLUTION FEATURES IN SEMICONDUCTOR DEVICES - Methods of forming semiconductor devices and features in semiconductor device structures include conducting an anti-spacer process to remove portions of a first mask material to form first openings extending in a first direction. Another anti-spacer process is conducted to remove portions of the first mask material to form second openings extending in a second direction at an angle to the first direction. Portions of the second mask material underlying the first mask material at intersections of the first openings and second openings are removed to form holes in the second mask material and to expose a substrate underlying the second mask material. | 12-18-2014 |
| 20150044853 | THERMALLY STABLE HIGH-K TETRAGONAL HFO2 LAYER WITHIN HIGH ASPECT RATIO DEEP TRENCHES - A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %. | 02-12-2015 |
| 20150118821 | METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND METHODS OF FORMING CAPACITOR STRUCTURES - A method of forming a semiconductor device structure comprises forming a mold template comprising trenches within a mold material. Structures are formed within the trenches of the mold template. A wet removal process is performed to remove the mold template, a liquid material of the wet removal process remaining at least in spaces between adjacent pairs of the structures following the wet removal process. A polymer material is formed at least in the spaces between the adjacent pairs of the structures. At least one dry removal process is performed to remove the polymer material from at least the spaces between the adjacent pairs of the structures. Additional methods of forming a semiconductor device structure, and methods of forming capacitor structures are also described. | 04-30-2015 |
| 20150357402 | DT CAPACITOR WITH SILICIDE OUTER ELECTRODE AND/OR COMPRESSIVE STRESS LAYER, AND RELATED METHODS - Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; forming a metal-insulator-metal (MIM) stack within a portion of the deep trench, the MIM stack forming including forming an outer electrode by co-depositing a refractory metal and silicon into the deep trench; and filling a remaining portion of the deep trench with a semiconductor. | 12-10-2015 |
| 20160013263 | Methods of Forming Capacitors | 01-14-2016 |
| 20160027783 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - One production method for semiconductor devices includes sequentially forming a stopper film and a BPSG film, forming a cylinder etch laminated mask upon the BPSG film, forming openings having a prescribed pattern in the cylinder etch laminated mask, then, using same as a mask, forming a cylinder hole that pierces from the BPSG film to the stopper film in the thickness direction. Next, forming a conductive layer that adjoins the side surfaces of the BPSG film, the stopper film, and a polysilicon film being part of the cylinder etch laminated mask, then removing the polysilicon film and the BPSG film . | 01-28-2016 |
| 20160043164 | Capacitor and Method of Forming a Capacitor - A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode. | 02-11-2016 |
| 20160064277 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING NANOWIRES - Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes. | 03-03-2016 |
| 20160097121 | MULTIPLE VAPOR SOURCES FOR VAPOR DEPOSITION - A vapor deposition method and apparatus including at least two vessels containing a same first source chemical. A controller is programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels, each of the doses having a substantially consistent concentration of the first source chemical. The apparatus may also include at least two vessels containing a same second source chemical. The controller can be programmed to simultaneously pulse to the reaction space doses or pulses of a gas from the vessels containing the second source chemical, each of the doses having a substantially consistent concentration of the second source chemical. The second source chemical can be pulsed to the reaction space after the reaction space is purged of an excess of the first source chemical. | 04-07-2016 |
| 20180026040 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 01-25-2018 |
