| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 377077000 | Particular transfer means | 72 |
| 20080205582 | PROCESSING ELEMENT AND RECONFIGURABLE CIRCUIT INCLUDING THE SAME - A processing element includes a shift register including n stages of registers mutually connected in series. Data held among the n stages of registers is rotated in synchronization with a clock signal. A number-of-stages determining circuit determines the number of stages to be used among the n stages of registers. An output terminal of the register in the last stage connects to an input terminal of the register in the first stage. | 08-28-2008 |
| 20080219400 | Event Counter - A counting method and a counter using an integrated circuit memory area, including at least one step of storage of partial values in several words of identical memory sizes, the result of the counting being obtained by arithmetically adding the values contained in the different words. | 09-11-2008 |
| 20090180584 | DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LATCH DATA - The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register. | 07-16-2009 |
| 20110129052 | SHIFT REGISTER WITH TWO-WAY TRANSMISSION AND LIQUID CRYSTAL DISPLAY DEVICE USING SAME - A shift register includes individually connected shift register units. Each shift register unit includes a switching unit, a pre-charging unit, a pulse signal output unit, a low level voltage signal control unit, a first clock pulse signal input, a second clock pulse signal input, and an output. The first and the second clock pulse signal inputs respectively receive a first clock signal and a second clock signal, the first clock signal and the second clock signal having reverse clock pulses during each clock cycle. The switching unit receives at least one external starting signal and a high level signal, when the at least one external starting signal is high level, the switching unit is turned on and outputs the high level signal to the pre-charging unit. When the second clock signal is high level, the pre-charging unit receives the high level signal and charges, and when the first clock signal is high level, the pre-charging unit discharges. The pulse signal output unit receives the first clock signal and outputs the first clock signal to the output after the pre-charging unit charges and before the pre-charging unit finishes discharging. The low level voltage signal control unit receives the first clock signal and the second clock signal, after the pre-charging unit finishes discharging, the low level voltage signal control unit pulls down a voltage level on the output at low level when the second clock signal are high level. | 06-02-2011 |
| 20110142192 | SHIFT REGISTER CIRCUIT - A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal. | 06-16-2011 |
| 20110228893 | SHIFT REGISTER CIRCUIT - A shift register circuit includes a first transistor which supplies a clock signal to an output terminal, and an inverter which drives a second transistor for discharging a gate of the first transistor. An input node of the inverter is separated from the gate of the first transistor, and the gates of the first and second transistors are charged and discharged by separate circuits, respectively. | 09-22-2011 |
| 20120250816 | SHIFT REGISTER OF LCD DEVICES - A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage. | 10-04-2012 |
| 20130170607 | LEVEL SHIFTER, INVERTER CIRCUIT, AND SHIFT REGISTER - A level shifter includes: an input terminal to which an input voltage is applied; a capacitor; a first transistor provided between the input terminal and one of electrodes of the capacitor, and having a gate electrode connected to the other of the electrodes of the capacitor; a second transistor provided between the input terminal and the other electrode of the capacitor; a signal generating unit which generates a signal for switching the second transistor between conduction and non-conduction and supply the signal to the gate electrode of the second transistor, in a period when the input voltage is provided to the input terminal; and an output terminal for outputting a voltage at the other electrode of the capacitor which is level-shifted by a change in the second transistor to a non-conducting state in the period as an output voltage. | 07-04-2013 |
| 20140079176 | SHIFT REGISTER AND DRIVING METHOD THEREOF - A shift register includes an input terminal, an output terminal, a first clock signal terminal, a second clock signal terminal, a first level signal terminal, a second level terminal, a first capacitor and a second capacitor, and five transistors. The five transistors are controlled by first and second clock signals applied to the respective first and second signal terminals to shift a signal received from the input terminal to the output terminal with a half cycle period delay while maintaining a stable level of the shifted signal at the output terminal. | 03-20-2014 |
| 20150016585 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings. | 01-15-2015 |
| 20150043705 | SHIFT REGISTER UNIT, SHIFT REGISTER, ARRAY SUBSTRATE AND DISPLAY APPARATUS - The present disclosure relates to a field of display. Particularly, embodiments of the present invention disclose a shift register unit, a shift register, an array substrate and a display apparatus that enable the respective shift register units to be reset independently. The shift register unit includes a sampling part, an output part and a reset part, wherein the sampling part includes a first switching transistor and a second switching transistor, the output part includes a fifth switching transistor, a sixth switching transistor, a first capacitor and a second capacitor, and the reset part includes a third switching transistor and a fourth transistor. | 02-12-2015 |
| 20150371715 | SYSTEMS AND METHODS FOR ACOUSTIC WAVE ENABLED DATA STORAGE - The present disclosure provides systems and methods for storing, reading, and writing data using particle-based acoustic wave driven shift registers. The shift registers may physically shift particles along rows and/or columns of wells through the interactions of two parallel surfaces. A transducer may generate an acoustic wave to displace one or more of the two parallel surfaces. The particles may be transferred to and/or otherwise constrained by a buffer surface during at least a portion of the acoustic wave, such that the particles may be shifted during one or more cycles of the acoustic wave. In various embodiments, the amplitude of the acoustic wave may correspond to the spacing distance between each of the wells. The wells may be physical and/or potential wells. | 12-24-2015 |
| 377078000 | Phase clocking or synchronizing | 57 |
| 20080260090 | Shift register and shift registering apparatus - A shift register is provided for use in a data driver. The shift register includes a shift registering unit. The shift registering unit selectively receives a clock signal. The shift registering unit includes a flip-flop; and a first selection circuit. The first selection circuit selectively sends the clock signal to the flip-flop according to a first selection signal, wherein before the flip-flop receives a data signal that is enabled, the first selection circuit sends the clock signal to the flip-flop according to the first selection signal so that the flip-flop correctly outputs the enabled data signal according to the clock signal. | 10-23-2008 |
| 20080285705 | SHIFT REGISTER WITH INDIVIDUAL DRIVING NODE - A shift register having individual driving nodes is disclosed. The shift register includes a first clock pull-down module, a second clock pull-down module, a key pull-down module, a self feedback module, and a driving output unit. The first clock pull-down module is used to pull-down the potential of a gate line to a low voltage when the first clock signal is in a high voltage level. The second clock signal pull-down module pulls down the potential of the gate line to the low voltage when the second clock signal is in a high voltage level. The key pull-down module rapidly pulls down the potential of the gate line to the low voltage level after the gate line outputs an output signal. The self feedback module is used to output a driving signal to the key pull-down module. The driving signal output unit outputs a next stage driving signal which is irrelative to the operation of the previous stage shift register. | 11-20-2008 |
| 20090161813 | SEMICONDUCTOR DEVICE - In a semiconductor device including an N-line M-stage shift register circuit operated at high speed of, for example, several hundreds MHz. Input circuits input a common test pattern to each of pairs of shift registers in, for example, two lines out of the N lines. A plurality of outputs of the pairs of shift registers in the two lines are compared in comparators, and the comparison results are output. The N-line M-stage shift register circuit and the comparators are operated in synchronization with a clock signal at several hundreds MHz. Hence, even when the circuit scale (area) of the N-line M-stage shift register circuit is increased to involve apparent wiring delay, a defect in the shift register circuit can be detected at an actual speed. | 06-25-2009 |
| 20090185654 | Shift circuit capable of reducing current consumption by controlling latch operation - Disclosed is a shift circuit capable of reducing current consumption and circuit area and increasing the operation speed. The shift circuit includes a transfer unit for transferring input data to a first node in response to a clock signal, and a latch unit for latching the data on the first node in response to a clock signal. | 07-23-2009 |
| 20090245455 | SHIFT REGISTERS - A shift register including shift register units controlled by first and second clock signals for generating an output signal. For each unit, in an active period, the first driving device drives the first switch device to activate the output signal, and the second driving device provides a voltage signal according to the first clock signal to drive the first switch device to de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the voltage signal to serve as the output signal according to the second clock signal. In the active period, the voltage signal has a low level, and the first and second clock signals are set as alternating-current signals and are opposite to each other. In a blanking period, the voltage signal has a high level, and each of the first and second clock signals is set as a direct-current signal. | 10-01-2009 |
| 20090290677 | BOOTSTRAP CIRCUIT, SHIFT REGISTER EMPLOYING THE SAME AND DISPLAY DEVICE - Disclosed is a shift register which includes first transistor connected between a first clock signal terminal and an output terminal, a second transistor with a gate connected to an input terminal and a source connected to a gate of the first transistor, a third transistor with a gate connected to a second clock signal terminal, an inverter with an input connected to the input terminal, a fourth transistor cascode connected to the third transistor with a gate connected to an output of the inverter, a fifth transistor connected between the gate of the first transistor and a power supply terminal, a sixth transistor connected between the fourth transistor and the power supply terminal with a gate connected to the input terminal, and a seventh transistor connected between the output terminal and the power supply terminal, the fifth and seventh transistors having gates connected in common to a connection node of the fourth and the sixth transistors. | 11-26-2009 |
| 20100284508 | Systems and Methods for Signal Delay and Alignment - Various embodiments of the present invention provide systems and methods for event alignment control. For example, an event alignment control circuit is disclosed that includes a delay table, a flag write controller circuit, and a signal reconstruction circuit. The delay table includes at least a first register and a last register, and is operable to transfer data from the first register to the last register. The flag write controller circuit is operable to receive an indication of assertion of an event flag and to write information relevant to the event flag to the first register of the delay table. The signal reconstruction circuit is electrically coupled to the last register, and reconstructs the event flag based at least in part on the information relevant to the event flag obtained from the last register. | 11-11-2010 |
| 20110085635 | SHIFT REGISTER AND DISPLAY DEVICE AND DRIVING METHOD THEREOF - The power consumption of a shift register or a display device including the shift register is reduced. A clock signal is supplied to a shift register by a plurality of wirings, not by one wiring. Any one of the plurality of wirings supplies a clock signal in only part of the operation period of the shift register, not during the whole operation period of the shift register. Therefore, the capacity load caused with the supply of clock signals can be reduced, leading to reduction in power consumption of the shift register. | 04-14-2011 |
| 20110135050 | Electronic System with Shift Register - An electronic system including a shift register is disclosed. The shift register includes a first transistor, a first trigger circuit, a second transistor, and a second trigger circuit. The first transistor receives a first input signal. The first trigger circuit is serially connected to the first transistor between a first level and a second level and is connected with the first transistor in a first node. The second transistor receives a second input signal inverted to the first input signal. The second trigger circuit receives the level of the first node, is serially connected to the second transistor between a third level and the second level, and is connected with the second transistor in a second node. | 06-09-2011 |
| 20110158376 | SHIFT REGISTER - A shift register comprises a plurality of stages, {S | 06-30-2011 |
| 20110222645 | SCANNING LINE DRIVING CIRCUIT - Provided are a bi-directional scanning type gate line driving circuit that does not require a dummy unit shift register and a method of driving the same. In a gate line driving circuit including a multi-stage shift register capable of bi-directional shifting, a start pulse is input to a unit shift register at a first stage and a unit shift register at the last stage of the multi-stage shift register. In forward shifting, a clock signal supplied to the unit shift register at the last stage is kept at a deactivation level during a period from a time at which an activation period of an output signal of the unit shift register at the last stage ends to a time at which the start pulse is activated during a subsequent frame period. | 09-15-2011 |
| 20110317804 | PROGRAM VERIFY METHOD FOR OTP MEMORIES - A method for executing a program verify operation in a non-volatile memory. A data register having master and slave latching circuits is used for concurrently storing two different words of data. In a program operation, the master latch stores program data which is used for programming selected memory cells. In a program verify operation, the data programmed to the memory cells are read out and stored in the slave latches. In each data register stage, the logic states of both latches are compared to each other, and a status signal corresponding to a program pass condition is generated if opposite logic states are stored in both latches. The master latch in each stage is inverted if programming was successful, in order to prevent re-programming of that bit of data. | 12-29-2011 |
| 20120093276 | GATE-ON ARRAY SHIFT REGISTER - A gate-on array shift register includes a signal-input unit, a control transistor and at least three stable modules. The signal-input unit receives and outputs a previous-stage output signal. The control terminal of the control transistor is electrically coupled to the signal-input unit for receiving the previous-stage output signal. The control transistor outputs corresponding output signal on output terminal of the shift register according to the previous-stage output signal. Each of the stable modules is electrically coupled to the control terminal of the control transistor and the output terminal of the shift register to stabilize voltage of the terminals. | 04-19-2012 |
| 20120134460 | LAYOUT STRUCTURE OF SHIFT REGISTER CIRCUIT - An exemplary layout structure of a shift register circuit includes a first shift register and a second shift register arranged adjacent to the first shift register. The first shift register and the second shift register each receive a first signal and a second signal phase-inverted with respect to the first signal. Moreover, the first shift register and the second shift register share a common signal routing trace for receiving the first signal. The common signal routing trace is arranged extending into between the first shift register and the second shift register. | 05-31-2012 |
| 20140010341 | SHIFT REGISTER - A shift register for providing a plurality of gate signals includes an Nth stage shift register unit and an (N+1)th stage shift register unit. The Nth stage shift register unit includes a first pull up unit, a first driving unit, a first control unit and a first auxiliary pull down unit. The (N+1)th stage shift register unit includes a second pull up unit, a second driving unit, a first pull down unit and a second auxiliary pull down unit. The first and second pull up units are both coupled to the first and second driving units for controlling the first and second driving units to generate gate signals. The first and second auxiliary pull down units are both coupled to the first control unit for pulling down the gate signals. | 01-09-2014 |
| 20140056400 | DRIVER CIRCUIT, DISPLAY DEVICE INCLUDING THE DRIVER CIRCUIT, AND ELECTRONIC APPLIANCE INCLUDING THE DISPLAY DEVICE - An object of the present invention is to provide a driver circuit including a normally-on thin film transistor, which driver circuit ensures a small malfunction and highly reliable operation. The driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor. The first to third transistors each include a semiconductor layer of an oxide semiconductor and are depletion-mode transistors. An amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit. | 02-27-2014 |
| 377079000 | Field-effect transistor | 41 |
| 20080219401 | SHIFT REGISTER CIRCUIT AND IMAGE DISPLAY APPARATUS CONTAINING THE SAME - Threshold voltage shifts of transistors which are constituents of a bidirectional shift register are reduced to prevent a malfunction in the shift register. A bidirectional unit shift register includes first and second pull-down circuits ( | 09-11-2008 |
| 20090135991 | PRE-CHARGE CIRCUIT AND SHIFT REGISTER WITH THE SAME - A pre-charge circuit includes a receiving module, an enabling module, and a reset module. The receiving module receives the received driving signal of the pre-charge circuit and outputs the receiving driving signal according to a control signal. The enabling module outputs a pre-charge signal when receiving the driving signal. The reset module is electrically coupled between the receiving module and the enabling module for receiving a reset signal to reset the pre-charge signal. | 05-28-2009 |
| 20090213982 | SHIFT REGISTER AND LIQUID CRYSTAL DISPLAY (LCD) - The present invention provides a shift register having simple circuit scheme capable of increasing lifetime of whole circuit and a related Liquid Crystal Display (LCD). The shift register includes a plurality of shift register units connected in cascade, wherein at least one of the plurality of shift register units includes: an output terminal, a first switch element, a second switch element, a third switch element, a fourth switch element, a fifth switch element, and a sixth switch element. In addition, The LCD includes a plurality of gate output signal lines and the shift register mentioned above. The plurality of shift register units connected in cascade are coupled to the plurality of gate output signal lines, respectively. | 08-27-2009 |
| 20090220041 | SHIFT REGISTER CIRCUIT AND DISPLAY DEVICE - A shift register circuit can be manufactured in a simple manner. A shift register circuit is composed of a plurality of cascade-connected latch circuits that latch an input signal in synchronization with a clock signal and output a resultant signal. Two input signals IN and /IN having phases inverted relative to each other are input to each latch circuit, which latches the input signals IN and /IN in synchronization with a clock signal CLK input to a control input, and outputs latched inverted and non-inverted signals /OUT and OUT. | 09-03-2009 |
| 20090304138 | SHIFT REGISTER AND SHIFT REGISTER UNIT FOR DIMINISHING CLOCK COUPLING EFFECT - A shift register and a shift register unit for diminishing clock coupling effect are introduced herein. Each stage shift register unit includes at least one pull-up driving module, a pull-up module, at least one pull-down module and a pull-down driving module. Before a waveform of either a first clock signal or a second clock signal employed by the pull-up module transits into a rising edge, the pull-down driving module employs a first periodic signal to turn on the pull-down module in advance for a specific period, and/or before the waveform of the first or second clock signal employed by the pull-up module transits into a falling edge, the pull-down driving module employs a second periodic signal to turn off the pull-down module in advance for a specific period. Accordingly, the pull-down module can gain a sufficient capability against the clock coupling effect so as to optimize the waveform outputted from the shift register unit. | 12-10-2009 |
| 20090304139 | SHIFT REGISTER - A shift register includes a plurality of register units cascade-connected with each other. Each register unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit turns on in response to a driving pulse from a previous register unit and a second clock signal, and turns off in response to a third clock signal. The pull-down driving circuit which is coupled to an input node of the pull-down circuit, turns on in response to a first clock signal, and turns off in response to a the first clock signal or output of the pull-up driving circuit. | 12-10-2009 |
| 20100054392 | SHIFT REGISTER - A shift register includes a plurality of stages cascade-connected with each other. Each stage includes a pull-up circuit, a pull-up driving circuit, and a pull-down circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit includes a control circuit and a first transistor. The control circuit has a gate coupled to a previous stage, and a drain coupled to a second clock signal. The first transistor includes a gate coupled to the source of the control circuit, a drain coupled to a driving end of the previous stage, and a source coupled to a first input end. The pull-down circuit pulls down voltage on the first input end. | 03-04-2010 |
| 20100086097 | SHIFT REGISTER CIRCUIT AND DISPLAY MODULE - A shift register circuit includes a latch unit, a leakage current control unit, and a first output unit. The latch unit outputs a latch signal in accordance with a clock signal and an input signal. The first output unit outputs an output signal in accordance with the latch signal. The leakage current control unit is electrically connected between the latch unit and the first output unit for outputting the latch signal to the first output unit in accordance with the clock signal. | 04-08-2010 |
| 20100150302 | SHIFT REGISTER - A shift register comprises a plurality of stages, {S | 06-17-2010 |
| 20100150303 | SHIFT REGISTER WITH PRE-PULL-DOWN MODULE TO SUPPRESS A SPIKE - A shift register includes a plurality of shift register stages cascade-connected with each other. Each shift register stage includes a pull up module for outputting an output pulse in response to a first clock signal, a pull-up driving module for turning on the pull up module in response to a driving pulse of a previous one stage of the shift register, a pre-pull-down module coupled to a previous two stage of the shift register and a first node for pulling down voltage level of the first node in response to a output pulse of the previous two stage of the shift register, a pull down module coupled to the first node for pulling down voltage level of the first node in response to a pulling-down triggering signal, and a pulling down driving module for providing the pulling-down triggering signal. | 06-17-2010 |
| 20100158188 | Method of Driving a Gate Line and Gate Drive Circuit for Performing the Method - A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal. | 06-24-2010 |
| 20100226473 | SHIFT REGISTER - A shift register includes multiple cascade-connected stages. Each stage generates an output signal in response to a clock signal and a first control signal. Each stage includes a pull-up module, a pull-up driving module, a first pull-down module, a second pull-down module, and a third pull-down module. The pull-up module is used for providing the output signal based on the clock signal. The pull-up driving module turns on the pull-up module in response to a first control signal. The first pull-down module adjusts voltage level on the first node to a first supply voltage in response to a second control signal. The second pull-down module adjusts voltage level on the output end to a second supply voltage in response to the second control signal. The third pull-down module adjusts voltage level on the second node to a third supply voltage in response to a third control signal. | 09-09-2010 |
| 20100260312 | SHIFT REGISTER OF LCD DEVICES - A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage. | 10-14-2010 |
| 20100272228 | SHIFT REGISTER APPARATUS - A shift register apparatus is provided. Each of shift registers within the shift register apparatus of the present invention is only constituted by a few of active and passive elements without using conventional digital logic elements, and even the passive element are not required at some conditions. Therefore, the layout area occupied/consumed by each of the shift registers of the present invention is relatively smaller than that of the conventional shift register constituted by a CMOS D-flip-flop, and thus a fabrication cost can be reduced. | 10-28-2010 |
| 20100316182 | SHIFT REGISTER OF A DISPLAY DEVICE - A shift register includes a plurality of shift register units each including an input circuit, a pull-up circuit and a pull-down circuit. The shift register unit receives an input voltage at an input end and provides an output voltage at an output end. The input circuit controls the signal transmission path between a first clock signal and a first node according to the input voltage. The pull-up circuit controls the signal transmission path between a second clock signal and the output end according to the level of the first node. The pull-down circuit includes a pull-down unit and a control unit. The pull-down unit maintains the level of the first node or the output end according to the level of the second node. The control unit maintains the level of the second node according to the first clock signal, the second clock signal and the level of the first node. | 12-16-2010 |
| 20110007863 | SHIFT REGISTER - A shift register comprises a plurality of stages, {S | 01-13-2011 |
| 20110013740 | SHIFT REGISTER CIRCUIT HAVING BI-DIRECTIONAL TRANSMISSION MECHANISM - A shift register includes a plurality of shift register stages for providing gate signals. Each shift register stage has a pull-up unit, a carry unit, a carry control unit, an input unit and a pull-down unit. The pull-up unit is employed to pull up a gate signal according to a driving control voltage and a first clock. The carry unit generates a preliminary start pulse signal based on the driving control voltage and the first clock. The carry control unit outputs the preliminary start pulse signal to become a forward or backward start pulse signal according to first and second bias voltages. The input unit is utilized for inputting a start pulse signal generated by a preceding or succeeding shift register stage to become the driving control voltage. The pull-down unit pulls down the gate signal, the preliminary start pulse signal and the driving control voltage according to multiple clocks. | 01-20-2011 |
| 20110058641 | FAST DYNAMIC REGISTER - A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high causing the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations. | 03-10-2011 |
| 20110058642 | SHIFT REGISTER CIRCUIT AND GATE SIGNAL GENERATION METHOD THEREOF - A shift register circuit includes a plurality of shift register stages for providing plural gate signals to plural gate lines. Each shift register stage includes an input unit, a first pull-up unit, a second pull-up unit, a pull-down unit and an auxiliary pull-down unit. The input unit inputs a first gate signal generated by a preceding shift register stage to become a driving control voltage. The first pull-up unit pulls up a second gate signal according to the driving control voltage and a first clock signal. The second pull-up unit pulls up a third gate signal according to the driving control voltage and a second clock signal. The auxiliary pull-down unit is employed to pull down the driving control voltage according to a fourth gate signal generated by a subsequent shift register stage. The pull-down unit pulls down the first and second gate signals according to the driving control voltage. | 03-10-2011 |
| 20110064186 | DRIVER CIRCUIT, DISPLAY DEVICE INCLUDING THE DRIVER CIRCUIT, AND ELECTRONIC DEVICE INCLUDING THE DISPLAY DEVICE - A driver circuit where malfunctions in the circuit can be suppressed even when a thin film transistor is changed into an enhancement transistor or a depletion transistor is provided. In a pulse output circuit, a circuit for raising potentials of source terminals of first and second transistors from low power supply potentials is provided between the source terminals of the first and second transistors and a wiring for supplying a low power supply potential. Further, a switch for setting the potentials of the source terminals of the first and second transistors to low power supply potentials is provided. The switch is controlled by a judgment circuit for judging whether the first and second transistors are enhancement transistors or depletion transistors. | 03-17-2011 |
| 20110075790 | SHIFT REGISTER AND GATE LINE DRIVING DEVICE - It discloses a shift register and a gate line driving device, relating to the technology field for a liquid crystal display, it is made to reduce the switching on errors for gate lines and improve the quality of the image. Said shift register includes: a first thin film transistor, a second thin film transistor, a third thin film transistor, a storage capacitor, a feedback module, and a switch module, wherein said feedback module is used to receive a trigger signal of the feedback module of the previous stage and a clock signal in order to pull up the level of the first node Qa as a pull up node, and to output a feedback signal to the shift register of the previous stage and output a trigger signal to the feedback module of the next stage, said switch module is used to maintain the output terminal of the shift register of the present stage at a low level when the shift register of the present stage does not operate. An embodiment of the present invention is applied to a liquid crystal display panel. | 03-31-2011 |
| 20110116592 | SHIFT REGISTER WITH LOW POWER CONSUMPTION - A shift register comprising a plurality of shift register stages {S | 05-19-2011 |
| 20110158377 | SHIFT REGISTER CIRCUIT - A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal. | 06-30-2011 |
| 20110216877 | SHIFT REGISTER CIRCUIT - A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal. | 09-08-2011 |
| 20110255653 | SHIFT REGISTER - The present invention relates to a shift register in which a structure of a switching device of an output buffer unit is changed for reducing power consumption. The shift register includes a plurality of stages each having a plurality of switching devices, for forwarding a scan pulse in succession, wherein the at least one of the plurality of switching device has a first area at which a gate electrode thereof overlaps with a first electrode thereof with a size different from a second area at which the gate electrode overlaps with a second electrode thereof. | 10-20-2011 |
| 20110274236 | SHIFT REGISTER CIRCUIT - An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period). | 11-10-2011 |
| 20110293063 | SHIFT REGISTER CIRCUIT AND GATE SIGNAL GENERATION METHOD THEREOF - A shift register circuit includes a plurality of shift register stages for providing plural gate signals to plural gate lines. Each shift register stage includes an input unit, a first pull-up unit, a second pull-up unit, a pull-down unit and an auxiliary pull-down unit. The input unit inputs a first gate signal generated by a preceding shift register stage to become a driving control voltage. The first pull-up unit pulls up a second gate signal according to the driving control voltage and a first clock signal. The second pull-up unit pulls up a third gate signal according to the driving control voltage and a second clock signal. The auxiliary pull-down unit is employed to pull down the driving control voltage according to a fourth gate signal generated by a subsequent shift register stage. The pull-down unit pulls down the first and second gate signals according to the driving control voltage. | 12-01-2011 |
| 20120008731 | BI-DIRECTIONAL SHIFT REGISTER - A shift register of an LCD device includes a plurality of shift register units coupled in series. Each shift register unit includes an input circuit and a pull-down circuit having symmetric structures which enable the LCD device to function in a forward-scan mode and a reverse-scan mode. | 01-12-2012 |
| 20120008732 | SHIFT REGISTER WITH LOW POWER CONSUMPTION - A shift register comprising a plurality of shift register stages {S | 01-12-2012 |
| 20120076256 | Shift Register And Display Device - Disclosed are a shift register and a display device which can suppress noise of output of each stage without causing an increase in circuit scale. Each stage (Xi) of the shift register includes a first output transistor (M | 03-29-2012 |
| 20120140871 | SHIFT REGISTER CIRCUIT - A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit, a pull-up unit, a pull-down unit, a control unit and an auxiliary pull-down unit. The input unit is put in use for outputting a driving control voltage according to at least one first input signal. The pull-up unit pulls up a corresponding gate signal according to the driving control voltage and a system clock. The pull-down unit pulls down the corresponding gate signal to a first power voltage according to a control signal. The control unit is utilized for generating the control signal according to the corresponding gate signal. The auxiliary pull-down unit pulls down the driving control voltage to a second power voltage according to a second input signal. | 06-07-2012 |
| 20120140872 | SHIFT REGISTER WITH LOW POWER CONSUMPTION - A shift register comprising a plurality of shift register stages {S | 06-07-2012 |
| 20120140873 | SHIFT REGISTER - An exemplary shift register includes a control circuit and an output transistor. The control circuit has a start pulse signal input terminal, a first clock pulse signal input terminal and a power supply voltage input terminal and includes a first control transistor and a second control transistor. The output transistor is electrically coupled to the first control transistor and includes a gate driving signal output terminal and a second clock pulse signal input terminal. Moreover, the first control transistor, the second control transistor and the output transistor all are negative threshold voltage transistors. | 06-07-2012 |
| 20120155604 | SHIFT REGISTER CIRCUIT - A shift register circuit includes plural shift register stages for providing plural gate signals. The Nth shift register stage of the shift register stages includes an input unit, a pull-up unit and a pull-down unit. The input unit is put in use for outputting an Nth driving control voltage according to an (N−1)th gate signal and an (N−2)th driving control voltage which are generated respectively by the (N−1) th shift register stage and the (N−2) th shift register stage of the shift register stages. The pull-up unit pulls up an Nth gate signal according to the Nth driving control voltage and a system clock. The pull-down unit pulls down the Nth gate signal and the Nth driving control voltage according to an (N+2)th gate signal generated by the (N+2)th shift register stage of the shift register stages. | 06-21-2012 |
| 20120170707 | SWITCH DEVICE AND SHIFT REGISTER CIRCUIT USING THE SAME - A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit and a pull-up unit. The pull-up unit is utilized for pulling up a gate signal according to a system clock and a driving control voltage. The input unit is employed for outputting the driving control voltage according to a control signal and an input signal. The input unit includes a switch device having a first transistor and a second transistor. The first transistor has a first end for receiving the input signal, a gate end for receiving the control signal, and a second end. The second transistor has a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the first end of the first transistor, and a second end for outputting the driving control voltage. | 07-05-2012 |
| 20120219105 | SHIFT REGISTER CIRCUIT - A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal. | 08-30-2012 |
| 20120300894 | SHIFT REGISTER UNIT, GATE DRIVE CIRCUIT, AND DISPLAY APPARATUS - Provided are a shift register unit, a gate drive circuit, and a display apparatus. The shift register unit comprises: input module for inputting first clock signal, second clock signal, frame start signal, high voltage signal, and low voltage signal, first clock signal is identical with phase-inverted signal of second clock signal within one frame; a processing module comprising multiple TFTs, for generating gate drive signal according to the first clock signal, the second clock signal, and the frame start signal, and configuring positive feedback of voltage changes between first node and second node formed by the TFTs to cut off transient DC path formed by high voltage signal input terminal, low voltage signal input terminal, and at least one TFT in time; output module for sending the gate drive signal. The present disclosure decreases the transient current, and reduces the power consumption of the shift register unit. | 11-29-2012 |
| 20130114783 | SHIFT REGISTER CIRCUIT - A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal. | 05-09-2013 |
| 20130272487 | SHIFT REGISTER CIRCUIT AND IMAGE DISPLAY COMPRISING THE SAME - In a shift register circuit, a defective operation while an output signal is not outputted and a drive capability lowering while the output signal is outputted are prevented. A unit shift register comprises a first transistor for supplying a clock signal inputted to a first clock terminal to an output terminal, and the first transistor is driven by a drive circuit. A second transistor is connected between the gate of the first transistor and the output terminal and has a gate connected to the first clock terminal. The second transistor connects the gate of the first transistor to the output terminal based on the clock signal when the gate of the first transistor is at L (Low) level. | 10-17-2013 |
| 20140334596 | ELECTRONIC DEVICE - A single-crystal semiconductor layer is separated from a single-crystal semiconductor substrate and is fixed to an insulating substrate to form a TFT over the insulating substrate. Then, a driver circuit is formed using the TFT. The TFT has excellent current characteristics because an active layer is almost in a single-crystal state. Accordingly, a small thin display device with low power consumption can be manufactured. Further, a controller and a shift register which is included in a source driver are operated at the same power supply voltage. Thus, power consumption can be reduced. | 11-13-2014 |
| 20150348646 | SHIFT REGISTER AND METHOD OF DRIVING THE SAME, AND GROUP OF SHIFT REGISTERS AND METHOD OF DRIVING THE SAME - A shift register circuit is disclosed. In some embodiments, the shift register circuit includes six transistors and no capacitors. A group of such shift register circuits is also disclosed. In some embodiments, the shift registers of the group are connected so as to be configured to provide driving signals for a display. A method of using the shift registers is also disclosed. | 12-03-2015 |
| 377080000 | Parallel clocking | 1 |
| 20110228894 | SHIFT REGISTER CIRCUIT AND GATE DRIVING CIRCUIT - An exemplary shift register circuit includes a shift register, a first switching circuit and a second switching circuit. The shift register has a start pulse signal input terminal and a start pulse signal output terminal. The first switching circuit includes a first input switch unit and a second output switch unit respectively electrically coupled to the start pulse signal input terminal and the start pulse signal output terminal. The second switching circuit includes a second input switch unit and a first output switch unit respectively electrically coupled to the start pulse signal input terminal and the start pulse signal output terminal. Moreover, on-off states of the first input and first output switch units are opposite to on-off states of the second input and second output switch units. Moreover, a gate driving circuit using the above-mentioned shift register and switching circuits also is provided. | 09-22-2011 |
| 377081000 | Logic circuit | 2 |
| 20090110138 | Shift Register Circuit - A shift register circuit includes a plurality of bit register units, coupled in series, for transferring an input signal among the plurality of bit register units to sequentially output the input signal to a plurality of data output terminals according to a control signal and a clock signal, wherein the number of the plurality of data output terminals is greater than that of the plurality of bit register units, and a control unit for generating the control signal to control transference of the input signal. | 04-30-2009 |
| 20110033022 | DIGITAL LOGIC CIRCUIT, SHIFT REGISTER AND ACTIVE MATRIX DEVICE - A digital logic circuit includes a plurality of transistors of a same conduction type. In at least one embodiment, a first transistor has a source, gate and drain connected to a first circuit node, a second circuit node and a first power supply line, respectively. A second transistor has a source, gate and drain connected to the second node, the first node and the first supply line, respectively. A third transistor has a drain connected to the first node. A fourth transistor has a gate and drain connected to a third circuit node and the second circuit node, respectively. A fifth transistor has a gate and drain connected to the first and third nodes, respectively. Such a circuit may be used, for example, as a latch in a shift register of an active matrix addressing arrangement. | 02-10-2011 |
