| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 377002000 | Control | 9 |
| 20090034677 | Deactivatable measurement apparatus - Measurement apparatus is described that comprises a measurement portion for acquiring object measurements and an output portion (for outputting measurement data relating to the acquired object measurements. A deactivation portion is provided for inhibiting normal operation of the measurement apparatus such that output of the measurement data is prevented. The deactivation portion, in use, reads apparatus usage information from an apparatus usage module and inhibits normal operation of the measurement apparatus if said apparatus usage information fails to meet one or more predetermined criteria. The apparatus usage module may be provided as an integral part of the measurement apparatus or as a separate activation button. The measurement apparatus may comprise a measurement probe such as a touch trigger measurement probe. | 02-05-2009 |
| 20100195784 | ROTATION SPEED DETECTION CIRCUIT AND MOTOR DRIVER APPARATUS HAVING THE SAME - A rotation speed detection circuit includes an internal clock generation portion which receives an input of a period signal whose period varies in accordance with rotation speed of a motor and generates an internal clock signal having a predetermined number of pulses in one period of the period signal, and an internal clock counter portion which counts the number of pulses of the internal clock signal for a predetermined period every one period of the period signal and delivers a count value thereof as a digital data signal. | 08-05-2010 |
| 20110069805 | DRIVER CIRCUIT, DISPLAY DEVICE INCLUDING THE DRIVER CIRCUIT, AND ELECTRONIC APPLIANCE INCLUDING THE DISPLAY DEVICE - An object of the present invention is to provide a driver circuit including a normally-on thin film transistor, which driver circuit ensures a small malfunction and highly reliable operation. The driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor. The first to third transistors each include a semiconductor layer of an oxide semiconductor and are depletion-mode transistors. An amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit. | 03-24-2011 |
| 20110080989 | START-UP CIRCUIT AND START-UP METHOD - A start-up circuit receives a start-up signal instructing start-up of an equipment mounted with the circuit, and executes a predetermined sequence when start-up is instructed by the start-up signal. An oscillator generates a clock signal. A sequence circuit receives the start-up signal and a clock signal output from the oscillator, measures time by counting the clock signal when the start-up signal transits to a predetermined level, and executes a predetermined event at a predetermined timing. The oscillator operates for a period where the start-up signal is at the predetermined level if the start-up signal is at the predetermined level during the period the power key of the equipment mounted with the circuit is being pushed. | 04-07-2011 |
| 20120140869 | OUTPUT TIMING CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - An output timing control circuit of a semiconductor apparatus includes a delay amount counter block configured to count a delay amount of an output reset pulse signal based on an external clock signal and output a first counting code, wherein the delay amount counter block is configured to control the delay amount of the output reset pulse signal depending upon a frequency of the external clock signal; an operation block configured to subtract a code value of the first counting code from a code value of a data output delay code, and output a delay control code; and a phase control block configured to control a phase of a read command signal by the number of clocks of a DLL clock signal corresponding to a code value of the delay control code, and output an output enable flag signal. | 06-07-2012 |
| 20120236981 | UNIVERSAL COUNTER/TIMER CIRCUIT - A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters. | 09-20-2012 |
| 20150030116 | SHIFT REGISTER, DRIVER CIRCUIT AND DISPLAY DEVICE - A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second intermediate stage is initially activated after the operation period starts, the clock signal supplied to the second input terminal of the second intermediate stage is inactive. | 01-29-2015 |
| 20150110238 | Fragment Counting and Control System - A fragment counting and control system, consisting of mechanical and electronic components such as a fragment counting execution mechanism, a sensor platform, various sensors, a signal counting and processing instrument, a timer, a motor driver and the like. A fragment falls onto the sensor platform from the outlet of the fragment counting execution mechanism, such that the sensor on the sensor platform generates a signal; the signal is transmitted to the signal counting and processing instrument; the signal counting and processing instrument processes the signal and compares the processed signal with a preset value; the processing instrument transmits a control signal to the timer and the motor driver according to the ratio; the timer controls the motor driver to start and stop; the motor driver processes the processing instrument signal, and transmits a driver signal to the motor; and the motor changes rotation according to the driver signal so as to drive a vertical shaft to change rotation, thus controlling the frequency of falling fragments. | 04-23-2015 |
| 20160078338 | Hand Pliers - The invention relates to hand pliers ( | 03-17-2016 |
