Entries |
Document | Title | Date |
20080260086 | CARRIER SYNCHRONIZING CIRCUIT AND CARRIER SYNCHRONIZING METHOD - Disclosed herein is a carrier synchronizing circuit including at least frequency synchronizing means and phase synchronizing means. The phase synchronizing means includes residual frequency error detecting means for detecting a residual frequency error after a frequency synchronizing process by the frequency synchronizing means and supplying the residual frequency error to the frequency synchronizing means, and the frequency synchronizing means performs frequency pull-in for the residual frequency error supplied from the residual frequency error detecting means after first timing. | 10-23-2008 |
20080285696 | Techniques for integrated circuit clock management using multiple clock generators - A clock generator system ( | 11-20-2008 |
20090046822 | System and Method for Clock Drift Compensation - Embodiments for compensating clock drift in a system have been described and depicted. | 02-19-2009 |
20090097605 | SYSTEM FOR PHASE OFFSET CANCELLATION IN SYSTEMS USING MULTI-PHASE CLOCKS - A system for use with a multi-phase clock generator is disclosed. It should also be understood that the multiphase clock generator can be a phase lock loop (PLL), delay lock loop (DLL), or any other circuit capable of providing a multiphase clock. The system comprises at least two phase detectors coupled to the multi-phase clock generator for receiving component clock signals of the multi-phase clock generator, wherein at least some of the component clock signals are offset from each other in phase. Each of the phase detectors detects phase differences between pairs of component clock signals. The system includes a summer coupled to the at least two phase detectors for measuring the phase differences between the at least two phase detectors. The system includes at least one variable delay element for receiving the measured phase difference and for providing a delay which is proportional to an output value of the summer. The delay is used to reduce the phase differences. | 04-16-2009 |
20090168942 | Apparatus and method for frequency synthesis using delay locked loop - An apparatus and method for frequency synthesis using a Delay Locked Loop (DLL) are provided. The apparatus includes the DLL, an edge pulse generator, and an inductive-capacitive (LC) tank switch. If phases of a reference frequency signal and a feedback signal are the same and thus are locked, the DLL delays the reference frequency signal. The edge pulse generator generates a plurality of pulse signals representing phase delay amounts of signals. The LC tank switch combines the plurality of pulse signals and generates frequency. | 07-02-2009 |
20090245448 | Adaptation of a digital receiver - A method and apparatus to improve adaptation speed of a digital receiver is presented. The receiver includes an equalizer to initiate adaptation to a transmission channel responsive to a first control signal, a slicer coupled to the equalizer to generate symbol decisions based at least in part on an equalized digital signal, logic to receive the symbol decisions and generate a selection signal when a lock onto a training sequence of the symbol decisions occurs, first and second phase detectors to detect phase errors of the equalized digital signal and an incoming digital signal, respectively, and a clock generator to generate a clock signal responsive to one of the first and second phase errors. | 10-01-2009 |
20090262875 | Communication apparatus - A conventional apparatus has a problem that delay occurs in selection of the phase of a synchronization clock. A communication apparatus according to the present invention includes: a first unit | 10-22-2009 |
20090279655 | FAST LOCKING CLOCK AND DATA RECOVERY - A clock data recovery comprises a phase detector, a phase interpolator, an initial phase detector, and an initial phase decoder. The phase detector receives an incoming data stream and an interpolated clock signal and output an early/late value indicating timing relationship between the incoming data stream and the interpolated clock signal. The phase interpolator receives the early/late signal and at least one reference clock signal and generate an interpolated clock signal considering the early/late value and the at least one reference clock signal. The initial phase detector receives the incoming data stream and output a first data indicating a phase of the incoming data stream. The initial phase decoder receives data indicating a phase of the incoming data stream and select the at least one reference clock signal from a plurality of clock signals considering the data indicating a phase of the incoming data stream. | 11-12-2009 |
20090316847 | Automatic Synchronization of an Internal Oscillator to an External Frequency Reference - An internal integrated circuit clock oscillator is automatically synchronized to an external frequency reference by counting the number of periods of the internal clock oscillator (hereinafter “count”) that occur within a period of a lower frequency external frequency reference then comparing the count to the reference count. When the reference count is greater than the count, the frequency of the internal clock oscillator is increased. When the reference count is less than the count, the frequency of the internal clock oscillator is decreased. When the reference count and the count are substantially the same, the frequency of the internal clock oscillator is not changed. | 12-24-2009 |
20100040184 | METHOD AND SYSTEM FOR COEXISTENCE IN A MULTIBAND, MULTISTANDARD COMMUNICATION SYSTEM UTILIZING A PLURALITY OF PHASE LOCKED LOOPS - Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs. | 02-18-2010 |
20100067633 | FAST POWERING-UP OF DATA COMMUNICATION SYSTEM - A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up. | 03-18-2010 |
20100158182 | Method and System for Reducing Duty Cycle Distortion Amplification in Forwarded Clocks - A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is filtered to substantially remove therefrom low frequency components before the clock signal is used by the receiver to recover data from the data signal. | 06-24-2010 |
20100322367 | Fast Phase Alignment for Clock and Data Recovery - Disclosed herein are systems and methods for fast phase alignment and clock and data recovery. Systems and methods may include a fast phase alignment component configured to generate a selected phase signal based on a characteristic of an incoming signal. A clock and data recovery component may also be configured to receive the selected phase signal and perform a clock and data recovery function on the incoming signal using the selected phase signal. | 12-23-2010 |
20120177162 | Symmetric Phase Detector - In one embodiment, a circuit includes a first mixer cell and a second mixer cell that each have respectively a first cell input, a second cell input, and a cell output. The circuit includes a first circuit input configured to receive a first input signal having a first phase. The first circuit input is connected to the first cell input of the first mixer cell and the second cell input of the second mixer cell. The circuit includes a second circuit input configured to receive a second input signal having a second phase separated from the first phase by a nominal value. The second circuit input is connected to the second cell input of the first mixer cell and the first cell input of the second mixer cell. | 07-12-2012 |
20130003907 | ENHANCED PHASE DISCRIMINATOR FOR FAST PHASE ALIGNMENT - One embodiment of the present invention relates to a phase alignment system including a plurality of samplers, a clock distributor, a phase detector and a phase alignment control. The samplers are configured to receive an incoming signal and a phase adjusted clock signal and to provide samples according to the incoming signal. The clock distributor receives a clock adjustment signal and generates the phase adjusted clock signal, which triggers sampling of the incoming signal. The clock adjustment signal indicates a direction of phase adjustment and can include an amount of phase adjustment. The phase detector receives the samples and provides extended phase alignment commands derived from the samples. The phase alignment control receives the extended phase alignment commands and provides the clock adjustment signal to the clock distributor. | 01-03-2013 |
20130070882 | Phase Averaging-Based Clock and Data Recovery - In one embodiment, a method includes adjusting a first frequency of a first clock signal based on a frequency difference between the first frequency and a reference clock signal frequency of a reference clock signal, and further adjusting the first frequency and a first phase of the first clock signal based on a phase difference between the first clock signal and an input data bit stream and the frequency difference between the first frequency and the reference clock signal frequency to substantially lock the first frequency and the first phase of the first clock signal to the input data bit frequency and input data bit phase of the input data bit stream. | 03-21-2013 |
20140037035 | PHASE INTERPOLATOR FOR CLOCK DATA RECOVERY CIRCUIT WITH ACTIVE WAVE SHAPING INTEGRATORS - A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal. | 02-06-2014 |
20140185726 | FREQUENCY SWEEP SIGNAL GENERATOR, FREQUENCY COMPONENT ANALYSIS APPARATUS, RADIO APPARATUS, AND FREQUENCY SWEEP SIGNAL GENERATING METHOD - A frequency sweep signal generator in which the frequency error is small even when the control values and the oscillating frequencies have a non-linear relation. The frequency sweep signal generator includes a variable frequency oscillator that changes an oscillating frequency according to a change of an input control value, and a first controller that generates a first control value so that the oscillating frequency within a predetermined frequency sweeping range is output. The first controller controls an increment of the first control value to be output to the variable frequency oscillator per unit time so that, when a change of the oscillating frequency with respect to the increment of the first control value is non-linear, the oscillating frequency is changed linearly with respect to a passage of time. | 07-03-2014 |
20140205047 | LOW LATENCY SYNCHRONIZER CIRCUIT - An apparatus for synchronizing an incoming signal with a clock signal comprises two or more synchronizer circuits, wherein each synchronizer circuit receives the incoming signal and the clock signal. Each synchronizer circuit generates a synchronized signal, wherein the state of each synchronized signal changes on a different phase of said clock signal in response to a change of the state of said incoming signal. A decision mechanism circuit receives the synchronized signals generated by each synchronizer circuit, wherein the decision mechanism circuit determines the output signal in response to the change of the state of the incoming signal. The decision mechanism circuit further comprises a memory element having a state which is set according to a previously detected state of said signal, wherein the output signal is determined according to the state of the memory element. | 07-24-2014 |
20140241480 | HITLESS EFFICIENT TRANSMITTER PROTECTION OF ALL OUTDOOR RADIOS - A method is provided for synchronizing a first radio unit with a second radio unit associated with an all outdoor radios system, the method including: receiving, at the first radio unit and the second radio unit, respectively, a communication signal from a common communication source; receiving, at the first radio unit and the second radio unit, respectively, a reference signal from a common reference source; synchronizing the communication signal at each of the first radio unit and the second radio unit with the reference signal such that the each of the first radio unit and the second radio unit generates an output signal having substantially the same frequency and substantially the same phase; and transmitting the output signal from each of the first radio unit and the second radio unit to a remote receiver through an antenna. | 08-28-2014 |
20140286469 | RECEPTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A burst mode CDR detects an edge from a data signal superimposed with a clock, and generates a recovered clock by means of a voltage controlled oscillator whose oscillation operation is reset based on a timing when the edge is detected. A phase adjustment unit adjusts the phase of a data signal so as to coincide with the phase of a recovered clock. A PLL-based CDR adjusts the oscillation frequency of the recovered clock by means of the voltage controlled oscillator, based on a phase difference between a data signal whose phase has been adjusted by the phase adjustment unit and a feedback clock from the voltage controlled oscillator. A determination unit determines the value of the data signal at a timing when the signal level of the recovered clock transitions. | 09-25-2014 |
20150063516 | COMMUNICATION CIRCUIT AND INFORMATION PROCESSING DEVICE - A communication circuit includes: a plurality of receiving units each configured to receive a serial signal over a transmission path from another device; a plurality of serial-to-parallel converters each configured to convert the received serial signal into a parallel signal; and a clock phase controller configured to send a clock phase control signal to any of the plurality of serial-to-parallel converters, wherein one of the serial-to-parallel converters that has received the clock phase control signal is configured to shift a phase of a parallel-signal clock signal that is to be used for a parallel signal obtained by conversion, so that a phase of a parallel signal to be obtained by conversion performed by the one of the serial-to-parallel converters is different from a phase of a parallel signal to be obtained by conversion performed by another one of the serial-to-parallel converters. | 03-05-2015 |
20150071396 | METHOD FOR DETERMINING PHASE OF CLOCK USED FOR RECEPTION OF PARALLEL DATA, RECEIVING CIRCUIT, AND ELECTRONIC APPARATUS - For each of a plurality of delayed phases, one of the plurality of delayed phases being the same as a phase of a reference clock and the others of the plurality of delayed phases delayed with respect to the phase of the reference clock, test parallel data transmitted in synchronism with the reference clock is received in synchronism with a delayed clock having the delayed phase and an adjacent delayed clock having a delayed phase adjacent to the delayed phase of the delayed clock, respectively; and a phase range containing a delayed phase with which the test parallel data has been received correctly and for which the result of the comparison indicates a match is determined from among the plurality of delayed phases; and the phase of a receive clock to be used for reception of parallel data is determined from the determined phase range. | 03-12-2015 |
20150098542 | METHOD FOR PORTABLE DEVICE PROCESSING DATA BASED ON CLOCK EXTRACTED FROM DATA FROM HOST - A method for a first electronic device processing data based on information from a second electronic device may comprise: receiving a first signal from the second electronic device; extracting a first clock based on the first signal; adjusting an oscillator based on the first clock so as to generate a second clock; and selecting one from the first and second clocks. In an embodiment of the present invention, the first electronic device may be configured to be hot plugged into the second electronic device. The method may further comprise processing a data stream from the second electronic device based on said selecting said one from the first and second clocks. The method may further comprise transmitting a data stream to the second electronic device based on said selecting said one from the first and second clocks. | 04-09-2015 |
20150304097 | CIRCUIT AND METHOD FOR CLOCK AND DATA RECOVERY - A dock and data recovery circuit includes a sampling module, a phase detect module, a parallel-to-serial converter and a phase adjust module. The sampling module generates a data signal and an edge signal according to input data, a first dock signal and a second dock signal. The phase detect module detects a phase of the data signal and a phase of the edge signal to generate first output recovered data and a first phase adjust signal. The parallel-to-serial converter performs a parallel-to-serial conversion on the first recovered data and the first phase adjust signal, so as to generate second output recovered data and a second phase adjust signal. The phase adjust module generates the first clock signal and the second clock signal, and adjusts the first clock signal and the second clock signal according to the second output recovered data and the second phase adjust signal. | 10-22-2015 |
20150341161 | APPARATUS AND METHOD FOR MODULAR SIGNAL ACQUISITION AND DETECTION - Apparatus and method for acquiring and tracking a data signal are disclosed. Two different CDR circuits are configured to acquire and track data based on two different modulation schemes. While in the acquisition mode, the first CDR circuit may acquire data signal by sampling the signal at a reduced clock rate and handover to the second CDR circuit when a preamble is found. Also in the acquisition mode, the data acquisition and tracking circuit may determine the power level of the preamble signal and dynamically adjust the threshold level for the tracking period upon finding of the preamble. | 11-26-2015 |