| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 375372000 | Elastic buffer | 11 |
| 20080240326 | HIGH SPEED DIGITAL WAVEFORM IDENTIFICATION USING HIGHER ORDER STATISTICAL SIGNAL PROCESSING - In some embodiments an apparatus includes a higher order statistical signal processor to process a jittered digital signal, a diagonal line average unit to identify a distinct line in a signal output from the higher order statistical signal processor, and a peak detection unit to determine a peak value in response to an output of the diagonal line average unit and to provide a data rate signal as an output. Other embodiments are described and claimed. | 10-02-2008 |
| 20080267333 | Method And Apparatus For Controlling Buffer Overflow In A Communication System - A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. An audio encoder marks a frame as “dropped” whenever a buffer overflow might occur. Only a small number of bits are utilized to process a lost frame, thereby preventing the buffer from overflowing and allowing the encoder buffer-level to quickly recover from the potential overflow condition. The audio encoder optionally sets a flag that provides an indication to the receivers that a frame has been lost. If a “frame lost” condition is detected by a receiver, the receiver can optionally employ mitigation techniques to reduce the impact of the lost frame(s). | 10-30-2008 |
| 20090052601 | METHOD AND APPARATUS FOR FRAME-BASED BUFFER CONTROL IN A COMMUNICATION SYSTEM - A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. The decoder buffer level limits are specified in terms of a maximum number of encoded frames (or duration). The transmitter can predict the number of encoded frames, F | 02-26-2009 |
| 20090086874 | Apparatus and method of elastic buffer control - A method, system, and apparatus for synchronizing an asynchronous data transmission between a transmitter and a receiver are presented. For example, an elastic buffer can include a symbol storage coupled to receive transition data from a transmitter and to store the transition data in a plurality of addressable symbol storage elements; a write clock domain, which operates at a recovery clock, for selecting a symbol storage element of symbol storage to store the transition data, determining whether a SKIP ordered set has occurred, and deleting a SKIP symbol of the SKIP ordered set based on the determination to prevent the deleted SKIP symbol from being stored in symbol storage; and a read clock domain, which operates at a local clock, for selecting a symbol storage element of the symbol storage to retrieve the transition data as receiver data, determining whether a SKIP ordered set is occurring, adding a SKIP symbol to the receiver data based on the determination; and providing the receiver data to a receiver. | 04-02-2009 |
| 20090116602 | High speed, wide frequency-range, digital phase mixer and methods of operation - The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims. | 05-07-2009 |
| 20090141844 | Methods and apparatus for interface buffer management and clock compensation in data transfers - A circuit for data stream buffer management, lane alignment, and clock compensation of data transfers across a clock boundary using a single first in first out (FIFO) buffer in each serial channel is described. The RapidIO® data channel, for example, operates using a clock recovered from the data stream. The RapidIO® data stream has embedded special characters, where a select sequence of embedded characters is a clock compensation pattern. A look ahead circuit is used to detect the clock compensation pattern early and generate a clock compensation indicator signal. The FIFO writes data and the associated clock compensation indicator signal in a clock compensation indicator bit in synchronism with the recovered clock. A read circuit using a second clock of a different frequency than the first clock reads data and clock compensation bits from the FIFO and generates an almost empty signal when appropriate. A multiplexer is used at the FIFO output to pad data to the system interface. A clock compensation control circuit generates a selection signal based on an AND of the almost empty signal and the clock compensation indicator bit associated with a data element read out of the FIFO and using the selection signal to control the multiplexer selection signal. | 06-04-2009 |
| 20090232266 | SIGNAL PROCESSING DEVICE - A signal processing device includes a phase shifting unit for supplying a second clock signal having a predetermined phase difference relative to a first clock signal, a head recognition bit adding unit for adding a head recognition bit to a predetermined position of data constituting a packet, an inputting unit for reading out a data signal from the memory in synchronization with the second clock signal, a clock replacing unit for inputting the data signal on the basis of the second clock signal and outputting the data signal on the basis of first clock signal, a data shifting unit for shifting the data signal by an amount corresponding to a predetermined number of clock cycles, and an enable signal generating unit for generating an enable signal for recognizing an available length of the packet after an appearance of the head recognition bit in the output signal. | 09-17-2009 |
| 20090296868 | Method for Shifting Data Bits Multiple Times Per Clock Cycle - A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal. | 12-03-2009 |
| 20100054385 | ADAPTIVE ELASTIC BUFFER FOR COMMUNICATIONS - Circuit and method for an adaptive elastic buffer for receiving data including timing signals. Received data is recovered and stored in the adaptive elastic buffer, and a recovery clock pointer is increased to identify the next buffer location for stuffing received data, responsive to a controller. When a data fetch enable condition occurs, the controller causes a receiver circuit to fetch the data stored at a location identified by a system clock pointer. Underflow and overflow conditions are detected and the controller adapts the effective elastic buffer depth to compensate for these conditions. A buffer of M/2 physical locations is adaptively operated to provide a data buffer of M virtual locations. A method of buffering received data with a buffer having M/2 physical locations so as to provide the benefit of a buffer with M virtual locations is disclosed. | 03-04-2010 |
| 20100166132 | PLL/DLL DUAL LOOP DATA SYNCHRONIZATION - A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages. | 07-01-2010 |
| 20150131766 | APPARATUS AND METHOD FOR FREQUENCY LOCKING - An apparatus and a method for frequency locking are provided. The apparatus includes a phase-locked loop (PLL), a local clock generator, a data buffer unit and a control unit. The PLL locks the phase and the frequency of a radio frequency signal to generate a recovery clock signal and received data. The data buffer unit writes the received data into an elastic buffer of the data buffer unit according to the frequency of the recovery clock signal, and reads the received data from the elastic buffer according to the frequency of a local clock signal generated by the local clock generator. The control unit obtains a write-in address and a read-out address in the elastic buffer, and sends a control signal to the local clock generator for adjusting the frequency of the local clock signal according to relationship between the write-in address and the read-out address. | 05-14-2015 |
