| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 375365000 | Synchronization word | 26 |
| 20080205568 | DSRC COMMUNICATION CIRCUIT AND DSRC COMMUNICATION METHOD - A DSRC communication and DSRC communication method for preventing UW detection errors as a result of shifts in timings of received data and a UW detection window. A configuration is adopted where a frame timing generating section that receives a UW detection window timing signal of a receiving slot of the head of a frame, synchronizes frames, and counts up a first synchronization bit counter to generate a frame timing, and a UW detection window timing generating section that generates a timing signal for a UW detection window of a receiving slot of the head of the next frame using the generated frame timing as a reference, are provided, and the frame timing is maintained by taking the UW detection timing at receiving slot | 08-28-2008 |
| 20080232528 | SYSTEMS AND METHODS FOR DETECTING A SPECIFIC TIMING FROM A SYNCHRONIZATION CHANNEL - A method for detecting a specific timing from a synchronization channel is described. A signal with a known sequence is received. Two or more correlation values between the received signal and the known sequence are calculated at two or more positions. The two or more correlation values are compared. A determination is made whether the position of the known sequence has been shifted based on the comparison. A specific timing of a synchronization channel is detected based on the determination. | 09-25-2008 |
| 20080298529 | ACQUISITION CIRCUIT FOR LOW CHIP RATE OPTION FOR MOBILE TELECOMMUNICATION SYSTEM - A User Equipment (UE) receives and samples communication signals, where the communication signals have a time frame format, a transmission chip rate and a synchronization code associated with a time slot that includes a midamble that indicates a modulation of the synchronization code where a specified modulation of received synchronization codes identifies the timing for a timeslot in which data is to be received. The UE preferably includes a synchronization code determination circuit, a midamble determination circuit, and a phase modulation sequence detection circuit operatively associated with the midamble determination circuit. The UE can be configured for use with the low chip rate option of the Third Generation Partnership Project (3GPP) Universal Mobile Telecommunication System (UMTS) standards that employ a predefined set of downlink SYNC codes that point to midambles which indicate SYNC code modulation sequence to enables reading of data in a subsequent Broadcast Channel (BCH) message. | 12-04-2008 |
| 20090154627 | METHODS AND APPARATUS FOR IDENTIFYING A PREAMBLE SEQUENCE AND FOR ESTIMATING AN INTEGER CARRIER FREQUENCY OFFSET - In accordance with a method for identifying a preamble sequence and for estimating an integer carrier frequency offset, a signal that comprises a preamble sequence from a set of possible preamble sequences is received. A reduced set of integer carrier frequency offset (CFO) candidates may be determined. Cross-correlation operations may be performed with respect to the received signal and multiple candidate transmitted signals. Each candidate transmitted signal may include one of the set of possible preamble sequences. In addition, each candidate transmitted signal may correspond to one of the reduced set of integer CFO candidates. Multiple correlation values may be determined as a result of the cross-correlation operations. The correlation values may be used to identify the preamble sequence and to estimate the integer CFO. | 06-18-2009 |
| 20090190704 | Synchronization of frame signals having two synchronization words - Apparatus for frame synchronization in a broadcast receiver where received frames comprise first and second synchronization words at predetermined locations in the frame, comprises: a correlator set with expected synchronization words for correlation with incoming symbols of said frame, to find probable locations of the first and second synchronization words within the frame, and a thresholder for thresholding the correlation according to both the first and second thresholds, thereby to allow, the receiver to synchronize with the frame. | 07-30-2009 |
| 20090252269 | DIGITAL RADIO PROCESSOR ARCHITECTURE WITH REDUCED DCO MODULATION RANGE REQUIREMENT - A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from π/2, π/4, π/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of π/2 | 10-08-2009 |
| 20090323878 | Communication appartus - A communication apparatus which includes a clock generation circuit outputting a plurality of clocks, each of said plurality of clocks having a different phase from each other; a synchronization detection block receiving a sync word and a payload having a predetermined length after receiving said payload, sampling said sync word by using each of said plurality of clocks and to output a first signal indicating a clock or clocks capable of sampling said sync word successfully, said synchronization detection block being capable of sampling said payload by using a clock or clocks inputted thereinto; a clock phase selection block coupled to said synchronization detection block to-receive said first signal to select one of said plurality of clocks in accordance with said first signal and to output a second signal indicating a selected clock; and a clock gate unit coupled between said clock generation circuit and said synchronization detection block and coupled to said clock phase selection block to receive each of said plurality of clocks and said second signal to output said selected one of said plurality of clocks to said synchronization detection block and not to output a rest of said plurality of said clocks based on said second signal during a period corresponding to said predetermined length of said payload. | 12-31-2009 |
| 20110007857 | Communication device - A communication device includes a current information storage unit | 01-13-2011 |
| 20110090998 | ADC-BASED MIXED-MODE DIGITAL PHASE-LOCKED LOOP - A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digital values by a charge pump and an Analog-to-Digital Converter (ADC). The stream of digital values is supplied to the digital loop filter which in turn supplies digital tuning words to the DCO. A number of types of ADCs can be used for the ADC including a continuous-time delta-sigma oversampling Digital ADC and a Successive Approximation ADC. The voltage signal on the charge pump output is a small amplitude midrange voltage signal. The small voltage amplitude of the signal leads to numerous advantages including improved charge pump linearity, reduced charge pump noise, and lower supply voltage operation of the overall PLL. | 04-21-2011 |
| 20120027149 | METHOD AND APPARATUS TO DETECT A SYNCHRONIZATION DELIMITER - A technique includes receiving a datum indicative of a candidate delimiter in a receiver; and processing the datum in a machine to determine whether the datum indicates a synchronization delimiter. The processing includes comparing the candidate delimiter with a reference delimiter to identify at least one error in the candidate delimiter; and basing the determination of whether the datum indicates the synchronization delimiter at least on a bit position of of each error. | 02-02-2012 |
| 20140072083 | GENERATING CODES FOR SYNC WORDS TO AVOID CYCLIC COLLISION - Disclosed are various embodiments for circuitry that generates a sync code for wireless transmission. The system generates a sync word according to an identifier of the transmitter, the sync word being unique under a cyclic shift of the sync word. The system inserts a plurality of instances of the sync word into a data stream. The system also transmits, via the transmitter, the data stream to a receiver, the receiver being operable to perform a sliding correlation operation on the sync word. | 03-13-2014 |
| 20140105342 | Frame and Symbol Timing Recovery for Unbursted Packetized Transmissions Using Constant-Amplitude Continuous-Phase Frequency-Modulation - A system and method for performing frame and symbol timing synchronization on samples of a received signal that includes a series of frames. Each frame includes a known preamble and payload data. A start-of-frame time is estimated by scanning the received signal samples for the self similarity of two successive preambles. A carrier frequency offset (CFO) is estimated by maximizing a correlation between a magnitude spectrum of the received signal and a magnitude spectrum of a known preamble model. A fine estimate for the CFO is determined by computing a phase difference between samples separated by p repetitions of the base pattern for various values of index p, and computing a slope of a least squares affine fit to the phase differences. Additional operations are performed to find an optimal symbol starting point, to perform carrier phase synchronization and to detect the start of payload data. | 04-17-2014 |
| 20160006561 | Systems and Methods for Detecting a Synchronization Code Word - Systems and methods for detecting a synchronization code word embedded in a plurality of frames of a signal are described. In one example embodiment, the synchronization code word contains “s” bits, embedded one bit per frame in “s” frames of an input signal. The method of detecting this synchronization code word includes: initiating a first segmentation procedure wherein “n” segments are defined in each signal frame of the input signal. A first correlation threshold value, which is based on the synchronization code word, is used to identify in the “n” segments, a first segment having the highest likelihood of containing at least a portion of the synchronization code word. The first segment is used to initiate a recursive detection procedure incorporating one or more additional segmentation procedures and one or more additional correlation threshold values, to detect the synchronization code word in a sub-divided portion of the first segment. | 01-07-2016 |
| 20160173272 | APPARATUS AND METHOD FOR CLOCK GENERATION | 06-16-2016 |
| 375367000 | Pseudo noise | 2 |
| 20080226007 | METHOD AND APPARATUS FOR POWER ESTIMATION FOR TDSOFDM IN TRANSMISSION - A method and apparatus for a receiver to estimate the received power for each transmitting BS. The power measure can be obtained by using some or all receiving antennas. | 09-18-2008 |
| 20080317184 | METHOD FOR TRANSMITTING SYNCHRONIZATION SIGNAL IN MOBILE MULTIMEDIA SYSTEM - The present invention discloses a method for transmitting a synchronization signal in a mobile multimedia system. In the method, a transmitter of the system transmits a synchronization signal sequence at a regular interval. The methods includes: generating a first synchronization signal sequence; generating a second synchronization signal sequence by performing a reversible transform for the first synchronization signal sequence; and transmitting the first and the second synchronization signal sequences in cascade. By the method provided by the present invention for transmitting a synchronization signal in a mobile multimedia system, a channel with wider delay spread can be handled, more precise and stabler synchronization performance can be achieved and the channel estimation module can be helped to get more accurate channel frequency domain response. | 12-25-2008 |
| 375368000 | Synchronizer pattern recognizers | 10 |
| 20080232529 | COMMUNICATION SYSTEM - To obtain a frame synchronization device and a frame synchronization method capable of preventing a malfunction when a frame is synchronized by using a frame synchronization pattern varying sequentially. A bit serial signal at every frame is transmitted sequentially in a shift register composed of flip-flop circuits. When a bit in each of the stages is detected to be coincided with a corresponding bit in a frame synchronization pattern by coincidence circuits, existence of a synchronized frame is determined. Each bit in the synchronization pattern is also inputted into an all-zero detection circuit. If an all-zero state is detected, a first AND circuit does not output a synchronization pattern detecting signal even with a case where coincidence is detected from the coincidence circuits. | 09-25-2008 |
| 20080273643 | APPARATUS AND METHOD OF EXACT TIME FRAMING IN A DMB-TH TRANSMITTER - A transmitter comprising: a digital encoder for encoding incoming digital information; and a digital to analog converter for converting the encoded digital information into analog information is described. The transmitter further comprises an exact time framing block disposed between the digital encoder and the digital to analog converter. The exact time framing block receives the digitally encoded information and comprises a method for synchronization. The method including the steps of: providing a clock signal having at least two adjacent pulses; providing information subjected to transmission in the form of a set of frames; and accommodating a whole number of frames between the two adjacent pulses. | 11-06-2008 |
| 20090175395 | DATA ALIGNMENT METHOD FOR ARBITRARY INPUT WITH PROGRAMMABLE CONTENT DESKEWING INFO - In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams. | 07-09-2009 |
| 20100260298 | SYSTEM AND METHOD FOR FRAME SYNCHRONIZATION - A method for identifying receipt of a sync word in a stream of signal data is provided. The method includes receiving a signal value representing an incoming bit in the stream of signal data. The method also includes inserting the signal value into a first shift register having the same length as the sync word. The method further includes calculating a bit value from the signal value. The method also includes storing the bit value into a second shift register having the same length as the sync word. The method further includes counting the number of matches between the bit values in the second shift register and the corresponding bits in the sync word. The method also includes computing a correlation of the signal data and the sync word by summing the product of each signal value in the first shift register and the corresponding bit in the sync word. The method further includes producing a normalized correlation by dividing the correlation by the energy. The method also includes outputting a signal indicating the presence of a sync word if the number of matches is at least equal to a predetermined hard correlation threshold and if the normalized correlation is at least equal to a predetermined soft correlation threshold. | 10-14-2010 |
| 20110007858 | METHOD OF DETECTING A FRAME SYNCHRONIZATION PATTERN OR UNIQUE WORD IN A RECEIVED DIGITAL SIGNAL - The recognition of a frame synchronization pattern or unique word of a received signal may be enhanced using a data-aided estimator of the signal-to-noise ratio (SNR) together with a correlation detector of the unique word to be received. Detecting a frame synchronization pattern or a unique word in a received signal, the SNR is estimated on the received signal with a data-aided SNR estimator using the unique word to be received. If the estimated SNR exceeds a certain threshold, an eventual recognition of the unique word established by a correlation correlator of the receiver is considered reliable. Comparing the SNR with the threshold may be carried out either before or after the correlator has processed the unique word. | 01-13-2011 |
| 20120195401 | SYSTEM AND METHOD FOR CORRELATING RECEIVED SIGNAL OVER TIME AND FREQUENCY - A system is provided for use with a frequency band including a transmission frequency and a received frequency. The transmission frequency includes a transmission signal having a transmitted unique word therein. The received frequency includes a received signal having a received unique word therein, wherein the received unique word had been received at a received time and at a received phase. The system includes a first sub-correlator, a second sub-correlator and a discrete Fourier transform device. The first sub-correlator can perform a first correlation of only a first portion of the received unique word with a corresponding first portion of the transmitted unique word over a plurality of instances of time and can output a first plurality of sub-correlation values. The second sub-correlator can perform a second correlation of only a second portion of the received unique word with a corresponding second portion of the transmitted unique word over the plurality of instances of time and can output a second plurality of sub-correlation values. The discrete Fourier transform device can perform a discrete Fourier transform over a plurality of frequencies within the frequency band on the first plurality of sub-correlation values and can perform a discrete Fourier transform over the plurality of frequencies within the frequency band on the second plurality of sub-correlation values. The first portion of the received unique word is different from the second portion of the received unique word. | 08-02-2012 |
| 20120294402 | METHOD AND APPARATUS FOR IMPLEMENTING PULSE SYNCHRONIZATION - The present invention relates to the communication field and discloses a method and an apparatus for implementing pulse synchronization, so that the control on a single-chip multi-channel device can be simplified. A method for implementing pulse synchronization includes: when a cycle count value corresponding to a reference symbol port of the multiple ports reaches a length of a predetermined pulse cycle, obtaining, by a microprocessor, cycle count values corresponding to the multiple ports; obtaining lengths of temporary synchronization cycles of the multiple ports according to the length of the predetermined pulse cycle and the cycle count values corresponding to the multiple ports; and sending the lengths of the temporary synchronization cycles to logic circuits corresponding to the multiple ports. Embodiments of the present invention are mainly applied in communication systems to output pulse symbols synchronously. | 11-22-2012 |
| 20130010909 | CLOCK REGENERATION METHOD, REFERENCE-LESS RECEIVER, AND CRYSTAL-LESS SYSTEM - A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided. | 01-10-2013 |
| 20130101076 | Polarity Detection - In an embodiment, a method includes receiving at a data interface a data stream having a first polarity and searching the received data having the first polarity for a unique pattern of a synchronization word within a first quantity of the received data, the synchronization word marking a start of a metaframe having a metaframe length. The polarity of the data stream is reversed to a second polarity if the synchronization word is not found within the first quantity of the received data and the received data having the second polarity is searched for the unique pattern of the synchronization word within a second quantity of the received data. | 04-25-2013 |
| 20150103963 | SEQUENCE SYNCHRONIZATION APPARATUS AND METHOD AND RECEIVER - Embodiments of the present disclosure provide a sequence synchronization apparatus and method and a receiver. The sequence synchronization apparatus includes: a signal receiving unit configured to receive a clock synchronized signal including a training symbol, the training symbol being in-phase modulated or being modulated with a fixed phase difference based on all or part of subcarriers; and a symbol detecting unit configured to detect the training symbol, so as to achieve sequence synchronization of the signal. With the embodiments of the present disclosure, not only sequence synchronization may be achieved by using minimum complexity as possible, but also the sequence synchronization apparatus is made simple, fast and accurate. | 04-16-2015 |
