| Entries |
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| 20080232526 | Digital signal processing employing a clock frequency which is always a constant integer multiple of the fundamental frequency of an input analog signal - A method and apparatus are disclosed for clocking a DSP at a frequency which is always a constant integer multiple of the fundamental frequency of the input analog signal. This invention applies in situations where the analog signal exhibits certain characteristics in which a fixed clock frequency is not desired, but rather what is needed is a clock which tracks the fundamental frequency of the analog signal, for example, a signal from a monophonic musical instrument or a polyphonic instrument being played one note at a time. | 09-25-2008 |
| 20080232527 | SYNCHRONOUS NETWORK DEVICE - A physical layer device comprises a first port that embeds a first clock into data transmitted over a first physical medium; a second port that embeds a second clock into data transmitted over a second physical medium; a first selection module that outputs the first clock to the first port based on one of a locally generated clock and a recovered clock; and a second selection module that outputs the second clock to the second port based on one of the locally generated clock and the recovered clock. A method comprises embedding a first clock into data transmitted over a first physical medium; embedding a second clock into data transmitted over a second physical medium; generating the first clock based on one of a locally generated clock and a recovered clock; and generating the second clock based on one of the locally generated clock and the recovered clock. | 09-25-2008 |
| 20080240323 | METHOD AND APPARATUS FOR DORMANT MODE SUPPORT WITH PAGING - Apparatuses and methods are disclosed herein for implementing dormant mode with paging in a WLAN. Power savings in the computing device and reduction in traffic across the network are achieved by requiring a computing device to inform the WLAN of its location only when it crosses a paging area boundary or is to receive IP traffic. Dormant mode with paging is implemented in a protocol that supports dormant functionality and paging functionality but does not itself provide methods or standards for implementing such functionality, such as the IEEE 802.11. The methods and apparatuses disclosed herein provide the methods needed to implement dormant mode with paging in such a protocol. Generally, the methods and apparatuses for implementing dormant mode with paging basically include (1) establishing paging areas; (2) communicating access group information to a computing device; and (3) locating a computing device. | 10-02-2008 |
| 20080260085 | Method and device for estimating integer carrier frequency offset - The method disclosed in the invention comprises setting a plurality of subcarrier position hypotheses for a received preamble according to a plurality of ideal subcarrier positions and the maximum amount of integer carrier frequency offset (ICFO), generating a plurality of preamble pattern hypotheses by retrieving the received preamble according to the subcarrier position hypotheses, calculating the correlation between the preamble pattern hypotheses and a plurality of specified preamble patterns, determining to which sector the received preamble belongs according to a correct preamble pattern, the specified preamble pattern having the highest correlation with the preamble pattern hypotheses, obtaining a correct subcarrier position according to the sector to which the received preamble belongs; and estimating the ICFO by calculating the offset between the correct subcarrier position and the subcarrier position hypothesis of the preamble pattern hypothesis having the highest correlation with the correct preamble pattern. | 10-23-2008 |
| 20080273642 | TIME REFERENCE POINT INFORMATION TRANSMITTING SYSTEM AND RECEIVER - A transmitter sets a time length, determines a time point at which phases of frequency signals coincide within a range of the time length, defines a determined time point as a time reference point, aligns the phases of the frequency signals based on the time reference point, combines phase-aligned frequency, and transmits combined frequency signals to a receiver by the time length as the communication signals. The receiver receives the communication signals, extracts the phases of the frequency signals, obtains a time point at which the phases coincide, and determines an obtained time point as the time reference point. | 11-06-2008 |
| 20080298527 | DIRECT DIGITAL FREQUENCY SYNTHESIZER WITH PHASE SELECTABLE INTERPOLATOR - The disclosure relates to improved direct digital frequency synthesizers. A synthesizer in one embodiment is comprised of an accumulator that provides a phase signal and an interpolator having two or more interpolation polynomials. The polynomial that processes the phase signal is selected by comparing the phase signal to a threshold value. A reduced complexity digital circuit is provided for implementing the improved synthesizer. | 12-04-2008 |
| 20080298528 | INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING THE SAME - According to one embodiment, an information processing apparatus has a radio communications unit, and has a first mode in which communications are established at a first communication speed and a second mode in which communications are established at a second communication speed lower than the first communication speed, and includes a determining unit configured to determine whether or not the apparatus is in a predetermined state, and a control unit configured to lower the communication speed of the radio communications unit and shift the first mode to the second mode if it is determined by the determining unit that the apparatus is in the predetermined state in the first mode. | 12-04-2008 |
| 20090010371 | SERIAL DATA COMMUNICATION SYSTEM AND METHOD - A serial data communication system ( | 01-08-2009 |
| 20090067560 | Parallel decoder - A parallel decoder for decoding a code division multiplexed (CDM) signal. The parallel decoder has two matched filters, both operating at a frequency equal to half the chip rate of the CDM signal. One matched filter correlates odd-numbered chips of the CDM signal with odd-numbered chips of the spreading code. The other matched filter correlates even-numbered chips of the CDM signal with even-numbered chips of the spreading code. The two resulting correlated signals are combined, and the decoded signal is obtained from the combined signal. This arrangement doubles the maximum possible chip rate of the CDM signal. | 03-12-2009 |
| 20090067561 | System and method for generating linear time code data - The present invention relates to a linear time code (LTC) generator that is adapted to generate LTC data. The LTC generator comprises a rising edge detector that is adapted to detect a frame sync input corresponding to a beginning of a frame time of video data and to generate a first synchronization signal corresponding to the frame sync input and a frame length measurement block that is adapted to count a number of clock cycles in the frame time. The LTC generator further comprises a bit rate calculator that is adapted to determine a bit rate of the frame time based on the number of clock cycles in the frame time and a bit rate counter block that is adapted to generate a second synchronization signal corresponding to the bit rate. Finally, the LTC generator comprises an output device that is adapted to insert a first data bit of the LTC data into a digital bit stream according to the first synchronization signal and to insert subsequent data bits of the LTC data ( | 03-12-2009 |
| 20090080582 | METHOD AND APPARATUS FOR ADJUSTING THE TIMING OF AN ELECTRONIC CIRCUIT - Methods and circuits for detecting variations in signal propagation rates within an electronic device, and for adjusting the output timing of the device in response to the variations in signal propagation rates. According to an embodiment of the invention, a signal may be propagated through an uncompensated delay chain and a compensated delay chain. If the signal passes through the compensated chain slower than through the uncompensated delay chain, then the device may delay a clock signal such that the output timing of the device will remain within the specification parameters. In contrast, if the signal passes through the uncompensated delay chain slower than through the compensated delay chain, the device may not delay the received clock signal such that the output timing of the device will remain within specification parameters. | 03-26-2009 |
| 20090092213 | Frequency Hold Mechanism in a Clock and Data Recovery Device - A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency. | 04-09-2009 |
| 20090116599 | Techniques for Signaling Reference Signal Parameters in a Wireless Communication System - A technique for operating a wireless communication device includes assigning a reference signal bandwidth to a reference signal. Cyclic shift control bits (associated with the reference signal) are then allocated based on the assigned reference signal bandwidth. The allocated cyclic shift control bits specify a cyclic shift associated with the reference signal. | 05-07-2009 |
| 20090122937 | FREQUENCY CALIBRATION APPARATUS OF FREQUENCY SYNTHESIZER AND FREQUENCY CALIBRATION METHOD THEREOF - A frequency calibration apparatus and method are provided. A frequency calibration method includes determining a frequency band according to results of frequency comparisons between a synchronized reference signal whose phase is synchronized to a phase of a prescale signal and a divided signal, and performing a Phase Locked Loop (PLL) operation on a reference signal and the divided signal at the determined frequency band to lock the divided signal. | 05-14-2009 |
| 20090147900 | METHOD AND DEVICE FOR DETECTING A SYNCHRONIZATION SIGNAL IN A COMMUNICATION SYSTEM - A method and a device for detecting a synchronization signal with a high identification rate are provided, which are suitable for a wide-area Orthogonal Frequency Division Multiplexing (OFDM) system. The method and device can precisely detect information of a synchronization signal, without being interfered by transmission channels and noises in an external environment. Three sliding windows are used to obtaining a balance value as an offset value for the output signal of the method and the device. A peak position of the output signal is identified and then compensated for a delay caused by the length of one of the sliding windows. Such a position is an edge of the synchronization signal. | 06-11-2009 |
| 20090175394 | METHODS AND APPARATUS FOR SYNCHRONIZATION AND DETECTION IN WIRELESS COMMUNICATION SYSTEMS - A synchronization and detection method in a wireless device may include performing coarse detection and synchronization with respect to a received signal. The synchronization and detection method may also include performing fine detection and synchronization for acquisition of the received signal. Results of the coarse detection and synchronization may be used for the fine detection and synchronization. The synchronization and detection method may also include performing tracking mode processing when the acquisition of the received signal has been achieved. | 07-09-2009 |
| 20090196389 | Signal processing method and circuit to convert analog signal to digital signal - A phase determination unit in a signal processing circuit generates sampling clocks with different phases in a clock generator and sequentially provides them to an analog-to-digital convertor. Then, the phase determination unit obtains differences between each adjacent two signal levels in each sampled digital signal by use of the sampling clocks, and monitors a polarity change in the differences, extracts a more inappropriate phase for use in sampling from phases of the sampling clocks on the basis of the absolute values of the differences where the polarity change is detected, and determines an antiphase of the extracted phase as a phase of the sampling clock to be provided to the analog-to-digital convertor. | 08-06-2009 |
| 20090202029 | OPTIMIZED PRIMARY SYNCHRONIZATION SEQUENCES FOR DEDICATED MULTIMEDIA BROADCAST/ MULTICAST SERVICE - A method optimizes a selection of primary synchronization channel (P-SCH) sequences from an available set of P-SCH indices for a dedicated Multimedia Broadcast/Multicast Service (MBMS). The criteria for selecting P-SCH indices include coprimeness, frequency offset sensitivity, multipath sensitivity, cross-correlation property in the time domain, auto-correlation property in the time domain and computation complexity at the receiver. | 08-13-2009 |
| 20090220038 | SYSTEMS AND METHODS FOR MULTIPLEXING MULTIPHASE CLOCKS - Various embodiments of the present invention provide systems, circuits and methods that allow for switching between two or more multiphase clocks. As one example, a system for switching between multiphase clocks is disclosed. The system includes a multiphase clock multiplexer. The multiphase clock multiplexer receives a first multiphase clock and a second multiphase clock. The first multiphase clock includes at least a first phase clock and a second phase clock, and the second multiphase clock includes at least a third phase clock and a fourth phase clock. The multiphase clock multiplexer receives a select signal, and is operable to output a first output corresponding to the first phase clock when the select signal is at a first assertion and corresponding to the third phase clock when the select signal is at a second assertion, and to output a second output corresponding to the second phase clock when the select signal is at the first assertion and corresponding to the fourth phase clock when the select signal is at the second assertion. | 09-03-2009 |
| 20090238320 | COMMUNICATION SYSTEM, COMMUNICATION METHOD, TRANSMITTING APPARATUS AND RECEIVING APPARATUS - A communication system, communication method, transmitting apparatus, and receiving apparatus are disclosed herein. The communication system includes: a first clock correlating unit, adapted to correlate a clock to be transmitted with a clock of a data frame at a transmitter of a clock transparent-transmission network; and a second clock correlating unit, adapted to correlate a clock of a data frame at a receiver of a clock transparent-transmission network with a clock to be recovered. The method includes: correlating the clock to be transmitted with the clock of the data frame at the transmitter of the clock transparent-transmission network, and correlating the clock of the data frame at the receiver of the clock transparent-transmission network with the clock to be recovered. | 09-24-2009 |
| 20090245446 | METHOD AND APPARATUS FOR DATA RATE CONTROL - Methods and apparatus for rate control are provided. An isochronous circuit controls data transmission between a first device and a second device. The first device outputs a set of data packets to the isochronous circuit at a first data rate, and the second device pulls the set of data packets from the isochronous circuit at a second data rate. The isochronous circuit comprises a buffer, a rate calculator and a register. The buffer buffers the set of data packets bound to the second device through a USB. The rate calculator monitors occupation of the buffer to estimate the second data rate. The register is coupled to the rate calculator for storage of the second data rate. The first device may access the estimate of the second data rate from the register to update the first data rate. | 10-01-2009 |
| 20090245447 | Generating a frequency switching local oscillator signal - Methods and systems of generating a frequency switching local oscillator signal are disclosed. One method includes generating a reference clock signal, and clocking a counter with the reference clock signal. The counter controls selection of a one of a plurality of analog values stored in at least one of a plurality of periodic signal generators. The frequency switching local oscillator signal is generated by selecting an output of a one of the plurality of periodic signal generators. | 10-01-2009 |
| 20090252266 | Arrangement for Synchronizing High-Frequency Transmitters of a Common-Wave Network - An arrangement for synchronizing a transmission time of a digital data stream in individual high-frequency transmitters of a common-wave network operating according to an ATSC standard and transmitting identical data at an identical frequency. The stream generated in a master station is supplied to the transmitters as a periodic succession of data frames, and a setpoint transmission time is calculated in the transmitters from a synchronizing time stamp inserted into the data frames within the master station and from a time reference used in the master station and transmitters, while the transmission of the frames by the transmitter is determined by a system clock in the transmitters. The setpoint transmission time is compared with the actual transmission time determined by the clock, and the clock frequency is regulated by a regulating circuit so that the actual transmission time determined by the clock corresponds with the calculated setpoint transmission time. | 10-08-2009 |
| 20090252267 | METHOD OF SYNCHRONIZING TWO ELECTRONIC DEVICES OF A WIRELESS LINK, IN PARTICULAR OF A MOBILE TELEPHONE NETWORK AND SYSTEM FOR IMPLEMENTING THIS METHOD - A method of synchronizing two electronic devices connected by a wireless link with at least one path including a transmission channel and a reception channel. The two devices are included in a network, such as a mobile telephone network. Synchronization information is transmitted directly from one electronic device to the other, as a clock pilot signal, via the channels. After recovery, the clock pilot signal is used for synchronization of a reference frequency of the receiving electronic device. | 10-08-2009 |
| 20090252268 | DATA RECEPTION APPARATUS - A data reception apparatus is disclosed. The data reception apparatus includes a strobe extractor for receiving a transmission signal and extracting a strobe signal from the transmission signal, the transmission signal including the strobe signal inserted between data signals and a clock signal following the strobe signal, the strobe signal having a different magnitude from a magnitude of a data signal, and the clock signal having an equal magnitude to the magnitude of the data signal, a clock recoverer for recovering the clock signal from the transmission signal, using the extracted strobe signal, and a sampler for sampling the data signals included in the transmission signal in response to the recovered clock signal. The probability of generating a timing skew error in the time interval between a clock signal and a data signal is minimized. Even though the level of a common component might change, the clock signal can be recovered accurately and the size of the clock recovery circuit can be reduced. Further, the data reception apparatus is suitable for transmitting/receiving data at a high transmission rate, and is robust against noise generated during transmission of the data signal and the clock signal, or against noise generated along a common path. | 10-08-2009 |
| 20090279654 | COMMUNICATION APPARATUS - There is provided a communication apparatus capable of reducing power consumption. The communication apparatus in accordance with the present invention includes a synchronization detection block | 11-12-2009 |
| 20090323877 | Data receiving apparatus and data receiving method - In a data receiving apparatus, a measuring section measures a first pulse width of a first pulse, a second pulse width of a second pulse and a third pulse width of a third pulse, during each of which a first signal level of a reception signal is continuous. The first pulse, the second pulse, and the third pulse are sequentially and continuously received by putting a portion of a second signal level different from the first signal level between the first and second pulse and the second and third pulse. A first comparing section performs a first determination based on a measured value of the first pulse width and a measured value of the second pulse width, and the first determination is that the first pulse indicates a start of the reception signal and the second pulse indicates a synchronization signal. A second comparing section performs a second determination based on the measured value of the first pulse width and the measured value of the second pulse width, and the second determination is that the second pulse and the third pulse indicate the synchronization signal. A control section determines the second pulse as a head of the synchronization signal, based on the first determination of the first comparing section and the second determination of the second comparing section. | 12-31-2009 |
| 20100034331 | FREQUENCY SYNCHRONIZATION APPARATUS - An apparatus for frequency synchronization is proposed to detect a synchronization signal from the baseband signals. It is featured that three types of detection values are introduced to detect whether the synchronization signal is received or not. More particularly, the claimed frequency synchronization apparatus provides at least one signal quality generator for receiving a predetermined number of symbols of the baseband signals, and further calculating an average quality value therefor. Further, the apparatus includes a signal selector for producing a first detection value according to the average quality value. Still further, the apparatus provides a decision unit to produce a second detection value. After that, a signal processor inside the decision unit is used to calculate a third detection value as combining the first detection value and the second detection. Consequently, the decision unit particularly decides whether the synchronization signal is received or not in reference with the third detection value. | 02-11-2010 |
| 20100086092 | Method of Efficiently Synchronizing to a Desired Timeslot in a Time Division Multiple Access Communication System - The time required for the receiving device to synchronize to a desired timeslot is reduced. In operation, a transmitting device selects a synchronization pattern associated with the desired timeslot that is at least mutually exclusive from synchronization patterns associated with other timeslots on the same frequency in the system. Once selected, the transmitting device transmits a burst embedding the synchronization pattern that was selected, where appropriate. If the receiving device detects the synchronization pattern, it immediately synchronizes with the timeslot with confidence that it is synchronizing to the desired timeslot. Using synchronization pattern associated with the desired timeslot that is at least mutually exclusive from synchronization patterns associated with the other timeslots on the same frequency also improves spectral efficiency in direct-mode transmissions, thus allowing more than one subscriber unit to simultaneously transmit in direct mode on a frequency without interfering with other transmissions on the frequency. | 04-08-2010 |
| 20100135447 | METHOD AND AN APPARATUS FOR SYNCHRONISING A RECEIVER TIMING TO TRANSMITTER TIMING - The present application relates to a method and an apparatus for synchronising a receiver timing to a transmitter timing using a known preamble of a signal. In at least one embodiment of the method and/or the apparatus of the present application, a power normalised cross-correlation metric (PNCC metric) is estimated based on a signal power and a noise floor power. According to a first embodiment, two cross-correlation functions, one based on the PNCC metric and the other based on a cross-correlation metric, are used to decide if synchronisation events occur and based on the analysis of time indexes and PNCC magnitude values, a timing synchronisation index used to synchronise receiver timing to transmitter timing is determined. According to a second embodiment, the cross-correlation function based on the PNCC metric is used to decide if synchronisation events occur and based on an analysis of time indexes and PNCC magnitude values using a clustering approach, a timing synchronisation index is determined. | 06-03-2010 |
| 20100135448 | SHARING APPARATUS OF REFERENCE SYNCHRONIZATION SIGNAL AND METHOD THEREOF - Provided are a reference synchronization signal sharing apparatus and a method thereof. The reference synchronization signal sharing apparatus according to the present invention includes a reference signal generator that generates an internal or external reference synchronization signal, and a system clock generator that generates a common system clock for detailed blocks of a wireless communication system in synchronization with the internal or external reference synchronization signal. | 06-03-2010 |
| 20100166130 | Phase Locked Loop with Optimal State Feedback Controller - In a method of recovering timing information over a packet network at a local receiver, timing information is received at intervals timing from a remote source and compared with a locally generated clock signal to generate an input signal y(k) subject to noise representative of the phase difference between the source clock signal and the local receiver clock signal. The input signal is applied to a state feedback controller, preferably including a Kalman filter, to generate a control signal with reduced noise. The control signal is used to control an oscillator in a way so as to reduce the phase difference and generate a slave clock. | 07-01-2010 |
| 20100172455 | METHOD AND SYSTEM FOR SWITCHING BETWEEN TWO (OR MORE) REFERENCE SIGNALS FOR CLOCK SYNCHRONIZATION - An apparatus and method is disclosed for synchronizing a timing signal for a computational system to different reference clock signals without impairing the operation of the computational system. A corresponding “offset” register is provided for each of the reference clock signals (RCS) for storing signal timing differences between the timing signal and RCS. When one of the reference clock signals not used for synchronizing the timing signal, is selected as the signal for synchronizing the timing signal, the corresponding offset register R | 07-08-2010 |
| 20100215135 | SYNCHRONOUS PROCESSING APPARATUS, RECEIVING APPARATUS AND SYNCHRONOUS PROCESSING METHOD - A receiving apparatus | 08-26-2010 |
| 20100260297 | APPARATUS AND METHOD FOR DETERMINING PHASE DIFFERENCE INFORMATION BETWEEN TWO SIGNALS - An apparatus for determining phase difference information between a first signal and a second signal includes a first detector, a second detector and a counter. The first detector is used for detecting a first value of the first signal, the second detector is used for detecting a second value of the second signal, and the counter is used for counting a timing when the first signal is at the first value and a timing when the second signal is at the second value with a reference clock signal to generate a counter value which serves as a basis of the phase difference information. | 10-14-2010 |
| 20100266080 | TRANSMISSION DEVICE, RECEIVING DEVICE AND COMMUNICATION SYSTEM - Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication system | 10-21-2010 |
| 20100303185 | Methods of Operating Wireless Communications Devices Including Detecting Times of Receipt of Packets and Related Devices - A method of operating a wireless communications device may include determining a wake-up time for a receiver using a low frequency clock. Beginning at the wake-up time, the receiver may listen for reception of a packet transmitted from a remote device over a wireless interface. An actual time of reception of the packet transmitted from the remote device may be detected, and a new wake-up time for the receiver may be determined using the low frequency clock and the actual time of reception of the packet. | 12-02-2010 |
| 20100322366 | METHOD FOR DETECTING FRAME SYNCHRONIZATION AND STRUCTURE IN DVB-S2 SYSTEM - Provided is a method for detecting frame sync and frame structure in a satellite broadcasting system, which acquires an estimated value for detecting frame structure and frame sync and overcomes distortion of correlation analysis values by summing differential correlation values for SOF positions in consideration of the variable frame length, and selecting a maximum value in a channel environment with low signal-to-noise ratio and high frequency error. SOF is a sync word indicating the start point of a frame. The method includes the steps of: acquiring SOF differential correlation value sequences; acquiring sums (d | 12-23-2010 |
| 20110002430 | SYNCHRONIZATION TRANSMISSIONS IN A WIRELESS COMMUNICATION SYSTEM - To support cell search, multiple (e.g., two) synchronization transmissions are sent in a frame with non-uniform spacing. Information is conveyed via the non-equal distances between consecutive synchronization transmissions. Multiple levels of non-uniform spacing may be used to convey different types of information. In one design, the multiple synchronization transmissions are sent in different subframes of a frame, and each synchronization transmission is sent in one of multiple symbol periods in a respective subframe. The synchronization transmissions may be sent in non-evenly spaced subframes to convey frame boundary. One synchronization transmission may be sent in one of multiple possible symbol periods depending on the information, e.g., a particular group of cell IDs, being conveyed. The distances between synchronization transmissions may also be used to convey cyclic prefix length. A secondary synchronization transmission carrying a cell ID may be sent at a predetermined offset from one of the multiple synchronization transmissions. | 01-06-2011 |
| 20110033017 | Method and Apparatus for Generating Synchronization Signals for Synchronizing Multiple Chips in a System - A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically. This invention resolves the uncertainty problem and allows the synchronization signals to be generated deterministically independent of the chip global clock cycle time. | 02-10-2011 |
| 20110058635 | Receiver for Receiving Signal Containing Clock Information and Data Information, and Clock-Embedded Interface Method - A receiver for receiving information that contains clock information and data information and a clock-embedded interface method. In the clock-embedded method, a clock signal and data may be reconstructed by receiving a pair of differential signals that contain clock information and data information and by using a change in a common voltage of the pair of differential signals. | 03-10-2011 |
| 20110080984 | COMMUNICATION APPARATUS USING SYNCHRONIZED CLOCK SIGNAL - A communication apparatus using a synchronized clock signal includes: a communication signal generation unit generating one of a baseband signal and a signal obtained by applying digital modulation to the baseband signal, as a communication signal; an interface unit transmitting the generated communication signal and receiving a communication signal from an external source; a communication signal analyzing unit analyzing the received communication signal; a clock signal providing unit providing a clock signal to the communication signal generation unit, the interface unit, and the communication signal analyzing unit; and a controller controlling the communication signal generation unit, the interface unit, the communication signal analyzing unit, and the clock signal providing unit. | 04-07-2011 |
| 20110122982 | BANDWIDTH SYNCHRONIZATION CIRCUIT AND BANDWIDTH SYNCHRONIZATION METHOD - Example embodiments are directed to a bandwidth synchronization circuit and a bandwidth synchronization method. The bandwidth synchronization circuit includes an upsizer and a syncdown unit. The upsizer includes a sync packer and a sync unpacker operating according to a first clock. The syncdown unit is connected to the upsizer and performs a syncdown operation on data of the upsizer in response to a second clock of a frequency lower than a frequency of the first clock. | 05-26-2011 |
| 20110150160 | METHODS AND SYSTEMS TO SYNCHRONIZE NETWORK NODES - Methods and systems to synchronize to a remote node counting rate, symbol rate, and carrier frequency as functions of an estimated frequency offset and relationships between the remote node carrier frequency and counting rate, and between the remote node carrier frequency and symbol rate. The carrier frequency offset may be scaled in accordance with a ratio between the carrier frequency and the remote counting rate to synchronize the local counting rate with the remote counting rate, and/or scaled in accordance with a relationship between the carrier frequency and the remote symbol rate to synchronize the a local receive path and/or transmit path sample rate with the remote symbol rate. The carrier frequency offset may applied as compensation in the receive path and/or the transmit path. The remote and local nodes may correspond to a network coordinator and an existing node, respectively, in a Multimedia Over Coax (MoCA) environment. | 06-23-2011 |
| 20110158364 | CLOCK SYNCHRONIZATION FOR A WIRELESS COMMUNICATIONS SYSTEM - Clock synchronization for a wireless communication system is described. The communication system utilizes a server with a radio coupled to receive a radio frequency (RF) signal and a clock interface to receive a reference clock signal. The server includes a network interface configured to receive, from a base station, a time that the RF signal was received at the base station. The server further includes a processing device configured to determine when the RF signal was transmitted and a location of the base station, and configured to calculate clock offset value representative of a time to delay a local clock signal at the base station to synchronize the local clock signal at the base station with the reference clock signal. | 06-30-2011 |
| 20110158365 | LOOP BANDWIDTH ENHANCEMENT TECHNIQUE FOR A DIGITAL PLL AND A HF DIVIDER THAT ENABLES THIS TECHNIQUE - A method of operating a phase locked loop (FIG. | 06-30-2011 |
| 20110235763 | SIGNALING SYSTEM WITH ASYMMETRICALLY-MANAGED TIMING CALIBRATION - In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time. | 09-29-2011 |
| 20110235764 | MESOCHRONOUS SIGNALING SYSTEM WITH MULTIPLE POWER MODES - In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time. | 09-29-2011 |
| 20110243288 | COOPERATIVE APPARATUS AND FREQUENCY SYNCHRONIZATION METHOD THEREOF FOR USE IN WIRELESS NETWORK - A cooperative apparatus and a frequency synchronization method thereof for use in a wireless network are provided. The wireless network comprises a base station and a subscriber station. The cooperative apparatus retrieves a signal from the base station and calculates a frequency offset between the base station and the cooperative apparatus according to the signal. Accordingly, the cooperative receives a cooperative information from the base station and forwards the cooperative information to the subscriber station based on the frequency offset. | 10-06-2011 |
| 20110261916 | SYSTEMS AND METHODS FOR DETECTING A SPECIFIC TIMING FROM A SYNCHRONIZATION CHANNEL - A method for detecting a specific timing from a synchronization channel is described. A signal with a known sequence is received. Two or more correlation values between the received signal and the known sequence are calculated at two or more positions. The two or more correlation values are compared. A determination is made whether the position of the known sequence has been shifted based on the comparison. A specific timing of a synchronization channel is detected based on the determination. | 10-27-2011 |
| 20110274227 | WIRELESS BASE STATION - A wireless base station capable of keeping an internal clock highly accurate even in a case where a malfunction occurs in an external time information notification server such as an NTP server. A wireless base station that performs wireless communication with a mobile terminal is connected to a plurality of time information notification servers. The wireless base station selects any of a plurality of pieces of time information notified from a plurality of time information notification servers, respectively, and corrects an internal clock based on the selected piece of time information. This can keep the internal clock of the wireless base station highly accurate. | 11-10-2011 |
| 20110299642 | NOISE SHAPED INTERPOLATOR AND DECIMATOR APPARATUS AND METHOD - Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator. | 12-08-2011 |
| 20110305307 | NETWORK NODE, COMMUNICATION SYSTEM, AND METHOD FOR TRANSMITTING CLOCK PACKET THROUGH TUNNEL - A network node, a communication system, and a method for transmitting a clock packet through a tunnel are disclosed. The method includes: encapsulating a tunnel ingress clock packet received at an ingress of a tunnel in an encapsulation mode corresponding to the tunnel, and performing clock correction for the encapsulated clock packet; and sending the corrected clock packet to an egress of the tunnel. The network node for processing a clock packet includes an encapsulating module and a sending module. The communication system includes the network node for processing a clock packet, and further includes an intra-tunnel network node and a tunnel egress network node. According to the present invention, a clock packet is re-encapsulated and transmitted through a tunnel. In the subsequent process of transmitting the clock packet transparently, the node itself serves as a clock reference point, and all network nodes do not need to synchronize time absolutely. | 12-15-2011 |
| 20120002772 | DATA CLOCK RECOVERY LOOP JAM SET USING SUBCARRIER FREQUENCY ESTIMATE - A method for jam setting an initial frequency of a data clock recovery loop according to one embodiment includes generating a frequency error signal in a frequency error detector from sideband signals within a backscattered radio frequency signal, wherein the frequency error accumulates in a frequency error filter coupled to an output of the frequency error detector; at about an end of an acquisition period, freezing the accumulated frequency error in the frequency error filter; and using the frozen accumulated frequency error to jam set an initial frequency of a data clock recovery loop. Such methodology may also be implemented as a system using logic for performing the various operations. Additional systems and methods are also presented. | 01-05-2012 |
| 20120014490 | REAL TIME DISTRIBUTED EMBEDDED OSCILLATOR OPERATING FREQUENCY MONITORING - A method for clock monitoring in a network is provided. The method comprises receiving a first network clock signal at a network device and comparing the first network clock signal to a local clock signal from a primary oscillator coupled to the network device. | 01-19-2012 |
| 20120033772 | SYNCHRONISER CIRCUIT AND METHOD - A synchronizer circuit and method for transferring data between mutually asynchronous source and destination clock domains. An input synchronizer cell clocked at an input clock frequency receives input data from the source domain and produces a corresponding intermediate signal. A frequency divider produces a divided clock signal whose frequency is equal to the input clock frequency divided by an integer. An output synchronizer module comprises first and second cascaded synchronizer cells clocked at the divided clock frequency, receives the intermediate signal and produces a corresponding output signal for the destination clock domain. | 02-09-2012 |
| 20120069942 | SYNC DETECTION AND FREQUENCY RECOVERY FOR SATELLITE SYSTEMS - A method of frame sync detection is described. A first and second differential correlation of a data stream is calculated, at a plurality of delay and conjugate multipliers. The first and second differential correlations are convolved with a previous set of differential correlations. A correlation peak is calculated, at a sync detector, using the convolved differential correlations, to detect a frame sync. | 03-22-2012 |
| 20120082281 | METHOD AND APPARATUS FOR CLOCK CHECKING - Disclosed is a method and apparatus for clock checking, to solve the problem of high resource occupation in existing clock checking methods. The method includes: a programmable device for performing frequency division on the source clock signal to obtain a reference clock signal; treating the source clock signal as a counting work clock to determine the counting value of rising edges and counting value of high levels of a clock signal being checked during each high level period out of N continuous high levels of the reference clock signal; and determining whether the clock signal being checked is valid according to the magnitude relationship between the counting value of the high levels of the clock signal being checked during each high level period and a first expected value, as well as the magnitude relationship between the counting value of the rising edges and a second expected value. | 04-05-2012 |
| 20120114087 | EXPLICIT SKEW INTERFACE FOR REDUCING CROSSTALK AND SIMULTANEOUS SWITCHING NOISE - Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise. | 05-10-2012 |
| 20120140862 | NON-COHERENT SECONDARY SYNCHRONIZATION SIGNAL DETECTING METHOD, DEVICE AND CORRESPONDING COMPUTER PROGRAM - A method and apparatus are provided for identifying a cell and a sub-frame by detecting a part of a secondary synchronization signal including a sequence of N OFDM symbols. For each OFDM symbol, the method obtains a set of metrics, each metric being associated with a predetermined combination of a cell identifier and a sub-frame alignment (CID/SF). For each metric, the method counts the number of times a metric exceeds a first predetermined threshold, delivering a summed value, and applies an M of N criterion to the summed value, delivering a ratio value. The ratios values are analyzed in order to identify the cell and the sub-frame, corresponding to a cell identifier and a sub-frame alignment, associated to a particular ratio value among the ratios values, which exceeds a second predetermined threshold. | 06-07-2012 |
| 20120155588 | CLOCK RESYNCHRONIZATION CIRCUIT AND METHOD - A control circuit receives a first clock signal at a first frequency, a frequency division signal specifying a divisor number, and a second clock signal at a second frequency (higher than the first frequency). The control circuit includes a phase control block that defines non-overlapping portions of a pulse of the second clock to include center, left and right portions. A determination is then made as to whether an edge of the first clock is located within the center portion. In response to such a determination, a number of periods of the second clock signal which occur within one or more periods of the first clock signal is compared to a number derived from the divisor number to generate a frequency selection signal indicative of that comparison. A controlled oscillator circuit generates the second clock signal at the second frequency, wherein the second frequency is specified by the frequency selection signal. To the extent the edge of the first clock is located within either the left or right portions, phase adjustment is made to move the edge towards the center portion. | 06-21-2012 |
| 20120163523 | SYNCHRONIZATION METHODS FOR DOWNHOLE COMMUNICATION - A method for synchronizing a waveform received in a subterranean borehole with a transmitted waveform includes at least one of a phase synchronization, a symbol synchronization, or a frame synchronization method. The phase and symbol synchronization methods make use of distinct loop filters which process corresponding feedback signals so as to output phase clock and symbol clock adjustments. Frame synchronization methods accumulate a preamble correlation on a symbol stream having at least one repeating preamble. | 06-28-2012 |
| 20120177160 | COMMUNICATION CIRCUIT AND METHOD OF ADJUSTING SAMPLING CLOCK SIGNAL - A communication circuit includes a sampling clock generating circuit generating a sampling clock signal having a frequency that is “m” times greater than a bit rate of the communication data and containing “n” pulses in each bit period of the communication data; and a sampling circuit sampling the communication data based on the sampling clock signal to obtain “n” sets of received data in each bit period of the communication data. The sampling clock generating circuit delays the sampling clock signal when a first one or more of the “n” sets of received data are different from a value of the rest of the “n” sets of received data, and advances the sampling clock signal when a value of a last one or more of the “n” sets of received data is different from a value of the rest of the “n” sets of received data. | 07-12-2012 |
| 20120230456 | MULTITONE SIGNAL SYNCHRONIZATION - In one embodiment, a method to generate a set of tone frequencies within an operating frequency range for use in a timing acquisition process in a wireless communication system comprises selecting a system frequency resolution generating a set of frequency tones which are relatively prime integers with respect to the frequency resolution and within an operating frequency range of the wireless communication system. Other embodiments may be described. | 09-13-2012 |
| 20120257700 | NETWORK ELEMENT OF A COMMUNICATION NETWORK - It is disclosed a network element for a communication network configured to synchronize its local clock to a reference clock signal. The network element comprises: a main board comprising an internal module configured to support an internal synchronization transport protocol, and a connector connected to the internal module; and a pluggable module configured to be removably connected to the connector. The pluggable module is configured to, when connected to the connector: exchange external synchronization information with a further network element, the external synchronization information being formatted according to an external synchronization transport protocol different from the internal synchronization transport protocol; exchange with the internal module internal synchronization information formatted according to the internal synchronization transport protocol; and interface the internal synchronization transport protocol and the external synchronization transport protocol. | 10-11-2012 |
| 20120275554 | Base Station Synchronization - The invention relates to transmission and reception of clock synchronization data in a wireless communication system. According to the invention a device for transmitting clock synchronization data obtains at least one time reference of a wireless communication system clock, controls transmission of a frequency reference of the wireless communication system clock via an air interface of the wireless communication system, and provides transmission of the time reference via a transport network associated with the wireless communication system, while the base station receives the frequency reference, locks an own oscillator to the frequency of the frequency reference, receives the time reference from the transport network and adjusts timing that is controlled by the oscillator based on the time reference. | 11-01-2012 |
| 20120275555 | METHODS AND APPARATUS FOR TRIMMING OF CDR CLOCK BUFFER USING PHASE SHIFT OF TRANSMIT DATA - Methods and apparatus are provided for trimming one or more clock buffers in a clock and data recovery system in a receiver using a phase shift of the transmit data. At least one clock buffer is trimmed by synchronizing the clock and data recovery system to a transmit clock received from a transmitter. A transmit data signal that is received from the transmitter is then sampled using at least a first latch in the receiver. A phase of the transmit data signal is adjusted in the transmitter until values sampled by the first latch satisfy a first predefined criteria (such as approximately 50% binary ones and 50% binary zeroes). The phase of the transmit data signal is adjusted again to an approximate phase location of a second latch in the receiver, and the transmit data signal is sampled using the second latch. A phase of a clock buffer associated with the second latch is then adjusted until values sampled by the second latch satisfy a second predefined criteria. | 11-01-2012 |
| 20120288046 | Signal Calibration Method and Client Circuit and Transmission System Using the Same - A signal calibration method for synchronizing a clock signal and at least one data signal in a transmission system is disclosed. The signal calibration method comprises detecting at least one transmission time difference between the clock signal and the at least one data signal transmitted in the transmission system, calculating a plurality of delay periods of the clock signal and the at least one data signal according to the at least one transmission time difference, and respectively delaying the clock signal and the at least one data signal for the plurality of delay periods to synchronize the clock signal and the at least one data signal. | 11-15-2012 |
| 20120294401 | METHOD OF CALIBRATING SIGNAL SKEWS IN MIPI AND RELATED TRANSMISSION SYSTEM - In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock signal, and a test data signal is provided by adjusting the phase of the data signal. By latching the test data signal according to the test clock signal, a latched data may be acquired for determining an optimized phase relationship corresponding to the clock lane and the data lane. When transmitting the clock signal and the data signal in normal mode, the signal delays of the clock lane and the data lane may be adjusted according to the optimized phase relationship. | 11-22-2012 |
| 20120300889 | METHOD AND A DEVICE FOR CONTROLLING FREQUENCY SYNCHRONIZATION - A device for controlling frequency synchronization includes a processor for controlling a frequency-controlled clock signal on the basis of received timing messages so as to achieve frequency-locking between the frequency-controlled clock signal and a reference clock signal. For the purpose of finding such timing messages which have experienced similar transfer delays and thus are suitable for the frequency control, the processor is configured to control a phase-controlled clock signal on the basis of the timing messages so as to achieve phase-locking between the phase-controlled clock signal and the reference clock signal, and to select the timing messages to be used for the frequency control on the basis of phase-error indicators related to the phase control. Thus, the phase-controlled clock signal is an auxiliary clock signal that is utilized for performing the frequency control. | 11-29-2012 |
| 20130034197 | METHOD AND SYSTEM FOR FREQUENCY SYNCHRONIZATION - The present invention provides a method of synchronising the frequency of a slave clock to that of a master, preferably using a packet network. An aspects of the invention provide a method of synchronizing the frequency of a slave clock in a slave device to a master clock in a master device, the method including the steps of: a) receiving in the slave device a first message from said master device having a first time-stamp which is a time-stamp of said master clock indicating the time of sending of said first message; b) extracting said time-stamp from said message and initializing a counter in the slave device which counts an output of said slave clock; c) receiving in the slave device a further message from said master device and reading the value of said counter at the time of receipt of said further message; d) extracting a further time-stamp which is the precise time of sending of the further message according to said master clock; e) determining an error signal which is representative of the difference between said value of the counter and the difference between said first and further time-stamps; and f) adjusting the frequency of said slave clock based on said error signal. An apparatus for synchronizing the frequency of a clock in a slave device which is communicatively coupled to a master device is also provided. | 02-07-2013 |
| 20130070881 | PHASE LOCKED LOOP AND ASSOCIATED PHASE ALIGNMENT METHOD - A phase locked loop and an associated alignment method are provided. A disclosed phase locked loop receives a reference signal to provide a feedback signal. The phase locked loop is first opened. When the phase locked loop is open, a frequency range of an oscillating signal from a voltage-controlled oscillator is substantially selected. The feedback signal is provided according to the oscillation signal. After the frequency range is selected, the phase locked loop is kept open and the phases of the reference signal and the feedback signal are substantially aligned. The phase locked loop is then closed after the reference signal and the feedback signal are aligned. | 03-21-2013 |
| 20130077724 | DIGITAL PHASE DETECTOR WITH ZERO PHASE OFFSET - An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal. | 03-28-2013 |
| 20130107998 | Clock Synchronization in Shared Baseband Deployments | 05-02-2013 |
| 20130107999 | Synchronization of Nodes in a Network | 05-02-2013 |
| 20130108000 | METHOD AND APPARATUS FOR PERFORMING SYNCHRONIZATION BETWEEN DEVICES | 05-02-2013 |
| 20130195235 | METHOD AND APPARATUS FOR SWITCHING CLOCK FREQUENCY IN A SYSTEM-IN-PACKAGE DEVICE - An apparatus includes a first clock source, a second clock source and circuitry configured to supply a clock signal to a circuit. The circuitry operates to change the clock signal from one frequency to another different frequency. This change is made in a manner whereby no clock signal is supplied during a period of time when the change from the one frequency to the another different clock frequency is being made. | 08-01-2013 |
| 20130230132 | RECEIVER AND SIGNAL TESTING METHOD THEREOF - A receiver includes a CDR circuit, serial-to-parallel converter, and test module. The CDR circuit is for receiving the test signal groups inputted in series and following transmitting frequency of the test signal groups to obtain a clock signal, wherein the clock signal is used to provide an operational frequency of the receiver. The serial-to-parallel converter is for receiving the test signal groups outputted by the CDR circuit and converting the serially-inputted test signal groups into a plurality of test bytes outputted in parallel, wherein each of the test bytes has multi-bit of data. The test module is for receiving the test bytes and the clock signal and comparing two adjacent bytes of the test bytes to determine whether the two adjacent test bytes are completely the same. | 09-05-2013 |
| 20130243140 | Method for Transmitting Synchronization Messages in a Communication Network - A method for transmitting synchronization messages in a communications network including a plurality of nodes having a first node and at least one second node, wherein in order to take into account differences in a reference clock frequency of a reference clock and an internal clock frequency of an internal clock of the at least one second node, a compensation interval, with which the second clock count state is adjusted on measurement of a delay time, is subdivided into smaller compensation timespans, and the smaller compensation timespans are used to determine a compensated time value for the delay time with a high degree of accuracy, where the compensated time value is then used to update the time information in the synchronization message. | 09-19-2013 |
| 20130243141 | COMMUNICATION SYSTEM, DATA TRANSMITTER, AND DATA RECEIVER CAPABLE OF DETECTING INCORRECT RECEIPT OF DATA - A transmitter cyclic pattern having a pattern length of N bits is generated and converted into an M-bit transmitter parallel data stream, where N≠M. A bit-sequence altered transmitter parallel data stream is generated by performing a transmitter altering process, converted into a serial data and transmitted together with a clock signal. The serial data is received and converted into an M-bit receiver parallel data stream, and a bit-sequence restored parallel data stream is generated by performing a process opposite to the transmitter altering process. A receiver cyclic pattern is generated by using bits in the bit-sequence restored parallel data stream and converted into an M-bit reference parallel data stream, and a bit-sequence altered reference parallel data stream is generated by performing a process same as the transmitter altering process and compared with the received parallel data to test if the data is correctly received. | 09-19-2013 |
| 20130243142 | Method of Synchronizing Two Electronic Devices of a Wireless Link, in Particular of a Mobile Telephone Network and System for Implementing This Method - A method of synchronizing two electronic devices connected by a wireless link with at least one path including a transmission channel and a reception channel. The two devices are included in a network, such as a mobile telephone network. Synchronization information is transmitted directly from one electronic device to the other, as a clock pilot signal, via the channels. After recovery, the clock pilot signal is used for synchronization of a reference frequency of the receiving electronic device. | 09-19-2013 |
| 20130287155 | SIGNAL SOURCE SYNCHRONIZATION CIRCUIT - A signal source synchronization circuit includes: a first TDC circuit that measures a first path delay time which is a time difference between an input time of a trigger signal to a first input terminal and an input time of the trigger signal to a second input terminal; and a second TDC circuit that measures a second path delay time which is a time difference between an input time of the trigger signal to a first input terminal and an input time of the trigger signal to a second input terminal, wherein a first phase shifter adjustment circuit sets a phase adjustment amount corresponding to the first path delay time in a first phase shifter, and a second phase shifter adjustment circuit sets a phase adjustment amount corresponding to the second path delay time in a second phase shifter. | 10-31-2013 |
| 20130315359 | Adaptive frequency synthesis for a serial data interface - Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate. | 11-28-2013 |
| 20140093023 | RF Carrier Synchronization and Phase Alignment Methods and Systems - A method comprising generating a baseband information signal by mixing a received modulated carrier signal with a local oscillator (LO) signal having an LO frequency; obtaining baseband signal samples of the baseband information signal having a baseband signal magnitude and a baseband signal phase; determining a cumulative phase measurement associated with baseband signal samples having a baseband signal magnitude greater than a threshold; and, applying a correction signal to compensate for an LO frequency offset of the LO frequency based on the cumulative phase. | 04-03-2014 |
| 20140093024 | RF Carrier Synchronization and Phase Alignment Methods and Systems - A method comprising generating a baseband information signal by mixing a received modulated carrier signal with a local oscillator (LO) signal having an LO frequency; obtaining baseband signal samples of the baseband information signal having a baseband signal magnitude and a baseband signal phase; determining a cumulative phase measurement associated with baseband signal samples having a baseband signal magnitude greater than a threshold; and, applying a correction signal to compensate for an LO frequency offset of the LO frequency based on the cumulative phase. | 04-03-2014 |
| 20140105341 | SYNCHRONIZATION SYSTEM AND METHOD FOR ACHIEVING LOW POWER BATTERY OPERATION OF A VEHICLE LOCATING UNIT IN A STOLEN VEHICLE RECOVERY SYSTEM WHICH RECEIVES PERIODIC TRANSMISSIONS - Synchronization for achieving low power battery operation of a vehicle locating unit in a stolen vehicle recovery system whose radio receiver receives periodic transmissions, includes receiving periodic transmissions; turning on a radio receiver for a limited time to detect an expected message; if an expected message is not found, turning off the receiver and turning it on again after a time asynchronous with the transmission period; and after finding an expected message, waiting for the period of the transmissions less the length of an expected message and then looking for a synchronization symbol in the expected message and synchronizing subsequent actuation of the receiver using that synchronization symbol. | 04-17-2014 |
| 20140126677 | HIGH PRECISION SYNCHRONIZED MEASURED VALUE ACQUISITION - The invention relates to a method for wire bound, high precision, temporal synchronization of measured value acquisition in a measurement system designed as a space coordinate measurement apparatus having a plurality of measurement sub-units with signaling of a time for triggering the measured value acquisition by means of a trigger signal and with the respective acquisition and intermediate storage of a measured value in the measurement sub-unit at the time determined by the trigger signal. Each acquisition of the measured value is carried out in the measurement sub-units in a time quantified manner with a local timing signal of the measurement sub-unit. A phase synchronization of the local timing signals of the measurement sub-units is then carried out using a synchronization signal in order to ensure simultaneity of the acquisition of the measured value in the measurement sub-units with a temporal uncertainty which does not exceed a phase jitter of the synchronization, and which is in any case less than 90% of a period duration of the local timing signal. | 05-08-2014 |
| 20140140457 | CLOCK FREQUENCY ADJUSTMENT FOR SEMI-CONDUCTOR DEVICES - A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer. | 05-22-2014 |
| 20140146931 | SYNCHRONIZATION CONTROL APPARATUS, ARITHMETIC PROCESSING DEVICE, PARALLEL COMPUTER SYSTEM, AND CONTROL METHOD OF SYNCHRONIZATION CONTROL APPARATUS - A synchronization control apparatus is included in an arithmetic processing device. The arithmetic processing device is connected to another arithmetic processing device via a data transfer device. The synchronization control apparatus is connected to a clock divider which divides an input clock signal into N. In the synchronization control apparatus: a detecting unit detects the rising or the falling of a divided clock signal; a monitoring unit monitors the elapsed time since the rising or the falling of the divided clock signal; a clock generating unit generates a control clock by multiplying the divided clock signal by N; a synchronization request receiving unit receives a synchronization request from the other arithmetic processing device; a clock control unit outputs the control clock; a synchronization request sending unit sends a synchronization request to the other arithmetic processing device via the data transfer device. | 05-29-2014 |
| 20140161214 | Automatic Clock Calibration of a Remote Unit Using Phase Drift - An automatic calibration of a clock of a wireless portable part with respect to a clock of a fixed part in a field environment. The calibration performed in the field environment negates the need to calibrate the clock during manufacture and negates the need for an initial field recalibration because of temperature differences between manufacture and the field. In performing the calibration the frequency of the clock of the portable part is varied until the portable part is synchronous with the fixed part to with in a range of timing bits. The portable part is declared calibrated after remaining calibrated for a defined number of data frames. | 06-12-2014 |
| 20140211897 | METHODS AND APPARATUS FOR GENERATING CLOCK SIGNALS BY NORMALIZING DUTY CODE TO PERIOD CODE - A clock signal generating method includes receiving a duty code that represents a duty of a clock signal, and a period code that represents a period of a clock signal, and normalizing the duty code to the period code to output a normalized duty code. The clock signal generating method further includes controlling a rising timing of a clock signal in response to the period code, and controlling a falling timing of the clock signal in response to the normalized duty code to generate a timing-controlled clock signal. | 07-31-2014 |
| 20140219406 | CLOCK DATA RECOVERY CIRCUIT MODULE AND METHOD FOR GENERATING DATA RECOVERY CLOCK - A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided. | 08-07-2014 |
| 20140241478 | Timing Phase Estimation for Clock and Data Recovery - In order to initialize the phase of the recovered clock signal used in clock-and-data recovery (CDR) circuitry, the normal, on-line CDR processing is disabled. The sum of the absolute values of analog-to-digital converter (ADC) samples are generated for different clock phases over each unit interval (UI) of the analog signal sampled by the ADC for a specified period of time. The phase corresponding to the maximum sum is selected as the initial phase for the recovered clock signal for enabled, on-line CDR processing, which among other things, automatically updates the clock phase to ensure that the ADC samples the analog signal near the center of each UI. | 08-28-2014 |
| 20140241479 | FREQUENCY DIFFERENCE DETECTION DEVICE, FREQUENCY DIFFERENCE DETECTION METHOD, AND PROGRAM - The present disclosure relates to a frequency difference detection device that can synchronize oscillation frequency with a master device in a network with high precision, and also relates to a frequency difference detection method and a program. | 08-28-2014 |
| 20140254733 | CIRCUIT TO RECOVER A CLOCK SIGNAL FROM MULTIPLE WIRE DATA SIGNALS THAT CHANGES STATE EVERY STATE CYCLE AND IS IMMUNE TO DATA INTER-LANE SKEW AS WELL AS DATA STATE TRANSITION GLITCHES - A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol is differentially encoded in state transitions of the differentially encoded signal. The clock extraction circuit may be adapted to obtain a clock signal from state transition signals derived from the state transitions while compensating for skew in the different data lines, and masking data state transition glitches. | 09-11-2014 |
| 20140270029 | APPARATUS AND METHOD FOR SUPPORTING DEVICE TO DEVICE COMMUNICATION - A method for operating a device in a wireless communication system supporting Device to Device (D2D) communication system includes receiving a reference signal from each of at least one transmitting device, estimating a frequency offset between the reference signals and a comparison reference signal corresponding to the reference signals, and adjusting a transmit frequency of a voltage controlled oscillator of the device using the estimated frequency offset estimation. An apparatus for compensating for a frequency offset of a device in a wireless communication system supporting Device to Device (D2D) communication system includes a frequency offset estimator configured to receive reference signals from each of at least one transmitting device, and estimating a frequency offset between the reference signals and a comparison reference signal corresponding to the reference signals, and a voltage controlled oscillator configured to adjust a transmit frequency using the estimated frequency offset. | 09-18-2014 |
| 20140286467 | NOISE SHAPED INTERPOLATOR AND DECIMATOR APPARATUS AND METHOD - Interpolator and decimator apparatuses and methods are improved by the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator. | 09-25-2014 |
| 20140294132 | CLOCK PHASE INTERPOLATOR, DATA TRANSMISSION AND RECEPTION CIRCUIT, AND METHOD OF CLOCK PHASE INTERPOLATION - A clock phase interpolator includes: a phase interpolation processing circuit configured to generate an interpolated clock signal whose phase is interpolated from a plurality of operation clock signals having different phases; a band adjustment element coupled to the phase interpolation processing circuit, and configured to adjust an operational frequency band of the phase interpolation processing circuit by changing a setting value of itself; and a control circuit coupled to the phase interpolation processing circuit, and configured to detect a transition state for a reference clock signal of the interpolated clock signal, and configured to control the setting value of the band adjustment element on the basis of the detected transition state. | 10-02-2014 |
| 20140321586 | SYSTEM FOR HIGH-CLOCK SYNCHRONIZATION AND STABILITY - Systems and methods for high-clock synchronization and stability are disclosed. | 10-30-2014 |
| 20140328443 | Synchronous Data Transmission System - A synchronous data transmission system for transmission of data between two communication partners, of which one serves as a transmitter and one as a receiver, comprising a clock signal producer which produces a transmission clock signal with a transmission clock signal rate from the transmitter to the receiver, which during the occurrence of one of the events equals an event specific transmission clock signal rate associated with the arising event and during an event free period of time equals a fundamental clock rate different of all event specific transmission clock signal rates. | 11-06-2014 |
| 20140334583 | CLOCK EMBEDDED OR SOURCE SYNCHRONOUS SEMICONDUCTOR TRANSMITTING AND RECEIVING APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING SAME - The present invention relates to a clock-embedded or source synchronous semiconductor transmitting and receiving apparatus and to a semiconductor system including same. The semiconductor apparatus according to one embodiment of the present invention includes: a data providing unit for providing differential data; a multi-phase clock generator for generating a first clock signal provided to the data providing unit, and a second clock signal having a different phase from the first clock signal; and a combining unit for receiving the differential data and the second clock signal and combining same to generate a combined signal, wherein the second clock signal is a single clock signal and has n (here, n is an integer of two or greater) times a symbol period of the differential data, the first and second clock signals have a 90 degree phase difference, and the combination signal is transmitted to the outside through differential transmission lines. | 11-13-2014 |
| 20140348281 | SEMICONDUCTOR DEVICES AND ELECTRONIC SYSTEMS INCLUDING THE SAME - Semiconductor devices are provided. The semiconductor device includes an internal clock generator and an internal strobe signal generator. The internal clock generator generates an internal clock signal having a frequency which is higher than that of an input clock signal according to a phase difference between the input clock signal generated from an external device and a first input control signal. The internal strobe signal generator generates an internal strobe signal having a frequency which is higher than that of an input strobe signal according to a phase difference between the input strobe signal generated from the external device and a second input control signal. | 11-27-2014 |
| 20150023459 | RECEPTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A reception circuit includes: a plurality of block circuits that each include a phase control circuit that controls a phase of a first clock, and a plurality of internal circuits that are driven by a second clock generated based on the phase-controlled first clock, wherein the phase control circuit in each of the block circuits is controlled by means of a control signal from an operation phase control circuit in such a way that an error rate for reception data due to the plurality of block circuits decreases. | 01-22-2015 |
| 20150036774 | CLOCK AND DATA RECOVERY CIRCUIT - A CDR circuit includes an AD converter that converts an analog input signal to a digital output signal according to an operation clock signal; a phase adjuster that subtracts a first phase from a first clock signal having a first frequency equal to a frequency of the input signal to output a second clock signal having a second frequency as the operation clock signal to the AD converter; a phase detector that detects a second phase in the output signal of the AD converter; a filter that obtains a third phase by performing a filtering process based on the first phase, the second phase, and the third phase output from the filter; an adder that adds the first phase and the third phase to obtain a fourth phase; and a decision circuit that obtains recovered data from the output signal of the AD converter using the fourth phase. | 02-05-2015 |
| 20150043695 | RECEPTION CIRCUIT - A reception circuit has: a phase detector that detects a phase code based on a phase of data in relation to a first clock signal; a calibration signal generator that, in a calibration mode, adjusts a frequency of the first clock signal or the data so that the phase code detected by the phase detector changes; a calibrator that, in the calibration mode, stores a difference between the phase code and an ideal value of the detected phase, and that, in a normal operation mode, outputs the ideal value in correspondence with the phase code detected by the phase detector; and a phase adjustor that, in the normal operation mode, adjusts a phase of the first clock signal based on the phase code detected by the phase detector and the ideal value, and that outputs to the phase detector. | 02-12-2015 |
| 20150071394 | WIRELESS COMMUNICATION DEVICE AND ACTIVATION METHOD OF THE WIRELESS COMMUNICATION DEVICE - A wireless communication device includes a BBIC for performing baseband signal processing, an RFIC for performing radio-frequency signal processing, and a quartz resonator. The RFIC has a storage unit which stores an adjustment value for adjustment of a clock frequency that is based on an oscillation frequency of the quartz resonator, and outputs the adjustment value when its resetting active state is canceled; a frequency adjusting unit for adjusting the clock frequency according to the adjustment value; and an RF signal processing unit which operates based on the clock signal and performs the radio-frequency signal processing. | 03-12-2015 |
| 20150098541 | SYNCHRONIZING PHASES BETWEEN LOCAL LO GENERATION CIRCUITS - Embodiments of a system and method for synchronizing chains in a transceiver using central synchronization signals are generally described herein. In some embodiments, an RF signal having a reference frequency in a differential mode and a synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are produced at a oscillator generation circuit. The RF signal having a reference frequency in a differential mode and the synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are provided over each of a plurality of LO lines to a plurality of local LO generation circuit chains. Each synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode is extracted at the plurality of local LO generation circuit chains. A phase of each RF signal having a reference frequency in a differential mode is synchronized in each of the plurality of local LO generation circuit chains using each extracted synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode. | 04-09-2015 |
| 20150110231 | SYSTEMS AND METHODS FOR WIRELESS CLOCK SYNCHRONIZATION - Systems and methods are disclosed herein to provide improved clock synchronization between wireless data communication transmitters and receivers, including Orthogonal Frequency Division Multiplexing (OFDM) communication systems. In accordance with one or more embodiments, a clock synchronization system is disclosed that includes an adaptive threshold function operative in conjunction with a synchronizer that adjusts the frequency and phase of a receive clock oscillator. Such a synchronization system may offer improved capabilities such as resistance to radio frequency (RF) channel impairments and noise, rejection of mis-decoded clock synchronization signals, and handling of multiple transmitters. | 04-23-2015 |
| 20150124916 | SYSTEM TIMING MARGIN IMPROVEMENT OF HIGH SPEED I/O INTERCONNECT LINKS BY USING FINE TRAINING OF PHASE INTERPOLATOR - Methods and apparatus for improving system timing margin of high speed I/O (input/output) interconnect links by using fine training of a phase interpolator are described. In some embodiments, I/O links use forward clock architecture to send data from transmit driver to receiver logic. Moreover, at the receiver side, Phase Interpolator (PI) logic may be used to place the sampling clock at the center of the valid data window or eye. In an embodiment, a Digital Eye Width Monitor (DEWM) logic may be used to measure data eye width in real time. Other embodiments are also disclosed. | 05-07-2015 |
| 20150124917 | CLOCK SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR DEVICE - A clock synchronization circuit is configured to capture an input data bit according to an input clock signal, and to synchronize and output the input data bit. The clock synchronization circuit includes a clock buffer for generating an internal clock signal according to the input clock signal and transmitting the internal clock signal to a clock line. The clock synchronization circuit further includes a D flip-flop for capturing and outputting the input data bit at an edge timing of the internal clock signal. The clock buffer includes an inverter core portion and an electric current suppressing portion. The inverter core portion is configured to generate the internal clock signal through alternately supplying an electric current to the clock line and drawing the electric current from the clock line according to the input clock signal. The electric current suppressing portion is configured to suppress an amount of the electric current. | 05-07-2015 |
| 20150333901 | HIGH-SPEED SERIAL COMMUNICATION RECEIVER CIRCUIT - A high-speed serial communication receiver circuit includes a receiver circuit which receives a high-speed differential signal generated by adding a clock signal to communication data, to convert the differential signal to a binarized input data signal, a clock data recovery circuit which synchronizes an internal clock signal with the input data signal from the receiver circuit in phase to reproduce a restored clock signal and restored communication data for output, and a controller which controls an oscillation frequency of the internal clock signal to synchronize with the input data signal in phase, and controls the oscillation frequency of the internal clock signal to be constant when the high-speed operation signal contains noise. | 11-19-2015 |
| 20150341159 | NOISE SHAPED INTERPOLATOR AND DECIMATOR APPARATUS AND METHOD - An interpolator or decimator includes an elastic storage element in the signal path between first and second clock domains. The elastic element may, for example, be a FIFO which advantageously allows short term variation in sample clocks to be absorbed. A feedback mechanism controls a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator. | 11-26-2015 |
| 20150341164 | COMPUTING SYSTEM WITH SYNCHRONIZATION MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: a communication unit configured to: identify a first synchronization symbol and a second synchronization symbol corresponding to a synchronization signal, generate the synchronization signal including the first synchronization symbol and the second synchronization symbol using a synchronization generator mechanism and a prefix generator mechanism; and an inter-device interface coupled to the communication unit, configured to communicate the synchronization signal for synchronizing a first device and a second device for communicating a serving content. | 11-26-2015 |
| 20150358150 | RISING AND FALLING EDGE DETECTION AND RE-ASSEMBLY FOR HIGH SPEED SERIAL DATA COMMUNICATIONS - A method according to one embodiment includes receiving a serialized data stream; detecting rising and falling edges in the serialized data stream; correlating the rising and falling edges to data values using a clock signal that is not derived from the serialized data stream; and converting the serialized data stream to a parallel data stream. In a further embodiment a system includes a processor and logic integrated with and/or executable by the processor. The logic is configured to receive a serialized data stream; detect rising and falling edges in the serialized data stream; correlate the rising and falling edges to data values using a clock signal that is not derived from the serialized data stream; and convert the serialized data stream to a parallel data stream. | 12-10-2015 |
| 20150365225 | TRACING DATA FROM AN ASYNCHRONOUS INTERFACE - An apparatus for tracing data from a data bus in a first clock domain operating at a first clock frequency to a trace array in a second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency. The apparatus includes a change detector to detect a change of the data on the data bus in the first clock domain, a trigger responsive to the change detector to send a trigger pulse to the second clock domain, pulse synchronization on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse to the second clock frequency of the second clock domain by a meta-stability latch, as well as a data capture in the second clock domain responsive to the pulse synchronization to capture data from the data bus and to store the captured data in the trace array. | 12-17-2015 |
| 20160006557 | RECEPTION APPARATUS, PHASE ERROR ESTIMATION METHOD, AND PHASE ERROR CORRECTION METHOD - In a phase error corrector, a signal extractor extracts received reference signals from received signals, and an error vector calculator calculates the error vectors of phase errors by comparing the extracted received reference signals with a known reference signal that is to be transmitted. A representative vector calculator divides, according to frequency, the error vectors into two or more groups and calculates representative vectors for the respective groups. A correction value calculator calculates, on the basis of the representative vectors, phase correction values for the respective frequencies. A phase corrector uses the calculated phase correction values to correct the phase errors for the respective frequencies. | 01-07-2016 |
| 20160013928 | CDR CIRCUIT AND SEMICONDUCTOR DEVICE | 01-14-2016 |
| 20160065358 | SYNCHRONIZATION METHOD, INTERMEDIATE NODE, AND SLAVE NODE OF COMMUNICATION NETWORK SYSTEM - The present invention provides a synchronization method, an intermediate node, and a slave node. An intermediate node obtains, according to a local clock frequency of the intermediate node and an obtained clock frequency of a previous node, a frequency offset of the intermediate node relative to the previous node; the intermediate node obtains, according to the frequency offset of the intermediate node relative to the previous node and an obtained frequency offset of the previous node relative to a master clock, a frequency offset of the intermediate node relative to the master clock; the intermediate node transmits the frequency offset of the intermediate node relative to the master clock to a next node, so that a slave node corrects, according to the frequency offset of the intermediate node relative to the master clock, a clock frequency of the slave node or a clock frequency and time of the slave node. | 03-03-2016 |
| 20160072620 | PHASE INTERPOLATOR - Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction. | 03-10-2016 |
| 20160112182 | Network Packet Timing Synchronization For Virtual Machine Host Systems - Network timing synchronization for virtual machine (VM) host systems and related methods are disclosed that provide synchronization of master/slave clocks within VM host hardware systems. Master timing messages are sent from the master clocks to slave clocks within VM guest platforms hosted by the VM host hardware system within a virtualization layer, and return slave timing messages are communicated from the VM guest platforms to the master clock. Virtual switches within the virtualization layer use virtual transparent clocks to determine intra-switch delay times for the timing packets traversing the virtual switch. These intra-switch delay times are then communicated to target destinations and used to account for variations in packet transit times through the virtual switch. The VM guest platforms synchronize their timing using the timing messages. The master/slave timing messages can be PTP (Precision Time Protocol) timing messages and/or timing messages based upon some other timing protocol. | 04-21-2016 |
| 20160127117 | SYSTEMS AND METHODS FOR SYNCHING A HOST COMPUTER WITH A VARIETY OF EXTERNAL DEVICES - A method of calculating the difference between a device clock and a host clock over a communication network is provided. In a preferred embodiment, the method comprises: a.) sending a sync requests over the communication network; b.) storing in memory a sent host time T | 05-05-2016 |
| 20160127120 | SERIAL DATA TRANSMISSION CIRCUIT AND RECEPTION CIRCUIT, TRANSMISSION SYSTEM USING THE SAME, ELECTRONIC DEVICE, AND SERIAL DATA TRANSMISSION METHOD - Transmission circuit for transmitting serial data with superposed clock signal includes encoder to scramble parallel data of information and apply predetermined coding scheme to generate D symbols having clock signal embedded therein, and to output alternately continuous predetermined number of the D symbols and one of K symbols as synchronization control codes for the scrambling; and parallel-to-serial converter configured to convert the D symbols and the K symbols output from the encoder into serial data, wherein, for each period of the scrambling, the encoder outputs K symbols, each of which is allocated to one of the first code indicating beginning of the period of the scrambling, the second code allocated at equal interval among remaining ones of the K symbols other than that for the first code, and a third code allocated among remaining ones of the K symbols other than those for the first code and the second code. | 05-05-2016 |
| 20160149693 | SYMBOL TRANSITION CLOCKING CLOCK AND DATA RECOVERY TO SUPPRESS EXCESS CLOCK CAUSED BY SYMBOL GLITCH DURING STABLE SYMBOL PERIOD - A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a comparator that provides a comparison signal indicating whether an input signal matches a level-latched instance of the input signal, a first set-reset latch that provides a filtered version of the comparison signal, where the first set-reset latch is set by a first-occurring active transition of the comparison signal and is unaffected by further transitions of the comparison signal that occur during a predefined period of time, delay circuitry that receives the filtered version of the comparison signal and outputs a first pulse on a first clock signal, and a second set-reset latch configured to provide a second pulse on an output clock signal when the first pulse is present on the first clock signal and the comparison signal indicates that the level-latched instance of the input signal does not match the input signal. | 05-26-2016 |
| 20160173107 | CLOCK DATA RECOVERY CIRCUIT AND SEMICONDUCTOR DEVICE | 06-16-2016 |
| 20160173270 | SEMICONDUCTOR APPARATUS AND SYSTEM | 06-16-2016 |
| 20160173274 | SERIALIZER AND DATA TRANSMITTER COMPRISING THE SAME | 06-16-2016 |
| 20160173315 | METHOD AND DEVICE FOR DETECTING UPLINK SYNCHRONIZATION SIGNAL IN EACH STEP IN WIRELESS ACCESS SYSTEM SUPPORTING HIGH FREQUENCY BAND | 06-16-2016 |
| 20160183209 | BASE STATION APPARATUS AND CALIBRATION METHOD | 06-23-2016 |
| 20170237549 | DIRECT DIGITAL FREQUENCY GENERATION USING TIME AND AMPLITUDE | 08-17-2017 |
