| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 375360000 | With transition detector | 35 |
| 20080198957 | APPARATUS, METHOD, AND PROGRAM FOR VERIFYING LOGIC CIRCUIT OPERATING WITH MULTIPLE CLOCK SIGNALS - A verification apparatus that can verify a circuit in a shorter time while taking possible metastability into consideration. A clock domain crossing (CDC) detector finds CDC paths between circuit elements operating with different clocks in the circuit. A delay generator inserter produces a delay-insertable version of the circuit by embedding a delay generator into each found CDC path. When activated, those delay generators give a signal delay to the corresponding CDC paths. A simulator simulates the behavior of the delay-insertable circuit by using a specified simulation pattern while deactivating the embedded delay generators. A delay pattern generator creates a delay pattern from simulation results, which activates or deactivates delay generators individually so as to produce signal delays that could affect output signals of the circuit. A verifier verifies the circuit by applying the delay pattern to each delay generator in the circuit. | 08-21-2008 |
| 20080267330 | FEEDBACK OF REINTERLEAVED CORRECTLY DECODED DATA BLOCK TO DECODER FOR USE IN ADDITIONAL CHANNEL DECODING OPERATIONS OF CHANNEL CODED WORD CONTAINING DATA BLOCK - The feedback of reinterleaved correctly decoded data blocks to a decoder is provided for use in channel decoding operations of channel coded word containing data block. Once a properly decoded data block has been determined, feedback of constraints on the estimated bit sequences decoded data characteristics to a turbo decoder assist in additional decoding operations. Estimated bit sequences may be selected from those trellises that pass through the constraint imposed by knowledge of re-interleaving properly decoded data blocks. This allows the decoder to generate solutions having a minimum probability of error that are also confined by the re-interleaved properly decoded data blocks. | 10-30-2008 |
| 20080310571 | Pulsed Serial Link Transmitting Data and Timing Information on a Single Line - A method of encoding data and timing information on a single line comprising: asserting a first edge on the single line to encode said timing information; asserting a second edge on the single line a selectable time period after said first edge, said selectable time period representing said data, characterised in that: said step of asserting said first edge comprises supplying a clock signal to a clock input of a flip-flop; and the step of asserting the second edge comprises supplying the output of the flip-flop to an input of a programmable delay line having a data input connected to receive said data and an output connected to a reset input of the flip-flop, whereby an output of the flip-flop provides said encoded data and timing information on the single line. | 12-18-2008 |
| 20090074123 | Phase/Frequency Detector and Charge Pump Architecture for Referenceless Clock and Data Recovery (CDR) Applications - A stream of data may flow over a fiber or other medium without any accompanying clock signal. The receiving device may then be required to process this data synchronously. Embodiments describe clock and data recovery (CDR) circuits which may sample a data signal at a plurality of sampling points to partition a clock cycle into four phase regions P | 03-19-2009 |
| 20090086869 | METHOD AND SYSTEM OF RECEIVING TAG SIGNAL FROM RFID READER - Disclosed are a method and system for receiving a tag signal in a Radio Frequency Identification (RFID) reader. The method includes generating an edge signal using a tag signal received from an RFID tag; extracting edge information from the generated edge signal, and generating an edge clock corresponding to the extracted edge information; and determining bit data with respect to the tag signal using the generated edge clock. | 04-02-2009 |
| 20090092212 | CLOCK EMBEDDED DIFFERENTIAL DATA RECEIVING SYSTEM FOR TERNARY LINES DIFFERENTIAL SIGNALING - A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal. | 04-09-2009 |
| 20090116598 | Semiconductor memory device having data clock training circuit - A data clock frequency divider circuit includes a training decoder and a frequency divider. The training decoder outputs a clock alignment training signal, which is indicative of the start of a clock alignment training, in response to a command and an address of a mode register set. The frequency divider, which is reset in response to an output of the training decoder, receives an internal data clock to divide a frequency of the internal data clock in half. The data clock frequency divider circuit secures a sufficient operating margin so that a data clock and a system clock are aligned within a pre-set clock training operation time by resetting the data clock to correspond to a timing in which the clock training operation starts, thereby providing a clock training for a high-speed system. | 05-07-2009 |
| 20090122935 | False frequency lock detector - A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rate—to detect if the clock signal is incorrectly locked to the first rate. | 05-14-2009 |
| 20090122936 | METHOD AND CIRCUIT FOR DYNAMICALLY CHANGING THE FREQUENCY OF CLOCK SIGNALS - A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges. | 05-14-2009 |
| 20090135975 | APPARATUS AND METHOD FOR RECOVERING DATA - An apparatus for recovering data and a method thereof are provided. The apparatus includes a reference clock generator which generates a reference clock, and a data recovering unit which detects an edge of received data and recovers the data using a time difference between a reference point of the reference clock and the detected edge. | 05-28-2009 |
| 20090154626 | CONTINUOUS RECEIVER CLOCK ALIGNMENT AND EQUALIZATION OPTIMIZATION - The available bandwidth of an Input/Output (I/O) communications link is increased by removing the need for retraining events on a communications link. This results in removing a potentially severe system performance degradation penalty that may occur from data traffic stoppage during the retraining events. The available bandwidth is further increased by removing a timing error which results in increasing a timing margin for other components. This results in an increase in the maximum speed of systems with high speed I/O and communication transceiver Integrated Circuits (IC)s. | 06-18-2009 |
| 20090196388 | SIGNAL TRANSMISSION SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Disclosed is a semiconductor integrated circuit device including a transmitting circuit and a receiving coil inductively coupled to a transmitting coil. The transmitting circuit transmits data by supplying a current through the transmitting coil not at the time of transition of data but at every rising edge or falling edge of a clock used in transmission of data. At every rising edge or falling edge of the clock, a receiving circuit captures a voltage induced in the receiving coil due to the current flowing through the transmitting coil, reproduces the transmitted data and outputs the reproduced data. | 08-06-2009 |
| 20090290670 | METHOD OF ACQUIRING INITIAL SYNCHRONIZATION IN IMPULSE WIRELESS COMMUNICATION AND RECEIVER - A receiver in an impulse wireless communication. The receiver ( | 11-26-2009 |
| 20090310727 | METHOD AND DEVICE FOR THE GENERATION OF OUT-OF-PHASE BINARY SIGNALS, AND USE OF THE SAME - A method for the generation of binary signals (So | 12-17-2009 |
| 20100002821 | CLOCK DETERMINATION FOR A SENSOR - A method for determining a clock for a sensor signal which has a synchronization signal, which method involves a control unit measuring the period between a first edge and a second edge of the synchronization signal, wherein both edges are either rising or falling, and the control unit taking the period as a basis for determining a clock for sampling data in the sensor signal. | 01-07-2010 |
| 20100104057 | Clock and Data Recovery with a Data Aligner - In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock. | 04-29-2010 |
| 20100128831 | CIRCUIT FOR DETECTING CLOCK AND APPARATUS FOR PROVIDING CLOCK - A circuit for detecting a clock has a plurality of first transmission elements, a plurality of first exclusive OR gates and a first AND gate. Each first transmission element is coupled to a last first transmission element for receiving output data, and the data received by each first transmission element is transmitted to an input terminal of a next first transmission element. In addition, the input of a first transmission element is coupled to a clock source for receiving a predetermined clock signal of which a frequency is less than a frequency of a local clock signal. Furthermore, the first and second input terminals of a k | 05-27-2010 |
| 20100316175 | Packet detection, synchronization, and frequency offset estimation - Techniques are disclosed for detecting a packet. One technique includes sampling a received signal to produce a sequence of samples wherein the sequence of samples includes a plurality of subsequences of samples; cross correlating the subsequences of samples with a known form of the subsequence to produce cross correlations; self correlating the cross correlations to produce a plurality of self correlations; summing the self correlations; and processing the sum of the self correlations. | 12-16-2010 |
| 20110096884 | System and method for implementing a phase detector to support a data transmission procedure - A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a voltage-controlled oscillator. The phase detector includes a positive-edge detector circuit that generates an edge detection signal P to indicate whether data transitions are present in the input data. The phase detector also includes a lead/lag indicator circuit that generates a lead/lag indicator signal T to indicate whether the clock signal is early or late with respect to the input data. | 04-28-2011 |
| 20110164711 | DECODER AND METHOD FOR ADAPTIVELY GENERATING A CLOCK WINDOW - A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window. | 07-07-2011 |
| 20120014489 | METHOD AND SYSTEM FOR MAINTAINING WIRELESS LINKS IN A COMMUNICATION NETWORK - A method of operating a communication system comprises sending a frame by an access node to a wireless device where the frame comprises a packet. A counter is initialized and a timer for each frame is initiated. The method continues with the access node determining if a response associated with the packet is received before the expiration of the timer. If the response is received prior to the expiration of the timer, the counter and the timer are reset. If a response is not received prior to the expiration of the timer, the counter is incremented. Upon the counter meeting a criteria of a certain quantity of lost packets, the access node performs a synchronization process. | 01-19-2012 |
| 20120076251 | DIGITAL NRZI SIGNAL FOR SERIAL INTERCONNECT COMMUNICATIONS BETWEEN THE LINK LAYER AND PHYSICAL LAYER - Systems and methods of operating a serial interconnect interface provide for generating a pulse in response to a state change in a data signal of the serial interface interconnect, and transmitting the pulse from a physical layer of the serial interconnect interface to a link layer of the serial interconnect interface. The duration of the pulse can be selected based on whether the state change corresponds to an end of packet (EOP) condition. In addition, the data signal may include a non return to zero invert (NRZI) encoded signal, wherein the pulse is part of a digital NRZI signal. | 03-29-2012 |
| 20120082280 | SAMPLER CIRCUIT - A sampler circuit comprises a plurality of series-connected sampler cells and a detector circuit. Each successive stage comprises twice the number of sampler cells, in parallel, as the previous stage, and is clocked at half the sampling frequency of the previous stage. Each sampler cell comprises two parallel branches of series-connected clocked inverters. A clocked inverter is operative to invert an applied signal during one phase of an applied sampling clock, and to render a high impedance output during the other sampling clock phase. Successive clocked inverters are clocked with opposite (i.e., positive/negative) versions of the sampling clock. The detector circuit examines the outputs of the last stage of sampler cells, and may for example comprise an OR function to detect a state transition in an applied input signal. The sampler circuit exhibits immunity to metastability and low power consumption. | 04-05-2012 |
| 20120121051 | RECEIVE TIMING MANAGER - A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement. | 05-17-2012 |
| 20130003905 | TRANSITION DETECTOR - An embodiment of a detector includes first and second generators. The first generator is operable to receive a transition of a first signal and to generate in response to the transition a first pulse having a length that is approximately equal to a length of a detection window. And the second generator is operable to receive a second signal and to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window. | 01-03-2013 |
| 20130044844 | ELECTRONICS DEVICE CAPABLE OF EFFICIENT COMMUNICATION BETWEEN COMPONENTS WITH ASYNCRONOUS CLOCKS - An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component. | 02-21-2013 |
| 20130044845 | LOW POWER EDGE AND DATA SAMPLING - An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit. | 02-21-2013 |
| 20140254732 | TRANSCODING METHOD FOR MULTI-WIRE SIGNALING THAT EMBEDS CLOCK INFORMATION IN TRANSITION OF SIGNAL STATE - A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires. | 09-11-2014 |
| 20140294131 | CLOCK DETERMINATION FOR A SENSOR - A method for determining a clock for a sensor signal which has a synchronization signal, which method involves a control unit measuring the period between a first edge and a second edge of the synchronization signal, wherein both edges are either rising or falling, and the control unit taking the period as a basis for determining a clock for sampling data in the sensor signal. | 10-02-2014 |
| 20150030112 | THREE PHASE CLOCK RECOVERY DELAY CALIBRATION - System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. A clock recovery circuit may be calibrated based on state transitions in a preamble transmitted on two or more connectors. A calibration method is described. The method includes detecting a plurality of transitions in a preamble of a multiphase signal and calibrating a delay element to provide a delay that matches a clocking period of the multiphase signal. Each transition may be detected by only one of a plurality of detectors. The delay element may be calibrated based on time intervals between detections of successive ones of the plurality of transitions. | 01-29-2015 |
| 20150071393 | LOW POWER DIGITAL FRACTIONAL DIVIDER WITH GLITCHLESS OUTPUT - A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is used to eliminate glitches during the clock shift. | 03-12-2015 |
| 20150117580 | SIMULTANEOUS TRANSMISSION OF CLOCK AND BIDIRECTIONAL DATA OVER A COMMUNICATION CHANNEL - Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a modulator to generate a modulated signal including a clock signal and a data signal, the clock signal being modulated by a first signal edge of the modulated signal and the data signal being modulated by a position of a second signal edge of the modulated signal; a driver to drive the modulated signal on a communication channel; an echo canceller to subtract reflected signals on the communication channel; and a data recovery module to recover a signal received on the communication channel, the received signal being encoded by Return-to-Zero (RZ) encoding, the signal being received simultaneously with driving the modulated signal on the communication channel. | 04-30-2015 |
| 20150146831 | SENSOR, CONTROL UNIT AND METHOD TO COMMUNICATE BETWEEN SENSORS AND CONTROL UNITS - A sensor may include a clock generator configured to generate a clock. A receiver may be configured to receive signals from a control unit, and a transmitter they be configured to send signals to the control unit. In one implementation, the transmitter is configured to send a synchronization signal based on the clock. A period between a first edge and a second edge of the synchronization signal may be dependent on the clock and both edges are either rising or falling. | 05-28-2015 |
| 20150358149 | WIRELESS DEVICE AND METHOD FOR CONTROLLING WIRELESS DEVICE - A wireless device including an oscillator circuit, a detector circuit, and a controller circuit. The oscillator circuit generate a clock signal. The detector circuit detect respective phase differences of received wireless signals of a plurality of frequency bands from respective reference phases. The controller circuit control, for each of the plurality of frequency bands, at least one of a receiving process and a transmitting process on the wireless signal on the basis of the clock signal such that the phase difference is compensated. | 12-10-2015 |
| 20160080140 | A NETWORK RECEIVER FOR A NETWORK USING DISTRIBUTED CLOCK SYNCHRONIZATION AND A METHOD OF ADJUSTING A FREQUENCY OF AN INTERNAL CLOCK OF THE NETWORK RECEIVER - A network receiver for a network using distributed clock synchronization and a method of adjusting a frequency of an internal clock of the network receiver are provided. The network receiver receives from the network an input signal and has an internal clock for generating a clock signal. The network receiver further includes a clock bit comparator and an adjustment signal generator. The clock bit comparator compares lengths of a first time period lapsed while receiving at least five consecutive bits of the signal and of an internal clock time interval representing the same number of bits as a number of bits of the first time period. The adjustment signal generator generates a frequency adjustment signal for controlling a frequency of the internal clock in dependence of a result of the comparison of the lengths to reduce a difference between the lengths. | 03-17-2016 |
