Class / Patent application number | Description | Number of patent applications / Date published |
375357000 | Synchronization failure prevention | 20 |
20080310569 | Input/output circuit - Disclosed is a SERDES circuit including a clock and data recovery circuit that allows operational margin in temporal and voltage directions to be measured, using a phase offset signal and a threshold voltage control signal, a pre-emphasis driver circuit and an equalizer circuit in order to reduce ISI on a transmission line, and an optimization control circuit for controlling the overall circuit. The optimization control circuit controls an equalizer control signal that is for adjusting characteristics of the equalizer circuit and a driver control signal that is for adjusting characteristics of the pre-emphasis driver circuit and sets the equalizer control signal and driver control signal so that the operational margin of the clock and data recovery circuit is maximized. | 12-18-2008 |
20080310570 | DEVICE AND METHOD FOR PREVENTING LOST SYNCHRONIZATION - A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses. | 12-18-2008 |
20090168936 | Methods and Apparatus for Detecting a Loss of Lock Condition in a Clock and Data Recovery System - Methods and apparatus are provided for detecting a loss of lock condition in a clock and data recovery system. A loss of lock condition is detected in a clock and data recovery system that generates a recovered clock signal from a received signal by sampling the received signal for a plurality of different phases using one or more latches clocked by the recovered clock; evaluating the samples to monitor a data eye associated with the received signal; and detecting the loss of lock condition if the data eye does not satisfy one or more predefined conditions. Generally, the predefined conditions identify a loss of the data eye (e.g, when the data eye cannot be substantially detected), for example, based on a degree of opening of the data eye. The clock and data recovery system can optionally be restarted if the loss of lock condition is detected. | 07-02-2009 |
20090168937 | RF RECEIVER HAVING TIMING OFFSET RECOVERY FUNCTION AND TIMING OFFSET RECOVERY METHOD USING THEREOF - There is provided an RF receiver recovering timing offset by shifting timing slots in response to timing offset occurring when a signal is sampled. An RF receiver having timing offset recovery function according to an aspect of the invention includes: a preprocessing unit sampling and digitalizing an analog received signal; a differential operation unit delaying the digitalized received signal from the preprocessing unit for predetermined periods of time and differentiating the delayed signals; a correlation unit correlating the differentiated received signals from the differential operation unit with a plurality of predetermined PN code sequences and sequentially outputting correlation values; a setting unit sequentially storing the correlation values from the correlation unit, detecting a maximum value among the stored correlation values, and shifting a plurality of determination slots by a difference between a storage location of the detected maximum value and a reference storage location; and a demodulation value estimation unit estimating as a demodulation value of the received signal, a symbol of a PN code sequence corresponding to the maximum value from the shifted determination slots. | 07-02-2009 |
20090175393 | METHOD AND DEVICE FOR FRAME SYNCHRONIZATION - A method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; characterized by defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle. | 07-09-2009 |
20090213971 | COHERENT SINGLE ANTENNA INTERFERENCE CANCELLATION FOR GSM/GPRS/EDGE - A method for midamble estimation comprises the steps of receiving a burst of symbols, selecting a subset of the burst of symbols that comprises a first midamble symbol, calculating, for each symbol in the subset, a corresponding midamble estimation error, and determining the lowest calculated midamble estimation error to locate the first midamble symbol. A receiver comprises an antenna configured to receive a burst of symbols, a timing estimator configured to select a subset of the burst of symbols that comprises a first midamble symbol, a midamble estimator configured to calculate, for each symbol in the subset, a corresponding midamble estimation error, and a processor configured to select the symbol in the subset corresponding to a lowest calculated midamble estimation error as the first midamble symbol. | 08-27-2009 |
20090257538 | Methods and Apparatus for Fast Downlink Information of Uplink Out-of-Synchronization - Information systems, detectors, and methods for a communication link, such as the downlink of a cellular telephone system, reduce the problem of uplink transmit power peaks when the uplink is out of synchronization (OoS). One method of indicating that a first link to a communication node is OoS includes the step of including an OoS signal in signals that are sent by the node on a second link. The OoS signal includes at least one data bit transmitted by the node that indicates that the first link is synchronized or OoS. A method of determining that a first link to a communication node is OoS includes the step of detecting an OoS signal in signals that are sent by the node on a second link. The OoS signal includes at least one data bit that indicates that the first link is synchronized or OoS. | 10-15-2009 |
20090296864 | Synchronization Detection Using Bandwidth and Antenna Configuration - User Equipment in a wireless communication network considers the downlink channel bandwidth in setting out of synchronization (OoS) and in synchronization (IS) thresholds and filter durations. Additionally, the UE may consider transmitter antenna configuration—that is, the number of transmitting antennas in a MIMO system—in setting the OoS and IS thresholds. The UE determines it is OoS when a monitored, filtered, downlink channel quality metric, such as reference symbol SINR, is below the OoS threshold. | 12-03-2009 |
20100034330 | CLOCK GENERATING DEVICE AND METHOD THEREOF - A clock generating device includes: a frequency divider having an input node coupled to a transmission interface for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit having a data input node coupled to the transmission interface and a reference clock input node coupled to an output node of the frequency divider, for generating an output clock signal according to one of the input data received at the data input node and the reference clock signal received at the reference clock input node. | 02-11-2010 |
20100260296 | Embedded Clock Recovery - Systems and methods for synchronizing a source and sink device are disclosed. A sink device can efficiently determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method for transmitting a source data stream from a source device to a sink device includes, forming a logical channel from a source device to a sink device, where the logical channel is configured to carry the source data stream, and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel. A method for a sink device to recover a source data rate includes, detecting a logical channel in a received data stream where the logical channel includes the source data stream, recovering one or more rate parameters from the received data stream, determining a data rate of the logical channel, and determining the data rate of the source data stream based on the data rate of the logical channel and the one or more rate parameters. Corresponding systems and computer program products are also described. | 10-14-2010 |
20110228885 | TIME SYNCHRONIZATION SYSTEM VIA TWO-WAY INTERACTIVE WIRELESS COMMUNICATION - The time synchronization system according to the present invention can allow the master and slave time Tx/Rx devices to communicate information therebetween via two-way interactive wireless communication, so that it can rapidly detect an error that occurs in the system, via a monitoring device and a network management device for performing real-time integral management. Therefore, the system can reduce the user's system maintenance fee and can also maximize efficiency. In addition, the time synchronization system can allow for the easy extension of the equipment construction coverage area even in a long distance environment, by installing only repeaters, and can manage log information that may be used as evidence data for various incidents. | 09-22-2011 |
20120207258 | Fault-Tolerant Self-Stabilizing Distributed Clock Synchronization Protocol for Arbitrary Digraphs - A self-stabilizing network in the form of an arbitrary, non-partitioned digraph includes K nodes having a synchronizer executing a protocol. K−1 monitors of each node may receive a Sync message transmitted from a directly connected node. When the Sync message is received, the logical clock value for the receiving node is set to between | 08-16-2012 |
20120219099 | SYSTEM, METHOD, AND DEVICE TO DISTRIBUTE ACCURATE SYNCHRONIZATION TIMESTAMPS IN AN EXPANDABLE AND TIMING CRITICAL SYSTEM - Techniques are described to provide a device and network of devices that collect distributed coordinated timestamps from distributed time counters in a multi-module or multi-integrated circuit system. The interconnect between the modules can be a single-wire or a two-wire interconnect. The modules communicatively coupled to the interconnect can use a collision-avoidance protocol for triggering the broadcasting of timestamps among the modules as well for allowing all modules to transmit their timestamps. Timestamps from multiple clocks can be transmitted by all modules and then collected and compared to produce correction factors to clock signals of each module to potentially achieve distributed clock synchronization in multiple independent modules or integrated circuits. | 08-30-2012 |
20120328062 | METHOD AND APPARATUS FOR CORRECTING SYNCHRONIZATION ERRORS BETWEEN AUDIO SIGNALS AND VIDEO SIGNALS - The present invention relates to an apparatus and method for correcting synchronization errors, which involve correcting synchronization errors occurring between video signals and audio signals when multiple videos are combined. The apparatus and method of the present invention involve: storing synchronization errors between an initial video signal and an initial audio signal of each video to be combined when combining different pieces of video content; and combining multiple pieces of video content such that the initial synchronization error which is set to synchronize existing video signals with existing audio signals can be maintained when combining multiple pieces of video content. The apparatus and method of the present invention enable the drawbacks of conventional techniques, i.e. that video signals and audio signals are uniformly combined, errors are corrected, and thus the video signals and the audio signals are unsynchronized which results in unnatural video, to be overcome. | 12-27-2012 |
20130243139 | DEVICE AND METHOD FOR PREVENTING LOST SYNCHRONIZATION - A method for synchronizing two connection nodes by a reception node of the connection nodes with a clock data recovery circuit that generates a synchronization clock from input data. The method includes performing a synchronization process to establish synchronization between the connection nodes based on the synchronization clock, performing a connection failure process when the synchronization is not established when a first time elapses after receiving the input data, correcting the clock data recovery circuit when the synchronization is not established when a second time elapses after receiving the input data, wherein the second time is shorter than the first time, and performing a resynchronization process to establish synchronization between the connection nodes based on a synchronization clock, which is generated by the clock data recovery circuit that has been corrected, before the first time elapses and after the second time elapses. | 09-19-2013 |
20130287154 | DEVICE AND METHOD FOR PREVENTING LOST SYNCHRONIZATION - A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses. | 10-31-2013 |
20130315358 | METHODS FOR DETECTION OF FAILURE AND RECOVERY IN A RADIO LINK - A method, telecommunication apparatus, and electronic device for detecting a status of a radio link are disclosed. A transceiver | 11-28-2013 |
20150341158 | LOOP GAIN CALIBRATION APPARATUS FOR CONTROLLING LOOP GAIN OF TIMING RECOVERY LOOP AND RELATED LOOP GAIN CALIBRATION METHOD - A loop gain calibration apparatus has an exciting signal generator, an exciting signal extracting circuit, and a loop gain control circuit. The exciting signal generator generates a first exciting signal and injects the first exciting signal into a timing recovery loop while the timing recovery loop is operating in response to a reception signal received under a normal reception mode. The exciting signal extracting circuit extracts a second exciting signal from the timing recovery loop after the first exciting signal is injected into the timing recovery loop. The loop gain control circuit receives the first exciting signal from the exciting signal generator, receives the second exciting signal from the exciting signal extracting circuit, and controls a loop gain of the timing recovery loop according to the first exciting signal and the second exciting signal. | 11-26-2015 |
20150381337 | SEGMENTED DIGITAL-TO-TIME CONVERTER CALIBRATION - This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a calibration system can include a calibration path configured to represent a segment of the DTC, a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment, and a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the DTC using the timing error information. | 12-31-2015 |
20160127118 | METHOD AND APPARATUS FOR PROVIDING IN-VEHICLE NETWORK TIME SYNCHRONIZATION USING REDUNDANT GRANDMASTER - A method for providing network time synchronization using a redundant grandmaster includes sensing a loss of the grandmaster. A sync message is generated according to a sensed result. The generated sync message is transmitted through a clock master port. | 05-05-2016 |