Class / Patent application number | Description | Number of patent applications / Date published |
375327000 | Phase locked loop | 23 |
20080240298 | Method and/or apparatus for stabilizing the frequency of digitally synthesized waveforms - An apparatus comprising a first circuit, a second circuit, a third circuit and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to (i) a modulated signal and (ii) a seed value. The second circuit may be configured to generate a first control signal in response to the demodulated signal. The third circuit may be configured to generate a second control signal in response to (i) the first control signal and (ii) a compensation signal. The fourth circuit may be configured to generate the seed value in response to the second control signal. | 10-02-2008 |
20090016466 | Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection - A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a controller, which multiplies the phase error by a gain factor selected to stabilize and optimize the phase locked loop and produces an output signal for use in extracting a frequency deviation present in the complex digital input signal. The output signal is also input to a numerically controlled oscillator that tracks the phase of the complex digital input signal based on the output signal and produces the complex digital feedback signal. | 01-15-2009 |
20090122919 | RECEIVER CIRCUIT, APPLICATION OF A FIRST AND A SECOND PROPORTIONAL ELEMENT OF A DIGITAL PLL STRUCTURE, AND METHOD FOR RECEIVING A FREQUENCY-SHIFT KEYED SIGNAL - A receiver circuit, application of a first proportional element and a second proportional element of a digital PLL structure, and method for receiving a frequency-shift keyed signal are provided. A phase signal is calculated from an in-phase signal and a quadrature signal. A feedback signal is subtracted from the phase signal to form a difference signal. An output signal is determined from the difference signal by a nonlinear transfer function. The output signal is evaluated with an evaluation circuit. A first signal and a second signal are added to form a summation signal. The first signal is produced by multiplication of the output signal or the difference signal by a first proportionality factor. The second signal is produced by multiplication of the output signal or the first signal or the difference signal by a second proportionality factor, followed by integration, and the feedback signal is produced by integration of the summation signal. | 05-14-2009 |
20090135956 | METHOD AND APPARATUS FOR PRECISE OPEN LOOP TUNING OF REFERENCE FREQUENCY WITHIN A WIRELESS DEVICE - A communications subsystem for a wireless device for correcting errors in a reference frequency signal. The communications subsystem comprises a frequency generator for generating the reference frequency signal and a closed loop reference frequency correction module that generates a reference frequency adjustment signal for correcting the reference frequency signal when the communications subsystem operates in closed loop mode. The subsystem further includes an open loop frequency correction means that that samples values of the reference frequency adjustment signal during the closed loop mode and generates a frequency correction signal for correcting the reference frequency signal when the communications subsystem operates in a mode other than closed loop mode. | 05-28-2009 |
20090207943 | Semiconductor Circuit Device - A semiconductor circuit device is provided which can attain more stable operations against noise in a data communication system without increasing the power consumption of an overall system, thereby improving the reliability of data communication. For a demodulation baseband signal (S | 08-20-2009 |
20090245426 | STORING LOG LIKELIHOOD RATIOS IN INTERLEAVED FORM TO REDUCE HARDWARD MEMORY - An apparatus and method for storing log likelihood ratios in an interleaved form comprising receiving a plurality of interleaved codewords; obtaining at least one log likelihood ratio (LLR) for the plurality of interleaved codewords; storing the at least one LLR in a memory; deinterleaving the plurality of interleaved codewords after the at least one LLR has been stored in the memory; and performing a bit decision of the deinterleaved codewords using the stored at least one LLR. | 10-01-2009 |
20090279642 | Calibrated Quadrature Generation for Multi-GHZ Receiver - An integrated receiver circuit includes aphase locked loop circuit ( | 11-12-2009 |
20090296857 | Frequency lock detection - A system and method are provided for detecting the frequency acquisition of a synthesized signal in a non-synchronous communications receiver. The method accepts a non-synchronous communication signal having an input data signaling frequency, and compares the input data signaling frequency to a synthesized signal frequency. In response to the comparing, a difference signal pulse is generated. More explicitly, the difference signal is generated at a rate responsive to the difference between the input data signaling frequency and the synthesized signal frequency. The method counts synthesized signal pulses occurring simultaneously with the difference signal pulse. If the counted synthesized signal pulses exceed a threshold (before the disappearance of the difference signal pulse), it is determined that the input data signaling frequency is about equal to the synthesized signal frequency, and a lock signal is generated. | 12-03-2009 |
20100142652 | DEMODULATOR WITH SIGNAL PRECONDITIONER - A method and apparatus for demodulating an input signal, for example, in a communications system, is disclosed. The apparatus includes a signal preconditioner and a demodulator. The signal preconditioner may include a low-pass filter and a hysteretic comparator that are configured to precondition a preconditioner input signal to provide a preconditioner output signal. The modulator may be configured to demodulate the preconditioner output signal. | 06-10-2010 |
20100232548 | DEMODULATION AND DECODING FOR FREQUENCY MODULATION (FM) RECEIVERS WITH RADIO DATA SYSTEM (RDS) OR RADIO BROADCAST DATA SYSTEM (RBDS) - Demodulation and decoding for frequency modulation (FM) receivers with radio data system (RDS) or radio broadcast data system (RBDS). An example of a method for processing a signal in a receiver includes quantizing a demodulated signal to generate bits in response to receipt of the demodulated signal. The method also includes grouping the bits into one or more blocks. The method further includes computing a syndrome for a block from the one or more blocks. Moreover, the method includes identifying error, corresponding to the syndrome, in the block based on type of demodulation. The type of demodulation includes a coherent demodulation and a differential demodulation. Furthermore, the method includes correcting the error in the block. | 09-16-2010 |
20100278285 | WIRELESS SIGNAL RECEIVING METHOD AND RECEIVER UTILIZING THE SAME - A receiver receiving a Radio Frequency (RF) signal and generating a baseband signal is provided. An RF module receives the RF signal and down convert the RF signal according to a first oscillation frequency to generate an Intermediate Frequency (IF) signal. An IF module is coupled to the RF module and arranged to receive the IF signal and down convert the IF signal according to a second oscillation frequency to generate the baseband signal. A calibration module is coupled to the RF module and arranged to calculate the IF signal according to a third oscillation frequency to detect an I/Q mismatch, and generate an adjustment signal, accordingly, to calibrate the I/O mismatch. | 11-04-2010 |
20110116578 | Mobile Communication System with Integrated GPS Receiver - A receiver includes a mixer, a poly phase filter, a channel select filter, an analog-to-digital converter and a HI/LO side reject selection unit. The mixer downconverts a signal to generate an in-phase signal and a quadrature signal. The poly phase filter for generates differential IF signals based on the in-phase signal and the quadrature signal. The channel select filter filters out unwanted channel signals from the differential IF signals. The analog-to-digital converter converts the filtered signal into a digital output signal. The HI/LO side reject selection unit is coupled between the mixer and the poly phase filter and capable of rejecting image signals while the mixer is at a high side frequency or at a low side frequency. | 05-19-2011 |
20110280344 | DYNAMIC BANDWIDTH CONTROL SCHEME OF A FRAC-N PLL IN A RECEIVER - A receiver, in accordance with one embodiment of the present invention, includes a mixer, a filter, a received signal strength indicator, and a control loop. The mixer is adapted to convert the frequency of a received signal. The filter is adapted to filter out undesired noise that may be present in the output signal of the mixer. The received signal strength indicator is adapted to detect blocker (also known as jammer) signals that may be present in the output signal of the low-pass filter and generate a feedback signal in response. The control loop is adapted to vary its bandwidth in response to an output signal of the received signal strength indicator. The control loop supplies an oscillating signal to the mixer. | 11-17-2011 |
20120121043 | EHF Wireless Communication Receiver Using Beamforming with a Scalable Number of Antenna Paths - The invention relates to a EHF wireless communication receiver comprising a phased array radio arranged for receiving a beam of signals in a predetermined frequency band. The phased array radio comprises a plurality of antenna paths, each arranged for handling one of the incoming signals and forming a differential I/Q output signal, each antenna path comprises a downconversion part and a phase shifting part for applying a controllable phase shift; a signal combination circuitry is connected to the antenna paths and is arranged for combining the differential I/Q output signals; and a control circuitry is connected to the phase shifting parts of the antenna paths and is arranged for controlling the controllable phase shift. In each antenna path, the phase shifting part is a baseband part downstream from the downconversion part and the phase shifting part comprises a set of variable gain amplifiers arranged for applying controllable gains to the respective downconverted incoming signals in the I/Q branches. The control circuitry sets the controllable gains of the variable gain amplifiers to coefficients of a rotational matrix. | 05-17-2012 |
20130195223 | Receiver Architecture and Methods for Demodulating Binary Phase Shift Keying Signals - A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference. | 08-01-2013 |
20140016727 | LOW PHASE-NOISE INDIRECT FREQUENCY SYNTHESIZER - A low phase noise frequency synthesizer, comprising, arranged in series, a first mixer receiving a reference signal at a reference frequency F | 01-16-2014 |
20140023163 | RECEIVER ARCHITECTURE AND METHODS FOR DEMODULATING BINARY PHASE SHIFT KEYING SIGNALS - A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference. | 01-23-2014 |
20140161211 | RECEIVER, SIGNAL DEMODULATION MODULE AND DEMODULATION METHOD THEREOF - A signal demodulation module is disclosed. The signal demodulation module includes an injection-locked oscillator, an envelope detector and a data slicer. The injection-locked oscillator has a central oscillating frequency equal to a frequency of a digital modulation signal received, and outputs a phase-locked oscillating signal which is in phase to the digital modulation signal. When input phase of the digital modulation signal changes, output phase of the injection-locked oscillator changes synchronously. The envelope detector is used for detecting an envelope line of the phase-locked oscillating signal and outputting an envelope signal accordingly. The data slicer is used for receiving the envelop signal and outputting a first digital signal according to a reference voltage and the envelop signal. | 06-12-2014 |
20140241467 | PHASE LOCKED LOOP FREQUENCY SYNTHESIZER WITH REDUCED JITTER - A phase locked loop frequency synthesizer has a controlled oscillator for generating an output signal at a desired frequency, a phase/frequency detector module for comparing a feedback signal derived from the controlled oscillator with a reference signal to generate an error signal, a loop filter for processing said at least one error signal from said phase/frequency detector module to generate a combined control signal for the controlled oscillator. The gain of the phase/frequency detector module can be adjusted, preferably by varying the pulse width and pulse cycle, to maintain the overall gain of the phase locked loop within a given range and thereby maximize signal to noise ratio. | 08-28-2014 |
20140270004 | METHOD AND APPARATUS FOR COMPENSATING FOR FREQUENCY ERRORS BETWEEN BASE STATION AND MOBILE STATION - Methods and apparatuses for compensating for frequency mismatch between a base station and mobile station are disclosed. At a first oscillator, a fixed reference oscillation signal is generated. At a second oscillator, a baseband oscillation signal is generated. A frequency divided version of the baseband oscillation signal is locked to a frequency divided version of the first reference oscillation signal. At a third oscillator, a first RF oscillation signal is generated. A frequency divided version of the first RF oscillation signal is locked to the frequency divided version of the second reference oscillation signal. A frequency adjustment signal is inputted to the second and third oscillators. At the second and third oscillators, frequency errors of the baseband oscillation signal and first RF oscillation signal, respectively, are compensated based on the frequency adjustment signal. | 09-18-2014 |
20150010113 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATING METHOD THEREOF - A semiconductor integrated circuit includes a first wireless access system reception unit including a first analog reception unit and a first digital reception unit, a voltage-controlled oscillator, a phase locked loop, and a digital interface. The first analog reception unit comprises a first reception mixer for down-converting an RF reception signal into a first analog reception signal and a first analog-digital converter for converting the first analog reception signal into a first digital reception signal. The first wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop enable switching from a reception operation for a first RF reception signal of a first system to a reception operation for a second RF reception signal of a second system. | 01-08-2015 |
20160006421 | FREQUENCY SYNTHESISER CIRCUIT - The invention relates to frequency synthesiser circuits, and in particular to frequency synthesiser circuits characterised by a small channel spacing. Embodiments disclosed include a frequency synthesiser circuit ( | 01-07-2016 |
20160191138 | MULTIPLE ANTENNA DISTRIBUTED RADIO SYSTEM - A radio receiver including: a serial data interface configured to receive a serial data signal from another radio receiver; a clock/data recovery circuit configured to produce a clock signal and a data signal from the serial data signal; and a radio front-end configured to receive the clock signal from the clock/data recovery circuit to produce a received signal; and signal combining circuit configured to combine the received signal and the data signal. | 06-30-2016 |