Class / Patent application number | Description | Number of patent applications / Date published |
375319000 | Automatic bias circuit for DC restoration | 88 |
20080212716 | BURST MODE RECEIVER FOR PASSIVE OPTICAL NETWORK - A receiver assembly for use in an optical telecommunications network is provided that automatically generates a reference level for the incoming signal burst based on its preamble without the need to pre-process the entire signal burst. The entire signal burst is fed directly from the TIA into the input of the limiting amplifier. A differential amplifier, tapped from the data and data bar outputs of the limiting amplifier, samples the signal stream to capture the preamble portion of each signal burst. The preamble portion of the signal burst is then passed, post amplification, into a sample and hold circuit. The sample and hold circuit samples the amplitude of this preamble portion of the signal and then holds the sampled level for use as a reference level for the processing of following payload signal. | 09-04-2008 |
20080232512 | METHOD AND SYSTEM FOR BLOCKER AND/OR LEAKAGE SIGNAL REJECTION BY DC BIAS CANCELLATION - Methods and systems for blocker and/or leakage signal rejection by DC bias cancellation are disclosed and may include undersampling a received signal including a desired signal and an undesired signal. A biasing current in the wireless system may be utilized to reduce a measured DC signal generated by the undersampling of the received signal. The received signal may be undersampled at a frequency of or an integer sub-harmonic of the undesired signal, which may include a leakage signal and/or a blocker signal. The DC biasing current may be controlled utilizing successive approximation, control logic and a digital to analog converter. The output DC voltage may correspond to said undesired signal, and the received signal may be undersampled utilizing a mixer. | 09-25-2008 |
20080240294 | Method and system for determining and removing DC offset in communication signals - According to one exemplary embodiment, a method and system for determining and removing DC offset in an AC signal includes receiving an AC signal having a first-channel and a second-channel, e.g. an I-channel and a Q-channel, receiving a plurality of first-channel and second-channel samples, storing a negative first-channel sample corresponding to a first sign change in the plurality of second-channel samples, and storing a positive first-channel sample corresponding to a second sign change in the plurality of second-channel samples. The method further includes determining an average value of the negative first-channel sample and the positive first-channel sample, where the average value is the DC offset in the first-channel. The method can further include subtracting the determined DC offset from samples received in the first-channel (or the second-channel) prior to demodulation. The method and system can be implemented in, for example, a Bluetooth receiver. | 10-02-2008 |
20080292023 | DIRECT SAMPLING TYPE WIRELESS RECEIVER AND METHOD USING THE SAME - There are provided a direct sampling type wireless receiver and a method using the same that reduce nonlinearity and DC offset by using a multi-port network and a carrier frequency direct conversion method with a low sampling rate of a direct sampling method in a wireless communication receiver. A direct sampling type wireless receiver according to an aspect of the invention includes: a reference signal generation unit supplying a first reference signal having a predetermined frequency and a second reference signal having a higher frequency than the first reference signal; a down sampling unit sampling an input RF signal according to the first reference signal; an analog-to-digital converting unit converting the signal sampled by the down sampling unit into a digital signal according to the second reference signal; and a multiple-input multiple-output port unit dividing the digital signal from the analog-to-digital converting unit into a plurality of digital signals, generating a plurality of carrier signals having different phases from each other by shifting phases of the digital signals, and outputting a plurality of phase signals having different phases from each other by adding the plurality of carrier signals and the plurality of digital signals to each other. | 11-27-2008 |
20080298506 | DYNAMIC DC OFFSET CANCELING APPARATUS AND DYNAMIC DC OFFSET CANCELING METHOD - The dynamic DC offset canceling apparatus includes: section | 12-04-2008 |
20080317170 | Embedding a Secondary Information Signal in a Channel Data Stream - The present invention relates to a method and a corresponding device for embedding a secondary information signal in a channel data stream of encoded primary information signal. In order to make it more difficult for unauthorized persons or devices to retrieve the location of storage of the secondary information signal or its content itself a device is proposed according to the present invention comprising:
| 12-25-2008 |
20090003491 | SYSTEM AND METHOD FOR DC OFFSET COMPENSATION AND BIT SYNCHRONIZATION - A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D converter connected to the radio module, a DC tracking loop connected to the A/D converter, and a multi-hypothesis bit synchronizer. | 01-01-2009 |
20090022245 | Low latency analog QAM coherent demodulation algorithm - A digital demodulation method for a quadrature amplitude modulated signal uses a phase locked loop to generate a local carrier signal. The phase locked loop uses a feedback signal derived from one or more demodulated signals of interest. The loop has a filter characteristic with a stop band within the information bandwidth(s) of the information signal(s). The preferred method generates an error signal from DC components of in-phase and quadrature-phase baseband signals. DC components are preferably isolated using a low-latency, AC rejection filter. | 01-22-2009 |
20090022246 | Communication Device, Multi-Band Receiver, and Receiver - In a direct-conversion type orthogonal demodulator used in a multi-band receiver, influence to signal-receiving characteristics of the receiver, caused by DC offset drift produced when a band is switched to another, is reduced. In a multi-band receiver including a plurality of orthogonal demodulators each carrying out orthogonal demodulation for each of a plurality of band inputs, a switch which selects one of outputs transmitted from the orthogonal demodulators in accordance with a band-switching control signal and a high pass filter receiving an output transmitted from the switch, a cut-off frequency of the high pass filter is raised when a band is switched to another, to thereby shorten a convergent time of DC offset drift included in an output signal. | 01-22-2009 |
20090041161 | DC offset estimation system and method - A DC offset estimation system is disclosed. A DC offset estimation system includes a carrier frequency offset estimator receiving an input signal and estimating a carrier frequency offset value, a symbol timing recovery unit providing a symbol boundary of the input signal, and a DC offset estimator estimating a DC offset value to compensate the input signal based on the input signal, the carrier frequency offset value, and the symbol boundary. | 02-12-2009 |
20090052582 | Method for improving the performance of ofdm receiver and a receiver using the method - One or more parameters of a tuner of a receiver may be adjusted by generating for the receiver one or more control signals associated with one or more parameters and applying control signals to the tuner during a cyclic prefix (CP) period. The receiver may generate a control strobe in synchronization with the CP period wherein the control strobe essentially begins with the CP period and has duration preferably shorter than the duration of the CP period. The duration of the control strobe may be chosen such that the one or more control signals, after being applied to the tuner, each reaches its steady state before the CP period lapses. The adjusted parameters, alone or in combination, may be, for example, the gain of the low-noise-amplifier (LNA), the synthesizer's local frequency, the DC correction level, the power gain amplifier, and the I/Q error, and the like. The demodulator of the receiver may generate one or more of the control signals required for adjusting one or more parameters. One or more control signals may be determined according to previously received symbols/transmissions, and by determining the tuner's parameters to be adjusted based on the receiver's continued performance evaluations, and generating and applying the control signals to the tuner as a consequence of or in relation to these evaluations. | 02-26-2009 |
20090080570 | INTEGRATED CIRCUIT AND METHOD OF GENERATING A BIAS SIGNAL FOR A DATA SIGNAL RECEIVER - An integrated circuit and method of generating a bias signal for a data signal receiver is disclosed. One embodiment provides a replica circuit configured to generate a feedback signal, wherein the replica circuit is a replica of at least a part of a data signal receiver, and wherein the feedback signal depends on a reference signal of the data signal receiver. A compensation circuit is configured to compensate an influence of the reference signal on the feedback signal. An amplifier circuit is configured to generate a bias signal based on the feedback signal, the bias signal being provided to the data signal receiver. | 03-26-2009 |
20090080571 | RECEPTION APPARATUS AND RECEPTION METHOD - A receiving apparatus includes an amplification section that amplifies a received signal and a frequency conversion section that converts a frequency of the received signal, from a radio frequency to a baseband, the baseband having a lower frequency than the radio frequency. A gain control section amplifies, by a predetermined gain, the signal that has been subjected to the frequency conversion to the baseband. A voltage calibration section performs calibration on an offset voltage generated in the signal subjected to frequency conversion to the baseband. A time constant control section sets a first time constant during a reception operation and sets a second time constant, which is reduced with respect to the first time constant, during the calibration. A filter section passes a received signal of a predetermined band, with the first time constant or the second time constant, an operation control section stops operation of the amplification section during the calibration, controls the amplification section to operate during the reception operation, and controls the operation of the amplification section so as to reduce a residual offset voltage caused by switching the operation of the amplification section. | 03-26-2009 |
20090147885 | MAJORITY DETECTOR APPARATUS, SYSTEMS, AND METHODS - Apparatus, methods, and systems are disclosed, including, for example, a data receiver to receive a calibration voltage and a reference voltage to calibrate the data receiver. The output of the data receiver is provided to a first ripple counter that counts the outputs from the data receiver and provides an output count. The ripple counter may count either ones or zeros. A second ripple counter counts the number of a clock signals over the same period of time. The output count is either multiplied by two or the count of clock signals is divided by two. A ripple comparator may then compare the outputs and adjust the reference voltage based upon the comparison results. | 06-11-2009 |
20090185639 | DC OFFSET CORRECTION CIRCUIT FOR CANCELING A DC OFFSET IN REAL TIME AND A RECEIVING SYSTEM HAVING THE SAME - A DC offset correction circuit includes a DC offset detector generating a detection voltage based on a result of a comparison of a first reference voltage and a voltage difference between signals input to the DC offset detector, a comparator comparing a second reference voltage and the detection voltage and a third reference voltage and the detection voltage and outputting first and second comparison signals, respectively, as a result of the comparisons, and an up/down counter performing an up or a down count operation in response to one of the first or second comparison signals and, as a result of the up or down count operation, outputting a signal that causes at least one control signal for canceling a DC offset in a signal input to a receiver to be generated. | 07-23-2009 |
20090202022 | SPLIT CHANNEL RECEIVER WITH VERY LOW SECOND ORDER INTERMODULATION - A high performance radio frequency receiver includes an isolated transconductance amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to multiple electrically isolated currents; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter. IIP2 calibration of the in-phase and quadrature channels may be optimized using the isolated transconductance amplifier. | 08-13-2009 |
20090245425 | ANTENNA DEVICE, DEMODULATING DEVICE AND RECEIVING DEVICE - An antenna device that is placed adjacent to an antenna | 10-01-2009 |
20090285334 | METHOD FOR AMPLITUDE INSENSITIVE PACKET DETECTION - The invention relates generally to the field of wireless communications and more particularly to a method of and device for detecting the presence of a received data packet in a digital receiver. The present invention proposes a simplified method of correlation by removing dependency on the amplitude fluctuations while at the same time maintaining phase relevancy. The key advancement involves mapping the complex quadrature amplitude modulation (QAM) preamble to a quantized phase shift keying (PSK) constellation before application to a matched complex correlator. The proposed process essentially “amplitude normalizes” the input signal without the use or complexity associated with a divider. This simplified normalization scheme makes the packet detection algorithm robust against amplitude variations in the input signal, while still allowing for good correlation output. In applications where interference is superimposed on the I/Q input signals, the invention improves the detection capability over automatic gain control (AGC) normalization methods. | 11-19-2009 |
20090316834 | APPARATUS FOR CONTROLLING SENSITIVITY BY USING DIGITAL GATING IN RECEIVER AND RECEIVER WITH THE SAME - Disclosed is a wireless communication system, more particularly, a receiver and a chipset for DSRC. A receiver includes: a low noise amplifier (LNA) amplifying a received radio (RF) signal while minimizing amplification of noise included in the received RF signal; a mixer down-converting a frequency of an output signal of the LNA to output an intermediate frequency (IF) signal; a frequency synthesizer generating and outputting a frequency signal for the frequency-down conversion of the mixer to the mixer; a bandpass filter passing a necessary band of a channel in an output signal of the mixer; a log amplifier amplifying an output signal of the bandpass filter in log scale and outputting a received signal strength indicator of an output signal of the bandpass filter; a detector comparing an output of the log amplifier with a predetermined binary threshold value, outputting a first binary signal when the output of the log amplifier is less than the predetermined binary threshold value, and outputting a second binary signal when the output of the log amplifier is equal to or greater than the predetermined binary threshold value; a switch serially connected with an output terminal of the detector; and a switch controller comparing the received signal strength indicator of the output signal of the log amplifier with an RSSI threshold, opening the switch when the received signal strength indicator is less than the RSSI threshold, and closing the switch when the received signal strength indicator is equal to or grater than the RSSI threshold. | 12-24-2009 |
20090323864 | SINGLE ENDED MULTIBAND FEEDBACK LINEARIZED RF AMPLIFIER AND MIXER WITH DC-OFFSET AND IM2 SUPPRESSION FEEDBACK LOOP - A receiver arrangement includes a single ended multiband feedback amplifier, at least one single ended input, differential output mixer arrangement including a main mixer and a trim mixer, and a mixer feedback loop circuit configured to receive differential output signals generated by the mixer arrangement. The mixer feedback loop circuit generates a feedback signal based on the received differential output signals and provides the feedback signal to the mixer arrangement to minimize DC-offset and second order intermodulation products. The single ended multiband feedback amplifier may include an input stage and a programmable resonance tank circuit connected to the input stage for suppressing downconverted noise from harmonics of the LO-frequency, and a configurable feedback net that shapes the frequency response of a feedback loop including the feedback net based on a band operation of the single ended multiband feedback amplifier. | 12-31-2009 |
20100002807 | Frequency Demodulation with Threshold Extension - A frequency demodulator comprises a frequency discriminator configured to generate a frequency modulation signal from frequency modulated signal, circuitry for generating a phase modulation signal from the frequency modulation signal, and a click reduction signal processing (CRSP) circuit operable to remove noise enhancements from the phase modulation signal caused by clicks. By first converting the frequency modulation signal to a phase modulation signal, noise enhancements caused by clicks are more readily distinguished from other noise in the phase modulation signal. After the noise enhancements have been removed by the CRSP, the frequency modulation is recovered substantially free of clicks. Removal of the clicks results in an improved output signal-to-noise ratio, thereby advantageously extending the onset of the threshold effect. | 01-07-2010 |
20100020903 | METHOD AND DEVICE FOR PROCESSING THE DC OFFSET OF A RADIOFREQUENCY RECEPTION SUBSYSTEM - A method may compensate for direct current (DC) offset in a radio frequency reception device. The method may include partitioning an analog portion of the reception device into a plurality of zones, for each zone, calibrating initial DC offset compensation to be applied within an operating range of a respective zone, the operating range of the other zones being limited to a threshold operating range, and determining DC offset compensation to be applied to the reception device throughout the operating range based on the basic DC offset compensations. | 01-28-2010 |
20100040174 | METHOD AND ARRANGEMENT FOR ESTIMATING DC OFFSET - A method and arrangement for estimating a DC offset for a signal received in a radio receiver. The received signal includes a digitally modulated signal component, a DC offset component, and a noise component. When the signal is of a known type, such as a Gaussian Minimum Shift Keying (GMSK)-modulated signal with constant amplitude in a GSM/EDGE cellular radio system, the method exploits the known characteristics of the statistical distribution for the known type of signal to obtain a better estimate of the DC offset. The statistical distribution of the received digitally modulated signal component is first analyzed. That statistical distribution is then compared to the known statistical distribution for the known type of signal to identify differences. The differences are then used to estimate the DC offset. Additional iterations may be performed to further improve the DC estimate. | 02-18-2010 |
20100046672 | System for and Method of Detecting Interference in a Communication System - A system for and method of detecting interference in a communication system. In an embodiment, a receiver acquires a communication signal, the communication signal comprising a carrier signal and an in-band interference signal. A signal processor conditions the communication signal and extracts the in-band interference signal without interrupting the carrier signal to form an error signal. The error signal is representative of the in-band interference signal. The signal processor is further configured to process the error signal to obtain one or more spectral properties of the error signal in a manner suitable for display. | 02-25-2010 |
20100061485 | Systems and Methods for DC Offset Correction in a Direct Conversion RF Receiver - Systems and methods for DC offset correction in analog and digital direct conversion RF receivers. A time derivate and subsequent integration of in-phase and quadrature phase signal path components is performed to effectively remove DC offset from the resultant down converted baseband signal. | 03-11-2010 |
20100061486 | Data processing apparatus and data processing system including the same - In a data processing apparatus and a data processing system including the same, the data processing apparatus includes a clock signal generation unit configured to receive a data signal comprising a preamble signal, information about DC balance codes for DC balance, an embedded clock signal between the DC balance codes, and information about serialized valid data, to generate a synchronous clock signal that is synchronized with the serialized valid data based on the data signal, and to generate at least one sample clock signal based on the synchronous clock signal; and a data processor configured to deserialize the serialized valid data based on the at least one sample clock signal, to decode deserialized data based on the DC balance codes, and to output decoded data. | 03-11-2010 |
20100074372 | METHOD AND APPARATUS OF DETERMINING A SET OF ZERO CORRELATION ZONE LENGTHS - A method of determining a set of Zero Correlation Zone (ZCZ) lengths, comprises: determining the length of a root sequence, and selecting such a set of ZCZ lengths that, for any cell radius, the maximum number of preambles obtained from a ZCZ length which is selected from the selected set of ZCZ lengths is closest to the maximum number of preambles determined from a ZCZ length which is selected from the set of all integers, wherein the maximum number of preambles is determined from the length of the root sequence and a ZCZ length selected. This disclosure provides a technical solution for selecting a better limited set of ZCZ lengths by which signaling overload is reduced. | 03-25-2010 |
20100080324 | DEVICE AND METHOD FOR DC OFFSET CANCELLATION - A device and method for DC offset cancellation device are disclosed. The method includes keeping a high pass module at off state, converting an analog radio frequency signal to a digital baseband signal by a direct down conversion receiving module, detecting a DC offset value during the conversion by an offset compensation module so as to provide an offset compensation signal corresponding to the DC offset value to the direct down conversion receiving module, and determining whether a control condition is reached by a control module so as to timely switch on the high pass module for canceling the residual DC offset in the direct down conversion receiving module. In the present invention, the offset compensation module provides preliminary offset compensation signals and then the high pass module accurately cancels residual DC offset, thereby significantly reducing the reaction time for DC offset cancellation. | 04-01-2010 |
20100080325 | Method and System for Independent I and Q Loop Amplitude Control for Quadrature Generators - Certain aspects of a method and system for independent in-phase (I) and quadrature (Q) loop amplitude control for quadrature generators may include determining an amplitude voltage associated with an in-phase (I) component and a quadrature (Q) component of a generated signal. A DC reference voltage associated with the I component and the Q component may be determined. The determined amplitude voltage may be compared with the determined reference voltage to generate a control signal. The amplitude mismatch between the I component and the Q component may be compensated by controlling a biasing current of one or more programmable buffers associated with one or both of the I component and the Q component, based on the generated control signal. | 04-01-2010 |
20100119009 | PROGRAMMABLE WIDE BAND DIGITAL RECEIVER/TRANSMITTER - A receiver uses a wideband intermediate frequency (IF) in the analog domain and performs low IF down-conversion in the digital domain, using low-power, high-speed, high resolution analog-to-digital converters. The receiver can be integrated into an integrated circuit as one of several receivers. Such an integrated circuit may include multiple transmitters using adaptive non-linear modeling pre-distortion. The non-linear modeling may include memory. Imbalance in intermediate frequency in-phase and quadrature signals may be corrected in the digital domains. DC offsets in the intermediate signal may be corrected in both analog and digital domains. In one instance, the receiver provides a feedback receiver for the adaptive pre-distorter in a transmitter on the integrated circuit. | 05-13-2010 |
20100128819 | APPARATUS FOR CANCELLING DC OFFSET AND METHOD THEREOF - An apparatus and method for canceling a DC offset efficiently removes the DC offset by calculating the DC offset after acquiring synchronization in a terminal receiver used for an orthogonal frequency division multiplexing system. The apparatus for canceling the DC offset includes an adding/averaging unit ( | 05-27-2010 |
20100166114 | METHOD OF REDUCING D.C. OFFSET - A method of reducing d.c. offset comprises comparing the a first variable signal with a second variable signal, producing a control signal in dependence upon the comparison, providing the control signal to a charge pump for generation of a feedback signal, and varying the first signal and/or the second signal in dependence upon the feedback signal thereby reducing any difference between the d.c. level of the first signal and the d.c. level of the second signal. | 07-01-2010 |
20100172441 | FREQUENCY TRANSLATION MODULE FREQUENCY LIMITING AMPLIFIER - A system for processing signal communications between a frequency translation module and an integrated receiver decoder. According to an exemplary embodiment, the decoder and the frequency translation module comprise a signal processing apparatus comprising an input for receiving an frequency shift keyed modulated signal, an amplifier having negative feedback coupled to said input, wherein said input is further coupled to a first source of reference potential and a second source of reference potential; and a tank circuit coupled between said differential amplifier and an output. More particularly, the amplifier may comprise a first transistor having a first collector, a first emitter and a first base coupled to a signal source wherein said first base is further coupled to said first collector and a second transistor with a second base, a second emitter coupled to said first emitter, and a second collector, wherein said second collector is coupled to a bandpass filter and said bandpass filter is further coupled to an output. | 07-08-2010 |
20100172442 | ACCESS CODE DETECTION AND DC OFFSET-INTERFERENCE CORRECTION - A method for detecting an access code in a receiver that does not require an explicit DC-offset interference correction block, comprising:
| 07-08-2010 |
20100177851 | COMPENSATION METHOD, PROGRAM, RECORDING MEDIUM, AND RECEIVER FOR OFDM SIGNAL HAVING CFO AND DCO - A frequency offset (CFO) and a direct current component offset (DCO) occur in an OFDM scheme signal. To address this, such a method has been suggested which allows a pilot signal to be mixed with a communicated signal for compensation. However, if the pilot signal has a long duration, then a compensation method without the pilot signal is required to compensate signals during that period. However, no such a method is conventionally available which compensates for both the CFO and DCO without the pilot signal. Using the orthogonality of the OFDM signal, the matrix of a system in which CDO and DCO have occurred is subjected to the singular value decomposition, thereby predetermining the CFO candidate value which allows for demodulating zero from the received signal and an array of numerical values of CFO check data. Then, in a compensation section (17), the received signal is successively multiplied by the numerical values. The typical CFO value provided when the minimum value has been demodulated is outputted as an estimate value for compensation. | 07-15-2010 |
20100215125 | COMMUNICATIONS DEVICE WITH IN-PHASE/QUADRATURE (I/Q) DC OFFSET, GAIN AND PHASE IMBALANCE COMPENSATION AND RELATED METHOD - A DC offset estimator and removal circuit removes the DC offsets for each of the I and Q signal components in a received signal. A gain imbalance estimator and compensator circuit estimates and compensates for gain imbalances within the I and Q signal components. A phase imbalance estimator and compensator circuit estimates and compensates for phase imbalances within the I and Q signal components to produce a communications signal that is compensated for received DC offsets and gain and phase imbalances within the I and Q signal components. | 08-26-2010 |
20100246722 | Data Slicer Threshold Adjustment for Disparity Controlled Signals - A system and method are provided for using disparity measurements to control the adjustment of a data slicer threshold. The method receives a serial stream of pseudorandom digital data signals having an average DC value, and compares data signal amplitudes to a slicer threshold value. In response to the slicer threshold value comparison, data signal “1” and “0” values are determined. A first sum of determined “1” values is created, and a second sum of determined “0” values is created. The slicer threshold value is adjusted in response to the comparison of the first and second sums. More explicitly, the slicer threshold value is adjusted to make “1” values more likely in response to the second sum being larger than the first sum. Alternately, the slicer threshold value is adjusted to make “0 ” values more likely in response to the second sum being smaller than the first sum. | 09-30-2010 |
20100246723 | METHOD FOR ESTIMATING AMOUNT OF DISTORTION IN CFO AND DCO, METHOD FOR COMPENSATING RECEIVED SIGNALS USING THE SAME, AND RECEIVER - A received signal delivered through a transmission line can be compensated for CFO and DCO to improve the SNR of the received signal, eventually resulting in an effective improvement in the error rate. In this context, methods for estimating and compensating for CFO and DCO have been studied, for example, using pilot signals or a blind method. However, the methods would require a huge amount of calculations for the estimation of CFO in the presence of DCO, as with the ML method, or never essentially eliminate errors from an estimated value. The received signal has convoluted influences through the transmission line, so that observation of the continual symbols of periodic pilot signals on the frequency axis shows just a phase shift by the CFO. Therefore, the CFO can be analytically found from the continual symbols of periodic pilot signals, thereby allowing the DCO to be estimated and both the CFO and the DCO to be compensated for. | 09-30-2010 |
20100254491 | DC OFFSET COMPENSATING SYSTEM AND METHOD - A system for removing a DC-offset component from an input signal is presented. The system includes a sorter to separate positive samples and negative samples of the input signal. The system further includes a positive sample average generator to calculate a positive sample average according to a number of positive samples in the input signal and a negative sample average generator to calculate a negative sample average according to a number of negative samples in the input signal. A balanced average generator is provided for receiving positive and negative sample averages from the positive and negative sample average generators and for generating a reference signal. The system further includes a subtractor for subtracting the reference signal from the input signal to generate a DC-offset compensated output signal. | 10-07-2010 |
20100260291 | Carrier Recovery Device and Related Method - A carrier recovery device for a communication receiver is disclosed. The carrier recovery device includes an A/D converter for converting an analog signal received by the communication receiver to a digital signal, a frequency compensator coupled to the A/D converter for compensating frequency of the digital signal according to a carrier frequency offset value, a filter coupled to the frequency compensator for filtering the digital signal to generate an output signal, and a frequency offset estimator coupled to the filter and the frequency compensator for estimating the carrier frequency offset value according to the output signal and providing the carrier frequency offset value to the frequency compensator for implementing carrier recovery. | 10-14-2010 |
20100284496 | Method and apparatus for dc offset compensation in a digital communication system - A method of compensating for dc offset of a received signal transmitted over a channel having a plurality of paths, the received signal comprising a modulated data signal and a modulated known training sequence signal, the method comprising the steps of: constructing ( | 11-11-2010 |
20100329390 | ADAPTIVE OFFSET-COMPENSATING DECISION-FEEDBACK RECEIVER - A circuit that receives input signals from a transmitter via proximity communication, such as capacitively coupled proximity communication, is described. Because proximity communication may block DC content, the circuit may restore the DC content of input signals. In particular, a refresh circuit in the circuit may short inputs of the circuit to each other at least once per clock cycle (which sets a null value). Furthermore, a feedback circuit ensures that, if there is a signal transition in the input signals during a current clock cycle, it is passed through to an output node of the circuit. On the other hand, if there is no signal transition in the input signals during the current clock cycle, the feedback circuit may select the appropriate output value on the output node based on the output value during the immediately preceding clock cycle. | 12-30-2010 |
20100329391 | INFORMATION DETECTING APPARATUS AND METHOD - Proposed are a highly reliable information detecting apparatus and an information detecting method. This information detecting apparatus includes a high pass filter unit configured in a manner of being able to freely change a time constant and for extracting a high frequency content of the communication signal, a squelch detection unit for detecting a region in which a signal level of the high frequency component of the communication signal exceeds a predetermined squelch detection threshold, an information detection unit for detecting the information superposed on the communication signal based on a detection output of the squelch detection unit, a DC fluctuation detection unit for detecting a level fluctuation of a DC component of the communication signal, a control unit for controlling the high pass filter to lower the time constant of the high pass filter unit when the level fluctuation of the DC component of the communication signal is detected by the DC fluctuation detection unit, and a mask unit for masking the detection output of the squelch detection unit so as to make it appear that the squelch detection unit has not detected a region exceeding the squelch detection threshold while the control unit is lowering the time constant of the high pass filter unit. | 12-30-2010 |
20110007845 | COMMUNICATION RECEIVER HAVING THREE FILTERS CONNECTED IN SERIES - A communication receiver includes a mixer, a filter group and an analog-to-digital converter. The mixer is used for mixing an input signal with a local oscillation signal to generate a mixed signal. The filter group is coupled to the mixer, and is used for filtering the mixed signal to generate a filtered signal, where the filter group includes a first one-pole filter, a second one-pole filter, and a complex-pole filter. The analog-to-digital converter is coupled to the filter group, and is used for performing an analog-to-digital converting operation on the filtered signal to generate a digital signal. | 01-13-2011 |
20110007846 | Modulation and Demodulation Circuit - The invention relates to the field of modulation and demodulation circuits, such as envelope detectors used to demodulate amplitude-modulated (AM) signals and amplitude-shift-keying (ASK) signals. By judiciously coupling an analog circuit comprising one resistor and two capacitors which are judiciously dimensioned to a port of a digital component, an extremely compact envelope detector can be obtained, which achieves demodulation of a binary ASK signal for direct coupling into a digital input port. Accordingly, a very compact envelope detector may advantageously be used in the data receiving part of a sealed device requiring post-manufacturing data transfer, in combination with additional components that provide electromagnetic coupling, such as inductive coupling, capacitive coupling, or radiative coupling. An example of such a device is a credit card sized authentication token, the electrical personalization of which happens after the production of the card-like housing. The digital port may additionally be used to modulate the backscattered wave, by switching the voltage of the diode port to the system ground level. In this way, the apparatus is advantageously equipped with a wireless bidirectional half-duplex transmission system. | 01-13-2011 |
20110007847 | DC COMPENSATION FOR VLIF SIGNALS - Receiver circuitry for processing a received Very Low Intermediate Frequency signal wherein the receiver circuitry comprises a main processing path. The main processing path comprises mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal. The receiver circuitry further comprises a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal. The receiver circuitry still further comprises signal summing circuitry arranged to add the DC cancellation signal in anti-phase with the main path signal. | 01-13-2011 |
20110026643 | CARRIER DETECT SYSTEM, APPARATUS AND METHOD THEREOF - A method of detecting an on-channel signal and synchronizing signal detection with correcting for DC offset errors in a direct conversion receiver is presented. A received signal is digitized, and a state machine operates to detect the presence of an on-channel signal. If the signal is not detected, a mixed mode training sequence is initiated in which the DC offset errors in both an analog and digital received signal path are corrected. While training, processing of the digitized samples by a digital signal processor and a host controller is suspended (while they are put into battery save mode) and the gain provided to subsequently received signals is minimized. The DC offset correction circuitry is bypassed and put into battery save mode at predetermined periods when DC offset correction is not performed. | 02-03-2011 |
20110051850 | FREQUENCY TUNING AND DIRECT CURRENT OFFSET CANCELING CIRCUIT FOR CONTINUOUS-TIME ANALOG FILTER WITH TIME DIVIDED - The present invention provides a frequency tuning/DC offset canceling circuit for continuous-time analog filter with time division, the frequency tuning/DC offset canceling circuit including: a frequency tuning/DC offset canceling unit for performing frequency tuning by comparing an output voltage with a reference voltage when a frequency tuning control signal is inputted, and canceling a DC offset after terminating the frequency tuning when a DC offset canceling control signal is inputted; and a control signal generator for generating the frequency tuning control signal and the DC offset canceling control signal based on a reference clock in time division. | 03-03-2011 |
20110064165 | DEMODULATION APPARATUS AND METHOD FOR RFID READER IN PASSIVE RFID ENVIRONMENT - A demodulation apparatus for a Radio Frequency Identification (RFID) reader includes: a direct current (DC) offset cancellation unit for cancelling DC-offset noise contained in a PSK-modulated or ASK-modulated subcarrier tag signal from the tag signal when the tag signal is received; and a subcarrier digital demodulator for eliminating a subcarrier from the tag signal from which DC-offset noise has been cancelled to demodulate the DC-offset noise-cancelled tag signal. | 03-17-2011 |
20110090989 | APPARATUS AND METHOD FOR REMOVING DC OFFSET IN WIRELESS COMMUNICATION SYSTEM - An apparatus and method for removing a Direct Current (DC) offset at a receiving terminal in a wireless communication system are provided. In the method, a frame is divided into at least two time resource blocks. Resource allocation information is used to discriminate between at least one time resource block of a data-unmapped interval and at least one time resource block of a data-mapped interval. The DC offset is measured during the data-unmapped interval. The DC offset is compensated during the data-unmapped interval on a time resource block basis by using the measured DC offset. | 04-21-2011 |
20110103518 | DC OFFSET SUPPRESSION CIRCUIT FOR A COMPLEX FILTER - The present invention relates to a direct current (DC) offset suppression circuit to suppress DC offsets occurring when a communication circuit where a complex filter is adopted performs self-mixing. The DC offset is suppressed by a DC feedback circuit adopted by a filter which is substituted for a complex filter in the communication circuit. But, the DC offset cannot be suppressed when a complex filter is used in the communication circuit. It is because phase changes of the complex filter cause output signal fed back to the input of the complex filter to generate phase differences. The present invention includes a phase compensation unit and a DC feedback unit. The phase compensation unit compensates a change in frequency between input and output of the complex filter for phase compensation. The DC feedback unit inverses and feeds back the compensated phase to an input of the complex filter. | 05-05-2011 |
20110122975 | ELECTRONIC TUNER AND HIGH FREQUENCY RECEIVING DEVICE USING THE SAME - Demodulator includes reception quality evaluation circuit for evaluating the quality of a received signal by comparison with a first reference value, and outputting an evaluation signal; and driving circuit receiving the evaluation signal. If reception quality evaluation circuit evaluates that the quality of the received signal is acceptable, power supply from driving circuit to DC offset control loop is stopped. This offers a high-frequency receiver that reduces power consumption. | 05-26-2011 |
20110170636 | Signal Separating Circuit, Signal Separating Method, Signal Multiplexing Circuit and Signal Multiplexing Method - When a data signal of a first channel is an RZ signal having a pulse period T | 07-14-2011 |
20110176641 | D.C. Offset Estimation - A combination of a phase shifter, a measurement receiver, and an offset estimator enable the d.c. offset in the transmit path of a quadrature transmitter to be distinguished from the d.c. offset in the measurement receiver. The measurement receiver performs a first measurement on the transmit path output with a “normal” phase shift of 0 degrees and 90 degrees for in-phase (I) and quadrature (Q) components, and a second measurement with a “special” phase-shift of 180 degrees and 270 degrees for the I and Q components, respectively | 07-21-2011 |
20110188611 | Signal Processing Circuit and Method Thereof - A signal processing circuit is provided. The signal processing circuit, adjusting a received radio frequency (RF) signal according to a gain, and generating a digital signal accordingly, the signal processing circuit including a signal analysis circuit, for analyzing the digital signal to generate the gain, determining whether the received RF signal is a target signal, and generating a reference value according to the digital signal, and a baseband circuit, for performing a carrier frequency offset (CFO) compensation to the digital signal according to the reference value, wherein, the reference value is generated while the signal analysis circuit is determining whether the received RF signal is the target signal. | 08-04-2011 |
20110188612 | DC OFFSET CANCELLATION IN DIRECT CONVERSION RECEIVERS - A method includes receiving a signal using a direct conversion receiver, while the receiver is set at a gain that is selected from a range of possible gain values. Multiple DC offset correction values are provided for use by a DC offset cancellation loop, each DC offset correction value being associated with a respective sub-range of the range of the possible gain values. A DC offset correction value is selected from among the multiple DC offset correction values based on the gain to which the receiver is set. A DC offset in the signal is canceled by setting the DC offset cancellation loop to the selected DC offset correction value. | 08-04-2011 |
20110286553 | DC OFFSET CALIBRATION - A mobile communication device comprises a plurality of receivers, a phase detection circuit, and a DC offset calibration circuit. Each receiver comprises a receiver chain and a divide-by-2 circuit that supplies Local Oscillating (LO) signal for the receiver chain. The LO signals leak to each receiver chain and create an undesirable DC offset voltage. The DC offset depends on an LNA gain and a phase relation among the LO leakages. In a first novel aspect, a two-dimensional DC offset calibration (DCOC) table is prepared for each receiver chain. In a second novel aspect, the phase detection circuit detects the phase relation among the LO leakages for each receiver chain. Based on the LNA gain and the detected phase relation of each receiver chain, a DCOC code is selected from a corresponding DCOC table such that the calibration circuit calibrates the DC offset for each receiver effectively and efficiently. | 11-24-2011 |
20110293043 | DC OFFSET CORRECTION TECHNIQUES - Techniques are disclosed that involve the reduction of DC offsets. For instance, embodiments may receive a baseband signal, and determine a DC characteristic of the baseband signal. When the DC characteristic has a value that is outside of a predetermined range, a correction signal is adjusted. The correction signal is injected into the baseband signal. | 12-01-2011 |
20120057656 | METHOD AND APPARATUS FOR PASSIVE RADIO FREQUENCY INDENTIFICATION (RFID) READER DIGITAL DEMODULATION FOR MANCHESTER SUBCARRIER SIGNAL - An apparatus and method for passive radio frequency identification (RFID) reader digital demodulation with respect to a Manchester subcarrier signal are disclosed. In a passive RFID environment where the Manchester subcarrier signal contains DC components in a frequency region, even when a tag signal containing the DC offset noise is input to a baseband, demodulation may be efficiently performed while the DC offset noise is removed. Therefore, accurate detection of tag information from the tag signal may be achieved. | 03-08-2012 |
20120163504 | AUTOMATIC FREQUENCY OFFSET COMPENSATION IN ZERO-INTERMEDIATE FREQUENCY RECEIVERS USING MINIMUM-SHIFT KEYING (MSK) SIGNALING - Carrier frequency offset (CFO) between a transmitter and receiver signaling at 2 Mbps data rate with a 11110000 pattern as the preamble period is corrected within one preamble time period using free-running coarse and fine carrier frequency offset estimations. Two estimates for the CFO are computed, coarse and fine. The fine one is computationally accurate but may not be correct because of a potential wrap at ±180° in the computation. The coarse one is not accurate but delivers the approximate CFO value without wrap over. The comparison between the coarse and fine estimates thus may be used to detect a wrap over in the fine estimate and modify the fine estimate accordingly. Thereafter the compensated fine CFO estimation is used for carrier frequency offset (CFO) compensation. | 06-28-2012 |
20120183099 | DYNAMIC DC-OFFSET DETERMINATION FOR PROXIMITY SENSING - The subject matter disclosed herein relates to dynamically determining DC-offset used for proximity sensing of a mobile device | 07-19-2012 |
20120307940 | PULSE RECEIVER AND METHOD FOR RECEIVING BURST SIGNAL - Provided is a pulse receiver capable of receiving a burst signal and decoding the burst signal with a bit error rate reduced to a target value or less by controlling a determination threshold such that decoding success rate is equal to or less than a predetermined value. A decode unit | 12-06-2012 |
20120328052 | Spur Mitigation For Radio Frequency Receivers Utilizing A Free-Running Crystal - Embodiments of a receiver for using a first oscillator signal provided by a crystal resonator to support multiple, different functionalities are provided. The receiver comprises a phase-locked loop (PLL) configured to provide a second oscillator signal based on the first oscillator signal provided by the crystal resonator; a first mixer configured to mix a received signal received over a first input path with the second oscillator signal received over a second input path to provide a first frequency-shifted signal; and an automatic frequency controller (AFC) configured to estimate a frequency offset of the second oscillator signal and adjust the PLL to compensate for the frequency offset. The receiver further can include solutions for mitigating potential sources of noise caused by the frequency of the first oscillator signal not being compensated for by the AFC. | 12-27-2012 |
20130016797 | METHOD AND APPARATUS FOR UPDATING SYMBOL RECOVERY PARAMETERS AND CORRECTING SYMBOL TIMING MISALIGNMENTAANM Naing; Kyaw M.AACI PlantationAAST FLAACO USAAGP Naing; Kyaw M. Plantation FL USAANM Doberstein; Kevin G.AACI ElmhurstAAST ILAACO USAAGP Doberstein; Kevin G. Elmhurst IL USAANM Han; DonghoAACI ParklandAAST FLAACO USAAGP Han; Dongho Parkland FL US - A radio receiver ( | 01-17-2013 |
20130148761 | METHOD FOR CORRECTING IMBALANCE ERRORS IN A DIRECT CONVERSION RECEIVER - A communication system comprises a direct conversion receiver for correcting imbalance errors. The direct conversion receiver receives a radio frequency (RF) signal and converts the RF signal to baseband signals. The direct conversion receiver further translates the baseband signals to digital signals having a direct current (DC) offset and applies a DC offset correction to the digital signals having the DC offset to generate first DC offset corrected signals. An imbalance correction unit of the direct conversion receiver applies an imbalance correction to the first DC offset corrected signals by estimating an error between an average envelope of the first DC offset corrected signals and an average envelope of second DC offset corrected signals. The imbalance correction unit is fixed at initial imbalance parameter values. The direct conversion receiver further updates the initial imbalance parameter values of the imbalance correction unit based on the estimated error for correcting imbalance errors. | 06-13-2013 |
20130188756 | Double Conversion Dual-Carrier Radio Frequency Receiver - In a dual-carrier, double-conversion Orthogonal Frequency Division Multiplexing (OFDM) receiver a frequency synthesizer generates a first local oscillator signal for the first down-conversions stage of the receiver. A frequency divider is used to derive a second local oscillator signal from the first local oscillator signal, thus eliminating the need for a separate frequency synthesizer for the second down-conversion stage. A controller determines the frequency of the first local oscillator signal and a divisor M to align subcarrier grids for said first and second baseband signals with DC. | 07-25-2013 |
20130223569 | WIRELESS RECEIVER - A direct-conversion type wireless receiver includes a pair of mixers for frequency-converting a radio signal received from an antenna into a base band signal by local signals having different phases; a first amplification circuit for amplifying the base band signal up to a demodulation level; a second amplification circuit provided between the mixer and the first amplification circuit; and a variable current circuit including a multi-stage current mirror to add a current 2n times as high as a reference current. The wireless receiver further includes a control unit configured to correct a DC offset of the mixer by allowing a current to flow into the second amplification circuit from the variable current circuit, based on an output of the first amplification circuit, and a capacitor connected between a gate and a source of a PchMOSFET which allows the reference current to flow therethrough. | 08-29-2013 |
20130223570 | APPARATUS FOR REMOVING DC COMPONENTS INHERENT IN A RADIO FREQUENCY CHAIN - Device for compensating a DC component inherent in any radio frequency chain in which from a single measurement, generally obtained from a digital stage, a set of multiple compensation values is determined by a compensation value vector generating module and which compensation values are applied to multiple compensation points of the analog chain. The compensation values are calculated by an iterative process converging toward cancellation of the DC component and avoid saturating amplification components and components of the analog-to-digital converter. The module includes compensation value calculation units each configured to calculate a respective compensation value and provide the calculated compensation value to the respective compensation point. | 08-29-2013 |
20130287145 | BASE BAND PROCESSOR WITH PEAK SUPPRESSION FUNCTION, TRANSMITTER WITH THE SAME AND METHOD OF TRANSMITTING SIGNAL - There are provided a base band processor having a peak suppression function, a transmitter, and a method of transmitting a signal. The base band processor includes: a signal generating unit generating digital signals; a variable up/down sampling unit changing a sampling rate in real time according to a magnitude of signal bandwidth changed in real time and sampling the digital signals from the signal generating unit according to the sampling rate; a peak suppression processing unit detecting peak power of sampled signals from the variable up/down sampling unit for a respective section in which a peak exists and suppressing corresponding peak power according to the peak power of the respective section; and a signal converting unit converting the digital signals from the peak suppression processing unit into analog signals. | 10-31-2013 |
20130294545 | METHOD AND APPARATUS FOR ELIMINATING DIRECT CURRENT OFFSET - The present invention provides a method and an apparatus for eliminating direct current offset. The method comprises the steps of: calculating Euclidean distances between every two demodulation symbols of a plurality of demodulation symbols based on Quadrature Phase Shift Keying (QPSK) modulation; determining four sets from the plurality of demodulation symbols in accordance with the Euclidean distances between the demodulation symbols, each set corresponding to a modulation direction for the QPSK modulation; performing Euclidean distance weighted summation on the determined four sets respectively, and selecting a demodulation symbol with the minimum weighted summation value from each set as a rough estimation point for the QPSK modulation, so as to obtain four rough estimation points; re-determining four sets from the plurality of demodulation symbols in accordance with the Euclidean distances between the demodulation symbols and the rough estimation points; performing Euclidean distance weighted summation on the re-determined four sets respectively, and selecting a demodulation symbol with the minimum weighted summation value from each set as a precise estimation point; and performing direct current offset calculation and compensation in accordance with the precise estimation points. The present invention can improve the demodulation performance of a system. | 11-07-2013 |
20130294546 | DOUBLE-SAMPLING RECEIVER WITH DYNAMIC OFFSET MODULATION FOR OPTICAL AND ELECTRICAL SIGNALING - A receiver architecture is disclosed which employs an RC double-sampling front-end and dynamic offset modulation technique. A low-voltage double-sampling technique provides high power efficiency by avoiding linear high-gain elements conventionally employed in typical transimpedance-amplifier (TIA) receivers. In addition, a demultiplexed output of the receiver helps save power in the subsequent digital blocks. Various applications are described including optical receivers, electrical on-chip interconnects, as well as pulse amplitude modulation. The receiver can be implemented in CMOS and is scalable and portable to other technologies. | 11-07-2013 |
20140044221 | DIGITAL RF RECEIVER - Embodiments provide a digital RF receiver including a signal converting unit which converts an RF signal received from an external device into a digital signal, a plurality of functional modules which processes the digital signal in accordance with a predetermined algorithm when the digital signal is input, and a signal processing controller which selects at least one of the plurality of functional modules to control the digital signal to be processed in consideration of whether an IF signal component is included in the digital signal or a sampling rate related with sampling information of the digital signal. | 02-13-2014 |
20140098908 | CURRENT REDUCTION IN DIGITAL CIRCUITS - A digital circuit includes at least one input node, a biasing circuit, and a digital baseband circuit. The input node receives a digital signal including samples at a plurality of sample instances, the samples including a positive sample and a negative sample and represented by first plurality of bits. The biasing circuit generates a biased digital signal by adding a bias value to the digital signal so as to change the positive sample and the negative sample to first sample and second sample respectively and represented by second plurality of bits. The digital baseband circuit is configured to receive and process the biased digital signal such that reduced current consumption is realized based on a number of bit toggles in the second plurality of bits being less than a number of bit toggles in the first plurality of bits. | 04-10-2014 |
20140105331 | DC OFFSET CANCELLATION IN DIRECT CONVERSION RECEIVERS - A method includes receiving a signal using a direct conversion receiver, while the receiver is set at a gain that is selected from a range of possible gain values. Multiple DC offset correction values are provided for use by a DC offset cancellation loop, each DC offset correction value being associated with a respective sub-range of the range of the possible gain values. A DC offset correction value is selected from among the multiple DC offset correction values based on the gain to which the receiver is set. A DC offset in the signal is canceled by setting the DC offset cancellation loop to the selected DC offset correction value. | 04-17-2014 |
20140192930 | SIGNAL RECEIVING APPARATUS AND SIGNAL RECEIVING METHOD - A signal receiving apparatus, applicable in a wireless system calibrating direct current offset, includes: an adjusting circuit arranged to receive an receiving signal having a first DC (Direct Current) signal, and adjust the first DC signal to generate the receiving signal having a second DC signal according to an adjusting signal; a first arithmetic circuit arranged to generate an error signal according to the second DC signal and a target DC signal; and a second arithmetic circuit arranged to calculate an error signal slope according to the error signal, and update the adjusting signal according to the error signal slope and the error signal. | 07-10-2014 |
20140269998 | System and Method For Internal AC Coupling With Active DC Restore and Adjustable High-Pass Filter for a PAM 2/4 Receiver - A receiver termination circuit includes an internal AC coupling capacitor and an adjustable resistor forming an adjustable high-pass filter (HPF) at a receiver side of a transmission medium, and a digital-to-analog converter (DAC) coupled to the adjustable HPF, the DAC configured to provide a signal having a low-pass filter response to the adjustable HPF to provide a DC restore function. | 09-18-2014 |
20140269999 | Polar Receiver Signal Processing Apparatus and Methods - A method of generating inphase and quadrature signals from a polar receiver providing a phase derivative signal and an envelope magnitude signal comprising receiving an estimated phase derivative signal; generating an estimated phase signal; mapping the estimated phase signal to an angular value; converting the estimated phase signal to an inphase signal and a quadrature signal based on the angular value; and, providing the inphase signal and quadrature signal to a demodulation circuit. | 09-18-2014 |
20140286456 | DEVICE AND METHOD FOR REMOVING DIRECT CURRENT OFFSET USING RANDOMIZED CONTROL PULSE - A device and method for solving problems of the prior art in which channel information as well as a DC offset is removed when removing the DC offset using a feedback signal of a baseband amplifier is provided. The device includes a DC offset correcting unit for removing the DC offset using an HPF function and controlling a feedback path according to a control signal to stop the HPF function and a signal generator for generating the control signal for controlling the HPF function, wherein the control signal is a signal for controlling formation and cutting-off of the feedback path. | 09-25-2014 |
20140307834 | DC OFFSET COMPENSATION - A method for estimating an unwanted component that a receiver introduces into a signal at a known frequency, the method comprising applying a frequency offset to a signal, which comprises a wanted component at the known frequency, to form an offset signal having a frequency spectrum in which the wanted component is not positioned at the known frequency, processing the offset signal in the receiver and estimating a component positioned at the known frequency in the frequency spectrum of the processed signal. | 10-16-2014 |
20140334574 | ADAPTIVE BLUETOOTH RECEIVER AND METHOD - A Bluetooth receiver comprises a RF front end configured to receive a Bluetooth signal including a preamble and 34-bit pseudo-number (PN); a DC estimator communicatively coupled to the RF front end; and a frame synchronizer communicatively coupled to the DC estimator. The DC estimator is configured to perform DC offset estimation by determining an average value of samples of the preamble and the frame synchronizer is configured to use the 34-bit PN for frame synchronization. | 11-13-2014 |
20150016571 | Blind Mechanism for Estimation and Correction of I/Q Impairments - A mechanism for blind estimation of parameters for correcting I/Q impairments. Complex samples of a complex baseband signal are received from a receiver. A cross-correlation is computed between an I component and a Q component of the complex samples. A mean square value is computed for the I component of the complex samples; and a mean square value is computed for the Q component of the complex samples. A cross-channel gain estimate is: computed based on the cross-correlation value and one or both of the mean square values; and used to apply a cross-channel gain correction to the complex samples. An estimate of an I/Q gain imbalance is computed based on the mean square values. The gain imbalance estimate is useable to correct an I/Q gain imbalance present in the complex samples. The parameters may be supplied to the receiver, enabling the receiver to apply online corrections. | 01-15-2015 |
20150036769 | APPARATUS AND METHOD FOR PROCESSING SIGNALS - An apparatus for processing signals, in particular physiological measuring signals, is provided with a number of channels with main signal inputs for receiving input signals. Each of the input signals has a specific signal component and a signal component common to all input signals. Each channel is provided with an impedance transforming input amplifier. The apparatus supplies a respective input signal to the first input of each input amplifier and an analog reference signal, which is equal for all channels, to the second input. The apparatus includes a digital signal processor and one or more analog-digital converters for supplying the signals provided by the input amplifiers to the digital signal processor. The signal processor converts signals received from the one or more analog-digital converters at least into one or more output signals. | 02-05-2015 |
20150085957 | Method Of Calibrating a Slicer In a Receiver Or the Like - A method of calibrating data slicer-latches in a receiver to remove offset errors in the slicer-latches. A known voltage is applied to all but one of the inputs of the slicer-latch. The remaining input receives an offset cancelation voltage from a DAC is stepped upward from a minimum voltage until the slicer-latch output transitions by incrementing a codeword to the DAC and the codeword that resulted the transition is saved. Then the offset cancelation voltage is swept downward in steps from a maximum voltage until the slicer-latch output transitions and the codeword that caused the transition is averaged with the stored codeword. The average of the codewords is applied to the DAC to generate the offset cancelation voltage used during normal operation of the receiver. | 03-26-2015 |
20150085958 | DC Correction for Accurate Detection of Pulses - Techniques are presented herein for distinguishing between the DC component of a real signal and DC energy of a received signal due to the radio receiver circuitry. Samples are obtained of a received signal derived from output of a receiver of a communication device. A mean of the samples is computed over a sample window comprising a predetermined number of samples. First and second thresholds are provided, the first threshold being greater than the second threshold. An absolute value of the mean is compared with respect to the first threshold and the second threshold as samples are obtained in the sample window. A selection is made between the first threshold and the second threshold for purposes of comparison with the absolute value of the mean to determine whether energy at DC is a true/real DC component of the received signal or is due to circuitry of the receiver. | 03-26-2015 |
20150312068 | Simplified and Effective Offset Calibration Circuit for RxLOS in Serdes - A method for offset cancellation in a receiver loss of signal (RxLOS) circuit of a serializer/deserializer (SerDes) receiver device includes receiving a differential input signal via the first stage of a peak detector cell of the RxLOS circuit and shorting the differential output of the first stage via a control switch of the second stage of the RxLOS circuit. The control switch may further transition the RxLOS circuit from normal operating mode to an offset cancellation mode wherein the control switch may manually or automatically short the differential output of the first stage. | 10-29-2015 |
20160134444 | METHOD AND APPARATUS FOR CORRELATION CANCELLER FOR INTERFERENCE MITIGATION WITH ADAPTIVE DC OFFSET CANCELLATION - A method and apparatus for a method and apparatus for correlation canceller for interference mitigation with adaptive DC offset cancellation for a dual mode communication device includes detecting an active signal transmitting in one mode; configuring integrators associated with the adaptive correlation canceller into gain amplifiers; detecting DC offset utilizing the gain amplifiers and comparators; and configuring the integrators from the gain amplifiers back to integrators with the DC offset applied thereto. The active signal transmitting in one mode can be Long Term Evolution (LTE) which is adjacent to a signal in another mode. | 05-12-2016 |
20160197746 | APPARATUS AND METHODS FOR DC BIAS TO IMPROVE LINEARITY IN SIGNAL PROCESSING CIRCUITS | 07-07-2016 |
20160380788 | SYSTEMS AND METHODS TO DYNAMICALLY CALIBRATE AND ADJUST GAINS IN A DIRECT CONVERSION RECEIVER - Method embodiments are provided herein for dynamically calibrating and adjusting a direct conversion receiver system. One embodiment includes applying one or more gain control signals to one or more gain elements of a receiver system, where the applying one or more gain control signals results in a gain change to the receiver system; in response to the gain change, determining whether the receiver system exhibits a DC (direct conversion) offset; and in response to a determination that the receiver system exhibits the DC offset, applying one or more DC offset correction control signals to one or more gain elements of the receiver system, where the one or more DC offset correction signals are configured to correct the DC offset. | 12-29-2016 |