| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 375318000 | Differential amplifier | 17 |
| 20080198949 | RECEIVER, WIRELESS DEVICE AND METHOD FOR CANCELLING A DC OFFSET COMPONENT - A receiver includes a memory for storing DC offset amounts generated by an analog circuit; an amplifier; a DC offset amount generator for generating a first offset value and a second offset value to be removed from the received signal amplified at the amplifier; a first DC offset component-removing unit for removing the first DC offset value from the received signal before the amplifier; a second DC offset component-removing unit for removing the second DC offset value from the received signal after the amplifier; and an updating unit for updating the DC offset amount stored in the memory in view of the second DC offset value generated by the DC offset amount generator. A maximum value of the second DC offset value is set larger than a multiplication value of a gain of the amplifier by a minimum resolution value of the first DC offset value. | 08-21-2008 |
| 20080279310 | ENHANCED SIGNALING SENSITIVITY USING MULTIPLE REFERENCES - A receiver circuit uses two or more comparators to detect the received data signal. Each comparator is set to compare the data signal to a different reference signal. The output signals of the comparators are received into a detector circuit, which provides a third output signal that establishes the logic state of the received signal based on whether or not the output signals of the comparators are equal. Depending on the logic state of the data signal, one of the comparators provides its output signal sooner than the other. Each comparator may be implemented by a differential amplifier. In one embodiment, the reference signals are threshold voltages which may be provided by the tripping voltages at the trip points for the logic HIGH and LOW states. | 11-13-2008 |
| 20090060092 | Circuit and method for improved offset adjustment of differential amplifier within data receiving apparatus - A data receiving apparatus is provided to receive command data encoded by using a combination of high-level periods during which there is radio wave and low-level periods during which there is no radio wave. The data receiving apparatus is provided with a receiving circuit including a differential amplifier circuit receiving the command data through an antenna, and a demodulator outputting a reproduced signal corresponding to the command data in response to an output of the differential amplifier; and an offset adjustment switch circuit judging a logic level of the reproduced signal in the low level periods of the command data while the receiving circuit receives the command data, and generates offset switch signals based on the logic level of the reproduced signal in the low level periods. The differential amplifier circuit includes an offset control section adjusting an offset value of the differential amplifier circuit in response to the offset switch signals. | 03-05-2009 |
| 20090103654 | LOW INTERMEDIATE FREQUENCY RECEIVER - One embodiment relates to a low intermediate frequency (IF) receiver. The low-IF receiver includes an analog front end that is configured to receive a modulated IQ data signal and provide an in-phase signal and a quadrature signal, where the in-phase signal is phase shifted by approximately 90° relative to the quadrature signal. The low-IF receiver further includes a digital processing block, and a single path that provides only one of the in-phase signal and the quadrature signal to the digital processing block. Other receivers and methods are also disclosed. | 04-23-2009 |
| 20090110117 | Active clamp circuit for electronic components - An active clamp circuit for electronic components includes two sets of diode connected transistors that are inversely connected in parallel across an output of the component for providing both positive and negative differential conducting paths. The diode connected transistors cooperatively operate to limit a differential output voltage between the positive and negative conducting paths. An emitter follower buffer includes the clamp circuit and is configured to limit RF energy incident to an analog to digital converter (ADC). The emitter follower buffer includes two input transistors having their emitters each connected to at least one diode connected transistor connected to the clamp circuit. A receiver includes the differential amplifier and an analog to digital converter. A method for limiting the energy of analog signals in the receiver includes the step of operating the clamp circuit to limit the analog signals transmitted to the analog to digital converter (ADC). | 04-30-2009 |
| 20110150142 | DISCRETE TIME RECEIVER - A discrete-time receiver includes: a sampling mixer sampling an input signal according to a sampling clock; a discrete-time filter adjusting a decimation rate by using a control signal and filtering the sampled signal by using a filter clock; and a clock generator generating a sampling clock to be supplied to the sampling mixer, and generating the control signal and the filter clock by comparing the frequency of the sampling clock with a pre-set output frequency. Over a broadband input signal, a dynamic range of an output signal can be improved. | 06-23-2011 |
| 20110176640 | SAMPLING CIRCUIT AND RECEIVER UTILIZING THE SAME - Disclosed are a sampling circuit and a receiver that have a high level of filter design flexibility and excellent image rejection characteristics. Signals with phases that differ by 90° are sampled using an IQ generating circuit ( | 07-21-2011 |
| 20110222633 | HIGH DYNAMIC RANGE RADIO ARCHITECTURE WITH ENHANCED IMAGE REJECTION - A circuit for down-converting an RF signal to a baseband signal includes a trans-admittance amplifier adapted to receive the RF signal and generate in response a pair of differential current signals. The circuit further includes a trans-impedance amplifier having at least four mixers and at least four linear amplifiers. The four mixers frequency down-convert the pair of differential current signals to generate four pairs of differential baseband current signals, wherein each pair of the differential baseband current signals has a different phase and is associated with each of the linear amplifiers. Additionally, the circuit includes a summing block that generates an in-phase signal using a first weighted sum of the four different baseband current signals and a quadrature signal using a second weighted sum of the four different baseband current signals. The circuit further includes an analog-to-digital converter for converting the in-phase and quadrature signals to respective digital representations. | 09-15-2011 |
| 20120321020 | COMPLENTARY DIFFERENTIAL INPUT BASED MIXER CIRCUIT - A method, an apparatus and/or a system of complementary differential input based mixer circuit is disclosed. In one aspect, the method includes inputting a single ended signal to a mixer circuit comprising a differential input circuit through a complementary differential transistor pair of the differential input circuit of the mixer circuit. The method also includes converting the signal ended signal to a differential signal through the complementary differential transistor pair of the differential input circuit to drive the mixer circuit. | 12-20-2012 |
| 20130259163 | Low Power Receiver - According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an s output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TTA) implemented using a current mode to buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced. | 10-03-2013 |
| 20140126673 | Differential signal detecting device - A differential signal detecting device includes a secondary amplifier; a front-end receiver and a final amplifier which are respectively connected to the secondary amplifier; and a signal outputter which is connected to the final amplifier. The front-end receiver receives two externally inputted channels of differential signals and an externally inputted reference threshold voltage, differentiates and transduces the two channels of differential signals. The secondary amplifier receives and amplifies the signals which are outputted by the front-end receiver, and outputs the signals amplified again. The final amplifier differentiates and amplifies the signals outputted by the secondary amplifier and outputs the two channels of differentiated signals. The signal outputter receives the two channels of differentiated signals which are outputted by the final amplifier and processes the two channels of differentiated signals with a logical conjunction before outputting. | 05-08-2014 |
| 20150063494 | Methods and Systems for Energy-Efficient Communications Interface - In a high-impedance communications interface, driver energy consumption is proportional to the number of signal transitions. For signals having three or more distinct levels, it is possible for a signal driver to salvage energy from some downward signal transitions and reuse it on some subsequent upward signal transitions. To facilitate this energy-conserving behavior, communication is performed using group signaling over sets of wires using a vector signaling code, with the design and use of the vector signaling code insuring that energy availability is balanced with energy demand. | 03-05-2015 |
| 20150092889 | Method and Apparatus for Calibrating an Input Interface - According to at least one example embodiment a two phase calibration approach is employed for calibrating an input/output interface having multiple single-ended receivers. During a first phase, amplifier offset calibration is applied to each of the multiple single-ended receivers. During a second phase, reference voltage calibration is applied to a single-ended receiver of the multiple single-ended receivers to determine a calibration reference voltage value. The calibration reference voltage value is then employed in each of the multiple single-ended receivers during an active phase of the input/output interface. | 04-02-2015 |
| 20160079942 | COMMON-GATE AMPLIFIER FOR HIGH-SPEED DC-COUPLING COMMUNICATIONS - In one embodiment, a receiver comprises a differential common-gate amplifier having a differential input and a differential output, wherein the differential input comprises a first input and a second input, and the differential common-gate amplifier is configured to amplify an input differential signal at the differential input into an amplified differential signal at the differential output. The receiver also comprises a common-mode voltage sensor configured to sense a common-mode voltage of the input differential signal, a replica circuit configured to generate a replica voltage that tracks a direct current (DC) voltage at at least one of the first and second inputs, and a comparator configured to compare the sensed common-mode voltage with the replica voltage, and to adjust a first bias voltage input to the differential common-gate amplifier based on the comparison, wherein the DC voltage depends on the first bias voltage. | 03-17-2016 |
| 20160126994 | DIVERSITY RECEIVER FRONT END SYSTEM WITH VARIABLE-GAIN AMPLIFIERS - Diversity receiver front end system with variable-gain amplifiers. A receiving system can include a controller configured to selectively activate one or more of a plurality of paths between an input of a first multiplexer and an output of a second multiplexer. The receiving system can further include a plurality of bandpass filters, each one of the plurality of bandpass filters disposed along a corresponding one of the plurality of paths and configured to filter a signal received at the bandpass filter to a respective frequency band. The receiving system can further include a plurality of variable-gain amplifiers (VGAs), each one of the plurality of VGAs disposed along a corresponding one of the plurality of paths and configured to amplify a signal received at the VGA with a gain controlled by an amplifier control signal received from the controller. | 05-05-2016 |
| 20160127014 | DIVERSITY RECEIVER FRONT END SYSTEM WITH PHASE-SHIFTING COMPONENTS - Diversity receiver front end system with phase-shifting components. A receiving system can include a controller configured to selectively activate one or more of a plurality of paths between an input of the receiving system and an output of the receiving system. The receiving system can further include a plurality of amplifiers, each one of the plurality of amplifiers disposed along a corresponding one of the plurality of paths and configured to amplify a signal received at the amplifier. The receiving system can further include a plurality of phase-shift components, each one of the plurality of phase-shift components disposed along a corresponding one of the plurality of paths and configured to phase-shift a signal passing through the phase-shift component. | 05-05-2016 |
| 20160127029 | DIVERSITY RECEIVER FRONT END SYSTEM WITH SWITCHING NETWORK - Diversity receiver front end system with switching network. A receiving system can include a plurality of amplifiers, each one of the plurality of amplifiers disposed along a corresponding one of a plurality of paths between an input of the receiving system and an output of the receiving system and configured to amplify a signal received at the amplifier. The receiving system can further include a switching network including one or more single-pole/single-throw switches, each one of the switches coupling two of the plurality of paths. The receiving system can further include a controller configured to receive a band select signal and, based on the band select signal, enable one of the plurality of amplifiers and control the switching network. | 05-05-2016 |
